Verification method and device of i2c device, electronic equipment and storage medium

Abstract

The application provides a verification method and device of an I2C device, electronic equipment and a storage medium, and relates to the technical field of chip verification. The verification method of the I2C device comprises the following steps: obtaining a first signal sequence pair of a to-be-tested I2C device and a reference I2C device in a transmission process of test data; the first signal sequence pair comprises a clock timing signal sequence on a bus mounted by the to-be-tested I2C device and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the to-be-tested I2C device and the reference I2C device are realized based on a same register conversion level circuit; at least one timing signal sequence in the first signal sequence pair is adjusted in a protocol range supported by the to-be-tested I2C device to obtain a second signal sequence pair; and the to-be-tested I2C device is tested by using the second signal sequence pair. The application can efficiently and comprehensively verify the to-be-tested I2C device.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip verification technical field, and in particular to an I2C device verification method and device, electronic equipment and storage medium. BACKGROUND

[0002] In the verification process of an I2C (Inter-Integrated Circuit) device, it is crucial to ensure the correctness of the timing behavior on the SCL (Serial Clock Line) and SDA (Serial Data Line), which is directly related to whether the I2C module can operate normally.

[0003] Traditional verification methods usually involve building master-slave device models or using existing I2C devices to communicate with the device under test. If the communication is successful, it is considered that the timing behavior of the device under test meets the requirements. In order to verify, the verification personnel need to write similar I2C modules according to the specification, which requires a lot of code writing time. Subsequently, the code needs to be compiled, debugged and simulated to find and correct errors. This repeated compilation and debugging process consumes a lot of time and significantly reduces the verification efficiency. Moreover, if a certain specific specification of I2C module is used to test the device under test, although communication may be successful under this specific configuration, this verification process cannot cover all possible communication scenarios and timing behaviors, and cannot guarantee that the device under test can communicate normally with other I2C devices of different specifications, which may cause problems in the actual application of the device under test and some I2C devices.

[0004] Therefore, how to efficiently and comprehensively verify the I2C device under test is a technical problem to be solved. SUMMARY

[0005] In view of the above problems in the prior art, the present application provides an I2C device verification method and device, electronic equipment and storage medium, which can efficiently and comprehensively verify the I2C device under test.

[0006] The present application provides an I2C device verification method, which is applied to a register translation level circuit verification environment, and includes the following steps.

[0007] Obtaining a first signal sequence pair of the to-be-tested I2C device and the reference I2C device in a transmission process of test data, wherein the first signal sequence pair comprises a clock timing signal sequence on a bus mounted by the to-be-tested I2C device and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the to-be-tested I2C device and the reference I2C device are implemented based on a same register conversion stage circuit; performing timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the to-be-tested I2C device to obtain a second signal sequence pair; and testing the to-be-tested I2C device by using the second signal sequence pair.

[0008] According to the I2C device verification method provided in the application, in the transmission process of the test data, the to-be-tested I2C device is a slave device, and the reference I2C device is a master device; the obtaining of the first signal sequence pair of the to-be-tested I2C device and the reference I2C device in the transmission process of the test data comprises: obtaining a clock timing signal sequence output by a serial clock line of the reference I2C device; obtaining a data timing signal sequence output by a serial data line of the reference I2C device; and obtaining the first signal sequence pair according to the clock timing signal sequence and the data timing signal sequence.

[0009] According to the I2C device verification method provided in the application, the timing adjustment on at least one timing signal sequence in the first signal sequence pair within the protocol range supported by the to-be-tested I2C device to obtain the second signal sequence pair comprises: expanding each signal length of the clock timing signal sequence according to a first preset proportion; reducing each signal length of the data timing signal sequence according to a second preset proportion; obtaining the second signal sequence pair according to the adjusted clock timing signal sequence and the data timing signal sequence; or reducing each signal length of the clock timing signal sequence according to a third preset proportion; expanding each signal length of the data timing signal sequence according to a fourth preset proportion; obtaining the second signal sequence pair according to the adjusted clock timing signal sequence and the data timing signal sequence; or reducing each signal length of the clock timing signal sequence according to a fifth preset proportion; reducing each signal length of the data timing signal sequence according to a sixth preset proportion; obtaining the second signal sequence pair according to the adjusted clock timing signal sequence and the data timing signal sequence; or expanding each signal length of the clock timing signal sequence according to a seventh preset proportion; expanding each signal length of the data timing signal sequence according to an eighth preset proportion; and obtaining the second signal sequence pair according to the adjusted clock timing signal sequence and the data timing signal sequence.

[0010] According to the I2C device verification method provided by the application, during the transmission of the test data, the I2C device to be tested is a master device, and the reference I2C device is a slave device; the first signal sequence pair of the I2C device to be tested and the reference I2C device in the transmission process of the test data is obtained, including: obtaining a clock timing signal sequence output by a serial clock line of the I2C device to be tested; obtaining a data timing signal sequence output by a serial data line of the reference I2C device; and obtaining the first signal sequence pair according to the clock timing signal sequence and the data timing signal sequence.

[0011] According to the I2C device verification method provided by the application, the at least one timing signal sequence in the first signal sequence pair is adjusted in the protocol range supported by the I2C device to be tested to obtain a second signal sequence pair, including: expanding each signal length of the data timing signal sequence according to a ninth preset proportion; obtaining the second signal sequence pair according to the clock timing signal sequence and the adjusted data timing signal sequence; or reducing each signal length of the data timing signal sequence according to a tenth preset proportion; and obtaining the second signal sequence pair according to the clock timing signal sequence and the adjusted data timing signal sequence.

[0012] According to the I2C device verification method provided by the application, the I2C device to be tested is tested by using the second signal sequence pair, including: in the case that the I2C device to be tested is a master device, instructing the I2C device to be tested to initiate the transmission of the test data; and in response to the I2C device to be tested sending a start signal, inputting a clock timing signal sequence in the second signal sequence pair to an input end of a serial clock line of the I2C device to be tested, and simultaneously inputting a data timing signal sequence in the second signal sequence pair to an input end of a serial data line of the I2C device to be tested; collecting the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested in the data transmission process to obtain a test result timing sequence; and determining a test result according to the test result timing sequence; or in the case that the I2C device to be tested is a slave device, inputting the clock timing signal sequence in the second signal sequence pair to the input end of the serial clock line of the I2C device to be tested, and simultaneously inputting the data timing signal sequence in the second signal sequence pair to the input end of the serial data line of the I2C device to be tested; collecting the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested in the data transmission process to obtain a test result timing sequence; and determining a test result according to the test result timing sequence.

[0013] The application further provides an I2C device verification device, including the following modules:

[0014] The first acquisition module is configured to acquire a first signal sequence pair of the I2C device to be tested and the reference I2C device in a transmission process of test data; the first signal sequence pair comprises a clock timing signal sequence on a bus mounted by the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are based on the same register conversion stage circuit; the second acquisition module is configured to perform timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the I2C device to be tested, to obtain a second signal sequence pair; and the test module is configured to test the I2C device to be tested by using the second signal sequence pair.

[0015] The application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor implements the verification method of the I2C device according to any one of the above when executing the computer program.

[0016] The application further provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program implements the verification method of the I2C device according to any one of the above when executed by a processor.

[0017] The application further provides a computer program product comprising a computer program, and the computer program implements the verification method of the I2C device according to any one of the above when executed by a processor.

[0018] The I2C device verification method, device, electronic device, and storage medium provided by the application acquire a first signal sequence pair of an I2C device to be tested and a reference I2C device in a transmission process of test data; at least one timing signal sequence in the first signal sequence pair is adjusted in timing within a protocol range supported by the I2C device to be tested, to obtain a second signal sequence pair, so that I2C timing fluctuating within a certain range is constructed without the need for a verification personnel to write an I2C module with similar functions, and the verification completeness is effectively enhanced, so that the I2C device to be tested can be fully tested and verified under diversified timing conditions; the second signal sequence pair can be used to simulate special fluctuations such as glitches and noises in a real scene, so that the verification precision is greatly improved, and the stability and reliability of the I2C device to be tested in actual application are ensured, so that the I2C device to be tested can be efficiently and comprehensively verified. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to make the technical solutions in the present application or prior art clearer, the accompanying drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0020] Figure 1 is a flowchart of the verification method of the I2C device provided by the present application.

[0021] Figure 2 is one of the flowcharts of the method for testing the I2C device to be tested by using the second signal sequence provided by the present application.

[0022] Figure 3 is the second flowchart of the method for testing the I2C device to be tested by using the second signal sequence provided by the present application.

[0023] Figure 4 is a schematic diagram of the I2C device serial port provided by the present application.

[0024] Figure 5 is a schematic diagram of the I2C bus timing.

[0025] Figure 6 is a schematic diagram of the I2C verification environment provided by the present application.

[0026] Figure 7 is a schematic diagram of the adjustment of the clock timing signal sequence and the data timing signal sequence provided by the present application.

[0027] Figure 8 is a schematic diagram of the method for testing the I2C device to be tested by using the second signal sequence provided by the present application.

[0028] Figure 9 is a schematic diagram of the timing of the start signal sent by the I2C master device.

[0029] Figure 10 is a structural schematic diagram of the verification device of the I2C device provided by the present application.

[0030] Figure 11 is a structural schematic diagram of the electronic device provided by the present application. DETAILED DESCRIPTION

[0031] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in conjunction with the drawings in the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0032] The present application will be described below in conjunction with Figures 1-9 The verification method of the I2C device of the present application is described.

[0033] Figure 1 The present application provides a flowchart of the verification method of the I2C device, which is applied to a verification environment of a register transfer level circuit.

[0034] Register transfer level (RTL) is an important concept in digital circuit design, which mainly focuses on the description of data transmission and logical relationship between registers. Register transfer level is widely used in various digital circuit designs, especially in the design of complex large-scale integrated circuits (ASIC) and field programmable gate arrays (FPGA). In these designs, the RTL level code is a key bridge connecting high-level algorithm description and bottom-level physical implementation.

[0035] The verification environment is realized by using computer-aided design software, which is a design tool for completing the processes of functional design, synthesis, verification, physical design (including layout, routing, layout, design rule checking, etc.) of very large scale integrated circuit (VLSI) chips. It can compile and simulate by inputting register transfer level (RTL) code, and confirm whether the design is correct by combining waveform information analysis.

[0036] I2C (Inter-Integrated Circuit) is a kind of serial communication bus, which uses a master-slave architecture, and is developed by Philips in the 1980s for connecting low-speed peripheral devices for motherboard, embedded system or mobile phone.

[0037] As shown in Figure 1 The verification method of the I2C device includes the following steps:

[0038] Step 101, obtaining a first signal sequence pair of a to-be-tested I2C device and a reference I2C device in a transmission process of test data.

[0039] The I2C device to be tested and the reference I2C device are I2C devices described using register translation level circuit, and both are implemented based on the same register translation level circuit.

[0040] I2C is a two-wire serial communication protocol, and the transmission bus is composed of two data lines: serial clock line (SCL) and serial data line (SDA). As shown in Figure 4 The I2C device implemented by the register translation level circuit includes a serial data line input end (sda_in), a serial data line output end (sda_o), a serial clock line input end (scl_in), and a serial clock line output end (scl_o).

[0041] The I2C device uses a master-slave structure, and in the communication process of multiple I2C devices, there is one master device (Master) and one or more slave devices (Slave). The master device controls the communication process, while the slave device passively accepts the control of the master device and performs data transmission and reception. As shown in Figure 5 The following are the basic steps of I2C communication:

[0042] 1. The master device sends a start signal to indicate the start of communication.

[0043] 2. The master device sends the address of the slave device and the read / write bit. The address is used to select a specific slave device, and the read / write bit is used to indicate the direction of the data (read or write).

[0044] 3. The selected slave device confirms the receipt of the address and sends an acknowledgement signal.

[0045] 4. The master device continues to send or receive data.

[0046] 5. After the data transmission is completed, the master device sends a stop signal to indicate the end of communication.

[0047] The first signal sequence pair includes the clock timing signal sequence on the bus mounted by the I2C device to be tested and the reference I2C device, and the data timing signal sequence output by the serial data line of the reference I2C device.

[0048] In the specific implementation process, as shown in Figure 6 , an I2C verification environment can be built in the verification environment, in which the I2C device to be tested and the reference I2C device are started to transmit test data (for example, data read operation or data write operation), and in the transmission process, the first signal sequence pair is obtained by using the monitoring component.

[0049] In some embodiments, during the transmission of the test data, the I2C device to be tested is a slave device, and the reference I2C device is a master device. In this embodiment, a clock timing signal sequence output by a serial clock line of the reference I2C device can be acquired, and a data timing signal sequence output by a serial data line of the reference I2C device can be acquired; and a first signal sequence pair can be obtained according to the clock timing signal sequence and the data timing signal sequence.

[0050] In some embodiments, during the transmission of the test data, the I2C device to be tested is a master device, and the reference I2C device is a slave device. In this embodiment, a clock timing signal sequence output by a serial clock line of the I2C device to be tested can be acquired, and a data timing signal sequence output by a serial data line of the reference I2C device can be acquired; and a first signal sequence pair can be obtained according to the clock timing signal sequence and the data timing signal sequence.

[0051] In the specific implementation process, the first signal sequence pair acquired can be saved in various ways, for example, in the form of a waveform file, and is not limited by the description in this specification.

[0052] In step 102, at least one timing signal sequence in the first signal sequence pair is adjusted in the protocol supported by the I2C device to be tested to obtain a second signal sequence pair.

[0053] The I2C protocol supports various data transmission rates to meet the needs of different devices and applications. In the standard mode, the highest rate is 100 kilobits per second, in the fast mode, the rate is 400 kilobits per second, and in the fast mode plus, the rate can even reach 1 kilobit per second.

[0054] For example only, if the I2C device to be tested supports the standard mode, the signal sequences in the first signal sequence pair can be adjusted within the rate range of 100 kilobits per second to simulate I2C devices of different manufacturers and different models, and at the same time, special fluctuations such as glitches and noises in real scenes can also be added.

[0055] In some embodiments, during the acquisition of the first signal sequence pair, the I2C device to be tested is a slave device, and the reference I2C device is a master device. In this embodiment, the timing of the clock timing signal sequence and the data timing signal sequence in the first signal sequence pair can be adjusted in various ways to obtain a second signal sequence pair.

[0056] For example, the length of each signal in the clock timing signal sequence can be expanded according to a first preset ratio, the length of each signal in the data timing signal sequence can be reduced according to a second preset ratio, and a second signal sequence pair can be obtained according to the adjusted clock timing signal sequence and the data timing signal sequence.

[0057] For another example, the lengths of the signals in the clock timing signal sequence can be reduced according to a third preset ratio, the lengths of the signals in the data timing signal sequence can be increased according to a fourth preset ratio, and the second signal sequence pair can be obtained according to the adjusted clock timing signal sequence and the adjusted data timing signal sequence.

[0058] For another example, the lengths of the signals in the clock timing signal sequence can be reduced according to a fifth preset ratio, the lengths of the signals in the data timing signal sequence can be reduced according to a sixth preset ratio, and the second signal sequence pair can be obtained according to the adjusted clock timing signal sequence and the adjusted data timing signal sequence.

[0059] For another example, the lengths of the signals in the clock timing signal sequence can be increased according to a seventh preset ratio, the lengths of the signals in the data timing signal sequence can be increased according to an eighth preset ratio, and the second signal sequence pair can be obtained according to the adjusted clock timing signal sequence and the adjusted data timing signal sequence.

[0060] In the implementation, the values of the first preset ratio, the second preset ratio, the third preset ratio, the fourth preset ratio, the fifth preset ratio, the sixth preset ratio and the seventh preset ratio can be set according to the test requirement, and are not limited by the description herein.

[0061] The values of the above ratios can be the same or different, and are not limited by the description herein.

[0062] In some embodiments, during the collection of the first signal sequence pair, the I2C device to be tested is a master device, and the reference I2C device is a slave device. During the communication of the I2C devices, the serial clock signal is sent by the master device. Therefore, in this embodiment, the timing of the data timing signal sequence in the first signal sequence pair can be adjusted in various ways to obtain the second signal sequence pair.

[0063] For example, the lengths of the signals in the data timing signal sequence can be increased according to a ninth preset ratio, and the second signal sequence pair can be obtained according to the clock timing signal sequence and the adjusted data timing signal sequence.

[0064] For another example, the lengths of the signals in the data timing signal sequence can be reduced according to a tenth preset ratio, and the second signal sequence pair can be obtained according to the clock timing signal sequence and the adjusted data timing signal sequence.

[0065] In the implementation, the values of the ninth preset ratio and the tenth preset ratio can be set according to the test requirement, and are not limited by the description herein.

[0066] The values of the above ratios can be the same or different, and are not limited by the description herein.

[0067] Step 103, test the I2C device to be tested by using the second signal sequence pair.

[0068] In the specific implementation process, as shown in Figure 8 , a test bus B can be established, the input end of the serial clock line and the input end of the serial data line of the I2C device to be tested are connected to the test bus, the clock timing signal sequence in the second signal sequence pair is used to drive the serial clock line of the test bus, and the data timing signal sequence is used to drive the serial data line, so as to test the I2C device to be tested.

[0069] By using different second signal sequence pairs to drive the test bus B, different types and different application scenarios of I2C devices are simulated to test the I2C device to be tested.

[0070] For the two embodiments of testing the I2C device to be tested by using the second signal sequence pair, refer to the related contents in Figure 2 and Figure 3 , which will not be repeated here.

[0071] For example, as shown in Figure 7 , when the length of each signal in the data timing signal sequence is reduced by equal ratio and the length of each signal in the clock timing signal sequence is extended by equal ratio, the rising edge of the serial clock signal may change the sampling of the serial data signal, resulting in transmission failure. Therefore, by using the adjusted second signal sequence pair, the potential various problems of the I2C device to be tested can be conveniently and accurately tested.

[0072] Figure 2 is one of the flowcharts of the method for testing the I2C device to be tested by using the second signal sequence pair provided by the application.

[0073] In the embodiment, the I2C device to be tested is a master device, as shown in Figure 2 , the method comprises the following steps:

[0074] Step 201, instruct the I2C device to be tested to initiate transmission of test data.

[0075] In the specific implementation process, the I2C device to be tested can be controlled to initiate data transmission by writing a specific test script or program.

[0076] Step 202, in response to the start signal sent by the I2C device to be tested, input the clock timing signal sequence in the second signal sequence pair to the input end of the serial clock line of the I2C device to be tested, and input the data timing signal sequence to the input end of the serial data line of the I2C device to be tested.

[0077] In the implementation process, after monitoring that the I2C device to be tested sends a start signal (as shown in Figure 9 The clock timing signal sequence and the data timing signal sequence are input to the input end of the serial clock line of the I2C device to be tested and the input end of the serial data line of the I2C device to be tested through the test bus.

[0078] Step 203, collecting the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested in the current data transmission process to obtain a test result timing sequence.

[0079] Step 204, determining the current test result according to the test result timing sequence.

[0080] In the implementation process, whether the I2C device to be tested makes a correct response in the test process can be determined according to the test result timing sequence, so as to determine whether the I2C device to be tested passes the current test.

[0081] In the embodiment provided by the application, in the case that the I2C device to be tested is a master device, the I2C device to be tested is instructed to initiate transmission of test data, and in response to the start signal sent by the I2C device to be tested, the clock timing signal sequence and the data timing signal sequence are input to the input end of the serial clock line of the I2C device to be tested and the input end of the serial data line of the I2C device to be tested, respectively. The clock timing signal sequence and the data timing signal sequence are used to simulate timing signals output by a plurality of different I2C slave devices, so that a rich and diverse test scene can be generated to efficiently and comprehensively verify the I2C device to be tested as a master device.

[0082] Figure 3 is a flowchart of a method for testing an I2C device to be tested by using a second signal sequence pair provided by the application.

[0083] In the embodiment, the I2C device to be tested is a slave device, and as shown in Figure 3 The method comprises the following steps.

[0084] Step 301, inputting the clock timing signal sequence and the data timing signal sequence in the second signal sequence pair to the input end of the serial clock line of the I2C device to be tested and the input end of the serial data line of the I2C device to be tested, respectively.

[0085] In this step, the clock timing signal sequence and the data timing signal sequence are used to simulate timing signals output by a plurality of different I2C master devices to initiate data transmission.

[0086] Step 302, collecting the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested in the current data transmission process to obtain a test result timing sequence.

[0087] In step 303, the test result is determined according to the test result time sequence.

[0088] In the implementation process, whether the I2C device under test makes a correct response in the test process can be determined according to the test result time sequence, so as to determine whether the I2C device under test passes the test.

[0089] In the embodiment provided by the application, in the case that the I2C device under test is a slave device, the second signal sequence pair is input to the input end of the serial clock line of the I2C device under test, and the data time sequence signal sequence is input to the input end of the serial data line of the I2C device under test, so that a plurality of different I2C master device output time sequence signals can be simulated by using the second signal sequence pair, thereby generating rich and diverse test scenes to efficiently and comprehensively verify the I2C device under test as a slave device.

[0090] The I2C device verification apparatus provided by the application is described below, and the I2C device verification apparatus described below can be correspondingly referred to the I2C device verification method described above.

[0091] Figure 10 FIG. 1 is a structural schematic diagram of the I2C device verification apparatus provided by the application, as shown in the figure, the apparatus 1000 comprises the following modules. Figure 10

[0092] The first acquisition module 1010 is configured to acquire a first signal sequence pair of the I2C device under test and the reference I2C device in the transmission process of the test data, wherein the first signal sequence pair comprises a clock time sequence signal sequence on the bus mounted by the I2C device under test and the reference I2C device, and a data time sequence signal sequence output by the serial data line of the reference I2C device, and the I2C device under test and the reference I2C device are implemented based on the same register conversion level circuit.

[0093] The second acquisition module 1020 is configured to perform time sequence adjustment on at least one time sequence signal sequence in the first signal sequence pair within the protocol range supported by the I2C device under test, to obtain a second signal sequence pair.

[0094] The test module 1030 is configured to test the I2C device under test by using the second signal sequence pair.

[0095] Figure 11 FIG. 2 is an entity structural schematic diagram of an electronic device, as shown in the figure, the electronic device comprises the following modules. Figure 11 ​As shown, the electronic device can include a processor 1110, a communications interface 1120, a memory 1130, and a communications bus 1140, wherein the processor 1110, the communications interface 1120, and the memory 1130 complete communication with each other through the communications bus 1140. The processor 1110 can invoke a logical instruction in the memory 1130 to execute a verification method of an I2C device, the method including: obtaining a first signal sequence pair of a to-be-tested I2C device and a reference I2C device in a transmission process for test data; wherein the first signal sequence pair includes a clock timing signal sequence on a bus mounted by the to-be-tested I2C device and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, the to-be-tested I2C device and the reference I2C device being implemented based on a same register conversion stage circuit; performing timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the to-be-tested I2C device to obtain a second signal sequence pair; and testing the to-be-tested I2C device by using the second signal sequence pair.

[0096] In addition, the logical instruction in the memory 1130 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application essentially or in part or parts of the technical solutions that make contributions to the prior art can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes several instructions for making a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0097] In another aspect, the present application also provides a computer program product comprising a computer program, which can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to perform the I2C device verification method provided by the above method, which comprises: obtaining a first signal sequence pair of a to-be-tested I2C device and a reference I2C device in a transmission process of test data; wherein the first signal sequence pair comprises a clock timing signal sequence on a bus mounted by the to-be-tested I2C device and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the to-be-tested I2C device and the reference I2C device are implemented based on a same register conversion level circuit; performing timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the to-be-tested I2C device to obtain a second signal sequence pair; and testing the to-be-tested I2C device by using the second signal sequence pair.

[0098] In another aspect, the present application also provides a non-transitory computer readable storage medium having a computer program stored thereon, and the computer program can be executed by a processor to implement the I2C device verification method provided by the above method, which comprises: obtaining a first signal sequence pair of a to-be-tested I2C device and a reference I2C device in a transmission process of test data; wherein the first signal sequence pair comprises a clock timing signal sequence on a bus mounted by the to-be-tested I2C device and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the to-be-tested I2C device and the reference I2C device are implemented based on a same register conversion level circuit; performing timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the to-be-tested I2C device to obtain a second signal sequence pair; and testing the to-be-tested I2C device by using the second signal sequence pair.

[0099] The device embodiments described above are only schematic, wherein the units shown as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the present embodiment scheme. Those skilled in the art can understand and implement without creative labor.

[0100] Those skilled in the art can clearly understand the technical solutions of the various embodiments from the above description of the embodiments, and the various embodiments can be implemented by means of software with the necessary general hardware platforms, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that makes a contribution, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0101] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A verification method for an I2C device, characterized in that, The method is applied in a verification environment for register conversion stage circuits, and the method includes: Acquire a first signal sequence pair between the I2C device under test and the reference I2C device during the transmission of test data; wherein the first signal sequence pair includes clock timing signal sequences on the buses connected to the I2C device under test and the reference I2C device, and data timing signal sequences output from the serial data line of the reference I2C device, and the I2C device under test and the reference I2C device are implemented based on the same register conversion stage circuit; For at least one timing signal sequence in the first signal sequence pair, timing adjustment is performed within the protocol range supported by the I2C device under test to obtain a second signal sequence pair, including: According to a first preset ratio, the length of each signal in the clock timing signal sequence is increased; According to the second preset ratio, the length of each signal in the data timing signal sequence is reduced; The second signal sequence pair is obtained based on the adjusted clock timing signal sequence and the data timing signal sequence; or According to the third preset ratio, the length of each signal in the clock timing signal sequence is reduced; According to the fourth preset ratio, the length of each signal in the data timing signal sequence is increased; The second signal sequence pair is obtained based on the adjusted clock timing signal sequence and the data timing signal sequence; or According to the fifth preset ratio, the length of each signal in the clock timing signal sequence is reduced; According to the sixth preset ratio, the length of each signal in the data timing signal sequence is reduced; The second signal sequence pair is obtained based on the adjusted clock timing signal sequence and the data timing signal sequence; or According to the seventh preset ratio, the length of each signal in the clock timing signal sequence is increased; According to the eighth preset ratio, the length of each signal in the data timing signal sequence is increased; The second signal sequence pair is obtained based on the adjusted clock timing signal sequence and the data timing signal sequence; or, According to the ninth preset ratio, the length of each signal in the data timing signal sequence is increased; The second signal sequence pair is obtained based on the clock timing signal sequence and the adjusted data timing signal sequence; or According to the tenth preset ratio, the length of each signal in the data timing signal sequence is reduced; The second signal sequence pair is obtained based on the clock timing signal sequence and the adjusted data timing signal sequence; The I2C device under test is tested using the second signal sequence pair, including: When the I2C device under test is the master device, it is instructed to initiate the transmission of the test data; and In response to the start signal issued by the I2C device under test, the clock timing signal sequence of the second signal sequence pair is input to the input terminal of the serial clock line of the I2C device under test, and the data timing signal sequence is input to the input terminal of the serial data line of the I2C device under test. The clock timing signal sequence and data timing signal sequence of the I2C device under test are collected during this data transmission process to obtain the test result timing sequence; The test results are determined based on the time sequence of the test results. When the I2C device under test is a slave device, the clock timing signal sequence of the second signal sequence pair is input to the input terminal of the serial clock line of the I2C device under test, and the data timing signal sequence is input to the input terminal of the serial data line of the I2C device under test. The clock timing signal sequence and data timing signal sequence of the I2C device under test are collected during this data transmission process to obtain the test result timing sequence; The test result is determined based on the time sequence of the test results.

2. The verification method for I2C devices according to claim 1, characterized in that, During the transmission of the test data, the I2C device under test is a slave device, and the reference I2C device is a master device; The acquisition of the first signal sequence pair between the I2C device under test and the reference I2C device during the transmission of test data includes: Obtain the clock timing signal sequence output from the serial clock line of the reference I2C device; Obtain the data timing signal sequence output from the serial data line of the reference I2C device; The first signal sequence pair is obtained based on the clock timing signal sequence and the data timing signal sequence.

3. The verification method for I2C devices according to claim 1, characterized in that, During the transmission of the test data, the I2C device under test is the master device, and the reference I2C device is the slave device. The acquisition of the first signal sequence pair between the I2C device under test and the reference I2C device during the transmission of test data includes: Obtain the clock timing signal sequence output from the serial clock line of the I2C device under test; Obtain the data timing signal sequence output from the serial data line of the reference I2C device; The first signal sequence pair is obtained based on the clock timing signal sequence and the data timing signal sequence.

4. A verification device for an I2C device, characterized in that, The device is located in the verification environment of the register conversion stage circuit, and the device includes: The first acquisition module is used to acquire a first signal sequence pair between the I2C device under test and the reference I2C device during the transmission of test data; wherein, the first signal sequence pair includes clock timing signal sequences on the buses connected to the I2C device under test and the reference I2C device, and data timing signal sequences output from the serial data line of the reference I2C device, and the I2C device under test and the reference I2C device are implemented based on the same register conversion stage circuit; The second acquisition module is configured to perform timing adjustment on at least one timing signal sequence in the first signal sequence pair within the protocol range supported by the I2C device under test, to obtain a second signal sequence pair, including: According to a first preset ratio, the length of each signal in the clock timing signal sequence is increased; According to the second preset ratio, the length of each signal in the data timing signal sequence is reduced; The second signal sequence pair is obtained based on the adjusted clock timing signal sequence and the data timing signal sequence; or According to the third preset ratio, the length of each signal in the clock timing signal sequence is reduced; According to the fourth preset ratio, the length of each signal in the data timing signal sequence is increased; The second signal sequence pair is obtained based on the adjusted clock timing signal sequence and the data timing signal sequence; or According to the fifth preset ratio, the length of each signal in the clock timing signal sequence is reduced; According to the sixth preset ratio, the length of each signal in the data timing signal sequence is reduced; The second signal sequence pair is obtained based on the adjusted clock timing signal sequence and the data timing signal sequence; or According to the seventh preset ratio, the length of each signal in the clock timing signal sequence is increased; According to the eighth preset ratio, the length of each signal in the data timing signal sequence is increased; The second signal sequence pair is obtained based on the adjusted clock timing signal sequence and the data timing signal sequence; or, According to the ninth preset ratio, the length of each signal in the data timing signal sequence is increased; The second signal sequence pair is obtained based on the clock timing signal sequence and the adjusted data timing signal sequence; or According to the tenth preset ratio, the length of each signal in the data timing signal sequence is reduced; The second signal sequence pair is obtained based on the clock timing signal sequence and the adjusted data timing signal sequence; The test module is used to test the I2C device under test using the second signal sequence pair, including: When the I2C device under test is the master device, it is instructed to initiate the transmission of the test data; and In response to the start signal issued by the I2C device under test, the clock timing signal sequence of the second signal sequence pair is input to the input terminal of the serial clock line of the I2C device under test, and the data timing signal sequence is input to the input terminal of the serial data line of the I2C device under test. The clock timing signal sequence and data timing signal sequence of the I2C device under test are collected during this data transmission process to obtain the test result timing sequence; The test results are determined based on the time sequence of the test results. When the I2C device under test is a slave device, the clock timing signal sequence of the second signal sequence pair is input to the input terminal of the serial clock line of the I2C device under test, and the data timing signal sequence is input to the input terminal of the serial data line of the I2C device under test. The clock timing signal sequence and data timing signal sequence of the I2C device under test are collected during this data transmission process to obtain the test result timing sequence; The test result is determined based on the time sequence of the test results.

5. An electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the verification method for the I2C device as described in any one of claims 1 to 3.

6. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the verification method for the I2C device as described in any one of claims 1 to 3.

7. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the verification method for the I2C device as described in any one of claims 1 to 3.

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