Method and system for loading SPARC architecture SoC based on general IO
By parsing and outputting code stream data that conforms to the serial port format through a method based on general IO, it solves the problems of cumbersome program loading and chip testing risks in the SPARC architecture processor boot method in the existing technology, and achieves flexible program replacement and efficient chip test.
Patent Information
- Application Number
- CN202411391855.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-08
- Publication Date
- 2025-01-24
AI Technical Summary
In the existing SPARC architecture processor boot method, non-volatile memory loading programs are more cumbersome and risk items are added in chip testing.
Load the SPARC architecture SOC based on a general IO method. By compiling and generating the executable ELF file, analyzing and splitting data, adding DSU writing data packet header and writing address, forming code flow data that conforms to the serial format, and through the general IO driver program The DSU interface output to the Sparc architecture SOC.
It achieves the flexibility and efficiency of program replacement, reduces the risk in chip testing, is suitable for frequent program debugging scenarios, and improves the efficiency of machine debugging.
Smart Images
Figure CN119357108A_ABST
Abstract
Description
Background Art
[0002] In the boot method of SPARC architecture processor in the prior art, the SPARC main core starts from Nor Flash, executes the boot loader, initializes the memory and memory controller, obtains the operating system information, writes the operating system from Nor Flash to the corresponding address of SRAM, and opens other cores to run the operating system. The configuration object of this method is a SPARC architecture processor, but it uses Nor Flash booting, which is non-volatile memory loading, and the replacement program is cumbersome, and it increases the risk item in chip testing.
[0003] Therefore, the existing SPARC architecture processor boot method has the problem that it is relatively cumbersome to load and replace the program for the non-volatile memory, and increases the risk item in the chip test. Summary of the invention
[0004] In order to solve the above-mentioned problem in the prior art, that is, the existing SPARC architecture processor booting method has the problem that the non-volatile memory is loaded, the replacement program is relatively cumbersome, and the risk item is increased in chip testing, the present invention provides a method for loading a SPARC architecture SoC based on a general IO, the method comprising:
[0005] Use the SPARC architecture SoC compiler to compile the SPARC architecture SoC project file to generate an executable ELF file;
[0006] Parsing the ELF file to obtain a set of loaded code segment data byte arrays in a 32-bit array output format;
[0007] Each 32-bit array of the set of the loaded code segment data byte array is split into 8M-bit data, and a DSU write data packet header and a write address data field are added to each 8M-bit data to form an 8M-bit array; the data field includes a DSU write data packet header and a write address;
[0008] Each data in each 8M bit array is parsed according to the bit position to obtain code stream data; the code stream number of the code stream data is the ratio of the general IO clock cycle to the baud rate;
[0009] For every 8M bits of data in the code stream data, 1 start bit and 1 stop bit are added to obtain the code stream data that conforms to the serial port; the code stream data that conforms to the serial port is read using a universal IO driver, and then the universal IO driver outputs the code stream data that conforms to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC.
[0010] In a preferred embodiment, the output format of the set of loaded code segment data byte arrays is a 32-bit bit array format; when the output format of the set of loaded code segment data byte arrays is a 32-bit array format, each of the 32-bit arrays is split into 8-bit data, a data field is added to each 8-bit data to form an 8-bit array, each data in each 8-bit array is parsed according to the bit to obtain code stream data, and 1 bit of start bit and 1 bit of stop bit are added to each 8-bit data in the code stream data to obtain code stream data that conforms to the serial port.
[0011] In a preferred implementation, the ELF file is an executable file that can be loaded into a SPARC architecture SoC for execution.
[0012] In a preferred implementation, each bit of the code stream data is composed of DSU protocol and loading code segment data.
[0013] In a preferred implementation, the set of the loaded code segment data byte array includes the physical start address of the loaded code segment, the size of the loaded code segment, and the actual data in the ELF file.
[0014] In a preferred implementation, parsing the ELF file includes: referring to the ELF file format definition and parsing the ELF file using a dynamic link library developed in a high-level language.
[0015] In a preferred embodiment, after the general IO outputs the code stream data conforming to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC, the following steps are included:
[0016] The general IO output pin is connected to the RX pin of the DSU interface of the SPARC architecture SoC and shares a common ground. The general IO uses LabVIEW language to call the board driver API. After obtaining the code stream data that conforms to the serial port, the general IO outputs the code stream data that conforms to the serial port from the general IO pin in the form of a digital waveform according to the general IO clock cycle. After the data output is completed, the SPARC architecture SoC starts to run.
[0017] In a preferred embodiment, the general IO is a digital waveform generator.
[0018] A second aspect of the present invention provides a system for loading a SPARC architecture SoC based on general IO, the system comprising:
[0019] A file compilation module, used for compiling a SPARC architecture SoC project file into an executable ELF file using a SPARC architecture SoC compiler;
[0020] A file parsing module, used for parsing the ELF file to obtain a set of loading code segment data byte arrays in a 32-bit array output format;
[0021] An array splitting module is used to split each 32-bit array of the set of the loaded code segment data byte array into 8-bit data, and each 8-bit data is added with a DSU write data packet header and a write address to form an 8-bit array;
[0022] A data analysis module is used to analyze each data in each 8-bit array according to the bit position to obtain code stream data; the code stream number of the code stream data is the ratio of the general IO clock cycle to the baud rate;
[0023] A data transmission module is used to add 1 start bit and 1 stop bit to every 8 bits of data in the code stream data to obtain code stream data that conforms to the serial port; use a universal IO driver to read the code stream data that conforms to the serial port, and then the universal IO driver outputs the code stream data that conforms to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC.
[0024] According to a third aspect of the present invention, an electronic device is proposed, comprising: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned method of loading a SPARC architecture SoC based on general IO.
[0025] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned method of loading a SPARC architecture SoC based on general IO.
[0026] Beneficial effects of the present invention:
[0027] (1) Since the present invention parses the executable file compiled and generated by the SPARC architecture SoC, changing the program only requires recompiling and generating the executable file. Therefore, it is very flexible and convenient, and is more suitable for scenarios that require frequent program replacement and debugging.
[0028] (2) The present invention uses a universal IO analog serial port to communicate with the SPARC DSU unit, which is the same as the principle of using a digital IO output code stream to configure the chip on an ATE machine. Test vector development and debugging can be performed in advance at the board level, providing a reference for machine testing and increasing the efficiency of machine debugging.
[0029] (3) The method of the present invention is an online configuration, which avoids the use of non-volatile memory in SPARC architecture SoC testing and reduces the risk of chip test failure due to problems with other devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:
[0031] Figure 1 It is a schematic diagram of a method for loading a SPARC architecture SoC based on general IO according to an embodiment of the present invention;
[0032] Figure 2 It is a flow chart of a method for loading a SPARC architecture SoC based on general IO according to an embodiment of the present invention;
[0033] Figure 3 It is a structural diagram of a computer system of a server for implementing the method, system, and device embodiments of the present application. DETAILED DESCRIPTION
[0034] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.
[0035] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.
[0036] The present invention provides a method for loading a SPARC architecture SoC based on general IO, such as Figure 1 As shown, the method includes:
[0037] Parsing the ELF file to obtain a set of loaded code segment data byte arrays;
[0038] Each array of the set of the loaded code segment data byte array is split into M-bit data, and a data field is added to each M-bit data to form an M-bit array; the data field includes a DSU write data packet header and a write address;
[0039] Each data in each M-bit array is parsed according to the bit position to obtain code stream data; the code stream number of the code stream data is the ratio of the general IO clock cycle to the baud rate;
[0040] Each M-bit data in the code stream data is added with a start bit and a stop bit to obtain code stream data that conforms to the serial port; the code stream data that conforms to the serial port is read using a universal IO driver, and then the universal IO driver outputs the code stream data that conforms to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC. In order to more clearly explain the method of loading a SPARC architecture SoC based on universal IO of the present invention, the following is combined with Figure 1 Each step in the embodiment of the present invention is described in detail.
[0041] like Figure 2 As shown, the method for loading a SPARC architecture SoC based on general IO according to the first embodiment of the present invention, each step is described in detail as follows:
[0042] Use the SPARC architecture SoC compiler to compile the SPARC architecture SoC project file to generate an executable ELF file;
[0043] In this embodiment, the ELF file is an executable file that can be loaded into a SPARC architecture SoC for execution.
[0044] Parsing the ELF file to obtain a set of loaded code segment data byte arrays;
[0045] In this embodiment, parsing the ELF file includes: referring to the ELF file format definition, using a dynamic link library developed in a high-level language to parse the ELF file. In this embodiment, software parsing can be used to parse the ELF format file, and the parsing software is written in C# language, and the parsing logic is formed by referring to the SPARC ELF format official document definition. It includes a file header parsing module and a code segment parsing module. The baud rate is configured to be 115200, the clock rate is configured to be 25MHz, and the clock cycle occupied by each bit in the serial communication is: 25000000 / 115200≈217. The serial port is set to 1 start bit, 8 data bits, and 1 stop bit.
[0046] In this embodiment, the set of the loaded code segment data byte array includes the physical starting address of the loaded code segment, the size of the loaded code segment, and the actual data in the ELF file. Each 32-bit array of the set of the loaded code segment data byte array is split into M-bit data, and a DSU write data packet header and a write address are added to each M-bit data to form an M-bit array; each data in each M-bit array is parsed according to the bit to obtain code stream data; the code stream number of the code stream data is the ratio of the general IO clock cycle to the baud rate;
[0047] In this embodiment, the output format of the set of loaded code segment data byte arrays is a 32-bit bit array format; when the output format of the set of loaded code segment data byte arrays is a 32-bit array format, each of the 32-bit arrays is split into 8-bit data, a data field is added to each 8-bit data to form an 8-bit array, each data in each 8-bit array is parsed according to the bit position to obtain code stream data, and 1 bit of start bit and 1 bit of stop bit are added to each 8-bit data in the code stream data to obtain code stream data that conforms to the serial port.
[0048] In this embodiment, each bit of the code stream data is composed of DSU protocol and loading code segment data. In the DSU protocol, data is written to a specific address, and the serial port data format is: a. write data packet header; b. start address; c. data.
[0049] Parsing and reorganizing the ELF file to obtain the bit stream data means that multiple clock cycle data of the general IO are combined into 1 bit of data in the serial communication according to the configured baud rate and clock size. Each bit of data is composed of the DSU protocol and the parsed loading code segment data.
[0050] A start bit and a stop bit are added to each M bits of data in the code stream data to obtain code stream data that conforms to the serial port; the code stream data that conforms to the serial port is read using a universal IO driver, and then the universal IO driver outputs the code stream data that conforms to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC.
[0051] In this embodiment, after the universal IO outputs the code stream data conforming to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC, it includes: connecting the universal IO output pin to the RX pin of the DSU interface of the SPARC architecture SoC and sharing the ground, the universal IO uses the LabVIEW language to call the board driver API, and after obtaining the code stream data conforming to the serial port, the universal IO outputs the code stream data conforming to the serial port from the universal IO pin in the form of a digital waveform according to the universal IO clock cycle. After the data output is completed, the SPARC architecture SoC starts to run.
[0052] Preferably, the general IO is a digital waveform generator, which uses LabVIEW language to call the board driver API, obtains the bit stream data, and then outputs the data from the IO pin according to the set 25 MHz clock rate.
[0053] After the data output is completed, the program will be loaded into the SoC. After the program is loaded, observe whether the indicator light connected to the status IO of the SoC is on or off, or use an oscilloscope or multimeter to measure whether the status IO pin has the expected waveform and level output.
[0054] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.
[0055] A system for loading a SPARC architecture SoC based on general IO according to a second embodiment of the present invention comprises:
[0056] A file compilation module, used for compiling a SPARC architecture SoC project file into an executable ELF file using a SPARC architecture SoC compiler;
[0057] A file parsing module, used for parsing the ELF file to obtain a set of loading code segment data byte arrays in a 32-bit array output format;
[0058] An array splitting module is used to split each 32-bit array of the set of the loaded code segment data byte array into 8-bit data, and each 8-bit data is added with a DSU write data packet header and a write address to form an 8-bit array;
[0059] A data analysis module is used to analyze each data in each 8-bit array according to the bit position to obtain code stream data; the code stream number of the code stream data is the ratio of the general IO clock cycle to the baud rate;
[0060] A data transmission module is used to add 1 start bit and 1 stop bit to every 8 bits of data in the code stream data to obtain code stream data that conforms to the serial port; use a universal IO driver to read the code stream data that conforms to the serial port, and then the universal IO driver outputs the code stream data that conforms to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC.
[0061] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.
[0062] It should be noted that the system based on general IO loading SPARC architecture SoC provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiment can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.
[0063] An electronic device according to the third embodiment of the present invention comprises: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned method of loading a SPARC architecture SoC based on general IO.
[0064] A computer-readable storage medium according to a fourth embodiment of the present invention stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned method of loading a SPARC architecture SoC based on general IO.
[0065] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the electronic device and storage medium described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.
[0066] Those skilled in the art should be able to appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two, and the programs corresponding to the software modules and method steps can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field. In order to clearly illustrate the interchangeability of electronic hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.
[0067] Reference below Figure 3 , which shows a schematic diagram of the structure of a computer system of a server for implementing the method, system, and device embodiments of the present application. Figure 3 The server shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.
[0068] like Figure 3 As shown, the computer system includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 602 or the program loaded from the storage part 608 to the random access memory (RAM) 603. Various programs and data required for system operation are also stored in the RAM 603. The CPU 601, ROM 602 and RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.
[0069] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed so that a computer program read therefrom is installed into the storage section 608 as needed.
[0070] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 609, and / or installed from the removable medium 611. When the computer program is executed by the central processing unit (CPU) 601, the above-mentioned functions defined in the method of the present application are executed. It should be noted that the above-mentioned computer-readable medium of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, an apparatus or a device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, an apparatus or a device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.
[0071] Computer program code for performing the operations of the present application may be written in one or more programming languages or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0072] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.
[0073] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.
[0074] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.
[0075] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.
Claims
1. A method for loading a SPARC architecture SoC based on general IO, characterized in that: The method comprises: Use the SPARC architecture SoC compiler to compile the SPARC architecture SoC project file to generate an executable ELF file; Parsing the ELF file to obtain a set of loaded code segment data byte arrays; Each array of the set of the loaded code segment data byte array is split into M-bit data, and a data field is added to each M-bit data to form an M-bit array; the data field includes a DSU write data packet header and a write address; Each data in each M-bit array is parsed according to the bit position to obtain code stream data; the code stream number of the code stream data is the ratio of the general IO clock cycle to the baud rate; A start bit and a stop bit are added to each M bits of data in the code stream data to obtain code stream data that conforms to the serial port; the code stream data that conforms to the serial port is read using a universal IO driver, and then the universal IO driver outputs the code stream data that conforms to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC.
2. According to the method of claim 1, wherein the method comprises: The output format of the set of loaded code segment data byte arrays is a 32-bit bit array format; when the output format of the set of loaded code segment data byte arrays is a 32-bit array format, each of the 32-bit arrays is split into 8-bit data, a data field is added to each 8-bit data to form an 8-bit array, each data in each 8-bit array is parsed according to the bit position to obtain code stream data, and 1 bit of start bit and 1 bit of stop bit are added to each 8-bit data in the code stream data to obtain code stream data that conforms to the serial port.
3. The method for loading a SPARC architecture SoC based on general IO according to claim 2, characterized in that: The ELF file is an executable file that can be loaded into a SPARC architecture SoC for execution.
4. The method for loading a SPARC architecture SoC based on general IO according to claim 3, characterized in that: Each bit of the code stream data is composed of DSU protocol and loading code segment data.
5. The method for loading a SPARC architecture SoC based on general IO according to claim 4, characterized in that: The set of the loaded code segment data byte array includes the physical start address of the loaded code segment, the size of the loaded code segment and the actual data in the ELF file.
6. The method for loading a SPARC architecture SoC based on general IO according to claim 5, characterized in that: Parsing the ELF file includes: referring to the ELF file format definition and parsing the ELF file using a dynamic link library developed in a high-level language.
7. The method for loading a SPARC architecture SoC based on general IO according to claim 6, characterized in that: After the general IO outputs the code stream data conforming to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC, it includes: The general IO output pin is connected to the RX pin of the DSU interface of the SPARC architecture SoC and shares a common ground. The general IO uses LabVIEW language to call the board driver API. After obtaining the code stream data that conforms to the serial port, the general IO outputs the code stream data that conforms to the serial port from the general IO pin in the form of a digital waveform according to the general IO clock cycle. After the data output is completed, the SPARC architecture SoC starts to run.
8. The method for loading a SPARC architecture SoC based on general IO according to claim 7, characterized in that: The general IO is a digital waveform generator.
9. A system for loading SPARC architecture SoC based on general IO, characterized in that: The system comprises: A file compilation module, used for compiling a SPARC architecture SoC project file into an executable ELF file using a SPARC architecture SoC compiler; A file parsing module, used for parsing the ELF file to obtain a set of loading code segment data byte arrays in a 32-bit array output format; An array splitting module is used to split each 32-bit array of the set of the loaded code segment data byte array into 8-bit data, and each 8-bit data is added with a DSU write data packet header and a write address to form an 8-bit array; A data analysis module is used to analyze each data in each 8-bit array according to the bit position to obtain code stream data; the code stream number of the code stream data is the ratio of the general IO clock cycle to the baud rate; A data transmission module is used to add 1 start bit and 1 stop bit to every 8 bits of data in the code stream data to obtain code stream data that conforms to the serial port; use a universal IO driver to read the code stream data that conforms to the serial port, and then the universal IO driver outputs the code stream data that conforms to the serial port in the form of a digital waveform to the DSU interface of the SPARC architecture SoC.
10. An electronic device, characterized in that: include: at least one processor; And a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the method of loading a SPARC architecture SoC based on general IO as described in any one of claims 1-8.