A data transmission method and interface circuit based on JESD204B protocol

Abstract

The present application discloses a data transmission method and interface circuit based on the JESD204B protocol, wherein the data transmission method based on the JESD204B protocol includes: obtaining a framing mode for a data channel configured based on the JESD204B protocol, wherein the data channel is used to transmit data from a sampling clock domain to a character clock domain; calculating a first frequency division coefficient of a sampling clock corresponding to the sampling clock domain and a second frequency division coefficient of a character clock corresponding to the character clock domain according to configuration parameters corresponding to the framing mode; adjusting a first clock frequency of the sampling clock according to the first frequency division coefficient, and adjusting a second clock frequency of the character clock according to the second frequency division coefficient; transmitting data from the sampling clock domain to the character clock domain through the data channel according to the adjusted first clock frequency and second clock frequency. The technical solution of the present application can reduce data link transmission problems caused by clock frequency configuration errors.

Description

Technical Field

[0001] The present application relates to the technical field of communication circuit design, and in particular to a data transmission method and interface circuit based on the JESD204B protocol. Background Art

[0002] In the JESD204B protocol, when the analog-to-digital converter transmits data, it needs to transfer the data in the sampling clock domain to the character clock domain according to the protocol based on different configuration parameters. In this process, the user needs to adjust the clock frequencies of the sampling clock and the character clock according to parameters such as the number of converters, the number of samples in one clock cycle of a single converter, and the number of channels used in the physical layer to ensure that the data bandwidth in the sampling clock domain is consistent with the data bandwidth in the character clock domain.

[0003] In the existing JESD204B design, some necessary configuration parameters need to be set manually. These configurations are the data framing methods of the framing module of the data path. And users are often required to have a deep understanding of JESD204B in order to avoid the problem of clock frequency configuration errors when using the JESD204B protocol.

[0004] For technicians who are new to the JESD204B protocol, they often do not know what the corresponding clock frequency should be configured to in different framing modes, which can easily lead to transmission problems in the data link. Summary of the invention

[0005] In order to solve the above technical problems, an embodiment of the present application provides a level converter and a digital logic circuit.

[0006] According to one aspect of an embodiment of the present application, a data transmission method based on the JESD204B protocol is provided, including: obtaining a framing mode for a data channel configured based on the JESD204B protocol, the data channel being used to transmit data in a sampling clock domain to a character clock domain; calculating a first frequency division coefficient of a sampling clock corresponding to the sampling clock domain and a second frequency division coefficient of a character clock corresponding to the character clock domain according to configuration parameters corresponding to the framing mode; adjusting a first clock frequency of the sampling clock according to the first frequency division coefficient, and adjusting a second clock frequency of the character clock according to the second frequency division coefficient; and transmitting the data in the sampling clock domain to the character clock domain through the data channel according to the adjusted first clock frequency and second clock frequencies.

[0007] In some embodiments of the present application, based on the above technical solution, the configuration parameters corresponding to the framing mode include a multiple of data downsampling, a number of signal sampling times of each signal converter in each frame of data, and a data transmission byte; according to the configuration parameters corresponding to the framing mode, a first frequency division coefficient of the sampling clock corresponding to the sampling clock domain and a second frequency division coefficient of the character clock corresponding to the character clock domain are calculated, including: calculating the first frequency division coefficient of the sampling clock corresponding to the sampling clock domain according to the multiple of the data downsampling; calculating the second frequency division coefficient of the character clock corresponding to the character clock domain according to the number of signal sampling times of each signal converter in each frame of data, the data transmission byte and the first frequency division coefficient.

[0008] In some embodiments of the present application, based on the above technical solution, the first frequency division coefficient of the sampling clock corresponding to the sampling clock domain is calculated according to the multiple of data downsampling, including: determining the numerical value corresponding to the multiple of the data downsampling as the first frequency division coefficient.

[0009] In some embodiments of the present application, based on the above technical solution, the second division coefficient of the character clock corresponding to the character clock domain is calculated according to the signal sampling times, the data transmission bytes and the first division coefficient of each signal converter in each frame of data, including: determining the division coefficient weight value according to the signal sampling times and the data transmission bytes, and determining the second division coefficient according to the first division coefficient and the division coefficient weight value.

[0010] In some embodiments of the present application, based on the above technical solution, the method of determining the division coefficient weight value according to the signal sampling times and the data transmission byte, and determining the second division coefficient according to the first division coefficient and the division coefficient weight value, includes: determining the ratio of the signal sampling times to the data transmission byte as the division coefficient weight value; and determining the second division coefficient according to the product of the first division coefficient and the division coefficient weight value.

[0011] In some embodiments of the present application, based on the above technical solution, the configuration parameters corresponding to the framing mode also include the number of valid conversions in each frame of data, the number of bits sampled each time, and the number of transmission links; before determining the ratio of the signal sampling times to the data transmission bytes as the frequency division coefficient weight value, it also includes: determining the number of first data frames that can be transmitted in one sampling clock cycle in the sampling clock domain according to the valid conversion number, the signal sampling times and the number of bits, and determining the number of second data frames that can be transmitted in one sampling clock cycle in the character clock domain according to the number of transmission links and the data transmission bytes; determining the frequency multiple of the first clock frequency and the second clock frequency according to the first data frame number and the second data frame number, and determining the frequency multiple as the ratio of the signal sampling times to the data transmission bytes.

[0012] In some embodiments of the present application, based on the above technical solution, adjusting the first clock frequency of the sampling clock according to the first frequency division coefficient, and adjusting the second clock frequency of the character clock according to the second frequency division coefficient, includes: obtaining a reference clock input to the data channel; determining the first clock frequency according to the first frequency division coefficient and the reference clock, and determining the second clock frequency according to the second frequency division coefficient and the reference clock.

[0013] In some embodiments of the present application, based on the above technical solution, the data of the sampling clock domain is transmitted to the character clock domain through the data channel according to the adjusted first clock frequency and the second clock frequency, including: according to the adjusted first clock frequency and the second clock frequency, adjusting the data bandwidth of the sampling clock domain to be consistent with the data bandwidth of the character clock domain, and transmitting the data of the sampling clock domain to the character clock domain through the data channel based on the data bandwidth.

[0014] According to another aspect of an embodiment of the present application, an interface circuit based on the JESD204B protocol is provided, including: a parameter configuration module, used to store configuration parameters corresponding to a framing mode; a frequency ratio calculation module, electrically connected to the parameter configuration module, used to calculate a first frequency division coefficient of a sampling clock corresponding to the sampling clock domain, and a second frequency division coefficient of a character clock corresponding to the character clock domain, according to the configuration parameters corresponding to the framing mode; a clock module, electrically connected to the frequency ratio calculation module, used to adjust a first clock frequency of the sampling clock according to the first frequency division coefficient, and to adjust a second clock frequency of the character clock according to the second frequency division coefficient; a data transmission module, electrically connected to the parameter configuration module and the clock module, respectively, used to transmit data from the sampling clock domain to the character clock domain through the data channel according to the adjusted first clock frequency and second clock frequency.

[0015] In some embodiments of the present application, based on the above technical solution, the clock module includes a sampling clock module and a character clock module; the input end of the sampling clock module is electrically connected to the frequency ratio calculation module to input the first frequency division coefficient calculated by the frequency ratio calculation module into the sampling clock module; the input end of the character clock module is electrically connected to the frequency ratio calculation module to input the second frequency division coefficient calculated by the frequency ratio calculation module into the character clock module.

[0016] In the technical solution of the embodiment of the present application, the above invention content can at least bring the following beneficial effects:

[0017] When setting the first clock frequency corresponding to the sampling clock domain and the second clock frequency corresponding to the character clock domain, the framing mode for the data channel configured by the JESD204B protocol can be obtained, and the first division coefficient of the sampling clock corresponding to the sampling clock domain and the second division coefficient of the character clock corresponding to the character clock domain are calculated according to the configuration parameters corresponding to the framing mode, and the corresponding first clock frequency and second clock frequency are obtained based on the adjustment effect of the first division coefficient and the second division coefficient, so that the first clock frequency and the second clock frequency do not need to be manually configured, and the first clock frequency and the second clock frequency comply with the framing mode, thereby avoiding data link transmission problems caused by clock frequency configuration errors during data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0019] Figure 1 The present invention is a flowchart of a data transmission method based on the JESD204B protocol according to an exemplary embodiment of the present invention.

[0020] Figure 2 This is a flowchart of a method for calculating a first frequency division coefficient and a second frequency division coefficient according to an exemplary embodiment of the present application.

[0021] Figure 3 This is a flowchart of a method for calculating a second frequency division coefficient according to an exemplary embodiment of the present application.

[0022] Figure 4 This is a flowchart of a method for determining a first clock frequency and a second clock frequency according to an exemplary embodiment of the present application.

[0023] Figure 5 The present invention is a schematic diagram of a circuit connection relationship of an interface circuit based on the JESD204B protocol, showing an exemplary embodiment of the present application.

[0024] Figure 6 The present invention is a schematic diagram showing the circuit connection relationship of an interface circuit based on the JESD204B protocol according to another exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose and implementation method of the present application clearer, the exemplary implementation method of the present application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of the present application. Obviously, the described exemplary embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0026] It should be noted that the brief description of terms in this application is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their common and usual meanings.

[0027] The terms "first", "second", "third", etc. in the specification and claims of this application and the above drawings are used to distinguish similar or similar objects or entities, and do not necessarily mean to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances.

[0028] The terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0029] It should be noted that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0030] Figure 1 The overall flow chart of a data transmission method based on the JESD204B protocol is shown as an exemplary embodiment of the present application. Figure 1 As shown, the present application provides a data transmission method based on the JESD204B protocol, and the data transmission method at least includes the following execution steps:

[0031] S100, obtaining a framing mode for a data channel configured based on the JESD204B protocol, where the data channel is used to transfer data from a sampling clock domain to a character clock domain;

[0032] S101, calculating a first frequency division coefficient of a sampling clock corresponding to a sampling clock domain and a second frequency division coefficient of a character clock corresponding to a character clock domain according to configuration parameters corresponding to a framing mode;

[0033] S102, adjusting a first clock frequency of the sampling clock according to a first frequency division coefficient, and adjusting a second clock frequency of the character clock according to a second frequency division coefficient;

[0034] S103 . Transmit the data in the sampling clock domain to the character clock domain through a data channel according to the adjusted first clock frequency and second clock frequency.

[0035] It should be noted that in the JESD204B protocol, data is divided into the sampling clock domain (Sample Clock domain) and the character clock domain (Character Clock domain). The sampling data of the ADC (Analog-to-Digital Converter) belongs to the sampling clock domain, and when the data is sent through the PHY (Physical layer), the PHY data belongs to the character clock domain.

[0036] In the design of JESD204B, in the process of transferring the data in the sampling clock domain to the character clock domain according to the protocol, it is necessary to configure the configuration parameters such as M, S, Nb, L, F, and DCM. Among them, M represents the number of valid conversions in each frame of data; S represents the number of signal sampling times of each signal converter in each frame of data; Nb represents the number of bits sampled each time; L represents the number of transmission links; F represents the data transmission bytes; and DCM represents the multiple of data downsampling.

[0037] The above multiple configuration parameters are necessary parameters for transferring data from the sampling clock domain to the character clock domain. At the same time, based on these configuration parameters, the data framing mode of the framing module of the data path can be configured. Under the premise that the framing mode of the data channel is determined, the configuration parameters corresponding to the framing mode can be obtained.

[0038] In the technical solution of the present application, when setting the clock frequency during data transmission, the first division coefficient of the sampling clock corresponding to the sampling clock domain and the second division coefficient of the character clock corresponding to the character clock domain can be calculated according to the configuration parameters corresponding to the framing mode through the calculation method set by the program.

[0039] For example, when DCM=2, that is, the data needs to be downsampled by 2 times, the clock frequency corresponding to the sampling clock should also be divided by two based on the input reference clock, that is, the first division coefficient can be obtained according to the specific value of DCM, that is, the first division coefficient should be the same as the downsampling multiple.

[0040] At the same time, in the chip design corresponding to data transmission, the data bit width of the data channel is determined. Take the data bit width of sampled data as 512 bits (16 bits × 4 × 8, 16 bits is the maximum bit width of single sampled data, 4 is the number of samples of a single converter in one sampling clock cycle, and 8 is the maximum number of converters supported), and the data bit width of character data as 256 bits (32 bits × 8, 32 is the data bit width of a single data transmission link of PHY, and 8 is the maximum number of data transmission links supported by PHY) as an example.

[0041] For example, assume that M=8, S=1, and Nb=16. In the sampling clock domain, Nb=16 means that there are 16 bits in one sampling, S means that each converter has only one sampling in one frame of data, and M=8 means that 8 converters are valid in one frame of data. Since the data bit width is 16×4×8, that is, there will be at most 4 samplings of 8 converters in one sampling clock cycle, and 1 sampling of 8 converters is one frame of data, so in the sampling clock domain, one sampling clock cycle can transmit 4 frames of data, and 1 frame of data is 128 bits.

[0042] Let's take another example to illustrate. Set L=8, F=2. Since the data bit width is 32×8, that is, in the character clock domain, each transmission link will transmit 4 bytes of data in one character clock cycle, and at the same time, there are 8 transmission links to transmit data. L=8, F=2 means that in the character clock domain, 1 frame of data requires 8 transmission links, and 2 bytes must be transmitted to match one frame of data in the character clock domain with one frame of data in the sampling clock domain. Therefore, one character clock cycle can output 2 frames of data.

[0043] It can be seen that when M=8, S=1, Nb=16, L=8, and F=2, one sampling clock cycle can transmit 4 frames of data, 1 frame of data is 128 bits, and one character clock cycle can output 2 frames of data. The clock frequency of the character clock should be twice the clock frequency of the sampling clock to make the bandwidth on both sides consistent.

[0044] Based on the above example, the process of determining the second frequency division coefficient is further described in detail by combining another example, as follows:

[0045] In another example, let's assume that M=2, S=4, and Nb=16. In the sampling clock domain, Nb=16 means that there are 16 bits in one sampling, S=4 means that each converter has 4 samplings in one frame of data, and M=2 means that there are 2 valid converters in one frame of data. Since the data bit width is 16×4×8, and now M=2, it means that in the sampled data, only the data channels of 2 converters out of 8 converters are valid, that is, only 16×4×2 bits of the sampled data are valid bits, so in the sampling clock domain, one sampling clock cycle can transmit 1 frame of data, and 1 frame of data is 128 bits.

[0046] Let's take another example to illustrate. Set L=8, F=2. Since the data bit width is 32×8, that is, in the character clock domain, each transmission link will transmit 4 bytes of data in one character clock cycle, and there are 8 transmission links transmitting data at the same time. L=8, F=2 means that in the character clock domain, 1 frame of data requires 8 transmission links, and 2 bytes must be transmitted to match one frame of data in the character clock domain with one frame of data in the sampling clock domain. Therefore, one character clock cycle can output 2 frames of data.

[0047] It can be seen that when M=2, S=4, Nb=16, L=8, and F=2, one sampling clock cycle can transmit 1 frame of data, 1 frame of data is 128 bits, and one character clock cycle can output 2 frames of data. The clock frequency of the character clock should be 1 / 2 times the clock frequency of the sampling clock to make the bandwidth of both sides consistent.

[0048] When DCM=2, M=8, S=1, Nb=16, L=8, F=2, the first frequency division coefficient = DCM=2, the second frequency division coefficient = 1, that is, the clock frequency corresponding to the sampling clock is generated by dividing the reference clock by two, and the clock frequency of the character clock is the same as the clock frequency of the reference clock, that is, the clock frequency of the character clock is twice the clock frequency of the sampling clock. When DCM=2, M=2, S=4, Nb=16, L=8, F=2, the first frequency division coefficient = DCM=2, the second frequency division coefficient = 4, that is, the clock frequency corresponding to the character clock is generated by dividing the reference clock by two, the clock frequency of the character clock is generated by dividing the reference clock by four, and the clock frequency of the character clock is 1 / 2 times the clock frequency of the sampling clock. It can be seen that the clock calculation results meet the framing requirements of the sampling data and character data.

[0049] Based on this, it can be concluded that the second frequency division coefficient can be obtained by calculating the first frequency division coefficient in combination with the specific values ​​of S and F.

[0050] Then, the first clock frequency of the sampling clock is adjusted according to the first frequency division coefficient, and the second clock frequency of the character clock is adjusted according to the second frequency division coefficient, so as to adjust the data bandwidth of the sampling clock domain and the data bandwidth of the character clock domain when data transmission is performed based on the adjusted first clock frequency and second clock frequency.

[0051] And, according to the adjusted first clock frequency and second clock frequency, the data in the sampling clock domain is transmitted to the character clock domain through the data channel.

[0052] In the above embodiment, when setting the first clock frequency corresponding to the sampling clock domain and the second clock frequency corresponding to the character clock domain, the framing mode for the data channel configured by the JESD204B protocol can be obtained, and the first division coefficient of the sampling clock corresponding to the sampling clock domain and the second division coefficient of the character clock corresponding to the character clock domain are calculated according to the configuration parameters corresponding to the framing mode, and the corresponding first clock frequency and second clock frequency are obtained based on the adjustment effect of the first division coefficient and the second division coefficient, so that the first clock frequency and the second clock frequency do not need to be manually configured, and the first clock frequency and the second clock frequency conform to the framing mode, thereby avoiding data link transmission problems caused by clock frequency configuration errors during data transmission.

[0053] In some embodiments of the present application, based on the above technical solution, Figure 2 This is a flowchart of a method for calculating the first frequency division coefficient and the second frequency division coefficient shown in an exemplary embodiment of the present application. Figure 2 As shown, for the above embodiment, according to the configuration parameters corresponding to the framing mode, the execution steps corresponding to calculating the first frequency division coefficient of the sampling clock corresponding to the sampling clock domain and the second frequency division coefficient of the character clock corresponding to the character clock domain may at least include the following execution steps:

[0054] S200, calculating a first frequency division coefficient of a sampling clock corresponding to a sampling clock domain according to a multiple of data downsampling;

[0055] S201, calculating a second frequency division coefficient of a character clock corresponding to a character clock domain according to the signal sampling times of each signal converter in each frame of data, the data transmission bytes and the first frequency division coefficient.

[0056] In the technical solution of the present application, since the first division coefficient and the second division coefficient respectively represent the division ratio of the clock frequency corresponding to the sampling clock domain and the division ratio of the clock frequency corresponding to the character clock domain, and normal data transmission can be guaranteed when the data bandwidth of the clock frequency corresponding to the sampling clock domain is consistent with the clock frequency corresponding to the character clock domain, the first division coefficient and the second division coefficient have a multiple relationship. Therefore, the present application first calculates the first division coefficient, and then calculates the multiple relationship with the second division coefficient according to the corresponding configuration parameters, so as to combine the multiple relationship with the first division coefficient to generate the second division coefficient.

[0057] Specifically, it can be obtained from the above embodiments that since there is a certain correlation between the multiples of data downsampling and the first division coefficient of the sampling clock corresponding to the sampling clock domain, the present application calculates the first division coefficient by the multiples of data downsampling to realize the automatic generation of the first division coefficient; similarly, since the number of signal sampling times, data transmission bytes and the first division coefficient of each signal converter in each frame of data are related to the second division coefficient of the character clock corresponding to the character clock domain, the multiple relationship between the first division coefficient and the second division coefficient is calculated by the signal sampling times and the data transmission bytes, and then based on the multiple relationship between the first division coefficient and the second division coefficient, the second division coefficient is calculated in combination with the calculated first division coefficient to realize the automatic generation of the second division coefficient.

[0058] In the above embodiment, the first frequency division coefficient is first calculated by the multiple of data downsampling, and then based on the calculated first frequency division coefficient, the signal sampling times and data transmission bytes of each signal converter in each frame of data are calculated to obtain the second frequency division coefficient, instead of directly calculating the multiple of data downsampling with the signal sampling times and data transmission bytes of each signal converter in each frame of data, thereby improving the correlation between the first frequency division coefficient and the second frequency division coefficient and reducing data discrepancies caused by separate calculations.

[0059] In some embodiments of the present application, based on the above technical solution, the execution steps corresponding to obtaining the first frequency division coefficient of the sampling clock corresponding to the sampling clock domain according to the multiple of data downsampling in the above embodiment may at least include:

[0060] A value corresponding to the multiple of the data downsampling is determined as the first frequency division coefficient.

[0061] In the technical solution of the present application, the calculation of the first frequency division coefficient is achieved by determining the numerical value corresponding to the multiple of data downsampling as the first frequency division coefficient.

[0062] This is explained by way of example, and is represented by the following expression in the corresponding program settings:

[0063] sample_clk_div_sel = DCM

[0064] In the above expressions, sample_clk_div_sel represents the first frequency division coefficient; DCM represents the multiple of data downsampling.

[0065] In some embodiments of the present application, based on the above technical solution, for the above embodiment, according to the signal sampling times of each signal converter in each frame of data, the data transmission bytes and the first frequency division coefficient, the execution steps corresponding to calculating the second frequency division coefficient of the character clock corresponding to the character clock domain may at least include:

[0066] The frequency division coefficient weight value is determined according to the signal sampling times and the data transmission byte, and the second frequency division coefficient is determined according to the first frequency division coefficient and the frequency division coefficient weight value.

[0067] In the technical solution of the present application, the weight value of the frequency division coefficient is first determined by the signal sampling times and the data transmission bytes, that is, the specific multiple relationship between the first frequency division coefficient and the second frequency division coefficient; and the second frequency division coefficient is determined according to the weight value of the frequency division coefficient and the first frequency division coefficient.

[0068] Further, in some embodiments of the present application, based on the above technical solution, Figure 3 FIG. 1 is a flowchart of a method for calculating a second frequency division coefficient according to an exemplary embodiment of the present application. Figure 3 As shown, in the above embodiment, the steps of determining the frequency division coefficient weight value according to the signal sampling times and the data transmission bytes, and determining the second frequency division coefficient according to the first frequency division coefficient and the frequency division coefficient weight value may at least include the following steps:

[0069] S300, determining the ratio of the signal sampling times to the data transmission bytes as the frequency division coefficient weight value;

[0070] S301. Determine a second frequency division coefficient according to a product of a first frequency division coefficient and a frequency division coefficient weight value.

[0071] The frequency division coefficient weight value in the above embodiment is determined by the ratio of the signal sampling times to the data transmission bytes, and the second frequency division coefficient is determined by the product of the first frequency division coefficient and the frequency division coefficient weight value.

[0072] This is explained by way of example, and is represented by the following expression in the corresponding program settings:

[0073] character_clk_div_sel = sample_clk_div_sel × S / F

[0074] In the above expression, sample_clk_div_sel represents the first frequency division coefficient; character_clk_div_sel represents the second frequency division coefficient; S represents the number of signal sampling times of each signal converter in each frame of data; and F represents the data transmission byte.

[0075] In some embodiments of the present application, based on the above technical solution, before determining the ratio of the signal sampling times to the data transmission bytes as the frequency division coefficient weight value, at least the following steps may be included:

[0076] Determine the number of first data frames that can be transmitted in one sampling clock cycle in the sampling clock domain according to the number of valid conversions, the number of signal sampling times and the number of bits, and determine the number of second data frames that can be transmitted in one sampling clock cycle in the character clock domain according to the number of transmission links and the data transmission bytes;

[0077] According to the first data frame number and the second data frame number, a frequency multiple of the first clock frequency and the second clock frequency is determined, and the frequency multiple is determined as a ratio of the number of signal sampling times to the data transmission bytes.

[0078] In the above implementation, by determining the first number of data frames that can be transmitted in one sampling clock cycle in the sampling clock domain and the second number of data frames that can be transmitted in one sampling clock cycle in the character clock domain, the frequency multiples of the first clock frequency and the second clock frequency can be determined.

[0079] The frequency multiple of the first clock frequency and the second clock frequency is reflected by the multiple of the first data frame number and the second data frame number. Since the value corresponding to the frequency multiple is the same as the value corresponding to the ratio of the signal sampling times to the data transmission bytes, the frequency multiple can be determined as the ratio of the signal sampling times to the data transmission bytes. Therefore, the present application can express the frequency multiple of the first clock frequency and the second clock frequency by the ratio of the signal sampling times to the data transmission bytes.

[0080] In some embodiments of the present application, based on the above technical solution, Figure 4 FIG. 1 is a flowchart of a method for determining a first clock frequency and a second clock frequency shown in an exemplary embodiment of the present application. Figure 4 As shown in the above embodiment, the step of adjusting the first clock frequency of the sampling clock according to the first frequency division coefficient and adjusting the second clock frequency of the character clock according to the second frequency division coefficient may at least include the following contents:

[0081] S400, obtaining a reference clock input to a data channel;

[0082] S401, determining a first clock frequency according to a first frequency division coefficient and a reference clock, and determining a second clock frequency according to a second frequency division coefficient and the reference clock.

[0083] Specifically, the division multiple corresponding to the first clock frequency is determined according to the first division coefficient. For example, if the first division coefficient is 1 / 2, it indicates that the division multiple corresponding to the first clock frequency is 1 / 2, and the corresponding first clock frequency is 1 / 2 times the reference clock. For another example, if the first division coefficient is 2, it indicates that the division multiple corresponding to the first clock frequency is 2, and the corresponding first clock frequency is twice the reference clock.

[0084] Similarly, the frequency division multiple corresponding to the second clock frequency is determined according to the second frequency division coefficient, which will not be described in detail here.

[0085] Based on this, the present application can calculate the first clock frequency and the second clock frequency respectively according to the input reference clock, the first frequency division coefficient and the second frequency division coefficient.

[0086] In some embodiments of the present application, based on the above technical solution, the step of transmitting the data in the sampling clock domain to the character clock domain through the data channel according to the adjusted first clock frequency and second clock frequency in the above embodiment may at least include the following contents:

[0087] According to the adjusted first clock frequency and second clock frequency, the data bandwidth of the sampling clock domain is adjusted to be consistent with the data bandwidth of the character clock domain, and the data of the sampling clock domain is transmitted to the character clock domain through the data channel based on the data bandwidth.

[0088] Specifically, in actual use of the present application, the data bandwidth of the sampling clock domain and the character clock domain are adjusted according to the adjusted first clock frequency and the second clock frequency, so that the data bandwidth of the sampling clock domain and the data bandwidth of the character clock domain are consistent, thereby reducing the probability of output data transmission errors when the data of the sampling clock domain is transmitted to the character clock domain through the data channel.

[0089] It should be noted that although the various steps of the method in the present application are described in a specific order in the drawings of the above-mentioned various embodiments, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0090] According to another aspect of the embodiment of the present application, Figure 5 The following is a schematic diagram of the circuit connection relationship of an interface circuit based on the JESD204B protocol shown in an exemplary embodiment of the present application. Figure 5 As shown, an interface circuit based on the JESD204B protocol is provided, including: a parameter configuration module, used to store configuration parameters corresponding to a framing mode, the framing mode is configured for a data channel based on the JESD204B protocol, and the data channel is used to transfer data from a sampling clock domain to a character clock domain; a frequency ratio calculation module, electrically connected to the parameter configuration module, used to calculate a first frequency division coefficient of a sampling clock corresponding to the sampling clock domain and a second frequency division coefficient of a character clock corresponding to the character clock domain according to the configuration parameters corresponding to the framing mode; a clock module, electrically connected to the frequency ratio calculation module, used to adjust a first clock frequency of the sampling clock according to the first frequency division coefficient, and to adjust a second clock frequency of the character clock according to the second frequency division coefficient; a data transmission module, electrically connected to the parameter configuration module and the clock module, respectively, used to transfer data from the sampling clock domain to the character clock domain through the data channel according to the adjusted first clock frequency and second clock frequency.

[0091] In the above implementation, compared with the prior art, the first frequency division coefficient of the sampling clock corresponding to the sampling clock domain and the second frequency division coefficient of the character clock corresponding to the character clock domain can be calculated based on the frequency ratio calculation module, so that the clock module can automatically generate the first clock frequency and the second clock frequency directly according to the first frequency division coefficient and the second frequency division coefficient, without the need for staff to configure the clock frequency corresponding to the sampling clock and the clock frequency corresponding to the character clock domain, thereby reducing data anomalies caused by clock frequency configuration errors when staff use the JESD204B protocol.

[0092] Further open the clock module, Figure 6 FIG. 1 is a schematic diagram of a circuit connection relationship of an interface circuit based on the JESD204B protocol, which is another exemplary embodiment of the present application. Figure 6 As shown, the clock module includes a sampling clock module and a character clock module; the input end of the sampling clock module is electrically connected to the frequency ratio calculation module to input the first frequency division coefficient calculated by the frequency ratio calculation module into the sampling clock module; the input end of the character clock module is electrically connected to the frequency ratio calculation module to input the second frequency division coefficient calculated by the frequency ratio calculation module into the character clock module.

[0093] In one example, the present application sets a frequency ratio calculation module to implement sample_clk_div_sel = DCM, character_clk_div_sel = sample_clk_div_sel × S / F, so that the present application can complete the calculation of the corresponding clock division coefficient through the configured DCM, S, F and other parameters, and then give the calculated division coefficient to the corresponding clock module to obtain the corresponding clock frequency that conforms to various framing modes. There is no need to worry about the inconsistency between the framing mode configuration (L, M, S, Nb, F) and the clock frequency configuration, resulting in problems in link establishment.

[0094] Specifically, during use, after obtaining the specific value of DCM, the frequency ratio calculation module calculates the first frequency ratio coefficient according to sample_clk_div_sel = DCM; and after obtaining the specific values ​​of S and F, the second frequency ratio coefficient is calculated according to character_clk_div_sel = sample_clk_div_sel × S / F; after obtaining the first frequency ratio coefficient and the second frequency ratio coefficient, the first frequency ratio coefficient is sent to the sampling clock module, and the second frequency ratio coefficient is sent to the character clock module; the sampling clock module calculates the first clock frequency according to the input reference clock and the first frequency ratio coefficient, and the character clock module calculates the second clock frequency according to the input reference clock and the second frequency ratio coefficient. In this way, the setting of the first clock frequency and the second clock frequency is realized.

[0095] It should be noted that although several modules or units of the interface circuit based on the JESD204B protocol are mentioned in the above detailed description, such division is not mandatory. In fact, according to the embodiment of the present application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units.

[0096] At the same time, in the interface circuit based on the JESD204B protocol, it should be noted that, unless otherwise clearly specified and limited, the terms setting, installing, connecting, and connecting should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal connection of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0098] For the convenience of explanation, the above description has been made in conjunction with specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The selection and description of the above embodiments are to better explain the principles and practical applications, so that those skilled in the art can better use the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A data transmission method based on the JESD204B protocol, characterized in that: include: Obtaining a framing mode for a data channel configured based on the JESD204B protocol, wherein the data channel is used to transfer data in a sampling clock domain to a character clock domain; Calculate a first frequency division coefficient of the sampling clock corresponding to the sampling clock domain according to the data downsampling multiple included in the configuration parameters corresponding to the framing mode; Calculate a second frequency division coefficient of the character clock corresponding to the character clock domain according to the signal sampling times and data transmission bytes of each signal converter in each frame of data included in the configuration parameters corresponding to the framing mode, and the first frequency division coefficient; adjusting a first clock frequency of the sampling clock according to the first frequency division coefficient, and adjusting a second clock frequency of the character clock according to the second frequency division coefficient; The data in the sampling clock domain is transmitted to the character clock domain through the data channel according to the adjusted first clock frequency and second clock frequency.

2. The data transmission method based on the JESD204B protocol according to claim 1, characterized in that: Calculating a first frequency division coefficient of the sampling clock corresponding to the sampling clock domain according to a data downsampling multiple included in the configuration parameters corresponding to the framing mode includes: A value corresponding to the multiple of the data downsampling is determined as the first frequency division coefficient.

3. The data transmission method based on the JESD204B protocol according to claim 1, characterized in that: The calculating the second frequency division coefficient of the character clock corresponding to the character clock domain according to the signal sampling times and data transmission bytes of each signal converter in each frame of data included in the configuration parameters corresponding to the framing mode, and the first frequency division coefficient, comprises: A frequency division coefficient weight value is determined according to the signal sampling times and the data transmission byte, and the second frequency division coefficient is determined according to the first frequency division coefficient and the frequency division coefficient weight value.

4. The data transmission method based on the JESD204B protocol according to claim 3, characterized in that: The step of determining a frequency division coefficient weight value according to the signal sampling times and the data transmission byte, and determining the second frequency division coefficient according to the first frequency division coefficient and the frequency division coefficient weight value comprises: Determine the ratio of the signal sampling times to the data transmission bytes as the frequency division coefficient weight value; The second frequency division coefficient is determined according to the product of the first frequency division coefficient and the frequency division coefficient weight value.

5. The data transmission method based on the JESD204B protocol according to claim 4, characterized in that: The configuration parameters corresponding to the framing mode also include the number of valid conversions in each frame of data, the number of bits sampled each time, and the number of transmission links; before determining the ratio of the number of signal sampling times to the data transmission bytes as the frequency division coefficient weight value, it also includes: Determine the number of first data frames that can be transmitted in one sampling clock cycle in the sampling clock domain according to the valid conversion number, the signal sampling number and the bit number, and determine the number of second data frames that can be transmitted in one sampling clock cycle in the character clock domain according to the transmission link number and the data transmission bytes; A frequency multiple of the first clock frequency and the second clock frequency is determined according to the first data frame number and the second data frame number, and the frequency multiple is determined as a ratio of the signal sampling times to the data transmission bytes.

6. The data transmission method based on the JESD204B protocol according to claim 1, characterized in that: The step of adjusting the first clock frequency of the sampling clock according to the first frequency division coefficient, and adjusting the second clock frequency of the character clock according to the second frequency division coefficient, comprises: Acquire a reference clock input to the data channel; The first clock frequency is determined according to the first frequency division coefficient and the reference clock, and the second clock frequency is determined according to the second frequency division coefficient and the reference clock.

7. The data transmission method based on the JESD204B protocol according to claim 1, characterized in that: The method of transmitting the data in the sampling clock domain to the character clock domain through the data channel according to the adjusted first clock frequency and second clock frequency includes: According to the adjusted first clock frequency and second clock frequency, the data bandwidth of the sampling clock domain is adjusted to be consistent with the data bandwidth of the character clock domain, and the data of the sampling clock domain is transmitted to the character clock domain through the data channel based on the data bandwidth.

8. An interface circuit based on the JESD204B protocol, characterized in that: include: A parameter configuration module, used for storing configuration parameters corresponding to a framing mode, wherein the framing mode is configured for a data channel based on the JESD204B protocol, and the data channel is used for transmitting data from a sampling clock domain to a character clock domain; A frequency ratio calculation module, electrically connected to the parameter configuration module, for calculating a first frequency division coefficient of the sampling clock corresponding to the sampling clock domain according to a multiple of data downsampling included in the configuration parameters corresponding to the framing mode; Calculate a second frequency division coefficient of the character clock corresponding to the character clock domain according to the signal sampling times and data transmission bytes of each signal converter in each frame of data included in the configuration parameters corresponding to the framing mode, and the first frequency division coefficient; a clock module, electrically connected to the frequency ratio calculation module, and configured to adjust a first clock frequency of a sampling clock according to the first frequency division coefficient, and to adjust a second clock frequency of a character clock according to the second frequency division coefficient; The data transmission module is electrically connected to the parameter configuration module and the clock module respectively, and is used to transmit the data in the sampling clock domain to the character clock domain through the data channel according to the adjusted first clock frequency and second clock frequency.

9. The interface circuit based on the JESD204B protocol according to claim 8, characterized in that: The clock module includes a sampling clock module and a character clock module; The input end of the sampling clock module is electrically connected to the frequency ratio calculation module so as to input the first frequency division coefficient calculated by the frequency ratio calculation module into the sampling clock module; An input end of the character clock module is electrically connected to the frequency ratio calculation module so as to input the second frequency division coefficient calculated by the frequency ratio calculation module into the character clock module.

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