Method for verifying digital beam forming chip by using cascade connection of multiple FPGAs (Field Programmable Gate Array)

Abstract

The invention discloses a method for verifying a digital beam forming chip by using cascade connection of multiple FPGAs (Field Programmable Gate Array). The method comprises the following steps: S1, setting and classifying the multiple FPGAs: setting a verification type FPGA and an excitation type FPGA; s2, constructing a verification platform: cascading verification type FPGAs, and connecting excitation type FPGAs to the verification type FPGAs corresponding to the lowest-level wave beams; s3, double cutting and single-chip testing are carried out, wherein first cutting is carried out on the digital beam forming chip; carrying out single-chip testing on the verification type FPGA; cutting the auxiliary logic unit; and S4, verification is carried out, and a result is checked by using a PC terminal. According to the method, the multiple verification type FPGAs are cascaded, and the excitation type FPGA is used for assisting partial verification type PFGA verification, so that verification and resource saving are both considered; and the digital beam forming chip and the partial verification type FPGA are subjected to double cutting, so that the number of required FPGAs is reduced under the condition that the verification effect is not influenced, and the cost is saved.

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