Delay Calculation Algorithm Based on Implicit Circuit Modeling and Model Order Reduction Algorithm

Abstract

The present invention discloses a time delay calculation algorithm based on implicit circuit modeling and model reduction algorithms, including the following steps: Step S1: Traverse the circuit to number the nodes and represent the topological structure with vectors; Step S2: Create an equivalent implicit differential model of the circuit; Step S3: Solve the linear system; Step S4: Perform model reduction through an improved Arnoldi algorithm; Step S5: Calculate the final time delay of the circuit through an iterative algorithm. The present invention discloses a time delay calculation algorithm based on implicit circuit modeling and model reduction algorithms. By optimizing the circuit model, performing reduction processing, calculating eigenvalues, incrementally updating the iterative algorithm results, etc., the efficiency and accuracy of time delay calculation are significantly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of circuit delay calculation, and particularly relates to a delay calculation algorithm based on implicit circuit modeling and model reduction algorithms. Background Art

[0002] Electronic Design Automation (EDA) refers to a collection of dedicated software tools and methods for designing, analyzing, and validating integrated circuits (ICs) and electronic systems. EDA tools cover the entire design process from the initial circuit concept to final manufacturing, including various aspects such as circuit simulation, layout and routing, logic synthesis, and timing analysis. With the continuous progress of semiconductor technology, the complexity and scale of integrated circuits have increased dramatically, and EDA has become an essential tool for chip design and manufacturing. Through automated and efficient algorithms, it enables designers to handle complex chip designs with billions of transistors, improving the design efficiency and accuracy, shortening the product development cycle, and reducing the development cost.

[0003] Static Timing Analysis (STA) is a key method for verifying the timing characteristics of digital circuits. STA evaluates the propagation time of signals from input to output by analyzing all possible paths in the circuit, ensuring that the circuit can operate correctly within a given clock cycle. STA does not rely on specific input vectors but conducts a comprehensive timing check on the circuit, covering the worst-case timing performance. Its main purpose is to ensure that the circuit can meet the timing requirements under various operating conditions (such as temperature, process, voltage variations, etc.) and avoid functional errors caused by timing issues. STA is widely used in various stages of digital IC design, including architecture evaluation in the initial design stage, optimization and adjustment during the design process, and timing verification after the design is completed. It helps designers identify and fix potential timing problems, improving the reliability and performance of the chip.

[0004] Delay calculation calculates the signal propagation time in a circuit and is a key step in ensuring the correctness and efficiency of static timing analysis. Delay calculation is mainly divided into two parts: gate delay and wire delay. Gate delay refers to the time it takes for a signal to pass through a logic gate (such as an inverter, AND gate, or OR gate). It includes the time from the change of the input signal to the stabilization of the output signal. Wire delay refers to the time it takes for a signal to pass through the circuit wiring (interconnects). This includes the transmission time of the signal in the wiring and the delay caused by the resistance and capacitance of the wiring.

[0005] Existing delay calculation methods generally include the following main steps. First, the designer needs to establish a set of differential equations describing the circuit behavior based on the circuit topology and component characteristics. These equations usually reflect the dynamic responses of components such as capacitors, resistors, and inductors. Second, model reduction techniques are used to simplify the high-order system to a low-order system to simplify the calculation. Common methods include time-domain and frequency-domain reduction techniques, such as the Krylov subspace method. However, the model reduction process itself is computationally intensive, and it is necessary to maintain the key dynamic characteristics of the system during the reduction process, increasing the computational complexity. Based on the reduced-order model, the designer needs to calculate the transfer function of the system to describe the relationship between the input signal and the output signal. Solving the eigenvalue problem of the asymmetric matrix when calculating the transfer function is a task with high computational complexity and prone to introducing numerical errors. Finally, in order to obtain the delay of the circuit, the designer uses an iterative algorithm to repeat the above steps to iteratively approximate the theoretical solution and calculate the final delay of the circuit.

[0006] One of the main problems faced by existing delay calculation methods is the huge computational amount. As the circuit scale increases, the matrix scale in the differential equations grows quadratically, and model reduction and eigenvalue calculation are also very complex, resulting in a significant increase in the overall computational amount. The iterative process needs to repeat the above steps, further increasing the computational amount. At the same time, the stability of the calculation is also a challenge. During the model reduction process, if not handled properly, the key characteristics of the system may be lost, resulting in inaccurate results; in the eigenvalue calculation of the asymmetric matrix, numerical instability is easily introduced; in the iterative process, numerical errors may gradually accumulate, leading to an increase in the error of the final result and even causing the collapse of STA calculation.

[0007] Therefore, in view of the above problems, further improvements are made. Summary of the Invention

[0008] The main object of the present invention is to provide a delay calculation algorithm based on implicit circuit modeling and model reduction algorithms. By optimizing methods such as circuit models, reduction processing, eigenvalue calculation, and incrementally updating the results of the iterative algorithm, the efficiency and accuracy of delay calculation are significantly improved.

[0009] To achieve the above object, the present invention provides a delay calculation algorithm based on implicit circuit modeling and model reduction algorithms, including the following steps:

[0010] Step S1: Traverse the node numbers of the circuit and represent the topology with vectors;

[0011] Step S2: Create an equivalent implicit differential model of the circuit;

[0012] Step S3: Solve the linear system;

[0013] Step S4: Model order reduction is performed by the improved Arnoldi algorithm (C-Arnoldi algorithm);

[0014] Step S5: The final delay of the circuit is calculated by an iterative algorithm.

[0015] As a further preferred technical solution of the above technical solution, for step S1, the RC network representation model is used to efficiently represent the RC network of the circuit. The RC network representation model includes a RES vector, a CAPS vector, and an SRCS vector, where:

[0016] The RES vector is used to record all resistor values;

[0017] The CAPS vector is used to record all capacitor values;

[0018] The SRCS vector is used to record the topological structure of the RC network (the SRCS vector is obtained by graph traversal methods, including but not limited to breadth-first search (BFS) and depth-first search (DFS). The values in the SRCS vector are all less than their index values).

[0019] As a further preferred technical solution of the above technical solution, for step S2, implicit expression is performed using small vectors including the RES vector, the CAPS vector, and the SRCS vector. The specific construction method of the equivalent implicit differential model is as follows:

[0020] G = A g · diag(1 / RES) · A g T ;

[0021] C = A c · diag(CAPS) · A c T ;

[0022] where G represents the admittance matrix, C represents the capacitance matrix, A g and A c are the adjacency matrices of resistors and capacitors in the circuit. The diag() function is used to construct a diagonal matrix. Without considering coupling capacitors, A c is the identity matrix. A g is constructed through the SRCS vector, specifically as follows:

[0023] Starting from the identity matrix, for each column of the matrix, the serial number is used as the index value to retrieve in the SRCS vector, and the retrieved number is used as the serial number of the matrix row. And the element of the A g matrix in this column and this row is set to -1. In this way, the A g matrix is guaranteed to be an upper triangular matrix.

[0024] As a further preferred technical solution of the above technical solution, for step S3, the linear system is directly solved through an equivalent implicit differential model and completed within linear time (without matrix factorization of traditional methods, such as LU factorization and QR factorization). The specific implementation is as follows:

[0025] Gx = C·b

[0026] A g y = C·b

[0027] A g T x = RES.*y;

[0028] Utilize the property that the A g matrix is an upper triangular matrix to directly obtain the LU factorization of the G matrix, thereby obtaining an efficient linear system solver, which is specifically divided into two steps;

[0029] First, use the A g matrix to solve the linear system of A g y = C·b to obtain the solution of y. This step takes O(n) time;

[0030] The second step is to solve A g *x = y to obtain the solution of x. This step also takes O(n) time.

[0031] As a further preferred technical solution of the above technical solution, for the algorithm of step S4, this algorithm is based on the norm of a vector with respect to a diagonal matrix C, called the C-norm, and the formula is defined as:

[0032]

[0033] Given matrices G and C, construct an orthogonal basis with respect to the C matrix. The first basis vector is:

[0034]

[0035] Its value is the vector G -1 b, and normalize it with respect to the C-norm. The second and subsequent basis vectors are constructed based on the previous basis vectors. To project the vector G -1 Cq i onto the subspace generated by the previous 1, 2... i basis vectors, and normalize the projection residue as the next basis vector. The formula is:

[0036] v = G -1 Cq i ;

[0037]

[0038] where v is the initial vector for calculating the next basis vector is the projection component on the previous basis vector q j By subtracting the projection component, the obtained vector q i+1 is perpendicular to all previous basis vectors q with respect to matrix C 1 , q 2 , …, q i , and finally it is normalized to obtain the next basis vector. Eventually, all basis vectors generate the Krylov subspace. Under the orthogonal basis with respect to matrix C, the initial G -1 matrix C is transformed into a tridiagonal matrix;

[0039] This is an iterative algorithm and can stop midway. For each iteration of the algorithm, a fast linear solver is used to solve the linear system A*b, and then the orthogonal basis symmetric with respect to matrix C is obtained through the non-orthogonal projection algorithm. These orthogonal bases form the projection matrix Q, and the coordinates under this orthogonal basis form the reduced-order matrix H. The H matrix is a symmetric tridiagonal matrix. Therefore, by calculating the diagonal elements and sub-diagonal elements, the complexity of this algorithm is O(n / k), where k is the system dimension to which it is reduced.

[0040] As a further preferred technical solution of the above technical solution, for step S5, the iterative process needs to repeat the above steps multiple times to approximate the actual delay value. In each iteration process, when the model of the gate circuit is updated, using the characteristics of the improved Arnoldi algorithm (i.e., C-Arnoldi algorithm), there is no need to perform a new model reduction, ensuring that the projection matrix Q remains unchanged, and only the reduced-order matrix H needs to be locally updated;

[0041] Specifically, when the model of the gate circuit is updated and its internal source resistance changes, only the last diagonal element of the reduced-order matrix H needs to be updated as follows:

[0042]

[0043] Where:

[0044] A r : The value of the last diagonal element of matrix A in the case of the original resistance value;

[0045] The updated value of the last diagonal element of matrix A after the resistance value is updated, where u represents update;

[0046] Δr: The change in resistance value (Δr = r new - r old );

[0047] ∑c i : The sum of all capacitance values;

[0048] e1 : Unit vector, the first element of the vector is 1 and the others are 0, e 1 = [1; 0; …];

[0049] e 1 ′ : The transpose of the unit vector, that is, a row vector.

[0050] The beneficial effects of the present invention are as follows:

[0051] 1. More efficient model representation method

[0052] By implicitly constructing a differential equation model corresponding to the circuit, using a vector of size O(n) to replace a matrix of size O(n^2), an efficient circuit model representation method is obtained, which is beneficial to greatly reducing the memory requirement of the algorithm and also solves the problem of memory limitation on parallel hardware (beneficial to GPUs).

[0053] 2. Computation optimization

[0054] First, through the implicit circuit model, the LU matrix is automatically obtained, avoiding LU decomposition with a complexity of O(n^3). Thus, the complexity of the linear system is reduced from O(n^4) to O(n^2). Secondly, the C-Arnoldi algorithm uses a linear solver, and its algorithm complexity is more efficient than the traditional Krylov subspace algorithm. At the same time, its result is a tridiagonal matrix, and the computational amount of its eigenvalues is greatly reduced, from O(n^3) to O(n^2). At the same time, its eigenmatrix does not require additional calculation, further optimizing the performance and memory. In the iterative algorithm, the incremental update only needs to update one element, reducing the algorithm complexity by one dimension.

[0055] 3. Enhanced numerical stability

[0056] The efficient model makes the linear system solver and the C-Arnoldi algorithm more stable, reducing the occurrence of extreme cases. The C-Arnoldi algorithm ensures that the result is a symmetric tridiagonal matrix, greatly improving the stability of subsequent eigenvalue calculations, without the need to handle complex situations such as complex eigenvalues, and ensuring that the system remains stable after order reduction. Description of the drawings

[0057] Figure 1 is a flowchart of the present invention. Detailed implementation manners

[0058] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0059] In the preferred embodiments of the present invention, those skilled in the art should note that the time delay and the like involved in the present invention may be regarded as prior art.

[0060] Preferred embodiments.

[0061] like Figure 1 As shown, the present invention discloses a delay calculation algorithm based on implicit circuit modeling and model reduction algorithm, comprising the following steps:

[0062] Step S1: traverse the numbering of nodes in the circuit and use vectors to represent the topological structure;

[0063] Step S2: creating an equivalent implicit differential model of the circuit;

[0064] Step S3: Solve the linear system (i.e., the HX linear solver in the figure);

[0065] Step S4: Model reduction is performed using an improved Arnoldi algorithm (C-Arnoldi algorithm);

[0066] Step S5: Calculate the final delay of the circuit through an iterative algorithm.

[0067] Specifically, for step S1, the RC network of the circuit is efficiently represented by an RC network representation model, and the RC network representation model includes a RES vector, a CAPS vector and a SRCS vector, wherein:

[0068] The RES vector is used to record all resistance values;

[0069] The CAPS vector is used to record all capacitance values;

[0070] The SRCS vector is used to record the topological structure of the RC network (the SRCS vector is obtained by graph traversal, including but not limited to breadth-based traversal (BFS) and depth-based traversal (DFS), and the value in the SRCS vector must be smaller than its index value).

[0071] More specifically, the voltage response of the circuit can be represented by a set of differential equations, which reflect the relationship between the voltage and current of each node in the circuit in matrix form. The basic equation is:

[0072] Among them, G represents the admittance matrix, C represents the capacitance matrix, V is the node voltage vector, and Vin is the input voltage. The present invention lies in not explicitly constructing large matrices such as G and C, but rather implicitly expressing them using small vectors such as RES, CAPS, and SRCS)

[0073] For step S2, it is implicitly expressed through small vectors including the RES vector, CAPS vector, and SRCS vector. The specific construction method of the equivalent implicit differential model is as follows:

[0074] G = A g ·diag(1 / RES)·A g T ;

[0075] C = A c ·diag(CAPS)·A c T ;

[0076] Among them, G represents the admittance matrix, C represents the capacitance matrix, A g and A c are the adjacency matrices of resistors and capacitors in the circuit. The diag() function is used to construct a diagonal matrix (RES and CAPS are the above vectors, where each element represents the resistance and capacitance values on the circuit nodes, and A g T represents the matrix transpose). Without considering the coupling capacitance, A c is the identity matrix, and A g is constructed through the SRCS vector. Specifically:

[0077] Starting from the identity matrix, for each column of the matrix, use its serial number as the index value to retrieve in the SRCS vector. The retrieved number is used as the serial number of the matrix row, and set the element of the A g matrix in this column and this row to -1. In this way, the A g matrix is guaranteed to be an upper triangular matrix.

[0078] Furthermore, for step S3, (for the linear system Gx = Cb or its variant x = A*b) directly solve the linear system through the equivalent implicit differential model and complete it in linear time (without matrix decomposition of traditional methods such as LU decomposition and QR decomposition). The specific implementation is as follows:

[0079] Gx = C·b

[0080] A g y = C·b

[0081] A g T x = RES.*y;

[0082] Among them, RES.*y is a dot product operation. Both RES and y are vectors. Each element in the vectors is multiplied to obtain a new vector. For example, the first element of RES is multiplied by the first element of y to obtain the first element of the resulting vector, and so on.

[0083] Utilize A g Since the matrix is an upper triangular matrix, directly obtain the LU decomposition of the G matrix, thereby obtaining an efficient linear system solver, which is specifically divided into two steps;

[0084] First, utilize A g Solve the linear system A g y = C·b to obtain the solution of y. This step takes O(n) time;

[0085] In the second step, solve A g *x = y to obtain the solution of x. This step also takes O(n) time.

[0086] Furthermore, for the algorithm in step S4, it improves the traditional Krylov subspace method, the Arnoldi algorithm (instead of constructing an orthonormal basis, it constructs an orthogonal basis with respect to the C matrix. Its advantage is that it does not require the input matrix to be symmetric. For a non-symmetric matrix, it can also ensure that the projected reduced-order matrix is a symmetric tridiagonal matrix). This algorithm is based on the norm of a vector with respect to the diagonal matrix C, called the C-norm, and the formula is defined as:

[0087]

[0088] Given matrices G and C, construct an orthogonal basis with respect to the C matrix. The first basis vector is:

[0089]

[0090] Its value is the vector G -1 b, and normalize it with respect to the C-norm. The second and subsequent basis vectors are constructed based on the previous basis vectors. To project the vector G -1 Cq i onto the subspace generated by the previous 1, 2... i basis vectors, and normalize the projection residue as the next basis vector. The formula is:

[0091] v = G -1 Cq i ;

[0092]

[0093] Among them, v is the initial vector for calculating the next basis vector, is its projection component onto the previous basis vector q j . By subtracting the projection component, the resulting vector qi+1 Regarding the matrix C being perpendicular to all the previous basis vectors q 1 , q 2 , …, q i , and finally normalizing it to obtain the next basis vector. Eventually, all the basis vectors generate the Krylov subspace. Under the orthogonal basis of the C matrix here, the initial G -1 The C matrix is transformed into a tridiagonal matrix; the tridiagonal matrix can be represented by two vectors d and e for the diagonal elements and sub-diagonal elements of the matrix respectively, thus avoiding constructing the complete matrix, saving space, and accelerating the calculation;

[0094] This is an iterative algorithm and can stop midway. For each iteration algorithm, a fast linear solver is used to solve the linear system A*b, and then the orthogonal basis symmetric about the C matrix is obtained through the non-orthogonal projection algorithm. These orthogonal bases form the projection matrix Q, and the coordinates under this orthogonal basis form the reduced-order matrix H. The H matrix is a symmetric tridiagonal matrix, so (only) the diagonal elements and sub-diagonal elements need to be calculated. The complexity of this algorithm is O(n*k), where k is the system dimension to which it is reduced (The C-Arnoldi algorithm can be combined with the Single Matrix Projection method to obtain the reduced-order equivalent system. The poles and residues of the equivalent system are obtained through eigenvalues, and the eigenvalues of the tridiagonal matrix are realized through efficient algorithms such as QR. The C-Arnoldi can be combined with the Double Matrix Projection method, and its applicable range includes double matrix projection methods such as PRIMA, and the result is still a symmetric tridiagonal matrix).

[0095] Preferably, for step S5, the iterative process needs to repeat the above steps (steps S1 - S4) multiple times to approximate the actual delay value. In each iteration process (the traditional method needs to update the model of the gate circuit and re-perform the system reduction), when the model of the gate circuit is updated (in step S2, specifically, the RES vector needs to be updated each time), using the characteristics of the improved Arnoldi algorithm (i.e., the C-Arnoldi algorithm), there is no need to perform a new model reduction, ensuring that the projection matrix Q remains unchanged, and only the reduced-order matrix H needs to be locally updated;

[0096] Specifically, when the gate circuit model is updated and its internal source resistance changes, only the last diagonal element of the reduced-order matrix H needs to be updated as follows:

[0097]

[0098] Where:

[0099] A r: The value of the last diagonal element of matrix A under the original resistance value;

[0100] The updated value of the last diagonal element of matrix A after the resistance value is updated, where u represents update;

[0101] Δr: The change in resistance value (Δr = r new -r old );

[0102] ∑c i : The sum of all capacitance values;

[0103] e 1 : The unit vector, the first element of the vector is 1, and the others are 0, e 1 = [1; 0; …];

[0104] e 1 ′ : The transpose of the unit vector, that is, the row vector.

[0105] For Figure 1 the calculated node waveforms:

[0106] 1. Perform eigenvalue decomposition on matrix A to obtain the transfer function;

[0107] 2. Solve the differential equation in the s domain;

[0108] 3. Obtain the waveform function in the time domain through inverse Laplace transform.

[0109] For the present invention:

[0110] 1. Represent the topological relationship of the RC network through vectors, including:

[0111] Sort and label the RC nodes. The capacitance number on each node is the number of its non - ground node, and the resistance number is the larger number of its two - end nodes. This numbering method can be but is not limited to breadth - first search (BFS) and depth - first search (DFS).

[0112] The smaller number of the two - end nodes of the resistance is stored in the vector SRCS, which is used to represent the topological structure of the RC network.

[0113] Characteristic: The value in SRCS is less than its index value.

[0114] Scope of application: Acyclic RC networks, including single - input multi - output RC networks and multi - input multi - output RC networks.

[0115] 2. Construct the equivalent ODE model of the circuit through three vectors, including:

[0116] Construct the critical matrix of the resistor through SRCS, and this matrix is an upper triangular matrix.

[0117] The method of implicitly constructing the G and C matrices. The G and C matrices will not be generated, reducing memory consumption and improving performance.

[0118] A solver with a linear complexity of O(n) that efficiently solves the linear system Ax = b. This method does not require explicit construction of the matrix and does not require matrix decomposition.

[0119] Features: Do not explicitly construct the system matrix, do not perform matrix decomposition, and have a linear complexity algorithm.

[0120] Scope of application: The ODE model corresponding to the numerical circuit acyclic RC network and the corresponding linear system.

[0121] 3. C-Arnoldi projection method, including:

[0122] Construct an orthogonal basis based on the diagonal matrix C during the projection process. This basis is not a standard orthogonal basis.

[0123] The projection result for any matrix is a tridiagonal matrix.

[0124] The process of solving the tridiagonal matrix, obtaining the eigenvalues, and calculating the poles of the transfer function of the RC network.

[0125] Features: During the projection process, construct an orthogonal basis for a certain matrix, rather than a standard orthogonal basis.

[0126] Scope of application: Projection algorithms for any square matrix, including but not limited to Krylov subspace projection and iterative algorithms.

[0127] 4. C-Arnoldi-based single matrix projection method, including:

[0128] Convert to a single matrix system, perform Krylov model reduction through C-Arnoldi to obtain a smaller system, and solve the poles and residues of the transfer function.

[0129] Instead of solving the final poles and residues, solve the absolute values of the poles, as well as the ratios of the residues to the absolute values of the poles. A method for solving the waveform function without the need for the final values of the poles and residues.

[0130] Incremental update method. When the resistance values of adjacent inputs change, a new reduced-order model of the system can be obtained by modifying the last value in the matrix. Applied to the STA iterative algorithm, a performance improvement of more than 4 times can be obtained.

[0131] Feature: Apply the C-Arnoldi algorithm in the single matrix projection method. Instead of recalculating the model reduction in the STA iteration, incremental modification is performed.

[0132] Scope of application: The single matrix projection method is used for system reduction, including but not limited to the reduction of circuit systems.

[0133] 5. The double matrix projection method based on C-Arnoldi includes:

[0134] The process of reducing the order of matrices G and C respectively by C-Arnoldi and then solving the transfer function.

[0135] Incremental update method: When the input adjacent resistance values change, there is no need to recalculate the reduced-order matrices G and C. Only the last diagonal value of G^-1C needs to be recalculated to obtain the reduced-order model of the new system.

[0136] Feature: Adopt the C-Arnoldi projection method in the double matrix projection method (such as PRIMA).

[0137] Scope of application: The PRIMA method is used for system reduction.

[0138] It is worth mentioning that the technical features such as time delay involved in this invention patent application should be regarded as the prior art. For the specific structures, working principles, possible control methods, and spatial layout methods of these technical features, conventional selections in the art can be adopted and should not be regarded as the inventive points of this invention patent. This invention patent will not be further specifically elaborated.

[0139] For those skilled in the art, the technical solutions recorded in the foregoing embodiments can still be modified, or some of the technical features can be equivalently replaced. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this invention shall be included in the protection scope of this invention.

Claims

1. A delay calculation algorithm based on implicit circuit modeling and model order reduction algorithm, characterized in that: The following steps are involved: Step S1: traverse the numbering of nodes in the circuit and use vectors to represent the topological structure; For step S1, the RC network of the circuit is efficiently represented by an RC network representation model, and the RC network representation model includes a RES vector, a CAPS vector, and a SRCS vector, wherein: The RES vector is used to record all resistance values; The CAPS vector is used to record all capacitance values; The SRCS vector is used to record the topology of the RC network; Step S2: creating an equivalent implicit differential model of the circuit; For step S2, implicit expression is performed through a small vector including RES vector, CAPS vector and SRCS vector. The specific construction method of the equivalent implicit differential model is as follows: G=A g ·diag(1 / RES)·A g T ; C=A c ·diag(CAPS)·A c T ; Among them, G represents the admittance matrix, C represents the capacitance matrix, and A g and A c is the adjacency matrix of resistors and capacitors in the circuit. The diag() function is used to construct a diagonal matrix. Without considering the coupling capacitor, A c That is, the identity matrix, A g It is constructed through SRCS vector, specifically: Starting from the identity matrix, for each column of the matrix, use its serial number as the index value to search in the SRCS vector, and use the search number as the serial number of the matrix row, and replace A g The matrix element in this column and row is set to -1, so that A g The matrix is ​​guaranteed to be upper triangular; Step S3: solving the linear system; Step S4: Model reduction is performed using the improved Arnoldi algorithm; For step S3, the linear system is solved directly through the equivalent implicit differential model and completed in linear time without LU decomposition. The specific implementation is: Gx=C·b A g y=C·b TO g T x=RES.*y; Using A g The matrix is ​​an upper triangular matrix, and the LU decomposition of the G matrix is ​​directly obtained, thereby obtaining an efficient linear system solver, which is divided into two steps; First, use A g Matrix Solution A g y = C·b This linear system is used to obtain the solution of y. The time complexity of this step is O(n); The second step is to solve A g *x=y, thus obtaining the solution of x. The time complexity of this step is also O(n); Step S5: Calculate the final delay of the circuit through an iterative algorithm.

2. The delay calculation algorithm based on implicit circuit modeling and model reduction algorithm according to claim 1, characterized in that: The algorithm of step S4 is an improvement on the traditional Krylov subspace method Arnoldi algorithm. The algorithm is based on the normal form of the vector about the diagonal matrix C, called C-normal form, and the formula is defined as: Given matrices G and C, construct an orthogonal basis about the C matrix. The first basis vector is: Its value is vector G -1 b, and normalize it to C-normal form. The second and subsequent basis vectors are constructed based on the previous basis vectors. -1 C i Project to the subspace generated by the first 1, 2…i basis vectors, and normalize the projection residual as the next basis vector. The formula is: v=G -1 Cq i ; Among them, v is the initial vector for calculating the next basis vector, is its preceding basis vector q j The projection component on the vector q is obtained by subtracting the projection component. i+1 The matrix C is perpendicular to all the basis vectors q1, q2, ..., q i , and finally normalize it to get the next basis vector. Finally, all basis vectors generate Krvlov subspace. Under this orthogonal basis about C matrix, the initial G -1 The C matrix is ​​transformed into a tridiagonal matrix; The algorithm of step S4 is an iterative algorithm and can be stopped midway. For each iterative algorithm, a fast linear solver is used to solve the linear system A*b, and then an orthogonal basis symmetric about the C matrix is ​​obtained through a non-orthogonal projection algorithm. These orthogonal bases constitute the projection matrix Q, and the coordinates under the orthogonal basis constitute the reduced-order matrix H. The H matrix is ​​a symmetric tridiagonal matrix, so the diagonal elements and sub-diagonal elements are calculated. The complexity of the iterative algorithm is O(n*k), where k is the system dimension to be reduced.

3. The delay calculation algorithm based on implicit circuit modeling and model reduction algorithm according to claim 2, characterized in that: For step S5, the iteration process needs to repeat the above steps multiple times to approximate the actual delay value. In each iteration process, when the gate circuit model is updated, the characteristics of the improved Arnoldi algorithm are used, and there is no need to perform a completely new model reduction to ensure that the projection matrix Q does not change. Only the reduced-order matrix H needs to be locally updated; Specifically, when the gate circuit model is updated and its internal source resistance changes, only the last diagonal element of the reduced-order matrix H needs to be updated as follows: in: A r : The value of the last diagonal element of matrix A under the original resistance value; The updated value of the last diagonal element of the A matrix after the resistance value is updated, u represents the update; Δ r : Change in resistance value; ∑c i : The sum of all capacitance values; e1: unit vector, the first element of the vector is 1, and the others are 0, e1 = [1; 0; ...]; e1 ′ : The transpose of a unit vector, or row vector.

Images