Digital integrated circuit optimization method and system based on GVAE and AIG

Abstract

The invention discloses a digital integrated circuit optimization method and system based on GVAE and AIG, and belongs to the technical field of integrated circuit design automation. According to the method, key features and deep modes of a circuit can be intelligently learned and extracted by using a graph variational automatic encoder GVAE, the dependence of a traditional method on manual feature design is broken through, and the insight and understanding of a reinforcement learning agent on a circuit structure are enhanced; the state of the circuit is effectively coded into an input vector with a fixed length, so that the operation efficiency and the overall performance of a reinforcement learning algorithm are improved, and rapid convergence is realized in a complex optimization task; a highly-integrated full-flow circuit optimization framework is provided, an automatic and efficient closed-loop system is constructed from the structure of a circuit netlist through multiple steps of structural feature extraction, intelligent optimization and the like, and the quality and productivity of circuit optimization are improved.

Description

Technical Field

[0001] The invention relates to a digital integrated circuit optimization method and system based on GVAE and AIG graph, belonging to the technical field of integrated circuit design automation. Background Art

[0002] The And-Inverter Graph (AIG) is a Boolean network composed of AND gates and NOT gates. It is a directed acyclic graph that can effectively describe and operate large-scale Boolean functions. In the process of digital integrated circuit design, especially in the process of logic synthesis and logic optimization, the AIG structure plays a vital role. Compared with other logical expressions, such as Boolean functions or Karnaugh maps, the AIG structure has a very compact representation form, which can more effectively describe complex logic circuits, making the logic synthesis and optimization process more efficient. The combination of AND gates and inverters enables the AIG structure to intuitively represent logical operations, facilitate various optimization operations, and support operations such as logic decomposition, reconstruction and simplification, helping to optimize the performance and efficiency of the circuit. In addition, the AIG structure is a common representation for verification tasks such as satisfiability analysis (SAT) and model checking. Its structural normalization enables the SAT solver to process the structure of the graph more effectively, which helps to find design errors and logic problems in the circuit. The AIG structure has good support for the representation and design of asynchronous circuits and can clearly capture the timing characteristics of asynchronous circuits. Therefore, in the process of logic optimization, the AIG structure has become an indispensable part of digital integrated circuit design.

[0003] Traditional tools usually use a series of combined steps to optimize AIG structures, such as logic rewrite, logic replacement, logic refactoring, and logic balance. Rewrite iteratively selects an AIG subgraph on a node, pre-calculates all its results and saves the subgraph, and replaces the current subgraph with a subgraph with better performance, so as to minimize the number of nodes. Resub tries to find similar subcircuits that can be reused, extracts these structures and reuses the subcircuits where needed. Refactor reorganizes and optimizes the AIG structure, including adjusting the hierarchical structure and optimizing the logic path. Balance balances the load and delay of different logic paths to ensure that the load balance and timing constraints of the circuit are met. For a high-level description input, it is usually necessary to repeatedly call the above optimization methods to form a set of optimization command sequences to gradually optimize the netlist to meet the design requirements. At the same time, after each optimization step, the results need to be verified and evaluated to check whether new errors or problems are introduced.

[0004] As the scale of circuit design becomes larger and the logic becomes more complex, the solution space of the above-mentioned optimization command sequence is huge. It is time-consuming and labor-intensive to explore it based on human experience, and the design space explored manually has certain limitations. Because each combination of command sequences may lead to different circuit structures and performances, this combinatorial optimization problem is essentially a dynamic programming problem, and reinforcement learning, as an important artificial intelligence technology, has excellent performance in solving dynamic programming problems. Reinforcement learning algorithms usually include three core components: agents, environments, and rewards. The main goal is for agents to learn how to make decisions through interaction with the environment to maximize the expected cumulative rewards. In the above process of selecting optimization commands, the structure of the current circuit can be defined as the state, the new optimization command can be defined as the action of the agent, and the reward function can be reasonably defined based on the optimization results. The agent selects a new command based on the current state of the circuit, then interacts with the environment, executes the selected command and observes the feedback from the environment. Based on the feedback from the environment, the agent will receive a reward to evaluate whether the selected command optimizes the circuit design. The agent adjusts its strategy based on the reward signal so that the commands selected in the future are more inclined to optimize the circuit design. By continuously interacting and learning with the environment, the reinforcement learning algorithm can gradually learn the optimal command sequence combination, thereby achieving automated optimization of circuit design.

[0005] However, there are some urgent problems to be solved in using AIG structure to represent the state of reinforcement learning. One of the main problems is that the size of AIG depends on the structure and complexity of the circuit. Different circuits may produce AIG structures of different sizes. However, reinforcement learning algorithms usually require fixed-length input vectors as state representations. Therefore, how to map the dynamically sized AIG graph to a fixed-length state vector is a challenge. In addition, in the process of mapping AIG to a fixed-length state vector through some traditional methods, the overly simplified state representation leads to insufficient understanding of the circuit structure by the algorithm, resulting in information loss and fuzzification, which reduces the reinforcement learning algorithm's ability to understand and express the circuit structure; the overly complex state representation affects the learning speed and generalization ability of the algorithm. Summary of the invention

[0006] In order to improve the design and optimization efficiency of complex circuit structures and improve the quality of circuit design, the present invention provides a digital integrated circuit optimization method and system based on Graph Variational Auto-Encoder (GVAE) and AIG graph. The technical solution is as follows:

[0007] The digital integrated circuit optimization method of the present invention comprises:

[0008] Step 1: Obtain a circuit netlist structure from the digital integrated circuit to be optimized;

[0009] Step 2: converting the circuit netlist structure into a directed acyclic graph represented by an AIG structure;

[0010] Step 3: extract the topological connection relationship between nodes from the AIG structure to form an adjacency matrix; use the timing and power analysis tools to analyze each circuit, extract the timing and physical information of each gate unit, form an initial feature vector, and concatenate the initial feature vectors of all gates to obtain a feature matrix;

[0011] Step 4: Encode the adjacency matrix and the feature matrix using a graph variational autoencoder GVAE to obtain a state vector of the digital integrated circuit to be optimized;

[0012] Step 5: input the state vector into the reinforcement learning agent, and the reinforcement learning agent selects the optimization command to be executed next according to the current circuit state;

[0013] Step 6: Execute the optimization command to obtain the AIG structure of the optimized circuit netlist;

[0014] Step 7: Repeat steps 3 to 6 until the optimized circuit performance meets the design requirements, and the optimization is completed.

[0015] Optionally, the training process of the reinforcement learning agent includes:

[0016] Step 51: Calculate the current state vector s using the differentiable strategy function π(a|s,θ) to obtain the probability distribution of each optimization command a under the current state;

[0017] Step 52: According to the probability distribution obtained in step 51, randomly sample an optimization command and execute it in a logic synthesis environment to obtain an optimized AIG structure, and evaluate the optimization result based on the area parameter and the delay parameter to calculate the reward value;

[0018] Step 53: After a round of optimization sequence is completed, the rewards of the entire sequence are accumulated according to the discount factor γ:

[0019]

[0020] Among them, T represents the total number of steps in this round of optimization sequence, t represents the current time step, k represents each time step from the current time step t to the end of the round, and R k Represents the immediate reward obtained at the kth time step;

[0021] Step 54: Update the parameters θ of the policy function and the parameters ω of the value function;

[0022] First, calculate the error δ, which is the difference between the accumulated reward and the current state value:

[0023] δ=Gv(S t ,ω)

[0024] Then use the Adam optimization algorithm to update the parameters:

[0025]

[0026]

[0027] Among them, v(s,ω) is the value function, which is used to estimate the expected reward value in each state and serves as a baseline to reduce the variance of the algorithm;

[0028] Step 55: Repeat steps 51 to 54 until the maximum number of iterations is met or the value of the loss function converges to a stable range.

[0029] Optionally, the training process of the graph variational autoencoder GVAE includes:

[0030] Step 41: The adjacency matrix A and the feature matrix X of the AIG structure to be optimized are input into the encoder, and processed through a multi-layer graph convolutional network to obtain the distribution parameters μ and σ of the latent space, and after re-parameterization, a low-dimensional state vector representation Z is generated:

[0031] Z=f encoder (A,X)

[0032] where Z∈R n×k is the output of the encoder, representing the k-dimensional latent vector, and n represents the number of nodes in the circuit;

[0033] Step 42: Input the low-dimensional vector representation Z into the decoder, and generate a reconstructed adjacency matrix through the deconvolution network. and the feature matrix

[0034]

[0035] Step 43: Define the loss function L:

[0036] L=L recon +βL KL

[0037] Among them, L recon represents the reconstruction loss, L KL represents the Kullback-Leibler (KL) divergence, and β is a hyperparameter used to balance the reconstruction loss and KL divergence;

[0038] Step 44: Using the back propagation algorithm, the parameters of the encoder and decoder are updated by gradient descent according to the loss function L:

[0039]

[0040] Among them, θ is the parameter of the encoder and decoder, α is the learning rate, is the gradient of the loss function with respect to the model parameters;

[0041] Step 45: Repeat steps 41 to 44, and perform training iterations until the loss function tends to stabilize or reaches a preset number of training rounds.

[0042] The optimization commands include: logic rewrite Rewrite, logic replacement Resub, logic reconstruction Refactor, logic balance Balance, and zero-cost rewrite Rewrite-z.

[0043] The present invention provides a digital integrated circuit optimization system, comprising: a logic optimization environment, an AIG structure conversion module, a feature extraction module, a graph variational autoencoder, a reinforcement learning agent, a command execution module and an optimization evaluation module;

[0044] The logic optimization environment is used to convert the digital integrated circuit to be optimized into a circuit netlist structure;

[0045] The AIG structure conversion module is used to convert the circuit netlist structure into a directed acyclic graph represented by the AIG structure;

[0046] The feature extraction module extracts the topological connection relationship between nodes from the AIG structure to form an adjacency matrix; uses a timing and power analysis tool to analyze each circuit, extracts the timing and physical information of each gate unit, and forms an initial feature vector. The initial feature vectors of all gates are concatenated to obtain a feature matrix;

[0047] The graph variational autoencoder is used to encode the adjacency matrix and the feature matrix to obtain the state vector of the digital integrated circuit to be optimized;

[0048] The reinforcement learning agent selects an optimization command to be executed next based on the input state vector;

[0049] The command execution module is used to execute the optimization command to be executed in the next step;

[0050] The optimization evaluation module is used to evaluate the optimization results.

[0051] Optionally, the training process of the reinforcement learning agent includes:

[0052] Step 51: Calculate the current state vector s using the differentiable strategy function π(a|s,θ) to obtain the probability distribution of each optimization command a under the current state;

[0053] Step 52: According to the probability distribution obtained in step 51, randomly sample an optimization command and execute it in a logic synthesis environment to obtain an optimized AIG structure, and evaluate the optimization result based on the area parameter and the delay parameter to calculate the reward value;

[0054] Step 53: After a round of optimization sequence is completed, the rewards of the entire sequence are accumulated according to the discount factor γ:

[0055]

[0056] Among them, T represents the total number of steps in this round of optimization sequence, t represents the current time step, k represents each time step from the current time step t to the end of the round, and R k Represents the immediate reward obtained at the kth time step;

[0057] Step 54: Update the parameters θ of the policy function and the parameters ω of the value function;

[0058] First, calculate the error δ, which is the difference between the accumulated reward and the current state value:

[0059] δ=Gv(S t ,ω)

[0060] Then use the Adam optimization algorithm to update the parameters:

[0061]

[0062]

[0063] Among them, v(s,ω) is the value function, which is used to estimate the expected reward value in each state and serves as a baseline to reduce the variance of the algorithm;

[0064] Step 55: Repeat steps 51 to 54 until the maximum number of iterations is met or the value of the loss function converges to a stable range.

[0065] Optionally, the training process of the graph variational autoencoder includes:

[0066] Step 41: The adjacency matrix A and the feature matrix X of the AIG structure to be optimized are input into the encoder, and processed through a multi-layer graph convolutional network to obtain the distribution parameters μ and σ of the latent space, and after re-parameterization, a low-dimensional state vector representation Z is generated:

[0067] Z=f encoder (A,X)

[0068] where Z∈R n×k is the output of the encoder, representing the k-dimensional latent vector, and n represents the number of nodes in the circuit;

[0069] Step 42: Input the low-dimensional vector representation Z into the decoder, and generate a reconstructed adjacency matrix through the deconvolution network. and the feature matrix

[0070]

[0071] Step 43: Define the loss function L:

[0072] L=L recon +βL KL

[0073] Among them, L recon represents the reconstruction loss, L KL represents KL divergence, β is a hyperparameter used to balance reconstruction loss and KL divergence;

[0074] Step 44: Using the back propagation algorithm, the parameters of the encoder and decoder are updated by gradient descent according to the loss function L:

[0075]

[0076] Among them, θ is the parameter of the encoder and decoder, α is the learning rate, is the gradient of the loss function with respect to the model parameters;

[0077] Step 45: Repeat steps 41 to 44, and perform training iterations until the loss function tends to stabilize or reaches a preset number of training rounds.

[0078] Optionally, the discount factor γ=0.9.

[0079] The present invention provides an integrated circuit optimization device, comprising a memory and a processor;

[0080] The memory is used to store computer programs;

[0081] The processor is used to implement the digital integrated circuit optimization method as described in any one of the above items when executing the computer program.

[0082] The present invention provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the digital integrated circuit optimization method as described in any one of the above items is implemented.

[0083] The beneficial effects of the present invention are:

[0084] According to the method of the present invention, the graph variational autoencoder GVAE is used to intelligently learn and extract the key features and deep patterns of the circuit, breaking through the traditional method's reliance on manual feature design, and helping to enhance the reinforcement learning agent's insight and understanding of the circuit structure; effectively encoding the circuit state as an input vector of fixed length helps to improve the operating efficiency and overall performance of the reinforcement learning algorithm, and quickly converge in complex optimization tasks; a highly integrated full-process circuit optimization framework is provided, starting from the structure of the circuit netlist, through multiple steps such as structural feature extraction and intelligent optimization, an automated and efficient closed-loop system is constructed, which improves the quality and productivity of circuit optimization. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0086] Figure 1 Schematic diagram of the state representation framework of the graph variational autoencoder GVAE used for reinforcement learning in the first embodiment of the present invention.

[0087] Figure 2 This is an operation flow chart of the graph variational autoencoder GVAE model in embodiment 1 of the present invention.

[0088] Figure 3 This is a diagram describing the process of optimizing a circuit using a reinforcement learning algorithm in Embodiment 1 of the present invention.

[0089] Figure 4 This is a partial architecture diagram of the reinforcement learning agent training process in Example 1 of the present invention. DETAILED DESCRIPTION

[0090] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0091] Embodiment 1:

[0092] This embodiment provides a digital integrated circuit optimization method based on graph variational autoencoder GVAE and reinforcement learning, see Figure 1 and Figure 2 , the method comprising:

[0093] Step 1: Obtain the circuit netlist structure from the digital integrated circuit to be optimized, including the circuit's logic elements, connection relationships, and timing information.

[0094] Step 2: Convert the circuit netlist structure into a directed acyclic graph represented by an AIG structure; the nodes in the AIG structure represent logic gates, and the edges represent the connection relationship between the gates. This representation method can more effectively describe the logical structure of the circuit.

[0095] Step 3: Extract the topological connection relationship between nodes from the AIG structure to form an adjacency matrix; use timing and power analysis tools to analyze each circuit, extract the timing and physical information of each gate unit, form an initial feature vector, and concatenate the initial feature vectors of all gates to obtain a feature matrix.

[0096] Step 4: Use the graph variational autoencoder GVAE to encode the adjacency matrix and the feature matrix to obtain the state vector of the digital integrated circuit to be optimized.

[0097] By training the GVAE model, the key features and patterns in the AIG structure can be automatically learned and mapped to low-dimensional vector representations in the latent space. These latent space vectors, as state vector representations of the circuit, encode important features and structural information of the circuit and can effectively represent the circuit state as a fixed-length input vector.

[0098] Step 5: Input the state vector into the reinforcement learning agent, which selects the next optimization command to be executed based on the current circuit state.

[0099] Reinforcement learning algorithms such as Monte Carlo policy gradient with baseline can be used. The agent selects the next optimization command to be executed based on the current circuit state, interacts with the environment to execute the selected command, and obtains the reward value based on the feedback from the environment. The goal of reinforcement learning is to maximize the total reward value. The agent selects the best next optimization command through training.

[0100] Step 6: Execute the optimization command in the logic optimization tool to obtain the optimized circuit netlist structure. Obtain the optimized circuit performance report through the timing and area analysis tools to evaluate the optimization effect.

[0101] Step 7: Repeat steps 3 to 6 to continuously optimize the circuit until the performance of the optimized circuit meets the design requirements, and the optimization is completed.

[0102] The structure of the graph variational autoencoder GVAE is as follows Figure 2As shown in the figure, it includes three main parts: encoder, decoder, and loss function; the input of the encoder is the adjacency matrix and feature matrix of the circuit, and the output is the low-dimensional vector representation of the potential space of the AIG structure; the input of the decoder is the potential low-dimensional vector representation of the encoder output, and the output is the reconstructed adjacency matrix and feature matrix; the loss function is used to measure the difference between the reconstructed matrix output by the decoder and the original input matrix.

[0103] The training steps of the architecture of the graph variational autoencoder GVAE in this embodiment are as follows:

[0104] S1: Extract the AIG structure from the circuit netlist to be optimized and generate the corresponding adjacency matrix A and feature matrix X. Where A∈R n×n represents the connection relationship between n nodes in the circuit, and X∈R n×d Represents the feature of each node, and d is the dimension of the feature.

[0105] S2: The adjacency matrix A and the feature matrix X are input into the encoder and processed through a multi-layer graph convolutional network (GCN) to obtain the distribution parameters μ and σ of the latent space, and then re-parameterized to generate a low-dimensional state vector representation Z:

[0106] Z=f encoder (A,X)

[0107] where Z∈R n×k is the output of the encoder, representing the k-dimensional latent vector.

[0108] S3: Input the latent vector Z output by the encoder into the decoder, and generate a reconstructed adjacency matrix through the deconvolution network and the feature matrix

[0109]

[0110] S4: Define the loss function L, including the reconstruction loss L recon and the Kullback-Leibler (KL) divergence L KL :

[0111] L=L recon +βL KL

[0112] Among them, the reconstruction loss L recon The reconstruction matrix used to measure the decoder output and The difference between the original input matrices A and X is:

[0113]

[0114] KL divergence L KL Used to regularize the distribution of the latent vector Z to make it close to the standard normal distribution N(0,1):

[0115] L KL =D KL (q(Z|X,A)||p(Z))

[0116] Among them, β is a hyperparameter used to balance the reconstruction loss and KL divergence.

[0117] S5: Using the back propagation algorithm, the parameters θ of the encoder and decoder are updated by gradient descent according to the loss function L:

[0118]

[0119] Among them, θ is the parameter of the encoder and decoder, α is the learning rate, is the gradient of the loss function with respect to the model parameters.

[0120] S6: Repeat steps S1 to S5, use all AIG graphs in the training set for training in each iteration to ensure the generalization ability of the model, update the model parameters after each iteration to improve the representation ability of the model.

[0121] S7: The training is iterated until the loss function becomes stable, or the training is completed after reaching the preset number of training rounds, and the model is saved for use in the subsequent circuit optimization process.

[0122] This embodiment uses the Monte Carlo policy gradient algorithm with a baseline to perform reinforcement learning training on the circuit optimization process, combined with GVAE for state representation and command selection. The Monte Carlo policy gradient algorithm with a baseline is a reinforcement learning algorithm based on policy gradients. At the end of each round, the rewards for the entire round are accumulated and used to update the policy. The training architecture diagram of the reinforcement learning agent in this embodiment is shown in Figure 1. Figure 4 As shown in Figure 1, the state vector encoded by GVAE is used as the input of the policy network and the value network to obtain the policy function π(a|s,θ) and the value function v(s,ω), respectively.

[0123] The steps of selecting a command sequence by the reinforcement learning algorithm of this embodiment are as follows:

[0124] S1: Select the circuit netlist structure to be optimized, convert it into an AIG structure, extract it into an adjacency matrix and a feature matrix, and then input it into the GVAE model for encoding to obtain the state vector s of the circuit to be optimized.

[0125] S2: The reinforcement learning agent uses a differentiable policy function π(a|s,θ), whose input is the current state vector s and output is the probability distribution of each optimized command a in the current state. This probability distribution is calculated by the softmax function.

[0126] S3: According to the probability distribution of π(a|s,θ), an optimization command is randomly sampled and executed in the logic synthesis environment. After execution, the environment returns the new AIG state and the evaluation results such as area and delay.

[0127] S4: After each round of optimization command execution, the reward value is calculated based on the changes in area and latency. Positive optimization (such as area reduction or latency reduction) will receive positive rewards, and negative optimization will receive negative rewards.

[0128] S5: After a round of optimization sequence is completed, the rewards of the entire sequence are accumulated according to the discount factor γ:

[0129]

[0130] Among them, γ is the discount factor, which represents the weight of future rewards. In the experiment, it is set to γ ​​= 0.9, T represents the total number of steps in this round of optimization sequence, t represents the current time step, k represents each time step from the current time step t to the end of the round, and R k Represents the immediate reward obtained at the kth time step.

[0131] S6: Update the parameters θ of the policy function and ω of the value function. First, calculate the error δ, which is the difference between the accumulated reward and the current state value:

[0132] δ=Gv(S t ,ω)

[0133] Then use the Adam optimization algorithm to update the parameters:

[0134]

[0135]

[0136] Where v(s,ω) is the value function, which is used to estimate the expected reward value in each state and serves as the baseline to reduce the variance of the algorithm. t represents the state at the current time step, t represents the current time step, A t Indicates the action taken in the current state;

[0137] S7: The training process of reinforcement learning is completed through multiple iterations. The criterion for the completion of iterations is the convergence of the algorithm, which includes one of the following two situations:

[0138] When the parameters θ of the policy network are updated, the value of the loss function converges to a stable range, that is, the loss change amplitude is less than the set threshold in multiple consecutive iterations;

[0139] Or when the preset maximum number of iterations N is reached, N is set to 200 in the experiment.

[0140] Each round of iteration generates a complete command sequence and adjusts the strategy based on the optimization effect. A variety of standard logic synthesis benchmark circuits are used in training, such as ISCAS'85 and MCNC circuits. The agent continuously adjusts the command selection strategy in each round by interacting with the environment, such as Figure 3 As shown, the global optimal logic optimization effect can be achieved.

[0141] The digital integrated circuit optimization method of this embodiment uses the graph variational autoencoder GVAE to intelligently learn and extract the key features and deep patterns of the circuit, breaking through the traditional method's reliance on manual feature design, and helping to enhance the reinforcement learning agent's insight and understanding of the circuit structure; effectively encoding the circuit state as an input vector of fixed length helps to improve the operating efficiency and overall performance of the reinforcement learning algorithm, and quickly converge in complex optimization tasks; provides a highly integrated full-process circuit optimization framework, starting from the structure of the circuit netlist, through multiple steps such as structural feature extraction and intelligent optimization, to build an automated and efficient closed-loop system, thereby improving the quality and productivity of circuit optimization.

[0142] Embodiment 2

[0143] This embodiment provides a digital integrated circuit optimization system based on graph variational autoencoder GVAE and reinforcement learning, including: a logic optimization environment, an AIG structure conversion module, a feature extraction module, a graph variational autoencoder GVAE, a reinforcement learning agent, a command execution module and an optimization evaluation module;

[0144] The logic optimization environment can receive input from a hardware description language (such as Verilog) and synthesize it into a circuit netlist structure. The environment is mainly composed of open source logic synthesis tools Yosys and ABC, which can parse and synthesize the input hardware description file to generate a standard logic netlist structure. The logic netlist structure includes logic elements, connection relationships and timing information, providing basic data for subsequent graph processing.

[0145] The AIG structure conversion module is used to convert the circuit netlist structure into a directed acyclic graph represented by an AIG structure. The AIG structure is a directed acyclic graph used to represent a combinational logic circuit, in which nodes represent logic AND gates and edges represent signal paths. Through the logic optimization environment, the AIG structure can be converted from the circuit netlist structure and can accurately describe the circuit logic structure.

[0146] The feature extraction module is used to extract the topological connection relationship between nodes from the AIG structure to form an adjacency matrix; the timing and power analysis tools are used to analyze each circuit, extract the timing and physical information of each gate unit, and form an initial feature vector. The initial feature vectors of all gates are concatenated to obtain a feature matrix;

[0147] The graph variational autoencoder GVAE model takes the adjacency matrix and feature matrix extracted above as input, encodes and outputs a low-dimensional vector representation of a fixed length as the state vector of the circuit to be optimized. The architecture and training process of GVAE are consistent with those in Example 1.

[0148] The reinforcement learning agent learns and makes decisions based on the state vector of the AIG structure and the optimization target (such as area, delay). The reinforcement learning agent selects the optimal optimization command from the optimization command space to maximize the optimization target through interaction with the logic optimization environment. The training process of the agent is consistent with that in Example 1.

[0149] The command execution module is used to execute the optimization command to be executed in the next step. The optimization command space contains a set of optimization operations for the AIG structure, including but not limited to logic rewrite (Rewrite), logic replacement (Resub), logic reconstruction (Refactor), logic balance (Balance), and zero-cost rewrite (Rewrite-z). By selecting and executing these commands, the reinforcement learning agent can dynamically adjust the circuit structure to achieve performance improvement.

[0150] The optimization evaluation module is used to evaluate the optimization results. It is used to analyze and evaluate the circuit performance after the optimization command is executed. The evaluation criteria include multiple dimensions such as area and delay. The evaluation results are not only used to measure the effect of the current optimization, but also serve as the basis for the reinforcement learning agent to obtain rewards, helping the agent to choose better commands in subsequent decisions.

[0151] In addition, as a preferred solution, interpolation operations in low-dimensional feature vectors of the latent space can be used to generate new circuit states between two known circuit states. In the interpolation operation, linear interpolation or more complex interpolation techniques can be used to generate smooth and continuous circuit states, discover the relationship between different design parameters, and generate new designs with smooth transition characteristics.

[0152] On the other hand, sampling operations in the latent space can be used to generate completely new circuit states that may be different from known states but still retain the characteristics of the latent space. In the sampling operation, different sampling techniques can be applied, such as random sampling, Gaussian sampling, etc., to discover the diversity in the circuit design space and explore a wider range of design possibilities.

[0153] In addition to performing interpolation and sampling operations separately, the method can explore the latent space in an interactive manner, achieving a more refined and personalized exploration of the circuit design space. The advantage of this interactive exploration is that it can dynamically adjust the interpolation and sampling operations based on real-time feedback and needs.

[0154] The digital integrated circuit optimization system of this embodiment uses the graph variational autoencoder GVAE to intelligently learn and extract the key features and deep patterns of the circuit, breaking through the traditional method's reliance on manual feature design, and helping to enhance the reinforcement learning agent's insight and understanding of the circuit structure; effectively encoding the circuit state as a fixed-length input vector helps to improve the operating efficiency and overall performance of the reinforcement learning algorithm, and quickly converge in complex optimization tasks; it provides a highly integrated full-process circuit optimization framework, starting from the structure of the circuit netlist, through multiple steps such as structural feature extraction and intelligent optimization, to build an automated and efficient closed-loop system, thereby improving the quality and productivity of circuit optimization.

[0155] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.

[0156] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital integrated circuit optimization method, characterized in that: The method comprises: Step 1: Obtain a circuit netlist structure from the digital integrated circuit to be optimized; Step 2: converting the circuit netlist structure into a directed acyclic graph represented by an AIG structure; Step 3: extract the topological connection relationship between nodes from the AIG structure to form an adjacency matrix; use the timing and power analysis tools to analyze each circuit, extract the timing and physical information of each gate unit, form an initial feature vector, and concatenate the initial feature vectors of all gates to obtain a feature matrix; Step 4: Encode the adjacency matrix and the feature matrix using a graph variational autoencoder to obtain a state vector of the digital integrated circuit to be optimized; Step 5: input the state vector into the reinforcement learning agent, and the reinforcement learning agent selects the optimization command to be executed next according to the current circuit state; Step 6: Execute the optimization command to obtain the AIG structure of the optimized circuit netlist; Step 7: Repeat steps 3 to 6 until the optimized circuit performance meets the design requirements, and the optimization is completed.

2. The digital integrated circuit optimization method according to claim 1, characterized in that: The training process of the reinforcement learning agent includes: Step 51: Calculate the current state vector s using the differentiable strategy function π(a|s,θ) to obtain the probability distribution of each optimization command a under the current state; Step 52: According to the probability distribution obtained in step 51, randomly sample an optimization command and execute it in a logic synthesis environment to obtain an optimized AIG structure, and evaluate the optimization result based on the area parameter and the delay parameter to calculate the reward value; Step 53: After a round of optimization sequence is completed, the rewards of the entire sequence are accumulated according to the discount factor γ: Among them, T represents the total number of steps in this round of optimization sequence, t represents the current time step, k represents each time step from the current time step t to the end of the round, and R k Represents the immediate reward obtained at the kth time step; Step 54: Update the parameters θ of the policy function and the parameters ω of the value function; First, calculate the error δ, which is the difference between the accumulated reward and the current state value: δ=Gv(S t ,oh) Then use the Adam optimization algorithm to update the parameters: ω=ω+Adam(δ▽ w v(S t ,oh)) θ=θ+Adam(γ t δ▽ w lnπ(A t |S t ,i)) Among them, v(s,ω) is the value function, which is used to estimate the expected reward value in each state and serves as a baseline to reduce the variance of the algorithm; Step 55: Repeat steps 51 to 54 until the maximum number of iterations is met or the value of the loss function converges to a stable range.

3. The digital integrated circuit optimization method according to claim 1, characterized in that: The training process of the graph variational autoencoder GVAE includes: Step 41: The adjacency matrix A and the feature matrix X of the AIG structure to be optimized are input into the encoder, and processed through a multi-layer graph convolutional network to obtain the distribution parameters μ and σ of the latent space, and after re-parameterization, a low-dimensional state vector representation Z is generated: Z=f encoder (A,X) where Z∈R n×k is the output of the encoder, representing the k-dimensional latent vector, and n represents the number of nodes in the circuit; Step 42: Input the low-dimensional vector representation Z into the decoder, and generate a reconstructed adjacency matrix through the deconvolution network. and the feature matrix Step 43: Define the loss function L: L=L recon +βL KL Among them, L recon represents the reconstruction loss, L KL represents KL divergence, β is a hyperparameter used to balance reconstruction loss and KL divergence; Step 44: Using the back propagation algorithm, the parameters of the encoder and decoder are updated by gradient descent according to the loss function L: θ=θ-α▽ θ L Among them, θ is the parameter of the encoder and decoder, α is the learning rate, ▽ θ L is the gradient of the loss function with respect to the model parameters; Step 45: Repeat steps 41 to 44, and perform training iterations until the loss function tends to stabilize or reaches a preset number of training rounds.

4. The digital integrated circuit optimization method according to claim 1, characterized in that: The optimization commands include: logic rewrite Rewrite, logic replacement Resub, logic reconstruction Refactor, logic balance Balance, and zero-cost rewrite Rewrite-z.

5. A digital integrated circuit optimization system, characterized in that: The system includes: a logic optimization environment, an AIG structure conversion module, a feature extraction module, a graph variational autoencoder, a reinforcement learning agent, a command execution module and an optimization evaluation module; The logic optimization environment is used to convert the digital integrated circuit to be optimized into a circuit netlist structure; The AIG structure conversion module is used to convert the circuit netlist structure into a directed acyclic graph represented by the AIG structure; The feature extraction module extracts the topological connection relationship between nodes from the AIG structure to form an adjacency matrix; uses a timing and power analysis tool to analyze each circuit, extracts the timing and physical information of each gate unit, and forms an initial feature vector. The initial feature vectors of all gates are concatenated to obtain a feature matrix; The graph variational autoencoder is used to encode the adjacency matrix and the feature matrix to obtain the state vector of the digital integrated circuit to be optimized; The reinforcement learning agent selects an optimization command to be executed next based on the input state vector; The command execution module is used to execute the optimization command to be executed in the next step; The optimization evaluation module is used to evaluate the optimization results.

6. The integrated circuit optimization system according to claim 5, characterized in that: The training process of the reinforcement learning agent includes: Step 51: Calculate the current state vector s using the differentiable strategy function π(a|s,θ) to obtain the probability distribution of each optimization command a under the current state; Step 52: According to the probability distribution obtained in step 51, randomly sample an optimization command and execute it in a logic synthesis environment to obtain an optimized AIG structure, and evaluate the optimization result based on the area parameter and the delay parameter to calculate the reward value; Step 53: After a round of optimization sequence is completed, the rewards of the entire sequence are accumulated according to the discount factor γ: Among them, T represents the total number of steps in this round of optimization sequence, t represents the current time step, k represents each time step from the current time step t to the end of the round, and R k Represents the immediate reward obtained at the kth time step; Step 54: Update the parameters θ of the policy function and the parameters ω of the value function; First, calculate the error δ, which is the difference between the accumulated reward and the current state value: δ=Gv(S t ,oh) Then use the Adam optimization algorithm to update the parameters: ω=ω+Adam(δ▽ w v(S t ,oh)) θ=θ+Adam(γ t δ▽ w lnπ(A t |S t ,i)) Among them, v(s,ω) is the value function, which is used to estimate the expected reward value in each state and serves as a baseline to reduce the variance of the algorithm; Step 55: Repeat steps 51 to 54 until the maximum number of iterations is met or the value of the loss function converges to a stable range.

7. The integrated circuit optimization system according to claim 5, characterized in that: The training process of the graph variational autoencoder includes: Step 41: The adjacency matrix A and the feature matrix X of the AIG structure to be optimized are input into the encoder, and processed through a multi-layer graph convolutional network to obtain the distribution parameters μ and σ of the latent space, and after re-parameterization, a low-dimensional state vector representation Z is generated: Z=f encoder (A,X) where Z∈R n×k is the output of the encoder, representing the k-dimensional latent vector, and n represents the number of nodes in the circuit; Step 42: Input the low-dimensional vector representation Z into the decoder, and generate a reconstructed adjacency matrix through the deconvolution network. and the feature matrix Step 43: Define the loss function L: L=L recon +βL KL Among them, L recon represents the reconstruction loss, L KL represents KL divergence, β is a hyperparameter used to balance reconstruction loss and KL divergence; Step 44: Using the back propagation algorithm, the parameters of the encoder and decoder are updated by gradient descent according to the loss function L: θ=θ-α▽ θ L Among them, θ is the parameter of the encoder and decoder, α is the learning rate, ▽ θ L is the gradient of the loss function with respect to the model parameters; Step 45: Repeat steps 41 to 44, and perform training iterations until the loss function tends to stabilize or reaches a preset number of training rounds.

8. The digital integrated circuit optimization system according to claim 5, characterized in that: The optimization commands include: logic rewrite Rewrite, logic replacement Resub, logic reconstruction Refactor, logic balance Balance, and zero-cost rewrite Rewrite-z.

9. An integrated circuit optimization device, characterized in that: including memory and processor; The memory is used to store computer programs; The processor is used to implement the digital integrated circuit optimization method according to any one of claims 1 to 4 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the digital integrated circuit optimization method according to any one of claims 1 to 4 is implemented.

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