Method of operating a memory, memory and storage system

Abstract

The application provides a memory operating method and a memory. The memory operating method comprises: biasing two poles of a memory cell formed by a first sub-memory cell and a second sub-memory cell in series in a first direction to make the memory cell reach a first threshold state or a second threshold state; and biasing the two poles of the memory cell in a second direction to make the memory cell reach a third threshold state or a fourth threshold state. The first direction bias and the second direction bias are opposite in the positive and negative directions of the two poles. The memory operating method, the memory and the storage system provided by the application can not only achieve multi-level storage, but also increase the read window margin and have better control uniformity, thereby solving the read window margin problem in multi-level storage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic devices, and in particular, to a memory operating method, a memory and a storage system. BACKGROUND

[0002] As a candidate for next-generation nonvolatile semiconductor memory, phase change random access memory (PCM) has been widely concerned due to its high-speed reading, high erasable number of times, non-volatility, small element size, low power consumption, strong vibration resistance and radiation resistance, etc., especially 3D PCM.

[0003] However, as the demand for increasing storage capacity increases, multi-level storage of each storage unit has become a trend, but how to make the multi-level storage of the phase change memory have sufficient read window margin (RWM) has been a problem. Although the industry has made efforts to remedy this problem from various aspects, it has not been well solved. SUMMARY

[0004] The purpose of the present application is to provide a memory operating method, a memory and a storage system to solve the problem of read window margin when multi-level storage.

[0005] In a first aspect, the present application provides a memory operating method, the operating method comprising:

[0006] biasing two poles of a storage unit in a first direction in a storage array, the storage unit being in series with a first sub-storage unit and a second sub-storage unit, to obtain a first threshold state or a second threshold state of the storage unit; and

[0007] biasing the two poles of the storage unit in a second direction to obtain a third threshold state or a fourth threshold state of the storage unit, the first direction bias and the second direction bias being opposite in positive and negative directions of the two poles.

[0008] Optionally, the operating method comprises using a SOM storage device as the first sub-storage unit and using a PCM storage device as the second sub-storage unit.

[0009] The step of biasing in the first direction comprises:

[0010] applying a first direction first bias to the storage unit to generate a 1-1-1 threshold voltage in the first sub-storage unit; and

[0011] applying a first-direction second bias to the memory cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-memory cell;

[0012] wherein the 1-1-1 threshold voltage and the 1-2-1 threshold voltage constitute the first threshold state, and the 1-1-1 threshold voltage and the 1-2-0 threshold voltage constitute the second threshold state.

[0013] Optionally, the step of applying a second-direction second bias comprises:

[0014] applying a second-direction first bias to the memory cell to generate a 2-1-0 threshold voltage in the first sub-memory cell; and

[0015] applying a second-direction second bias to the memory cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-memory cell;

[0016] wherein the 2-1-0 threshold voltage and the 2-2-1 threshold voltage constitute the third threshold state, and the 2-1-0 threshold voltage and the 2-2-0 threshold voltage constitute the fourth threshold state.

[0017] Optionally, the step of applying a first-direction second bias comprises:

[0018] applying a first-direction set bias to the memory cell to generate the 1-2-1 threshold voltage in the second sub-memory cell; or

[0019] applying a first-direction reset bias to the memory cell to generate the 1-2-0 threshold voltage in the second sub-memory cell.

[0020] Optionally, the step of applying a second-direction second bias comprises:

[0021] applying a second-direction set bias to the memory cell to generate the 2-2-1 threshold voltage in the second sub-memory cell; or

[0022] applying a second-direction reset bias to the memory cell to generate the 2-2-0 threshold voltage in the second sub-memory cell.

[0023] Optionally, the operation method further comprises:

[0024] making the 1-2-1 threshold voltage and the 2-2-1 threshold voltage in the same threshold level, and making the 1-2-0 threshold voltage and the 2-2-0 threshold voltage in the same threshold level; and

[0025] the first 1-1-1 threshold voltage is a set threshold voltage, the first 1-2-1 threshold voltage is a set threshold voltage, the first 1-2-0 threshold voltage is a reset threshold voltage, the second 2-1-0 threshold voltage is a reset threshold voltage, the second 2-2-1 threshold voltage is a set threshold voltage, and the second 2-2-0 threshold voltage is a reset threshold voltage.

[0026] Optionally, the step of applying a first direction bias includes applying a first direction single bias to the memory cell to set the memory cell to a first threshold state or a second threshold state, and the step of applying a first direction single bias includes:

[0027] applying a first direction set bias to the memory cell to generate a third 3-1-1 threshold voltage in the first sub-memory cell and a third 3-2-1 threshold voltage in the second memory cell; or

[0028] applying a first direction reset bias to the memory cell to generate a third 3-1-1 threshold voltage in the first sub-memory cell and a third 3-2-0 threshold voltage in the second memory cell;

[0029] wherein the third 3-1-1 threshold voltage and the third 3-2-1 threshold voltage form the first threshold state, and the third 3-1-1 threshold voltage and the third 3-2-0 threshold voltage form the second threshold state.

[0030] Optionally, the step of applying a second direction bias includes applying a second direction single bias to the memory cell to set the memory cell to a third threshold state or a fourth threshold state, and the step of applying a second direction single bias includes:

[0031] applying a second direction set bias to the memory cell to generate a fourth 4-1-0 threshold voltage in the first sub-memory cell and a fourth 4-2-1 threshold voltage in the second memory cell; or

[0032] applying a second direction reset bias to the memory cell to generate a fourth 4-1-0 threshold voltage in the first sub-memory cell and a fourth 4-2-0 threshold voltage in the second memory cell; the fourth 4-1-0 threshold voltage and the fourth 4-2-1 threshold voltage form the third threshold state, and the fourth 4-1-0 threshold voltage and the fourth 4-2-0 threshold voltage form the fourth threshold state.

[0033] Optionally, the method further includes:

[0034] the third-2-1 threshold voltage is a set threshold voltage, the third-2-0 threshold voltage is a reset threshold voltage, the fourth-1-0 threshold voltage is a reset threshold voltage, the fourth-2-1 threshold voltage is a set threshold voltage, and the fourth-2-0 threshold voltage is a reset threshold voltage.

[0035] the third-2-1 threshold voltage is a set threshold voltage, the third-2-0 threshold voltage is a reset threshold voltage, the fourth-1-0 threshold voltage is a reset threshold voltage, the fourth-2-1 threshold voltage is a set threshold voltage, and the fourth-2-0 threshold voltage is a reset threshold voltage.

[0036] In a second aspect, the present application provides a memory, comprising:

[0037] a memory array comprising a plurality of rows and a plurality of columns of memory cells arranged in a matrix, two poles of each of the memory cells being connected to a word line and a bit line, and one of the memory cells comprising a first sub-memory cell and a second sub-memory cell connected in series between the two poles;

[0038] a peripheral circuit configured to bias the two poles of the memory cell in a first direction to cause the memory cell to have a first threshold state or a second threshold state; and

[0039] bias the two poles of the memory cell in a second direction to cause the memory cell to have a third threshold state or a fourth threshold state, the first direction being opposite to the second direction.

[0040] Optionally, the first sub-memory cell comprises a SOM memory device, and the second sub-memory cell comprises a PCM memory device.

[0041] Optionally, the peripheral circuit comprises a word line driver configured to apply a first bias in the first direction to the memory cell to generate a first-1-1 threshold voltage in the first sub-memory cell; and

[0042] apply a second bias in the first direction to the memory cell to generate a first-2-1 threshold voltage or a first-2-0 threshold voltage in the second sub-memory cell;

[0043] wherein the first-1-1 threshold voltage and the first-2-1 threshold voltage constitute the first threshold state, and the first-1-1 threshold voltage and the first-2-0 threshold voltage constitute the second threshold state.

[0044] Optionally, the peripheral circuit further comprises a bit line driver configured to apply a second-direction first bias to the memory cell to generate a 2-1-0 threshold voltage in the first sub-memory cell; and

[0045] apply a second-direction second bias to the memory cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-memory cell;

[0046] wherein the 2-1-0 threshold voltage and the 2-2-1 threshold voltage form the third threshold state, and the 2-1-0 threshold voltage and the 2-2-0 threshold voltage form the fourth threshold state.

[0047] Optionally, the first-direction second bias comprises a first-direction set bias or a first-direction reset bias, and the second-direction second bias comprises a second-direction set bias or a second-direction reset bias.

[0048] Optionally, the 1-1-1 threshold voltage is a set threshold voltage, the 1-2-1 threshold voltage is a set threshold voltage, the 1-2-0 threshold voltage is a reset threshold voltage, the 2-1-0 threshold voltage is a reset threshold voltage, the 2-2-1 threshold voltage is a set threshold voltage, and the 2-2-0 threshold voltage is a reset threshold voltage.

[0049] Optionally, the peripheral circuit comprises a word line driver configured to apply a first-direction single bias to the memory cell to obtain a first threshold state or a second threshold state in the memory cell, and the first-direction single bias comprises:

[0050] a first-direction set bias to the memory cell to generate a 3-1-1 threshold voltage in the first sub-memory cell and a 3-2-1 threshold voltage in the second sub-memory cell; or

[0051] a first-direction reset bias to the memory cell to generate a 3-1-1 threshold voltage in the first sub-memory cell and a 3-2-0 threshold voltage in the second sub-memory cell;

[0052] wherein the 3-1-1 threshold voltage and the 3-2-1 threshold voltage form the first threshold state, and the 3-1-1 threshold voltage and the 3-2-0 threshold voltage form the second threshold state.

[0053] Optionally, the peripheral circuit further comprises a bit line driver configured to apply a second-direction single bias to the memory cell to obtain a third threshold state or a fourth threshold state in the memory cell, and the second-direction single bias comprises:

[0054] a second direction set bias voltage to generate a 4-1-0 threshold voltage in the first sub-memory cell and a 4-2-1 threshold voltage in the second sub-memory cell; or

[0055] a second direction reset bias voltage to generate a 4-1-0 threshold voltage in the first sub-memory cell and a 4-2-0 threshold voltage in the second sub-memory cell;

[0056] wherein the 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-0 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

[0057] Optionally, the 3-1-1 threshold voltage is a set threshold voltage, the 3-2-1 threshold voltage is a set threshold voltage, the 3-2-0 threshold voltage is a reset threshold voltage, the 4-1-0 threshold voltage is a reset threshold voltage, the 4-2-1 threshold voltage is a set threshold voltage, and the 4-2-0 threshold voltage is a reset threshold voltage.

[0058] In a third aspect, the present application provides a storage system, comprising: the memory as described above; and a controller electrically connected with the memory, for controlling the memory.

[0059] By the operation method of the memory, the memory and the storage system provided by the present application, not only can the multi-level storage be achieved, but also the read window margin can be increased, and the control uniformity can be better, so that the read window margin problem in multi-level storage can be solved. BRIEF DESCRIPTION OF DRAWINGS

[0060] The technical solutions and other beneficial effects of the present application will become apparent from the following detailed description of specific embodiments of the present application, taken in conjunction with the accompanying drawings.

[0061] Figure 1 is a functional module block diagram of the memory according to some embodiments of the present application;

[0062] Figure 2 is a storage array circuit schematic diagram of the memory according to some embodiments of the present application;

[0063] Figure 3 is a structure diagram of a phase change memory cell according to some embodiments of the present application;

[0064] Figure 4(a) is a set and reset operation schematic diagram of a phase change memory cell according to some embodiments of the present application;

[0065] Figure 4(b) is a schematic diagram of the operation of a bidirectional threshold switch according to some embodiments of the application;

[0066] Figure 4(c) is a schematic diagram of the operation of a selector-only memory cell according to some embodiments of the application;

[0067] Figure 5 Figure 5 is a flow chart of a method of operation according to some embodiments of the application;

[0068] Figure 6 Figure 6 is a schematic diagram of the establishment of threshold voltages for multi-level storage according to some embodiments of the application;

[0069] Figure 7 Figure 7 is a schematic diagram of an operating bias according to some embodiments of the application;

[0070] Figure 8 Figure 8 is a schematic diagram of the establishment of threshold voltages for multi-level storage according to some embodiments of the application;

[0071] Figure 9 Figure 9 is a schematic diagram of another operating bias according to some embodiments of the application;

[0072] Figure 10 Figure 10 is a schematic diagram of the establishment of threshold voltages for multi-level storage according to some embodiments of the application;

[0073] Figure 11 Figure 11 is a schematic block diagram of a memory system according to some embodiments of the application. DETAILED DESCRIPTION

[0074] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0075] It should be understood that although the terms first, second, etc. can be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. For example, a first component can be referred to as a second component, and similarly, a second component can be referred to as a first component without departing from the scope of the present application.

[0076] It should be understood that when one component is referred to as being "on" or "connected to" another component, it can be directly on or connected to the other component, or there can be intervening components present. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0077] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend over an entire underlying or overlying structure, or can have an area less than the area of the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer can be between any set of horizontal planes that are between the top and bottom surfaces of a continuous structure or at the top and bottom surfaces. Layers can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, where it can include one or more layers, and / or can have one or more layers on, above and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more electrically conductive layers and contact layers, as well as one or more dielectric layers.

[0078] It should be noted that the diagrams in the embodiments of the present application only schematically show the basic concept of the present application, and although only the components related to the present application are shown in the diagrams, the actual components, shapes and sizes are not drawn according to the number of components, shapes and sizes when the present application is implemented, and the shapes, numbers and proportions of the components can be arbitrarily changed, and the layout of the components can be more complex.

[0079] In this document, directions are expressed in Cartesian coordinates, with respect to a substrate, with "Z" representing a first direction that is perpendicular to the substrate, "X" representing a second direction that is parallel to the substrate, and "Y" representing a third direction that is parallel to the substrate and perpendicular to X.

[0080] First, refer to Figure 1 , Figure 1 is a functional block diagram of a memory provided according to some embodiments of the present application. The memory 200 mainly includes a storage array 10 and a peripheral circuit 20 connected to control the storage array 10.

[0081] As shown in Figure 1 , the peripheral circuit 20 is connected to the storage array 10. The peripheral circuit 20 generally includes at least a row decoder 240, a word line voltage generator 211, a word line driver 212, a column decoder 250, a bit line driver 251, a bit line voltage generator 271, a reference current generator 261, a sense amplification current comparator 262, and a logic control module 230 connected to the aforementioned devices for receiving operation instructions to control the aforementioned devices.

[0082] The row decoder 240 receives a row address signal from a bus (not shown) and decodes the row address signal to select an addressed word line.

[0083] The word line driver 212 is connected with the plurality of word lines WL<0:m>, the word line voltage generator 211, and the row decoder 240. The word line driver 212 receives the row address selection signal and the word line driving voltage, and outputs the word line driving voltage to at least one of the plurality of word lines WL<0:m> according to the row address selection signal <m>at least one row of memory cells.

[0084] The bit line driver 251, the bit line voltage generator 271 and the column decoder 250 belong to the column driving circuit, and are connected as shown. Figure 1 The bit line voltage generator 271 and the column decoder 250 are connected with the logic control module 230 to accept the control of the logic control module 230.

[0085] The column decoder 250 receives the column address signal and decodes the column address signal to select the addressed bit line connected with the operation target memory cell. The bit line voltage generator 271 generates the clamping voltage required by each selected bit line and outputs the set clamping voltage to each corresponding selected bit line.

[0086] The bit line driver 251 is connected with the plurality of bit lines, the bit line voltage generator 271 and the column decoder 250. The bit line driver 251 receives the bit line voltage and the column address selection signal and outputs the set clamping bit line voltage to at least one bit line BL <n>At least one column of storage units is connected.

[0087] The peripheral circuit 20 also includes a sensitive current amplification comparator 262, a reference current generator 261, and a data latch (not shown). The sensitive current amplification comparator 262 is connected to the reference current generator 261 and multiple bit lines BL<0:n>, and is also connected to the data latch 223. The sensitive current amplification comparator 262, upon receiving the read current, compares it with the reference current generated by the reference current generator 261 to determine the data stored in the selected memory cell. This data is then stored in the data latch 280 and, together with the data read from other bit lines, is output to the data bus via the input / output interface 290.

[0088] Based on the structural design of the peripheral circuit 20 of the memory described above, the operation of the memory can include erase operation, read operation and programming operation, or set and reset operation.

[0089] Please refer to Figure 2 As shown, Figure 2 This is a circuit diagram illustrating an example of a memory array 10 according to some embodiments of this application. The memory array 10 includes a plurality of memory cells 11 arranged in a multi-row, multi-column array, and word lines WLn and bit lines BLn respectively connecting the plurality of memory cells 11 in the multiple rows and columns. Each row of memory cells includes a plurality of memory cells 11 arranged along the row direction X. Each column of memory cells includes a plurality of memory cells 11 arranged along the column direction (i.e., the second direction Y). For example, Figure 2 Only the three rows (WLn-1 to WLn+1) and three columns (BLn-1 to BLn+1) of the memory cells are shown. In reality, the number of rows and columns of memory cells depends on the storage capacity. Furthermore, Figure 2 The illustrated storage cell is a phase-change storage cell 11, which includes an omonic threshold switch (OTS) 111 and a PCM storage cell 112 connected in series between the word line WLn and the bit line BLn. Both the omonic threshold switch (OTS) 111 and the PCM storage cell 112 are made of phase-change materials. However, in some technologies, since the PCM storage cell 112 is used as the threshold setting for data storage, in this embodiment, the two phase-change materials in the storage cell 11 are referred to as the omonic threshold switch (OTS) 111 and the PCM storage cell 112, respectively.

[0090] It should be understood that the memory cells in the memory array can be various types of memory cells, such as floating gate memory cells, ONO memory cells, resistive memory cells (RRAM), phase change memory cells (PCM / PCRAM / SOM), etc., and the present application is not limited thereto. However, the present application is particularly suitable for phase change memory cells, and thus the following will be described by taking phase change memory cells as an example, but it should be understood that the present application is not limited thereto.

[0091] Figure 3 A structural diagram of a memory cell provided for some embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the structure of a phase change memory cell provided by some embodiments of the present application includes a top electrode 11a and a bottom electrode 11b connected with a word line WLn and a bit line BLn respectively, and a phase change memory cell 112, an intermediate electrode 11c, and an OTS (Ovonic Threshold Switch) 111 located between the top electrode 11a and the bottom electrode 11b. It should be understood that in some embodiments, the intermediate electrode 11c can also not be provided, and thus the present application is not limited to the structure disclosed herein. Figure 3

[0092] The phase change memory cell 112 includes one or more phase change materials such as a Ge-Sb-Te (GST) based material, and one example can be Ge2Sb2Te5. At present, the phase change materials used by various institutions are more chalcogenides (represented by Intel) and synthetic materials containing germanium, antimony and tellurium (GST), such as Ge2Sb2Te5. The phase change material can have a large resistivity contrast between different phases (e.g., crystal phase and amorphous phase). For example, the phase change material can exhibit a relatively low resistivity in the crystal phase, but a relatively high resistivity in the amorphous phase, and the resistivity of the phase change material in the amorphous phase can be hundreds to thousands of times higher than that in the crystal phase. The phase change material can switch between different phases when heated to achieve the writing (including setting and resetting) of information (data). In the present embodiment, the electrodes 11a, 11c can heat the phase change memory cell 112 via the OTS 111 to change the phase of the heated region 112f in the phase change cell 112, thereby reducing the resistance of the phase change memory cell 112. In some embodiments, a heater (not shown) can also be added between the phase change memory cell 112 and the intermediate electrode 11c.

[0093] The top electrode 11a and the bottom electrode 11b are oppositely arranged and the positions thereof can be interchanged and overlap with the bit line BLn and the word line WLn outside, thereby forming a 3D phase change memory.

[0094] ​Figure 4(a) is a biasing diagram of the reset and set operations of a PCM storage cell, i.e., showing the operating principle and biasing diagram of a phase change memory cell 112, according to some embodiments of the present application. The basic storage principle of a phase change memory cell 112 is to apply voltage or current pulse signals of different width and height to the phase change material on the phase change memory cell, so that the phase change material in the heated region 1121f undergoes a physical phase change between the crystalline state (low resistance state) and the amorphous state (high resistance state), i.e., reversible phase transition between each other, thereby realizing the write operation of information, or said to realize the write of information, including writing 1 (set) or 0 (reset). The mutual conversion process includes the amorphization transition from the crystalline state to the amorphous state, and the crystallization transition from the amorphous state to the crystalline state, where the former is called amorphization process, and the latter is called crystallization process. Then rely on measuring the resistance difference between the two physical phases to realize the readout of information, this non-destructive reading process can ensure accurate reading of the information stored in the device unit. The resistivity of the phase change material in the crystalline and amorphous states differs by several orders of magnitude, making it have a high noise margin, enough to distinguish between "0" state and "1" state.

[0095] Figure 4(b) shows a plot of the logarithmic current versus voltage of a bidirectional threshold switch (OTS) 111 as a fast return selector or access element. Starting from a high resistance (reset) state at low electric field, the current in the bidirectional threshold switch (OTS) 111 increases 205 with very small current values as the voltage increases until it reaches the threshold voltage V TH OTS .

[0096] After the fast return point 210, as long as a current higher than the holding current I H OTS is flowing through the bidirectional threshold switch (OTS) 111, a high conductive dynamic ON state 215 is maintained in the bidirectional threshold switch (OTS) 111. This transient high conductive state is of electronic origin and does not involve any phase change in the bidirectional threshold switch (OTS) 111.

[0097] When the threshold voltage V TH OTS of the bidirectional threshold switch (OTS) 111 is exceeded, the bidirectional threshold switch (OTS) 111 switches from OFF state to ON state and allows a current to flow through the phase change memory cell 112 in series with the bidirectional threshold switch (OTS) 111. In the ON state, the voltage across the bidirectional threshold switch (OTS) 112 remains close to the holding voltage (V H OTS ) as the current flowing through the bidirectional threshold switch (OTS) 111 increases.

[0098] The bidirectional threshold switch (OTS) 111 can remain in the ON state until the current through the bidirectional threshold switch (OTS) 111 is below a holding current (I H OTS ) below which the bidirectional threshold switch (OTS) 111 can return to a high resistance, non-conducting OFF state until the V TH OTS or I TH OTS is exceeded again. Whenever directed, the bidirectional threshold switch (OTS) can repeatedly and reversibly switch between the OFF state and the ON state, but it does not crystallize.

[0099] In further studies of the present application, it is understood that the threshold voltage Vth in the OTS 111 is affected by many factors, such as device structure variations, amplitude, pulse width, ramp rate and relaxation time of the applied pulse. In further studies, it is found that when the OTS device is composed of a phase change material such as Ge-Te-As-Si, the threshold voltage Vth of the OTS 111 will change under the control of the polarity of the applied voltage, more specifically, a change in the threshold voltage occurs with a change in the polarity of the applied voltage. As shown in Figure 4(c), the Vth value in the current operation is greatly affected by the polarity of the previous pulse, resulting in two relatively stable Vth levels, Vth1 and Vth2, in the same pulse direction. In this work, the negative polarity Vth difference (AVth = |Vth1-Vth2|) is 260 mV, while the external resistance is increased, further enhancing the AVth (Figure 4(c)) by about 1 V, and the positive AVth becomes more pronounced. With this stable AVth, which can last for at least 1000 seconds (~17 minutes), the OTS device can be used independently as a binary storage device, so here the OTS 111 is also referred to as a SOM memory cell (selector only memory), or as an SSM memory cell (self-selecting memory).

[0100] Therefore, in further studies of the present application, the SOM memory cell formed by the OTS 111 is connected in series with a phase change memory cell (PCM memory cell) 112, and the performance of the 1S1R memory cell is enhanced by providing a dual SET state and a dual RESET state, each of which will have a significant difference. By operating with voltages of different polarities, the originally small read window margin RWM (0.85 V) is effectively expanded to ~1.7 and ~1.4 V. The 1S1R memory cell exhibits a fairly long retention time (up to 1 month @ 25°C), and a switching speed of more than 10 8 resistance states. That is, by the polarity operation of the OTS device or the SOM storage cell, the storage states can be doubled.

[0101] Therefore, according to some embodiments of the present application, the OTS 111 as a selective only memory cell (SOM) and the phase change memory cell 112 are proposed as a first sub-memory cell 111 and a second sub-memory cell 112 respectively in a memory cell 11, and an operation method of the memory is proposed as shown in Figure 5

[0102] The two poles of a memory cell 11 in the memory array, which is connected in series by the first sub-memory cell 111 and the second sub-memory cell 112, are biased in a first direction to obtain a first threshold state or a second threshold state of the memory cell 11 (step S1); and

[0103] The two poles of the memory cell 11 are biased in a second direction to obtain a third threshold state or a fourth threshold state of the memory cell 11, and the first direction bias and the second direction bias are opposite in the positive and negative directions of the two poles (step S2).

[0104] Specifically, the operation method includes, for example, using the SOM storage cell as the first sub-memory cell and using the PCM storage cell as the second sub-memory cell. Moreover, the storage value of the first sub-memory cell 111 (i.e. the SOM cell) represents one bit (e.g. the low bit) of a two-bit number, and the storage value of the second sub-memory cell 112 (i.e. the PCM cell) represents the second bit (e.g. the high bit) of the two-bit number. In this way, the storage value of the first sub-memory cell 111 has two states, and the storage value of the second sub-memory cell 112 also has two states. In combination of the two, the memory cell 11 can store four values 11, 10, 01 and 00 through the first threshold voltage (threshold state), the second threshold voltage (threshold state), the third threshold voltage (threshold state) and the fourth threshold voltage (threshold state) of different threshold states as shown in Figure 6

[0105] ​​It is to be understood herein that the first to fourth four value states under a general MLC (Multi-Level Cell) can be sequentially 11, 10, 01, 00 as described in the preceding paragraph, but in some places, the value 01 is also referred to as the second threshold state, and the value 10 is also referred to as the third threshold state. Therefore, which value applies to the second threshold state and which value applies to the third threshold state should be a variable matter, which is only a convenient way of expression, and does not affect the essence of the present application, and is not limited herein. That is, the second threshold state and the third threshold state are only used to represent different states, but the same serial number threshold state can represent different values in different places. In addition, it is also optional to represent the first bit (low bit) or the second bit (high bit) of the two-bit value by the storage value of the first sub-storage unit 111 (SOM cell), and although the preceding paragraph describes that the storage value of the second sub-storage unit 112 (PCM cell) represents the second bit (high bit) of the two-bit value, it can also represent the first bit (low bit) of the two-bit value, which is not limited herein.

[0106] For example, if the set (value 1) threshold voltage of the first sub-storage unit (OTS / SOM) 111 is 4V, the reset (value 0) threshold voltage is 4.7V, the set (value 1) threshold voltage of the second sub-storage unit (PCM cell) 112 is 0V, and the reset (value 0) threshold voltage is 1.5V, then in some embodiments, the first threshold state (threshold state / storage state) can be 4V (value 11), the second threshold state can be 5.5V (value 01), the third threshold state can be 4.7V (value 10), and the fourth threshold state can be 6.2V (value 00). But in other embodiments, the first threshold state (threshold state / storage state) can be 4V (value 11), the second threshold state can be 4.7V (value 10), the third threshold state can be 5.5V (value 01), and the fourth threshold state can be 6.2V (value 00). For simplicity, see Table 1 below.

[0107] State Threshold state (voltage) Vt Denomination of state 11 4V First threshold voltage (threshold state) 10 4.7V Second / third threshold voltage (threshold state) 01 5.5V Third / second threshold voltage (threshold state) 00 6.2V Fourth threshold voltage (threshold state)

[0108] Table 1

[0109] In detail, in one embodiment, the first threshold state of 4V can be formed by the combination of the set (1) threshold voltage 4V of the first sub-memory cell 111 and the set (1) threshold voltage 0V of the second sub-memory cell 112; the second threshold state of 5.5V can be formed by the combination of the set (1) threshold voltage 4V of the first sub-memory cell 111 and the reset (0) threshold voltage 1.5V of the second sub-memory cell 112; the third threshold state of 4.7V can be formed by the combination of the reset (0) threshold voltage 4.7V of the first sub-memory cell 111 and the set (1) threshold voltage 0V of the second sub-memory cell 112; and the fourth threshold state of 6.2V can be formed by the combination of the reset (0) threshold voltage 4.7V of the first sub-memory cell 111 and the reset (0) threshold voltage 1.5V of the second sub-memory cell 112. This can be simply shown in Table 2 as follows.

[0110] State Threshold state Vt Denomination of state PCM Vt SOM Vt 11 4V First threshold voltage (threshold state) 0V 4V 10 4.7V Third threshold voltage (threshold state) 0V 4.7V 01 5.5V Second threshold voltage (threshold state) 1.5V 4V 00 6.2V Fourth threshold voltage (threshold state) 1.5V 4.7V

[0111] Table 2

[0112] Therefore, according to some embodiments of the present application, the step of applying a first-direction first bias to the memory cell includes:

[0113] applying a first-direction first bias to the memory cell to generate a 1-1-1 threshold voltage in the first sub-memory cell; and

[0114] applying a first-direction second bias to the memory cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-memory cell;

[0115] wherein the 1-1-1 threshold voltage, the 1-2-1 threshold voltage and the 1-2-0 threshold voltage form the first threshold state and the second threshold state, respectively.

[0116] In further embodiments, the step of applying a first-direction second bias includes:

[0117] applying a first-direction set bias to the memory cell to generate the 1-2-1 threshold voltage in the second sub-memory cell; or

[0118] applying a first-direction reset bias to the memory cell to generate the 1-2-0 threshold voltage in the second sub-memory cell.

[0119] Specifically, as Figure 7 and Figure 8 As shown, the first direction biasing is applying a biasing from the word line WL, and the first direction first biasing is a first direction set-on biasing V111 for setting on the SOM storage cell 111 as the first sub-storage unit, which will generate a 1-1-1 threshold voltage Vth111 in the SOM storage cell 111 as the first sub-storage unit, which is 4V according to the threshold value example in Table 2 above, and the 1-1-1 threshold voltage Vth111 corresponds to the low bit value in the two-bit value, i.e. the low bit "1" in "11" and "01", which is a set-on value 1.

[0120] The first direction second biasing is a first direction set-on or reset biasing V121 or V120 for the PCM storage cell 112 as the second sub-storage unit, which will generate a 1-2-1 threshold voltage Vth121 of 0V or a 1-2-0 threshold voltage Vth120 of 1.5V in the PCM storage cell 112 as the second sub-storage unit according to the threshold value example in Table 2 above, and the 1-2-1 threshold voltage Vth121 corresponds to the high bit value in the two-bit value, i.e. the high bit "1" in "11"; and the 1-2-0 threshold voltage Vth120 also corresponds to the high bit value in the two-bit value, but corresponds to the high bit "0" in "01".

[0121] Further, the first direction second biasing is applied after the first direction first biasing in time. Through such biasing operations, the first threshold state "11" (4V) or the second threshold state "01" (5.5V) shown in Table 2 above can be generated under the combination of the first direction first biasing V111 and the first direction second biasing V121 or V120, i.e. the threshold voltage Vth111 of 4V and the threshold voltage Vth121V or Vth120V of 0V or 1.5V, respectively.

[0122] Similarly, according to some embodiments of the present application, the step of performing the second direction biasing comprises:

[0123] applying a second direction first biasing to the storage unit to generate a 2-1-0 threshold voltage in the first sub-storage unit; and

[0124] applying a second direction second biasing to the storage unit to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-storage unit;

[0125] wherein the 2-1-0 threshold voltage, the 2-2-1 threshold voltage and the 2-2-0 threshold voltage form the third threshold state and the fourth threshold state, respectively.

[0126] In further embodiments, the step of applying a second direction second bias comprises:

[0127] applying a second direction set bias to the memory cell to generate the 2-2-1 threshold voltage in the second sub-memory cell; or

[0128] applying a second direction reset bias to the memory cell to generate the 2-2-0 threshold voltage in the second sub-memory cell.

[0129] In particular, as also shown in Figure 7 and Figure 8 the second direction bias is a bias applied from the bit line BL, and the second direction first bias is a second direction reset-on bias V210 applied to the SOM memory cell 111 as the first sub-memory cell, which generates a 2-1-0 threshold voltage Vth210 in the SOM memory cell 111 as the first sub-memory cell, which according to the threshold examples in Table 2 above, is 4.7V, which corresponds to the low bit value in a two-bit value, i.e., the low bit "0" in "10" and "00", which is a reset value 0.

[0130] the second direction second bias is a second direction set or reset bias V221 or V220 applied to the PCM memory cell 112 as the second sub-memory cell, which generates a 2-2-1 threshold voltage Vth221 of 0V or a 2-2-0 threshold voltage Vth220 of 1.5V in the PCM memory cell 112 as the second sub-memory cell, according to the threshold examples in Table 2 above, which corresponds to the high bit value in a two-bit value, i.e., the high bit "1" in "10"; and the 2-2-0 threshold voltage Vth220 also corresponds to the high bit value in a two-bit value, but is the high bit "0" in "00".

[0131] Further, the second direction second bias V221 / V220 is also applied in time after the second direction first bias V210. Through such bias operations, under the combination of the second direction first bias V210 and the second direction second bias V221 or V220, i.e., the threshold voltage Vth210 of 4.7V and the threshold voltage Vth221 of 0V or the threshold voltage Vth220 of 1.5V, as shown in Figure 8 , the third threshold state "10" (4.7V) or the fourth threshold state "00" (6.2V) shown in Table 2 above is generated.

[0132] By the aforementioned operation method, it can be understood that the application of the first-direction second bias and the application of the second-direction second bias preferably make the first-2-1 threshold voltage Vth121 and the second-2-1 threshold voltage Vth221 in the same threshold level, and make the first-2-0 threshold voltage Vth120 and the second-2-0 threshold voltage Vth220 in the same threshold level. In this way, a better RWM control can be achieved between the threshold states of the memory cell 11. Moreover, the first-1-1 threshold voltage is a set threshold voltage, the first-2-1 threshold voltage is a set threshold voltage, the first-2-0 threshold voltage is a reset threshold voltage, the second-1-0 threshold voltage is a reset threshold voltage, the second-2-1 threshold voltage is a set threshold voltage, and the second-2-0 threshold voltage is a reset threshold voltage.

[0133] Specifically, as shown in Table 2 above, the first-2-1 threshold voltage Vth121 is a 0V set threshold voltage, the second-2-1 threshold voltage Vth221 is a 0V set threshold voltage, the first-2-0 threshold voltage Vth120 is a 1.5V reset threshold voltage, and the second-2-0 threshold voltage Vth220 is a 1.5V reset threshold voltage. However, it should be understood that in the above embodiment, although the threshold voltages are exemplified as reset threshold voltages and set threshold voltages, they can also be set to, for example, a half reset threshold voltage, or a 3 / 4 reset threshold voltage, etc., which is not limited herein, as long as it is sufficient to make the read window margin between the threshold voltages.

[0134] Hereinafter, further embodiments according to the present application will be described. Specifically, as shown in Table 3 below, when a bias is applied from the first direction, i.e., a first-direction single bias is applied to the memory cell 11 from the word line WL, the first threshold state and the second threshold state can be achieved for the memory cell 11, and the first-direction single bias can include a first-direction set bias V31 or a first-direction reset bias V30. Figure 9 and Figure 10 As shown in Table 3, when a bias is applied from the first direction, i.e., a first-direction single bias is applied to the memory cell 11 from the word line WL, the first threshold state and the second threshold state can be achieved for the memory cell 11, and the first-direction single bias can include a first-direction set bias V31 or a first-direction reset bias V30.

[0135] As the SOM storage cell 111 of the first sub-storage unit and the PCM storage cell 112 of the second sub-storage unit are simultaneously biased, and the biasing magnitude of the first direction set bias V31 or the first direction reset bias V30 is properly selected, a 3-1-1 threshold voltage Vth311 of 4V can be generated in the first sub-storage unit 111 and a 3-2-1 threshold voltage Vth321 of 0V can be generated in the second storage unit 112 when the first direction set bias V31 is applied, so as to form a first threshold state of 4V in the storage unit 11. Similarly, when the first direction reset bias V30 is applied, a 3-1-1 threshold voltage Vth311 of 4V can still be generated in the first sub-storage unit 111 due to the same direction as the first direction set bias V31, but a 3-2-0 threshold voltage Vth320 of 0.7V can be generated in the second storage unit 112.

[0136] Through the foregoing operation, a first threshold state of 4V composed of the 3-1-1 threshold voltage Vth311 and the 3-2-0 threshold voltage Vth321 can be generated in the storage unit 11 after the first direction single bias is applied, and the first threshold state represents a value "11", or a second threshold state of 4.7V composed of the 3-1-1 threshold voltage Vth311 and the 3-2-0 threshold voltage Vth320, and the second threshold state represents a value "10".

[0137] For example, as shown in FIG. 4, when a bias is applied from the first direction, i.e., a first direction single bias is applied to the storage unit 11 from the word line BL, a third threshold state or a fourth threshold state can be obtained for the storage unit 11, and the first direction single bias can include a first direction set bias V31 or a first direction reset bias V30. Figure 9 Figure 10 As shown in FIG. 4, when a bias is applied from the second direction, i.e., a second direction single bias is applied to the storage unit 11 from the word line BL, a third threshold state or a fourth threshold state can be obtained for the storage unit 11, and the second direction single bias can include a second direction set bias V41 or a second direction reset bias V40.

[0138] ​Since the SOM cell 111 of the first sub memory cell and the PCM cell 112 of the second sub memory cell are simultaneously biased, and the biasing magnitude of the second direction set bias V41 or the second direction reset bias V40 is properly selected, and since the biasing direction of the second direction set bias V41 or the second direction reset bias V40 is opposite to that of the first direction set bias V31 or the first direction reset bias V30, the 4-1-0 threshold voltage Vth410 of, for example, 5.5 V reset state will be generated in the first sub memory cell 111 when the second direction set bias V41 is applied, but the 4-2-1 threshold voltage Vth421 of, for example, 0 V set state will be generated in the second memory cell 112. Similarly, when the second direction reset bias V40 is applied, the 4-1-0 threshold voltage Vth410 of, for example, 5.5 V reset state will still be generated in the first sub memory cell 111, and the 4-2-0 threshold voltage Vth420 of, for example, 0.7 V reset state will be generated in the second memory cell 112.

[0139] Through the foregoing operation, after the second direction single bias is applied, a third threshold state of, for example, 5.5 V composed of the 4-1-0 threshold voltage Vth410 plus the 4-2-1 threshold voltage Vth421, and representing the value "01", or a fourth threshold state of, for example, 6.2 V composed of the 4-1-0 threshold voltage Vth410 plus the 4-2-1 threshold voltage Vth421, and representing the value "00", will be generated in the memory cell 11.

[0140] The following Table 3 shows the numerical examples of the foregoing threshold voltages and the composition of the threshold states. It is to be understood that, as mentioned above, the storage value of the first sub memory cell 111 (i.e. the SOM cell) representing the first bit (the low bit) or the second bit (the high bit) of a two-bit value is optional. Although the foregoing embodiment shows that the storage value of the second sub memory cell 112 (i.e. the PCM cell) represents the second bit (the high bit) of a two-bit value, it can also represent the first bit (the low bit) of a two-bit value. Therefore, in the present embodiment, the storage value of the second sub memory cell 112 (i.e. the PCM cell) represents the first bit (the low bit) of a two-bit value. Moreover, in the present embodiment, the second threshold state corresponds to the value "10", instead of the value "01" in the foregoing embodiment.

[0141] State Threshold state Vt Denomination of state PCM Vt SOM Vt 11 4V First threshold voltage (threshold state) 0V 4V 10 4.7V Second threshold voltage (threshold state) 0.7V 4V 01 5.5V Third threshold voltage (threshold state) 0V 5.5V 00 6.2V Fourth threshold voltage (threshold state) 0.7V 5.5V

[0142] Table 3

[0143] Therefore, according to the foregoing embodiment, the step of performing the first direction biasing includes applying a first direction single bias to the memory cell to obtain a first threshold state or a second threshold state for the memory cell 11, and the step of applying the first direction single bias includes:

[0144] applying a first direction set bias V31 to the memory cell 11 to generate a 3-1-1 threshold voltage in the first sub-memory cell 111 and a 3-2-1 threshold voltage in the second sub-memory cell 112; or

[0145] applying a first direction reset bias V30 to the memory cell 11 to generate a 3-1-1 threshold voltage in the first sub-memory cell 111 and a 3-2-0 threshold voltage in the second sub-memory cell 112.

[0146] The 3-1-1 threshold voltage and the 3-2-1 threshold voltage constitute the first threshold state, and the 3-1-1 threshold voltage and the 3-2-0 threshold voltage constitute the second threshold state.

[0147] Furthermore, according to the foregoing embodiment, the step of performing the second direction biasing includes applying a second direction single bias to the memory cell 11 to obtain a third threshold state or a fourth threshold state for the memory cell, and the step of applying the second direction single bias includes:

[0148] applying a second direction set bias V41 to the memory cell 11 to generate a 4-1-0 threshold voltage in the first sub-memory cell 111 and a 4-2-1 threshold voltage in the second sub-memory cell 112; or

[0149] applying a second direction reset bias V40 to the memory cell 11 to generate a 4-1-0 threshold voltage in the first sub-memory cell 111 and a 4-2-0 threshold voltage in the second sub-memory cell; the 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-1 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

[0150] It is incidentally mentioned that in some embodiments, the 3-2-1 threshold voltage and the 4-2-1 threshold voltage are in the same threshold level, and the 3-2-0 threshold voltage and the 4-2-0 threshold voltage are in the same threshold level. The 3-1-1 threshold voltage is a set threshold voltage, the 3-2-1 threshold voltage is a set threshold voltage, the 3-2-0 threshold voltage is a reset threshold voltage, the 4-1-0 threshold voltage is a reset threshold voltage, the 4-2-1 threshold voltage is a set threshold voltage, and the 4-2-0 threshold voltage is a reset threshold voltage. However, as mentioned above, each reset threshold voltage can also be a semi-reset threshold voltage or a semi-set threshold voltage, etc.

[0151] By the above-mentioned memory operation method, not only multi-level storage can be achieved, but also the read window margin can be increased, and better control uniformity can be achieved, thereby solving the read window margin problem in multi-level storage.

[0152] Further, according to the above-mentioned memory operation method, and with reference to Figure 1 and Figure 2 Some embodiments of the present application also provide a memory 200, which comprises:

[0153] a storage array 10 comprising a plurality of rows and a plurality of columns of storage cells 11 arranged in a matrix, two poles of each of the storage cells 11 being connected to a word line WLn and a bit line BLn, and one of the storage cells 11 comprising a first sub-storage cell 111 and a second sub-storage cell 112 connected in series between the two poles;

[0154] a peripheral circuit 20 configured to bias the two poles of the storage cell 11 in a first direction to cause the storage cell to have a first threshold state or a second threshold state; and

[0155] bias the two poles of the storage cell 11 in a second direction to cause the storage cell to have a third threshold state or a fourth threshold state, the first direction being opposite to the second direction.

[0156] In some embodiments, the first sub-memory cell comprises a SOM memory cell (selector only memory cell), also known as a SSM memory cell (self-selecting memory cell), and the second sub-memory cell comprises a PCM memory device. The phase change memory cell 112 comprises one or more phase change materials such as a germanium-antimony-tellurium (Ge-Sb-Te, GST)-based material, one example of which can be Ge2Sb2Te5. The phase change materials that are currently used by various institutions are chalcogenides (represented by Intel) and synthetic materials containing germanium, antimony, and tellurium (GST), such as Ge2Sb2Te5. The SOM memory cell is composed of a phase change material such as Ge-Te-As-Si.

[0157] Further referring to Figure 7 and Figure 8 In some embodiments, the peripheral circuit 20 comprises a word line driver 212 configured to apply a first direction first bias V111 to the memory cell 11 to generate a 1-1-1 threshold voltage Vth111 in the first sub-memory cell 111, and

[0158] a first direction second bias V121 / V120 to the memory cell 11 to generate a 1-2-1 threshold voltage Vth121 or a 1-2-0 threshold voltage Vth120 in the second sub-memory cell 112.

[0159] Wherein the 1-1-1 threshold voltage Vth111 and the 1-2-1 threshold voltage Vth121 or the 1-2-0 threshold voltage Vth120 constitute the first threshold state and the second threshold state, respectively.

[0160] In some embodiments, the peripheral circuit 20 further comprises a bit line driver 251 configured to apply a second direction first bias V210 to the memory cell 11 to generate a 2-1-0 threshold voltage Vth210 in the first sub-memory cell 111, and

[0161] a second direction second bias V221 / V220 to the memory cell 11 to generate a 2-2-1 threshold voltage Vth221 or a 2-2-0 threshold voltage Vth220 in the second sub-memory cell 112.

[0162] Wherein the 2-1-0 threshold voltage Vth210 and the 2-2-1 threshold voltage Vth221 or the 2-2-0 threshold voltage Vth220 constitute the third threshold state or the fourth threshold state, respectively.

[0163] Specifically, the second direction second bias V121 / V120 includes a first direction set bias V121 or a first direction reset bias V120. The second direction second bias V221 / V220 includes a second direction set bias V221 or a second direction reset bias V220.

[0164] Still further as Figure 9 With Figure 10 shown in some embodiments, Figure 1 The peripheral circuit 20 shown includes a word line driver 212, but the write bias applied by the word line driver 212 is to apply a first direction single bias V31 to the memory cell 11 to take the memory cell to a first threshold state or a second threshold state, and the first direction single bias includes:

[0165] a first direction set bias V31 to the memory cell 11 to generate a 3-1-1 threshold voltage in the first sub-memory cell 111 and a 3-2-1 threshold voltage in the second sub-memory cell 112; or

[0166] a first direction reset bias V30 to the memory cell 11 to generate a 3-1-1 threshold voltage in the first sub-memory cell 111 and a 3-2-0 threshold voltage in the second sub-memory cell 112;

[0167] wherein the 3-1-1 threshold voltage and the 3-2-1 threshold voltage constitute the first threshold state, and the 3-1-1 threshold voltage and the 3-2-0 threshold voltage constitute the second threshold state.

[0168] In some embodiments, the peripheral circuit 20 includes a bit line driver 251 to apply a second direction single bias to the memory cell 11 to take the memory cell 11 to a third threshold state or a fourth threshold state, and the second direction single bias includes:

[0169] a second direction set bias to generate a 4-1-0 threshold voltage in the first sub-memory cell 111 and a 4-2-1 threshold voltage in the second sub-memory cell 112; or

[0170] a second direction reset bias to generate a 4-1-0 threshold voltage in the first sub-memory cell 111 and a 4-2-0 threshold voltage in the second sub-memory cell 112;

[0171] wherein the 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-0 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

[0172] In some embodiments, the 3-1-1 threshold voltage is a set threshold voltage, the 3-2-1 threshold voltage is a set threshold voltage, the 3-2-0 threshold voltage is a reset threshold voltage, the 4-1-0 threshold voltage is a reset threshold voltage, the 4-2-1 threshold voltage is a set threshold voltage, and the 4-2-0 threshold voltage is a reset threshold voltage. In this configuration, not only can multi-level storage be achieved, but the read window margin can be increased, and better control uniformity can be achieved, thereby solving the problem of read window margin in multi-level storage.

[0173] According to some embodiments of the present application, as shown in Figure 11 Also provided is a storage system 400, as shown in

[0174] A controller 40 is electrically connected to the memory 200, and is configured to control the memory 200.

[0175] The word line driver 212 and the bit line driver 251 are controlled by the logic control module 230 in the memory 200, and the operation methods described in the above embodiments can be performed.

[0176] In some embodiments, the storage system can be implemented in the form of a universal flash storage (UFS) device, a solid state disk (SSD), a multimedia card in the form of an RS-MMC, an eMMC, an MMC, an SD, a miniSD, and a microSD, a storage device in the form of a personal computer memory card international association (PCMCIA) card, a storage device in the form of a peripheral component interconnect (PCI), a storage device in the form of a high-speed PCI (PCI-E), a compact flash (CF) card, a smart media card, or a memory stick, etc.

[0177] The above descriptions of the embodiments are only used to help understand the technical solutions and the core ideas of the present application; those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.< / n> < / m>

Claims

1. A method of operating a memory, the method comprising: The operating method includes: applying two different biases of a first direction to two poles of a storage cell in a storage array, which is formed by a first sub-storage cell and a second sub-storage cell in series, to make one of the first sub-storage cell and the second sub-storage cell have a different threshold state and the other have a same threshold state, to obtain a first threshold state and a second threshold state of the storage cell, respectively; and applying two different biases of a second direction to the two poles of the storage cell to make one of the first sub-storage cell and the second sub-storage cell have a different threshold state and the other have a same threshold state, to obtain a third threshold state and a fourth threshold state of the storage cell, respectively, wherein the first direction and the second direction are opposite to each other in polarity of the two poles, and the same threshold state under the first direction and the same threshold state under the second direction have different threshold values.

2. The operating method of memory according to claim 1, wherein, The operating method includes using a SOM storage device as the first sub-storage cell and using a PCM storage device as the second sub-storage cell. 3.The method of claim 1, wherein, The step of applying the first direction includes: applying a first direction first bias to the storage cell to generate a 1-1-1 threshold voltage in the first sub-storage cell; and applying a first direction second bias to the storage cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-storage cell; wherein the 1-1-1 threshold voltage and the 1-2-1 threshold voltage constitute the first threshold state, and the 1-1-1 threshold voltage and the 1-2-0 threshold voltage constitute the second threshold state.

4. The operating method of memory according to claim 3, wherein, The step of applying the first direction second bias includes: applying a first direction set bias to the storage cell to generate the 1-2-1 threshold voltage in the second sub-storage cell; or applying a first direction reset bias to the storage cell to generate the 1-2-0 threshold voltage in the second sub-storage cell.

5. The method of operating memory according to claim 3 or 4, characterized in that, The step of applying the second direction includes: applying a second direction first bias to the storage cell to generate a 2-1-0 threshold voltage in the first sub-storage cell; and applying a second direction second bias to the storage cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-storage cell; wherein the 2-1-0 threshold voltage and the 2-2-1 threshold voltage constitute the third threshold state, and the 2-1-0 threshold voltage and the 2-2-0 threshold voltage constitute the fourth threshold state.

6. The operating method of memory according to claim 5, wherein, The step of applying the second direction second bias includes: applying a second direction set bias to the storage cell to generate the 2-2-1 threshold voltage in the second sub-storage cell; or applying a second direction reset bias to the storage cell to generate the 2-2-0 threshold voltage in the second sub-storage cell.

7. The operating method of memory according to claim 6, wherein, The operating method further includes: the first 1-2-1 threshold voltage and the second 2-2-1 threshold voltage are in the same threshold level, and the first 1-2-0 threshold voltage and the second 2-2-0 threshold voltage are in the same threshold level; and the first 1-1-1 threshold voltage is a set threshold voltage, the first 1-2-1 threshold voltage is a set threshold voltage, the first 1-2-0 threshold voltage is a reset threshold voltage, the second 2-1-0 threshold voltage is a reset threshold voltage, the second 2-2-1 threshold voltage is a set threshold voltage, and the second 2-2-0 threshold voltage is a reset threshold voltage. 8.The method of operating a memory of claim 1, wherein, The step of performing the first direction biasing includes applying a first direction single bias to the memory cell to achieve a first threshold state or a second threshold state for the memory cell, and the step of applying the first direction single bias includes: applying a first direction set bias to the memory cell to generate a third 3-1-1 threshold voltage in the first sub-memory cell and a third 3-2-1 threshold voltage in the second sub-memory cell; or applying a first direction reset bias to the memory cell to generate a third 3-1-1 threshold voltage in the first sub-memory cell and a third 3-2-0 threshold voltage in the second sub-memory cell; wherein the third 3-1-1 threshold voltage and the third 3-2-1 threshold voltage form the first threshold state, and the third 3-1-1 threshold voltage and the third 3-2-0 threshold voltage form the second threshold state.

9. The operating method of memory according to claim 8, wherein, The step of performing the second direction biasing includes applying a second direction single bias to the memory cell to achieve a third threshold state or a fourth threshold state for the memory cell, and the step of applying the second direction single bias includes: applying a second direction set bias to the memory cell to generate a fourth 4-1-0 threshold voltage in the first sub-memory cell and a fourth 4-2-1 threshold voltage in the second sub-memory cell; or applying a second direction reset bias to the memory cell to generate a fourth 4-1-0 threshold voltage in the first sub-memory cell and a fourth 4-2-0 threshold voltage in the second sub-memory cell; the fourth 4-1-0 threshold voltage and the fourth 4-2-1 threshold voltage form the third threshold state, and the fourth 4-1-0 threshold voltage and the fourth 4-2-0 threshold voltage form the fourth threshold state.

10. The operating method of memory according to claim 9, wherein, The operation method further includes: the third 3-2-1 threshold voltage and the fourth 4-2-1 threshold voltage are in the same threshold level, and the third 3-2-0 threshold voltage and the fourth 4-2-0 threshold voltage are in the same threshold level; and the third 3-1-1 threshold voltage is a set threshold voltage, the third 3-2-1 threshold voltage is a set threshold voltage, the third 3-2-0 threshold voltage is a reset threshold voltage, the fourth 4-1-0 threshold voltage is a reset threshold voltage, the fourth 4-2-1 threshold voltage is a set threshold voltage, and the fourth 4-2-0 threshold voltage is a reset threshold voltage.

11. A memory, comprising: The memory includes: A memory array including a plurality of rows and columns of memory cells arranged in a matrix, two poles of each of the memory cells being connected to a word line and a bit line, respectively, and one of the memory cells including a first sub-memory cell and a second sub-memory cell connected in series between the two poles; a peripheral circuit configured to apply two different biases of a first direction to the two poles of the memory cell, one of the first sub-memory cell and the second sub-memory cell having a different threshold state and the other having a same threshold state, to obtain a first threshold state and a second threshold state of the memory cell, respectively; and apply two different biases of a second direction to the two poles of the memory cell, one of the first sub-memory cell and the second sub-memory cell having a different threshold state and the other having a same threshold state, to obtain a third threshold state and a fourth threshold state of the memory cell, respectively, the first direction and the second direction being opposite in polarity, and the same threshold state under the first direction and the same threshold state under the second direction having different threshold values.

12. The memory of claim 11, wherein, The first sub-memory cell includes a SOM memory device, and the second sub-memory cell includes a PCM memory device.

13. The memory of claim 11, wherein, The peripheral circuit includes a word line driver to apply a first bias of a first direction to the memory cell to generate a 1-1-1 threshold voltage in the first sub-memory cell; and apply a first bias of a second direction to the memory cell to generate a 1-2-1 threshold voltage or a 1-2-0 threshold voltage in the second sub-memory cell; wherein the 1-1-1 threshold voltage and the 1-2-1 threshold voltage constitute the first threshold state, and the 1-1-1 threshold voltage and the 1-2-0 threshold voltage constitute the second threshold state.

14. The memory of claim 13, wherein, The peripheral circuit further includes a bit line driver to apply a second bias of a first direction to the memory cell to generate a 2-1-0 threshold voltage in the first sub-memory cell; and apply a second bias of a second direction to the memory cell to generate a 2-2-1 threshold voltage or a 2-2-0 threshold voltage in the second sub-memory cell; wherein the 2-1-0 threshold voltage and the 2-2-1 threshold voltage constitute the third threshold state, and the 2-1-0 threshold voltage and the 2-2-0 threshold voltage constitute the fourth threshold state.

15. The memory of claim 13, wherein, The first bias of the second direction includes a first direction set bias or a first direction reset bias, and the second bias of the second direction includes a second direction set bias or a second direction reset bias.

16. The memory of claim 14, wherein, The 1-1-1 threshold voltage is a set threshold voltage, the 1-2-1 threshold voltage is a set threshold voltage, the 1-2-0 threshold voltage is a reset threshold voltage, the 2-1-0 threshold voltage is a reset threshold voltage, the 2-2-1 threshold voltage is a set threshold voltage, and the 2-2-0 threshold voltage is a reset threshold voltage.

17. The memory of claim 11, wherein, The peripheral circuit includes a word line driver to apply a first direction single bias to the memory cell to take the memory cell to a first threshold state or a second threshold state, and the first direction single bias includes: a first direction set bias to the memory cell to generate a 3-1-1 threshold voltage in the first sub-memory cell and a 3-2-1 threshold voltage in the second sub-memory cell; or a first direction reset bias to the memory cell to generate a 3-1-1 threshold voltage in the first sub-memory cell and a 3-2-0 threshold voltage in the second sub-memory cell; wherein the 3-1-1 threshold voltage and the 3-2-1 threshold voltage constitute the first threshold state, and the 3-1-1 threshold voltage and the 3-2-0 threshold voltage constitute the second threshold state.

18. The memory of claim 17, wherein, The peripheral circuit further includes a bit line driver to apply a second direction single bias to the memory cell to take the memory cell to a third threshold state or a fourth threshold state, and the second direction single bias includes: a second direction set bias to generate a 4-1-0 threshold voltage in the first sub-memory cell and a 4-2-1 threshold voltage in the second sub-memory cell; or a second direction reset bias to generate a 4-1-0 threshold voltage in the first sub-memory cell and a 4-2-0 threshold voltage in the second sub-memory cell; wherein the 4-1-0 threshold voltage and the 4-2-1 threshold voltage constitute the third threshold state, and the 4-1-0 threshold voltage and the 4-2-0 threshold voltage constitute the fourth threshold state.

19. The memory of claim 18, wherein, The 3-1-1 threshold voltage is a set threshold voltage, the 3-2-1 threshold voltage is a set threshold voltage, the 3-2-0 threshold voltage is a reset threshold voltage, the 4-1-0 threshold voltage is a reset threshold voltage, the 4-2-1 threshold voltage is a set threshold voltage, and the 4-2-0 threshold voltage is a reset threshold voltage.

20. A storage system, characterized by comprising: the memory of any one of claims 11-19; a controller electrically connected to the memory, configured to control the memory.

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