Method, system and maintenance method for predicting processing time of a plasma etching chamber

Abstract

The application provides a processing time prediction method, system and maintenance method of a plasma etching cavity. The processing time prediction method obtains the consumption rate of at least one position of the edge of a test control wafer with the same or similar material as the edge ring under a new process through experiments, as the consumption rate of the corresponding position of the edge ring under the new process. Thus, the processing time of the plasma etching cavity under the new process can be estimated according to the processing time (MTBC) of the plasma etching cavity under the existing process, the consumption rate of the corresponding position of the edge ring under the existing process and the consumption rate of the corresponding position of the edge ring under the new process. The processing time of the plasma etching cavity under the new process can be evaluated in a relatively timely and accurate manner at a low cost, so that the risk caused by the introduction of the new process can be avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method, system and maintenance method for predicting the processing time of a plasma etching cavity. Background Technology

[0002] Plasma etching is one of the commonly used etching methods in the etching process of semiconductor integrated circuit manufacturing. Please refer to [link / reference]. Figure 1 The etching occurs within a vacuum reaction chamber, which contains an electrostatic chuck (ESC) 11 that carries and adsorbs the wafer to be etched. An expendable edge ring 12 is typically provided around the outer periphery of the electrostatic chuck 11 to improve the etching uniformity and consistency of the wafer edge.

[0003] Please continue to refer to this. Figure 1 The height of the edge ring 12 has a crucial impact on the etching rate and plasma orientation of the wafer 20 edge. As process time and usage increase, the edge ring 12 gradually thins and tilts due to plasma consumption, leading to an increasingly faster etching rate and a more inward tilt of the plasma orientation. This negatively impacts product performance and yield. When the morphology of the edge ring 12 affects the product beyond the process window, maintenance (PM) is required to replace the edge ring 12. The time interval between two period maintenance (PM) sessions in the etching chamber is typically defined as the mean time between clean (MTBC). Clearly, on a plasma etching machine, the consumption of the edge ring 12 is the most important factor determining the MTBC.

[0004] Furthermore, in plasma etching equipment, due to the different process parameters such as process gas and RF power of different processes (also known as process recipes), the consumption rate of the edge ring varies. When a new process is introduced for product manufacturing, if its impact on the edge ring cannot be predicted in advance, the potential risks of the introduced new process cannot be avoided. In particular, when the consumption rate of the edge ring by the new process increases, the MTBC should theoretically decrease. If the MTBC remains unchanged, the risk of yield deterioration due to excessive edge ring consumption in the later stage will increase.

[0005] Therefore, there is an urgent need to develop a method, system, and maintenance method for predicting the processing time of a plasma etching cavity, which can be used to assess the processing time of a new process in advance before its introduction through offline simulation, and then avoid potential risks based on the assessment results. Summary of the Invention

[0006] The purpose of this invention is to provide a method, system, and maintenance method for predicting the processing time of a plasma etching cavity, which can assess the processing time of the etching cavity at a lower cost and relatively timely and accurate before the introduction of a new process, thereby avoiding the risks brought about by the introduction of a new process.

[0007] To achieve the above objectives, the present invention provides a method for predicting the processing time of a plasma etching cavity, comprising:

[0008] Experimental steps: Before introducing the new process for product manufacturing, a test control wafer is loaded into a plasma etching chamber with an edge ring, and the test control wafer is plasma etched using the new process. The material of the test control wafer is the same as or similar to that of the edge ring. During the plasma etching, the test control wafer and the edge ring are consumed simultaneously.

[0009] Key data acquisition steps: acquire the consumption rate at at least one location of the test control wafer, and acquire the processing time of the plasma etching cavity and the consumption rate at the corresponding location of the edge ring under the existing process;

[0010] Prediction Step: Based on the consumption rate at at least one location of the test control chip, the processing time of the plasma etching cavity under the existing process, and the consumption rate at the corresponding location of the edge ring, the processing time of the plasma etching cavity under the new process is predicted.

[0011] Optionally, in the experimental steps, the plasma etching cavity is first subjected to fabless automatic cleaning before the test control chip is loaded into the plasma etching cavity with the edge ring.

[0012] Optionally, in the experimental steps, after the test control chip is loaded into the plasma etching chamber with an edge ring and before the plasma etching is performed, a protective film is first deposited in the plasma etching chamber. The protective film covers the inner surface of the plasma etching chamber, the surface of the edge ring, and the surface of the test control chip. During the plasma etching, the plasma first simultaneously etches away the protective film on the surface of the edge ring and the surface of the test control chip, and then simultaneously etches away the edge ring and the test control chip.

[0013] Optionally, after the plasma etching is performed and before the consumption rate of at least one location of the test control wafer is obtained, the test control wafer is removed and the plasma etching cavity is subjected to a new process-based fabless automatic cleaning, and then the test control wafer is moved back into the plasma etching cavity; and / or, the test control wafer is left in the plasma etching cavity and the plasma etching cavity is subjected to a new process-based automatic cleaning.

[0014] Optionally, in the experimental step, before loading the test control wafer into the plasma etching chamber, an initial measurement is performed on the test control wafer using a corresponding measuring tool to obtain the thickness at at least one location on the edge of the test control wafer, the at least one location including a corresponding location on the front side and / or a corresponding location on the sidewall of the edge of the test control wafer; in the key data acquisition step, the test control wafer is measured again using the measuring tool to obtain the thickness at at least one location on the edge of the test control wafer after plasma etching, and based on the results of the initial measurement, the results of the second measurement, and the working time of the plasma etching chamber in the experimental step, the consumption rate at at least one location on the edge of the test control wafer is obtained.

[0015] Optionally, in the key data acquisition step, production data, edge ring consumption data, and equipment maintenance data from multiple batches of products produced using the existing process are collected to obtain the processing time of the plasma etching cavity and the consumption rate of the corresponding edge ring position under the existing process; or, the experimental steps are performed using a corresponding test control wafer and the existing process to obtain the processing time of the plasma etching cavity and the consumption rate of the corresponding edge ring position under the existing process.

[0016] Optionally, the consumption rate of at least one location of the test control wafer under the new process includes the consumption rate R1_new of the corresponding location on the front side of the test control wafer edge and / or the consumption rate R2_new of the corresponding location on the sidewall. The processing time of the plasma etching chamber under the existing process is MTBC_bsl. The consumption rate of the corresponding location of the edge ring under the existing process includes the consumption rate R1_bsl of the corresponding location on the front side of the edge ring and / or the consumption rate R2_bsl of the corresponding location on the sidewall. Then, the processing time of the plasma etching chamber under the new process obtained in the estimation step is MTBC_new = MTBC_bsl / / R_new.

[0017] Where R_new = R1_new / R1_bsl, or R_new = R2_new / R2_bsl, or R_new = max[(R1_new / R1_bsl),(R2_new / R2_bsl)], and R_new is the ratio of the consumption rate under the new process to the consumption rate under the existing process.

[0018] Based on the same inventive concept, the present invention also provides a processing time prediction system for a plasma etching cavity, comprising:

[0019] At least one test control chip, the material of which is the same as or similar to the edge ring in the plasma etching chamber, and at least a portion of the test control chips are loaded into the plasma etching chamber having the edge ring before being introduced into the new process for product manufacturing, and are plasma etched and consumed synchronously with the edge ring under the new process;

[0020] A key data acquisition component is used to acquire the consumption rate of at least one location of the test control wafer that is plasma etched and consumed under the new process, and to acquire the processing time of the plasma etching cavity and the consumption rate of the corresponding location of the edge ring under the existing process. The processing time of the plasma etching cavity under the new process is obtained based on the consumption rate of at least one location of the test control wafer, the processing time of the plasma etching cavity and the consumption rate of the corresponding location of the edge ring under the existing process.

[0021] Optionally, a portion of the test control wafers are loaded into a plasma etching chamber with the edge ring before being introduced into a new process for product manufacturing, and are simultaneously plasma etched and consumed along with the edge ring under the new process; another portion of the test control wafers are loaded into a plasma etching chamber with the edge ring, and are simultaneously plasma etched and consumed along with the edge ring under the existing process.

[0022] Alternatively, the processing time of the plasma etching cavity under the new process is MTBC_new=MTBC_bsl / R_new, and R_new=R1_new / R1_bsl, or R_new=R2_new / R2_bsl, or R_new=max[(R1_new / R1_bsl),(R2_new / R2_bsl)];

[0023] Wherein, R_new is the ratio of the consumption rate under the new process to the consumption rate under the existing process, R1_new is the front consumption rate at the edge of the test control wafer under the new process, R2_new is the sidewall consumption rate at the edge of the test control wafer under the new process, MTBC_bsl is the processing time of the plasma etching chamber under the existing process, R1_bsl is the front consumption rate of the edge ring under the existing process, and R2_bsl is the sidewall consumption rate of the edge ring under the existing process.

[0024] Based on the same inventive concept, the present invention also provides a method for maintaining a plasma etching cavity, comprising:

[0025] Plasma etching is performed on the wafer in the plasma etching chamber using existing processes, and equipment maintenance is performed on the plasma etching chamber based on the processing time of the plasma etching chamber under the existing processes.

[0026] A new process is used to perform plasma etching on the wafer in the plasma etching cavity, and the plasma etching cavity is maintained based on the processing time of the plasma etching cavity under the new process. The processing time of the plasma etching cavity under the new process is obtained by the plasma etching cavity processing time prediction method or the plasma etching cavity processing time prediction system as described in this invention.

[0027] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0028] 1. By experimentally obtaining the consumption rate at at least one location of a test control wafer with the same or similar material as the edge ring under the new process, this rate can be used as the consumption rate of the corresponding location of the edge ring under the new process. Based on the processing time (MTBC) of the plasma etching chamber under the existing process, the consumption rate of the corresponding location of the edge ring, and the consumption rate of the corresponding location of the edge ring under the new process, the processing time of the plasma etching chamber under the new process can be estimated. This allows for a relatively cost-effective and timely assessment of the processing time of the plasma etching chamber under the new process, thereby avoiding the risks associated with the introduction of the new process.

[0029] 2. The experimental procedure is designed to fully consider factors that affect the edge ring consumption, such as the formation of the protective film in the plasma etching chamber, post-etching cleaning, and different processes. This allows the test control chip to 100% simulate the entire edge ring consumption process, thereby improving the accuracy of the predicted processing time of the plasma etching chamber under the new process.

[0030] 3. By using the ratio of the side consumption rate to the front consumption rate, or the ratio of the side consumption rate to the front consumption rate, or the maximum of the two, the processing time of the plasma etching cavity under the new process can be estimated. This can improve the error caused by the difference between the measurement position and the material of the test control chip and the actual edge ring, and further improve the accuracy of the prediction of the processing time of the plasma etching cavity under the new process. Attached Figure Description

[0031] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0032] Figure 1 This is a schematic diagram illustrating the changes in the edge ring height and plasma direction within the plasma etching cavity under any process.

[0033] Figure 2 This is a schematic diagram showing the change in edge ring height with plasma etching chamber operating time under existing and new processes.

[0034] Figure 3 This is a flowchart illustrating the method for predicting the processing time of a plasma etching cavity according to a specific embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram illustrating the changes within the plasma etching cavity during the experimental steps of the plasma etching cavity processing time prediction method according to a specific embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram showing the changes inside the plasma etching cavity in a specific embodiment of the plasma etching method of the present invention. Detailed Implementation

[0037] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the terms "and / or" include any and all combinations of the associated listed items. The "Processing Time in Plasma Etching Chamber" (MTBC) in this document refers to the time interval between two equipment maintenance procedures performed due to edge ring wear under normal circumstances.

[0038] In plasma etching equipment, when a new process is introduced, if the new process consumes edge rings at a faster rate than the existing process, such as... Figure 2 As shown, the reasons for its potential risks are analyzed as follows:

[0039] First, the height of the new edge ring is A, and the MTBC corresponding to the existing process M1 is Y. Then, during the entire MTBC period (i.e., within the duration of Y) of the existing process M1, the height of the edge ring will be consumed from A to B. Here, B is the limit value of the preset safe height of the edge ring in the existing process, and MTBC=Y is the processing time of the etching cavity under the existing process, that is, the interval between two openings of the etching cavity and equipment maintenance due to the consumption of the edge ring when there is no unexpected failure.

[0040] Second, because the new process consumes edge rings faster than the existing process, the new process will consume the height of the edge ring from A to B in a relatively short time X, and then continue to consume the height of the edge ring from B to C in the time from X to Y.

[0041] In other words, after the new process is introduced, the actual MTBC=X is shorter than the MTBC=Y of the existing process. If the MTBC=Y of the existing process is still used for etching cavity maintenance after the new process is introduced, it will pose a risk to the manufactured products and may very likely result in wasted production capacity.

[0042] Therefore, the following two methods are commonly used in existing technologies to predict the impact of new processes on the edge ring in advance:

[0043] Method 1: A simulation experiment (dummy season) is conducted using a new process and a large number of control wafers. After the simulation experiment, the etching chamber is opened to measure the size of the edge ring. The actual consumption rate of the edge ring is calculated based on the process time (RF hour) of the etching chamber in the experiment. This method has the following disadvantages: (1) It requires a long simulation experiment to obtain results, the experimental data lacks timeliness, and it wastes production capacity; (2) It requires high measurement accuracy, and the consumption rate of the edge ring varies with the distance between the edge ring and the plasma. If only a partial MTBC seasoning is performed, the results obtained will differ from the actual results; (3) It requires a long simulation experiment, and the edge ring and other parts in the etching chamber are also consumed, which requires additional costs and wastes the edge ring and control wafers in the etching chamber.

[0044] Method 2: After a large number of product processes are completed, the consumption of edge rings is assessed by periodically detecting the etching rate, or by measuring the inline yield of existing products and the physical characteristics of the edge rings after use. This method has the following drawbacks: it has already affected some existing products and the impact is irreversible. If the new process introduced consumes edge rings faster and also affects some existing products (e.g., from...), the consumption may be further exacerbated. Figure 2 If the production time (MTBC) of the products manufactured within the time frame from X to Y has a negative impact, it is necessary to shorten the processing time (MTBC) or add radio frequency constraints to the existing process to make the MTBC of the existing process and the new process as comparable as possible. However, this requires a long period of data accumulation on the production line to make the adjustment in place, which is not timely and can easily lead to waste of production capacity.

[0045] Therefore, there is a need for a method, system, and method for predicting the processing time of a plasma etching cavity, which can accurately and timely assess the processing time of a new process in a low-cost manner before its introduction, using offline simulation. Based on the assessment results, timely equipment maintenance can be carried out to avoid the risks that may arise from the introduction of the new process and to prevent waste of production capacity.

[0046] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0047] Please refer to Figure 3 An embodiment of the present invention provides a method for predicting the processing time of a plasma etching cavity, comprising:

[0048] S1 (Experimental Steps): Before introducing the new process for product manufacturing, a test control wafer is loaded into a plasma etching chamber with an edge ring, and the test control wafer is plasma etched using the new process. The material of the test control wafer is the same as or similar to that of the edge ring. During the plasma etching, the test control wafer and the edge ring are consumed simultaneously.

[0049] S2 (Key Data Acquisition Step): Acquire the consumption rate at at least one location of the test control wafer, and acquire the processing time of the plasma etching cavity and the consumption rate at the corresponding location of the edge ring under the existing process.

[0050] S3 (Estimation Step): Based on the consumption rate at at least one location of the test control chip, the processing time of the plasma etching cavity under the existing process, and the consumption rate at the corresponding location of the edge ring, the processing time of the plasma etching cavity under the new process is estimated.

[0051] Please refer to Figure 4 As an example, the flow of S1 (experimental steps) includes:

[0052] S11, please refer to Figure 4 In step (A), before introducing the new process and before loading the test control chip 21 into the plasma etching chamber, a fabless automatic cleaning (WAC clean) is performed on the plasma etching chamber. In this step, a cleaning gas (not shown) and a purge gas (not shown) can be introduced sequentially or simultaneously into the plasma etching chamber. The cleaning gas, for example, is oxygen, sulfur hexafluoride, nitrogen trifluoride, carbon tetrafluoride, or chlorine, which can be ionized into plasma by the plasma etching chamber to clean residual products left from previous processes. The purge gas, for example, is an inert gas such as argon or helium, which can purge the inner surface of the plasma etching chamber and the exposed surfaces of components such as the electrostatic adsorption chuck 11 inside, thereby removing the cleaning gas and the cleaned residual products from the plasma etching chamber, thus providing a clean etching environment for the execution of the new process.

[0053] S12, please refer to Figure 4In step (A), after completing the fabless automatic cleaning (WAC clean), the corresponding test control chip 21 is loaded onto the electrostatic adsorption chuck 11 within the plasma etching chamber. The outer periphery of the test control chip 21 is surrounded by an edge ring 12. This edge ring 12 can be brand new or not brand new, but is preferably brand new. This avoids the height of the edge ring 12 dropping below the safety limit during the experiment, which would affect the accuracy of the predicted results. In addition, the material of the test control chip 21 needs to be the same as or similar to that of the edge ring 12, thereby ensuring that each position on the edge of the test control chip 21 can 100% simulate the consumption rate of the corresponding position on the edge ring 12 in the subsequent process. For example, when the edge ring 12 is made of glass, the material of the test control chip 21 can be glass, silicon dioxide, or a composite structure in which silicon dioxide is deposited on the surface of a silicon wafer.

[0054] S13, please refer to Figure 4 In step (B), a corresponding deposition gas is introduced into the plasma etching chamber. This deposition gas can form a protective film 13 on the inner surface of the plasma etching chamber, the exposed surfaces of components such as the edge ring 12 inside the plasma etching chamber, and the surface of the test control chip 21. Further combined with... Figure 5 In (A) and (B), the formation process of the protective film 13 can be the same as the process used in existing product manufacturing processes to form a protective film before plasma etching. Specifically, by adjusting process parameters such as the flow rate of the deposition gas, gas pressure, RF power, electrode current, and deposition time, the protective film 13 can be deposited on the surface of the test control wafer 21, the inner surface of the plasma etching chamber, and the exposed surfaces of all components except the electrostatic chuck 11. Furthermore, the uniformity and thickness of the protective film 13 can be controlled, thereby eliminating the influence of differences in surface properties between various structures within the plasma etching chamber on subsequent new process technologies and improving the accuracy of predicting the processing time of the plasma etching chamber under the new process.

[0055] S14, please refer to Figure 4In section (C), a new process is used to perform plasma etching on the test control wafer 21. During this process, the process gas in the plasma etching chamber and its process parameters such as flow rate, gas pressure, RF power, electrode current, and deposition time are all limited by the process formula of the new process, and the plasma direction in this plasma etching is vertically downward. In this embodiment, the protective film 13 formed in step S13 has the same thickness and material as the protective film formed in the existing process, and the thickness of the protective film 13 in step S14 is insufficient to support the completion of plasma etching under the new process, so that the plasma etching consumes the edge ring 12 and the test control chip 21. During the vertically downward plasma etching process, the consumption rate of the protective film 13 on the upper surface of the edge ring 12 and other components and the entire upper surface of the test control chip 21 is relatively large, while the consumption rate of the protective film on the inner sidewall and top surface of the plasma etching cavity is relatively small. Moreover, the edge ring 12 and the test control chip 21 are made of the same or similar materials. Therefore, the protective film 13 on the upper surface of the edge ring 12 and the upper surface of the test control chip 21 is quickly etched away synchronously. Afterwards, the edge ring 12 and the test control chip 21 continue to be synchronously etched and consumed under the new process. During this process, the consumption rate of the edge of the test control chip 21 can simulate the consumption rate of the edge ring 12 by 100%. It should be understood that in other embodiments of the present invention, when the thickness of the protective film 13 is sufficiently thick, the plasma etching under the new process is insufficient to completely consume the protective film 13. After the plasma etching is completed, the surfaces of the edge ring 12 and the test control chip 21 are still covered and protected by the protective film 13, so there will be no consumption. At this time, the consumption rate of the edge of the test control chip 21 and the consumption rate of the edge ring 12 are both 0. The consumption rate of the edge of the test control chip 21 can also be regarded as being able to 100% simulate the consumption rate of the edge ring 12.

[0056] S15, please refer to Figure 4In step (D), after the new process is completed, the plasma etching chamber can be automatically cleaned after etching without removing the test control wafer 21. In this case, the automatic cleaning process after etching consumes the edge ring 12 and simultaneously consumes the test control wafer 21. Thus, the edge of the test control wafer 21 can 100% simulate the entire consumption process of the edge ring 12 after the new process is introduced. At this time, by dividing the consumption thickness at the corresponding position at the edge of the test control wafer 21 by the sum of the process time (process recipe RF on) of the new process and the automatic cleaning time after etching (i.e., dividing the thickness and time), the consumption rate at the corresponding position at the edge of the test control wafer 21 after the new process is introduced can be obtained. This is also the consumption rate of the edge ring 12 at the corresponding position after the new process is introduced. This allows for full consideration of factors that affect edge ring consumption, such as the formation of the protective film 13 in the plasma etching chamber, automatic cleaning after etching, and different processes. This enables the edge of the test control wafer to 100% simulate the entire edge ring consumption process, thereby improving the accuracy of the plasma etching chamber processing time prediction under the new process.

[0057] In other embodiments, if the process parameters such as the gas used in the post-etching automatic cleaning process are selected reasonably, and the consumption of the edge ring 12 by the automatic cleaning process after different etching processes can be ignored, then in step S15, the test control wafer 21 can be removed from the plasma etching chamber first, and then the plasma etching chamber can be automatically cleaned without wafers after etching. Afterwards, the test control wafer 21 can be transferred back to the plasma etching chamber as needed, or it can be directly transferred to the corresponding measurement tool for key data measurement. In this case, the edge of the test control wafer 21 can also simulate the entire consumption process of the edge ring 12 after the introduction of the new process 100%. At this time, by dividing the consumption thickness at the corresponding position of the edge of the test control wafer 21 by the process time (process recipe RF on) of the new process, the consumption rate of the edge of the test control wafer 21 after the introduction of the new process can be obtained, which is also the consumption rate of the edge ring 12 after the introduction of the new process.

[0058] It should be understood that the process parameters such as gas type, gas flow rate, and cleaning time used in the automatic cleaning after etching in step S15 can be the same as those in the fabless automatic cleaning process in step S11, or can be reasonably selected based on the type and degree of residual products that may be generated by the new process in step S14.

[0059] In addition, the consumption rate of the front and sidewalls at the edge of the test control wafer 21 may vary depending on the plasma etching direction. Therefore, in step S2, one or both of the consumption rate of the front and sidewalls at the edge of the test control wafer 21 can be selected, and the consumption rate of the test control wafer obtained in step S2 can be used in step S3. In order to obtain the consumption rate of the front side and the consumption rate of the sidewall at the edge of the test control wafer 21, it is necessary to obtain the consumption thickness of the front side and the sidewall at the edge of the test control wafer 21. Therefore, before the new process is introduced, it is necessary to know the initial thickness D0 (hereinafter referred to as the initial front thickness at the edge of the test control wafer 21) at at least one position on the front side of the test control wafer 21 and the initial width W0 (hereinafter referred to as the initial sidewall thickness at the edge of the test control wafer 21) at at least one position on the sidewall of the test control wafer 21. After the new process is completed, the remaining thickness D1 or D2 (i.e. the thickness of the corresponding position on the front side of the edge of the test control wafer 21 after the new process, hereinafter referred to as the current front thickness at the edge of the test control wafer 21) and W1 or W2 (i.e. the width of the corresponding position on the sidewall of the edge of the test control wafer 21 after the new process, hereinafter referred to as the current sidewall thickness at the edge of the test control wafer 21) at the corresponding position of the test control wafer 21 are obtained. Therefore, if the plasma etching cavity lacks film thickness monitoring and measurement tools, before S12 in step S1, the test control wafer 21 is first transferred to the corresponding measurement tool, and the initial frontal thickness D0 and initial sidewall thickness W0 of the edge of the test control wafer 21 are initially measured. In step S2, the test control wafer 21, after the new process is completed and removed from the plasma etching cavity, is transferred to the measurement tool used in step S1, and the current frontal thickness (D1 or D2) and current sidewall thickness (W1 or W2) of the edge of the test control wafer 21 are measured again.

[0060] Therefore, by using the difference between the initial measurement result obtained in step S1 and the remeasurement result obtained in step S2, the wear thickness (△D=D0-D1 or D0-D2) at the corresponding position on the edge front of the test control piece 21 and / or the wear thickness (△W=W0-W1 or W0-W2) at the corresponding position on the sidewall can be calculated.

[0061] If the plasma etching chamber itself has a measurement tool for film thickness monitoring, then after S12 in step S1 and before executing step S13, the initial front thickness D0 and initial sidewall thickness W0 at the edge of the test control wafer 2 are measured using the measurement tool for film thickness monitoring built into the plasma etching chamber itself. In step S2, after the new process is completed or after the automatic cleaning after etching, the current front thickness (D1 or D2) and current sidewall thickness W1 or W2) at the edge of the test control wafer 2 are measured again using the measurement tool for film thickness monitoring built into the plasma etching chamber itself. The difference between the initial measurement result obtained in step S1 and the remeasurement result obtained in step S2 is calculated to obtain the consumed thickness (ΔD=D0-D1 or D0-D2) and sidewall consumed thickness (ΔW=W0-W1 or W0-W2) of the front edge of the test control wafer 21.

[0062] It is worth noting that D0 can be the initial thickness at any position on the front side of the edge of the test control wafer 21 (or a specified position on the front side of the edge), or the average or maximum value of the initial thicknesses at multiple positions on the front side of the edge of the test control wafer 21 (or multiple specified positions on the front side of the edge); W0 can be the initial thickness at any position on the sidewall of the edge of the test control wafer 21 (or a specified position on the sidewall of the edge), or the average or maximum value of the initial thicknesses at multiple positions on the sidewall of the edge of the test control wafer 21 (or multiple specified positions on the sidewall of the edge). Correspondingly, D1 or D2 can be the current remaining thickness on the front side of the edge of the test control wafer 21 after undergoing a new process, corresponding to the measurement position of D0, or the average or maximum value of the current remaining thicknesses at multiple positions on the front side of the edge corresponding to D0; W1 or W2 can be the current remaining thickness on the sidewall of the edge of the test control wafer 21 after undergoing a new process, corresponding to the measurement position of W0, or the average or maximum value of the current remaining thicknesses at multiple positions on the sidewall of the edge of the test control wafer 21 corresponding to W0.

[0063] Optionally, after completing the remeasurement, the edge of the test control piece 21 can be further sliced ​​and scanned by scanning electron microscopy (SEM) to verify the accuracy of the consumption thickness of the front side and the sidewall of the edge of the test control piece 21, so as to ensure the accuracy of the predicted results.

[0064] In step S2, after obtaining the consumption thickness of the front edge and the sidewall of the test control wafer 21 after undergoing the new process, the consumption rate of the front edge of the test control wafer 21 after undergoing the new process can be obtained by dividing the consumption thickness △D of the front edge by the process time t after the new process is introduced, and the consumption rate of the sidewall of the test control wafer 21 after undergoing the new process can be obtained by dividing the consumption thickness △W of the sidewall by the process time t after the new process is introduced, where △D=D0-D1 or D0-D2, △W=W0-W1 or W0-W2, and t=t1 or t1+t2, where t1 is the process time of the new process (process recipe RF on), and t2 is the process time of automatic cleaning after etching after the new process.

[0065] In step S2, it is also necessary to obtain the processing time MTBC_bsl of the plasma etching cavity under the existing process, the consumption rate R1_bsl at the corresponding position on the front of the edge ring, and the consumption rate R2_bsl at the corresponding position on the sidewall. R1_bsl can be the maximum or average value of the consumption rate at multiple positions on the front of the edge ring, or the consumption rate at a specified position. R1_bsl can also be the maximum or average value of the consumption rate at multiple positions on the sidewall of the edge ring, or the consumption rate at a specified position.

[0066] One approach is to collect a large amount of historical data from the production line (such as periodic etching rate testing, product yield, edge ring height measurement data, equipment maintenance cycle, etc.) and analyze this historical data. For example, collect production data, edge ring consumption data, and equipment maintenance data from the production line when producing multiple batches of products using the existing process. This allows you to obtain the processing time MTBC_bsl of the plasma etching chamber under the existing process (which is the time interval between two equipment maintenance operations due to edge ring 12 consumption without unexpected failures, and can be the average or minimum value) and the consumption rate (i.e., R1_bsl and / or R2_bsl) at the corresponding position of the edge ring.

[0067] Another method is to use another test control chip and an existing process to perform step S1 (i.e., the experimental step), wherein the process used in step S14 of step S1 is the existing process. This is similar to obtaining the consumption rate R1_new at the corresponding position on the front of the edge ring and the consumption rate R2_new at the corresponding position on the sidewall under the new process. Similarly, the consumption rate of at least one position at the edge of the other test control chip (including the corresponding position on the front and / or the corresponding position on the sidewall of the edge of the other test control chip, which are the same as the measurement position of D0 mentioned above) is obtained (the calculation method of the rate is also the same as that under the new process). Then, the front consumption rate R1_bsl and / or the sidewall consumption rate R2_bsl of the edge ring under the existing process are obtained accordingly (i.e., using the experimental steps provided by the present invention, the consumption rate collected under both the new process and the existing process is equivalent to the consumption rate of the side (or top) of the edge ring by the consumption rate of the side (or top) of the test control chip). In addition, by collecting relevant historical data from the production line, the processing time MTBC_bsl of the plasma etching cavity under this existing process can be obtained.

[0068] In step S3, based on the key data obtained in step S2, the processing time MTBC_new of the plasma etching cavity under the new process is calculated, as exemplarily shown in the following formula:

[0069] MTBC_new=MTBC_bsl / R_new.

[0070] Where R_new = R1_new / R1_bsl, or R_new = R2_new / R2_bsl, or R_new = max[(R1_new / R1_bsl),(R2_new / R2_bsl)], and R_new is the ratio of the consumption rate under the new process to the consumption rate under the existing process, MTBC_bsl is the processing time of the plasma etching cavity under the existing process, R1_bsl is the consumption rate at the corresponding position on the front side of the edge ring under the existing process, and R1_bsl can be the maximum consumption rate on the front side of the edge ring under the existing process, the consumption rate at any specified position, or the average consumption rate at multiple specified positions, and R2_bsl is the consumption rate at the corresponding position on the sidewall of the edge ring under the existing process, and R2_bsl can be the maximum consumption rate on the sidewall at the edge under the existing process, or the average consumption rate at any specified position. R1_new is the consumption rate at the corresponding position on the front side of the edge of the test control chip under the new process, and R1_new can be the maximum consumption rate on the front side of the edge under the new process, the consumption rate at any specified position, or the average consumption rate at multiple specified positions. R2_new is the consumption rate at the corresponding position on the sidewall of the edge of the test control chip under the new process, and R2_new can be the maximum consumption rate on the sidewall of the edge under the new process, the consumption rate at any specified position, or the average consumption rate at multiple specified positions. max[] is a function to take the maximum value, which can take the larger of the ratios R1_new / R1_bsl and R2_new / R2_bsl.

[0071] In this step, the processing time MTBC_new of the plasma etching cavity under the new process is estimated by using one of the maximum values ​​of R1_new / R1_bsl, R2_new / R2_bsl, and R1_new / R1_bsl\R2_new / R2_bsl, and further combined with MTBC_bsl. This can improve the error caused by the difference between the measurement position and the material of the test control chip 21 and the actual edge ring 12, and further improve the accuracy of the prediction of the processing time of the plasma etching cavity under the new process.

[0072] As can be seen from the above description, the plasma etching cavity processing time prediction method of this embodiment can use test control wafers to conduct experimental simulations to quickly obtain the consumption rate of the front and / or sidewalls of the edge ring under the new process. Then, by combining the ratio of the consumption rate under the new process to the consumption rate under the existing process (i.e., R1_new / R1_bsl or R2_new / R2_bsl or max[(R1_new / R1_bsl),(R2_new / R2_bsl)]) and the processing time MTBC_bsl under the existing process, the processing time MTBC_new under the new process can be estimated. This can reduce the number of samples required for the experiment, shorten the estimation time, and avoid the problems of experimental costs and production capacity waste caused by obtaining the MTBC_new of the new process through a large number of long-term experiments in the prior art. It can also avoid the risks of directly introducing the new process into the production line and evaluating it while production. Finally, the processing time corresponding to the new process can be evaluated at a lower cost and relatively timely and accurately. Then, the equipment can be maintained in a timely manner based on the evaluation results, avoiding the risks that may arise from the introduction of the new process.

[0073] Preferably, the processing time MTBC_new under the new process is estimated using max[(R1_new / R1_bsl),(R2_new / R2_bsl)] and the processing time MTBC_bsl under the existing process, i.e.:

[0074] MTBC_new=MTBC_bsl / max[(R1_new / R1_bsl),(R2_new / R2_bsl)].

[0075] This also takes into account the different consumption patterns of the edge ring on the front and sidewalls under different processes (some processes consume the edge ring quickly on the front but slowly on the sidewalls, while others consume the edge ring slowly on the front but quickly on the sidewalls), thereby improving the accuracy of the prediction results for the processing time MTBC_new under the new process.

[0076] Based on the same inventive concept, please combine Figure 4 An embodiment of the present invention also provides a processing time prediction system for a plasma etching cavity, which can be used to implement the processing time prediction method for the plasma etching cavity of the present invention. The processing time prediction system includes:

[0077] At least one test control chip 21, the material of which is the same as or similar to the edge ring 12 in the plasma etching chamber, and at least a portion of the test control chips 21 are loaded into the plasma etching chamber with the edge ring 12 before being introduced into the new process for product manufacturing, and are plasma etched and consumed synchronously with the edge ring 12 under the new process.

[0078] A key data acquisition component (not shown) is used to acquire the consumption rate at at least one location of the test control wafer that is being plasma etched and consumed under the new process, and to acquire the processing time of the plasma etching cavity and the consumption rate at the corresponding location of the edge ring under the existing process. The processing time of the plasma etching cavity under the new process is obtained based on the consumption rate at at least one location of the test control wafer, the processing time of the plasma etching cavity and the consumption rate at the corresponding location of the edge ring under the existing process.

[0079] Optionally, the key data acquisition component includes corresponding measurement tools (not shown) and calculation tools (not shown). The measurement tool can be integrated into the plasma etching chamber or located outside the plasma etching chamber. Before the introduction of the corresponding process (new or existing process), it obtains the initial thicknesses D0 and W0 at the corresponding positions on the edge of the test control wafer 21. After the completion of the corresponding process (new or existing process), it obtains the remaining thicknesses D1 or D2 and W1 or W2 at the corresponding positions on the test control wafer 21. The calculation tool can use the measurement results from the measurement tool and the corresponding process time to calculate the consumption rate at the corresponding position on the front side and / or the consumption rate at the corresponding position on the sidewall of the edge ring 12 under the corresponding process. Furthermore, it can combine the consumption rates at the corresponding positions on the front side and / or the corresponding positions on the sidewall of the edge ring 12 under the new and existing processes with the processing time MTBC_bsl of the plasma etching chamber under the existing process to calculate the processing time MTBC_new of the plasma etching chamber under the new process.

[0080] MTBC_new=MTBC_bsl / R_new.

[0081] Wherein, R_new = R1_new / R1_bsl, or R_new = R2_new / R2_bsl, or R_new = max[(R1_new / R1_bsl),(R2_new / R2_bsl)], R_new is the ratio of the consumption rate under the new process to the consumption rate under the existing process, R1_new is the consumption rate at the corresponding position on the front side of the test control wafer edge under the new process, and R1_new can be the maximum consumption rate on the front side of the test control wafer edge under the new process, the consumption rate at any specified position, or the average consumption rate at multiple specified positions; R2_new is the consumption rate at the corresponding position on the sidewall of the test control wafer edge under the new process, and R2_new can be the maximum consumption rate on the sidewall of the test control wafer edge under the new process, the consumption rate at any specified position, or the average consumption rate at multiple specified positions. MTBC_bsl is the processing time of the plasma etching cavity under the existing process. R1_bsl is the consumption rate of the front side of the edge ring under the existing process, and R1_bsl can be the maximum consumption rate on the front side of the edge under the existing process, the consumption rate at any specified position, or the average consumption rate at multiple specified positions. R2_bsl is the sidewall consumption rate of the edge ring under the existing process, and R2_bsl can be the maximum consumption rate on the sidewall of the edge under the existing process, the consumption rate at any specified position, or the average consumption rate at multiple specified positions. max[] is the maximum value function, which can take the larger of the ratios R1_new / R1_bsl and R2_new / R2_bsl.

[0082] It should be understood that, in other embodiments of the present invention, the key data acquisition component may also omit the computational tool, wherein the computation can be performed manually.

[0083] Optionally, the key data acquisition component may also include a slicing device (not shown) and a scanning electron microscope (SEM, not shown). The slicing device is used to slice the edge of the test control wafer 21 after measuring the wear thickness of the front side and the wear thickness of the sidewalls of the corresponding test control wafer 21 after undergoing the new process. The scanning electron microscope is used to scan the edge of the sliced ​​test control wafer 21 to verify the accuracy of the measured wear thickness of the front side and the wear thickness of the sidewalls of the test control wafer 21, so as to ensure the accuracy of the estimated results.

[0084] Optionally, a portion of the test control wafers 21 are loaded into a plasma etching chamber with an edge ring before being introduced into the new process for product manufacturing, and are simultaneously plasma etched and consumed along with the edge ring under the new process. Another portion of the test control wafers 21 are loaded into the same plasma etching chamber with an edge ring, and are simultaneously plasma etched and consumed along with the edge ring under the existing process.

[0085] Furthermore, it should be noted that in the above embodiments, when obtaining the consumption rate at corresponding positions on the front side of the edge ring under the new and existing processes through experiments using test control wafers, at least one position on the front side of the test control wafer edge is selected for thickness measurement and consumption rate calculation. This is because the edge of the test control wafer is relatively close to the edge ring, and the plasma etching situation at the edge of the test control wafer is closer to the plasma etching situation of the edge ring, thus ensuring the accuracy of the final estimated result. However, the technical solution of the present invention is not limited to this. In other embodiments of the present invention, when the plasma etching situation of the edge region and the central region of the test control wafer is basically the same, at least one position on the front side of the central region of the test control wafer can be selected for thickness measurement and consumption rate calculation, and the calculation result can be applied to the processing time of the plasma etching cavity under the new process. Alternatively, at least one position on the front side of the central region of the test control wafer and at least one position on the front side of the edge can be selected simultaneously for thickness measurement and average consumption rate calculation, and the average calculation result can be applied to the processing time of the plasma etching cavity under the new process.

[0086] Please refer to Figure 5 Based on the same inventive concept, an embodiment of the present invention also provides a method for maintaining a plasma etching cavity, which is used to enable timely maintenance of the plasma etching cavity during product manufacturing on a production line, and includes:

[0087] First, the wafer in the plasma etching chamber is plasma etched using the existing process, and the plasma etching chamber is maintained based on the processing time of the plasma etching chamber under the existing process.

[0088] Next, the wafer in the plasma etching cavity is plasma etched using a new process, and the plasma etching cavity is maintained based on the processing time of the plasma etching cavity under the new process. The processing time of the plasma etching cavity under the new process is obtained by the plasma etching cavity processing time prediction method or the plasma etching cavity processing time prediction system as described in this invention.

[0089] The aforementioned processes of plasma etching the wafer in the plasma etching chamber using existing processes and plasma etching the wafer in the plasma etching chamber using new processes include the following steps:

[0090] First, please refer to Figure 5 In step (A), the plasma etching chamber is subjected to waferless automated cleaning (WAC clean). This process can be referred to in step S11 above and will not be described in detail here.

[0091] Next, please refer to Figure 5In step (A), a protective film (pre-coat) 13 is deposited in the plasma etching chamber. The protective film 13 covers the inner surface of the plasma etching chamber and the surfaces of components such as the edge ring 12 and the electrostatic adsorption chuck 11. This process can be referred to the content of step S13 above, and will not be described in detail here.

[0092] Then, please refer to Figure 5 In (B) and (C), the wafer 20 is loaded into the plasma etching chamber and carried and adsorbed by the electrostatic adsorption chuck 11, and the corresponding process is run.

[0093] Next, please refer to Figure 5 (C) and (D) in the process are completed after the process. The wafer 20 is removed from the plasma etching chamber and the plasma etching chamber is cleaned again with waferless automatic cleaning (WAC clean). This step can be referred to the content of step S11 or S15 above, and will not be described in detail here.

[0094] The plasma etching method in this embodiment is relatively timely and accurate because the processing time of the plasma etching cavity under the new process is obtained by the plasma etching cavity processing time prediction method or the plasma etching cavity processing time prediction system described in this invention. This avoids the problem of premature or late equipment maintenance due to inaccurate processing time assessment after the introduction of the new process.

[0095] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A method for predicting the processing time of a plasma etching cavity, characterized in that, include: Experimental steps: Before introducing the new process for product manufacturing, a test control wafer is loaded into a plasma etching chamber with an edge ring, and the test control wafer is plasma etched using the new process. During the plasma etching, the test control wafer and the edge ring are consumed simultaneously. The material of the test control wafer is the same as that of the edge ring, or the material of the test control wafer is different from that of the edge ring, but it is ensured that each position on the edge of the test control wafer 100% simulates the consumption rate of the corresponding position of the edge ring during the plasma etching. Key data acquisition steps: acquire the consumption rate at at least one location of the test control wafer, and acquire the processing time of the plasma etching cavity and the consumption rate at the corresponding location of the edge ring under the existing process; Prediction Step: Based on the consumption rate at at least one location of the test control chip, the processing time of the plasma etching cavity under the existing process, and the consumption rate at the corresponding location of the edge ring, the processing time of the plasma etching cavity under the new process is predicted.

2. The processing time prediction method as described in claim 1, characterized in that, In the experimental steps, before loading the test control chip into the plasma etching cavity with an edge ring, the plasma etching cavity is first subjected to fabless automatic cleaning prior to the new process.

3. The processing time prediction method as described in claim 1, characterized in that, In the experimental steps, after the test control chip is loaded into the plasma etching chamber with an edge ring and before the plasma etching is performed, a protective film is deposited in the plasma etching chamber. The protective film covers the inner surface of the plasma etching chamber, the surface of the edge ring, and the surface of the test control chip. During the plasma etching, the plasma first simultaneously etches away the protective film on the surface of the edge ring and the surface of the test control chip, and then simultaneously etches away the edge ring and the test control chip.

4. The processing time prediction method as described in claim 3, characterized in that, After the plasma etching is performed and before the consumption rate of at least one location of the test control wafer is obtained, the test control wafer is removed and the plasma etching cavity is subjected to a new process-initiated fabless automatic cleaning, and then the test control wafer is moved back into the plasma etching cavity; and / or, the test control wafer is left in the plasma etching cavity and the plasma etching cavity is subjected to a new process-initiated automatic cleaning.

5. The processing time prediction method according to any one of claims 1-4, characterized in that, In the experimental step, before loading the test control wafer into the plasma etching chamber, an initial measurement is performed on the test control wafer using a corresponding measuring tool to obtain the thickness at at least one location on the edge of the test control wafer. The at least one location includes a corresponding location on the front side and / or a corresponding location on the sidewall of the edge of the test control wafer. In the key data acquisition step, the test control wafer is measured again using the measuring tool to obtain the thickness at at least one location on the edge of the test control wafer after plasma etching. Based on the results of the initial measurement, the results of the second measurement, and the working time of the plasma etching chamber in the experimental step, the consumption rate at at least one location on the edge of the test control wafer is obtained.

6. The processing time prediction method according to any one of claims 1-4, characterized in that, In the key data acquisition step, production data, edge ring consumption data, and equipment maintenance data from multiple batches of products produced using the existing process are collected to obtain the processing time of the plasma etching cavity and the consumption rate of the corresponding edge ring position under the existing process; or, the experimental steps are performed using a corresponding test control wafer and the existing process to obtain the processing time of the plasma etching cavity and the consumption rate of the corresponding edge ring position under the existing process.

7. The processing time prediction method as described in claim 1, characterized in that, The consumption rate of at least one location of the test control wafer under the new process is obtained, including the consumption rate R1_new of the corresponding location on the front side of the test control wafer edge under the new process and / or the consumption rate R2_new of the corresponding location on the sidewall. The processing time of the plasma etching cavity under the existing process is obtained as MTBC_bsl. The consumption rate of the corresponding location of the edge ring under the existing process includes the consumption rate R1_bsl of the corresponding location on the front side of the edge ring and / or the consumption rate R2_bsl of the corresponding location on the sidewall. Then, the processing time of the plasma etching cavity under the new process obtained in the estimation step is MTBC_new = MTBC_bsl / R_new, where R_new = R1_new / R1_bsl, or R_new = R2_new / R2_bsl, or R_new = max[(R1_new / R1_bsl),(R2_new / R2_bsl)], and R_new It is the ratio of the consumption rate under the new process to the consumption rate under the existing process.

8. A processing time prediction system for a plasma etching cavity, characterized in that, include: At least one test control wafer, at least a portion of which is used to be loaded into a plasma etching chamber with an edge ring before being introduced into a new process for product manufacturing, and to be plasma etched and consumed synchronously with the edge ring under the new process, wherein the material of the test control wafer is the same as that of the edge ring, or the material of the test control wafer is different from that of the edge ring, but it can be ensured that each position on the edge of the test control wafer 100% simulates the consumption rate of the corresponding position of the edge ring during the plasma etching; A key data acquisition component is used to acquire the consumption rate of at least one location of the test control wafer that is plasma etched and consumed under the new process, and to acquire the processing time of the plasma etching cavity and the consumption rate of the corresponding location of the edge ring under the existing process. The processing time of the plasma etching cavity under the new process is obtained based on the consumption rate of at least one location of the test control wafer, the processing time of the plasma etching cavity and the consumption rate of the corresponding location of the edge ring under the existing process.

9. The processing time prediction system as described in claim 8, characterized in that, One portion of the test control wafers are used to be loaded into a plasma etching chamber with the edge ring before being introduced into a new process for product manufacturing, and are plasma etched and consumed synchronously with the edge ring under the new process; another portion of the test control wafers are used to be loaded into a plasma etching chamber with the edge ring, and are plasma etched and consumed synchronously with the edge ring under the existing process. Alternatively, the processing time of the plasma etching cavity under the new process is MTBC_new=MTBC_bsl / R_new, and R_new=R1_new / R1_bsl, or R_new=R2_new / R2_bsl, or R_new=max[(R1_new / R1_bsl),(R2_new / R2_bsl)]; Wherein, R_new is the ratio of the consumption rate under the new process to the consumption rate under the existing process, R1_new is the consumption rate at the corresponding position on the front side of the test control wafer edge under the new process, R2_new is the consumption rate at the corresponding position on the sidewall of the test control wafer edge under the new process, MTBC_bsl is the processing time of the plasma etching chamber under the existing process, R1_bsl is the consumption rate at the corresponding position on the front side of the edge ring under the existing process, and R2_bsl is the consumption rate at the corresponding position on the sidewall of the edge ring under the existing process.

10. A method for maintaining a plasma etching cavity, characterized in that, include: Plasma etching is performed on the wafer in the plasma etching chamber using existing processes, and equipment maintenance is performed on the plasma etching chamber based on the processing time of the plasma etching chamber under the existing processes. A new process is used to perform plasma etching on the wafer in the plasma etching cavity, and the plasma etching cavity is maintained based on the processing time of the plasma etching cavity under the new process. The processing time of the plasma etching cavity under the new process is obtained by the plasma etching cavity processing time prediction method as described in any one of claims 1-7 or the plasma etching cavity processing time prediction system as described in claim 8 or 9.

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