Preparation method of high-power planar deep passivation isolation chip
By oxidizing, doping, and silicon nitride passivation layer treatment of the silicon wafers, the isolation band and doping area are formed, and metallic treatment is performed to solve the problem of easily rupture of the glass passivation layer during packaging, which improves the high power of high power Package reliability and fault tolerance of plane chips.
Patent Information
- Application Number
- CN202411509711.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-01-24
AI Technical Summary
In the prior art, the glass passivation layer is prone to form protrusions at the corners of the grooves during sintering, resulting in stress concentration during packaging, the glass passivation layer is prone to rupture, and has high requirements for the packaging of high-power large-area planar chips.
The preparation method of a high -power plane deep passivation chip is used, including oxidation, removing oxidation layer, doping treatment, sedimentary silicon nitride passivation layer for silicon wafer And sedimentary protective layers, metallic treatment is finally performed.
Through this method, the glass passivation layer is prevented from forming bulges at the corners of the slots, the stress concentration during packaging is reduced, the damage resistance of the chip and the fault tolerance rate of the packaging are improved, and it is suitable for high-power and large-size planar chip manufacturing. .
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Figure CN119361418A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a method for preparing a high-power planar deep passivation isolation chip. Background Art
[0002] Because the slot depth of pure table chips is deep, generally more than 50μm, glass powder is usually filled in the slot, and then a glass passivation layer is formed through sintering. Due to the shrinkage of glass powder during the sintering process, a convex glass passivation layer will be formed at the corner of the edge of the slot. When the frame is packaged, the frame is easy to contact with the protrusion, causing stress concentration, which makes the glass passivation layer easy to break. Therefore, the requirements for the packaging process are relatively high. The frame will come into contact with the protrusion if it is slightly deflected, and the assembly tolerance of the packaging frame and the chip is low. In the packaging process of existing planar chips, because the PN junction and the passivation layer are both on the surface, and the passivation layer is usually also a glass passivation layer, it is easy to form a protrusion at the corner of the slot during the sintering process. For products with high power dissipation requirements, especially for large-area and high-power planar chips, the packaging frame and solder are easy to gather on the surface, which is easy to cause damage and failure. Summary of the invention
[0003] In order to solve the defect that the glass passivation layer used in the prior art is easily damaged, the present invention provides a method for preparing a high-power planar deep passivation isolation chip.
[0004] The technical solution adopted by the present invention is as follows: A method for preparing a high-power planar deep passivation isolation chip comprises the following steps:
[0005] S1, oxidizing the silicon wafer to form an oxide layer on the surface of the silicon wafer;
[0006] S2, removing the oxide layer from part of the front area;
[0007] S3, doping phosphorus or boron in the area where the oxide layer is removed by diffusion process to form a pre-doped area;
[0008] S4, depositing a silicon nitride passivation layer on the surface of the silicon wafer;
[0009] S5, removing the silicon nitride passivation layer and the oxide layer from a part of the front area of the silicon wafer, and performing etching to form an isolation zone, wherein the isolation zone extends to the edge of the pre-doped area, and the depth of the isolation zone is not less than the depth of the pre-doped area;
[0010] S6, performing a push-up process on the pre-doped region through a diffusion process to form a doped region, so that the depth of the doped region is greater than the depth of the isolation zone;
[0011] S7, removing the silicon nitride passivation layer and the oxide layer on the surface of the silicon wafer;
[0012] S8, performing doping treatment on the back side of the silicon wafer, wherein the doping type is opposite to the doping type of the pre-doped area;
[0013] S9, performing secondary oxidation on the surface of the silicon wafer and depositing a protective layer;
[0014] S10, removing the protective layer and the oxide layer on the back side and the surface of the doped area, and performing metallization treatment.
[0015] In some embodiments, before the silicon wafer is oxidized once, the silicon wafer is thinned or subjected to acid-base corrosion treatment to make the thickness of the silicon wafer 200-270 μm, and the resistivity of the silicon wafer is 0.002-50 Ω·cm.
[0016] In one embodiment, the depth of the pre-doped region formed in step S3 is 10-30 μm.
[0017] In one embodiment, the depth of the isolation zone in step S5 is 10-60 μm.
[0018] In some embodiments, in step S5 , the edge of the pre-doped region is corroded to form a portion of the isolation zone.
[0019] Specifically, the depth of the doping region in step S6 is 50-80 μm.
[0020] Preferably, in step S6, the pre-doped region is subjected to a push-in treatment by a diffusion process, and diffusion is performed at a push-in temperature of 1255°C.
[0021] Specifically, the step of depositing a protective layer in step S9 includes:
[0022] (1) Deposition of SIPOS layer: placing the chip in a furnace tube, introducing SiH4 and N2O in a volume ratio of (1.5-3):1 at a temperature of 600-700°C, and forming a SIPOS layer at a vacuum pressure of 100-500 mTorr, with a thickness of 0.5-2 μm;
[0023] (2) Deposition of silicon nitride layer: The chip is placed in a low-pressure furnace tube at a temperature of 650-800°C, and NH3 and SiH2CL2 are introduced in a volume ratio of (1.5-3):1. The vacuum pressure is formed at 100-500 mTorr, and the thickness of the deposited SiN passivation layer is 0.1-0.5 μm;
[0024] (3) Deposition of silicon dioxide layer: placing the chip in a furnace tube, introducing tetraethyl orthosilicate at a temperature of 600-800° C., and controlling the pressure at 200-500 mTorr to form a silicon dioxide layer with a thickness of 0.8-1.5 μm.
[0025] Beneficial effects: In the present invention, the deposited protective layer protects the surface of the silicon wafer, and there is no protrusion formed at the corner of the groove when sintering to form a glass passivation layer. During packaging, the stress between the frame and the chip surface is small, which reduces the chance of chip damage and makes packaging easy; and the assembly position between the frame and the chip has a high tolerance rate, and a slight misalignment between the frame and the chip will not be affected, so the reliability is higher and it is more suitable for the manufacture of high-power and large-size (above 100 mil) planar chips. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 A schematic diagram of the structure formed in step S1;
[0027] Figure 2 A schematic diagram of the structure formed in step S2;
[0028] Figure 3 A schematic diagram of the structure formed in step S3;
[0029] Figure 4 A schematic diagram of the structure formed in step S4;
[0030] Figure 5 A schematic diagram of the structure formed in step S5;
[0031] Figure 6 A schematic diagram of the structure formed in step S6;
[0032] Figure 7 A schematic diagram of the structure formed in step S7;
[0033] Figure 8 A schematic diagram of the structure formed in step S8;
[0034] Fig. 9 A schematic diagram of the structure formed in step S9;
[0035] Fig.10 This is a schematic diagram of the structure formed in step S10.
[0036] In the figure, 1. primary oxide layer, 2. pre-doped region, 3. silicon nitride passivation layer, 4. isolation zone, 5. doped region, 6. back doped region, 7. secondary oxide layer, 8. SIPOS layer, 9. silicon nitride layer, 10. silicon dioxide layer, 11. metal layer. DETAILED DESCRIPTION
[0037] The present invention will be further described below in conjunction with specific implementation methods. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative changes belong to the protection scope of the present invention.
[0038] The present invention provides a method for preparing a high-power planar deep passivation isolation chip, comprising the following steps:
[0039] S1, oxidize the silicon wafer once to form an oxide layer 1 on the surface of the silicon wafer, such as Figure 1 As shown;
[0040] Before the silicon wafer is subjected to primary oxidation, the silicon wafer is subjected to a thinning machine thinning treatment or an acid-base etching treatment so that the thickness of the silicon wafer is 200-270 μm and the resistivity of the silicon wafer is 0.002-50 Ω·cm.
[0041] The oxidation step is as follows: hydrogen and oxygen are introduced in a volume ratio of 3:2 for oxidation, the temperature is set at 900-1100°C, and the time is 3-8h.
[0042] S2, remove the primary oxide layer 1 in the front part area, such as Figure 2 as stated;
[0043] The oxide layer can be removed by photolithography, and the specific parameters of the photolithography are as follows: photoresist with a thickness of 10,000 to 40,000 angstroms, exposure time of 6 to 15 seconds, development time of 20 to 40 seconds, and the oxide layer is removed by ammonium fluoride bleaching.
[0044] S3, doping phosphorus or boron in the area where the primary oxide layer 1 is removed by diffusion process to form a pre-doped area 5, such as Figure 3 as stated;
[0045] The diffusion process is as follows: placing the silicon wafer in a diffusion furnace, carrying liquid phosphorus oxychloride into the diffusion furnace by nitrogen, diffusing at a temperature of 900-1200°C, and a diffusion time of 0.5-5h. The final resistance value of the block resistor is 0.2-20Ω, and then high-temperature junction is pushed, the highest junction push temperature is 1255°C, and the N+ junction depth of the pre-doped area 5 formed is 10-30μm.
[0046] S4, depositing a silicon nitride passivation layer 3 on the surface of the silicon wafer, such as Figure 4 as stated;
[0047] The steps are as follows: placing a silicon wafer in a low-pressure furnace tube at a temperature of 650-800°C, introducing NH3 and SiH2CL2 in a volume ratio of (1.5-3):1, forming a vacuum pressure at 100-500 mTorr, and depositing a SiN passivation layer with a thickness of 0.1-0.5 μm.
[0048] S5, removing the silicon nitride passivation layer 3 and the oxide layer in a part of the front area of the silicon wafer, and etching to form an isolation zone 4, wherein the isolation zone 4 extends to the edge of the pre-doped area 5, and the depth of the isolation zone 4 is not less than the depth of the pre-doped area 5, such as Figure 5 as stated;
[0049] The silicon nitride passivation layer 3 and the oxide layer in the corresponding area are removed by photolithography, and the photolithography process in step S2 can be used. The edge of the pre-doped area 5 is etched to form a part of the isolation zone 4, and the depth of the isolation zone 4 is 10-60 μm.
[0050] S6, performing a push-up process on the pre-doped region 5 through a diffusion process to form a doped region 5, so that the depth of the doped region 5 is greater than the depth of the isolation zone 4, such as Figure 6 as stated;
[0051] The diffusion process in this step is specifically to perform high temperature push-in diffusion at a maximum push-in temperature of 1255° C. The depth of the doping region 5 is 50-80 μm.
[0052] S7, removing the silicon nitride passivation layer 3 and the primary oxide layer 1 on the surface of the silicon wafer, such as Figure 7 as stated;
[0053] The silicon nitride passivation layer 3 on the front and back surfaces is removed by dry etching, and the oxide layer is removed by ammonium fluoride.
[0054] S8, doping the back side of the silicon wafer, wherein the doping type is opposite to the doping type of the pre-doped region 5, to form a back side doped region 6, such as Figure 8 as stated;
[0055] Among them, the specific steps of S8 are to evenly spread the latex source on the back of the chip through a glue spreader, diffuse it at a temperature of 850 to 1100°C, and finally the block resistance is between 1 and 18Ω, forming P+ on the back of the chip.
[0056] S9, re-oxidize the surface of the silicon wafer and deposit a protective layer, such as Fig. 9 as stated;
[0057] The secondary oxidation may adopt the oxidation process in S1 to form a secondary oxidation layer 7;
[0058] The steps of depositing the protective layer include:
[0059] (1) Deposition of SIPOS layer 8: placing the chip in a furnace tube, introducing SiH4 and N2O in a volume ratio of (1.5-3):1 at a temperature of 600-700°C, and forming a SIPOS layer 8 at a vacuum pressure of 100-500 mTorr, with a thickness of 0.5-2 μm;
[0060] (2) Deposition of silicon nitride layer 9: The chip is placed in a low-pressure furnace tube at a temperature of 650-800° C., NH 3 and SiH 2 Cl 2 are introduced in a volume ratio of (1.5-3):1, and a vacuum pressure is formed at 100-500 mTorr. The thickness of the deposited SiN passivation layer is 0.1-0.5 μm;
[0061] (3) Deposition of silicon dioxide layer 10: placing the chip in a furnace tube, introducing tetraethyl orthosilicate at a temperature of 600-800° C., and controlling the pressure at 200-500 mTorr to form the silicon dioxide layer 10 with a thickness of 0.8-1.5 μm.
[0062] S10, removing the protective layer and the secondary oxide layer 7 on the back surface and the surface of the doping region 5, and performing metallization treatment to form a metal layer 11, such as Fig.10 described.
[0063] Among them, SIPOS is removed by rinsing with ammonium fluoride and hydrogen peroxide in a volume ratio of 5:1, the silicon nitride layer 9 is removed by dry etching, and the silicon dioxide and oxide layer are removed by rinsing with ammonium fluoride.
[0064] The metallization treatment is to perform metallization treatment on the back surface and the surface of the doped region 5, specifically:
[0065] (1) firstly, a nickel plating is performed, in which 0.6 to 1 μm of nickel is plated on the metal area in a nickel plating solution at 80 to 95° C., then a silicon-nickel alloy is formed at a temperature of 600 to 700° C., and then a secondary nickel plating is performed, i.e., 0.8 to 1.5 μm of nickel is plated on the metal area in a nickel plating solution at 80 to 95° C.;
[0066] (2) Evaporating metal is as follows: using an evaporation table to evaporate 3-8 μm of aluminum metal on the front side of the chip, etching the metal outside the active area by photolithography, and making a metal alloy at 300-600 °C, and then evaporating the metal on the back side of the chip to complete the metallization of the chip.
[0067] The above method does not have the protrusions formed at the corners of the grooves when the glass passivation layer is sintered. During packaging, the stress between the frame and the chip surface is small, which reduces the probability of chip damage and is easy to package. In addition, the assembly position tolerance between the frame and the chip is high, and a slight misalignment between the frame and the chip will not be affected, which has higher reliability and is more suitable for the manufacture of high-power and large-size (more than 100 mil) planar chips. At the same time, after forming a pre-doped area 5 of a certain depth, an isolation belt 4 is formed, and then a high-temperature push-junction treatment is performed, which can effectively control the range of the formed doped area 5.
[0068] Example 1
[0069] The steps include:
[0070] S1, select a P-type silicon wafer with a resistivity of 10Ω·cm, use a thinning machine to thin the silicon wafer to 200μm, perform a primary oxidation on the silicon wafer, and form a primary oxide layer 1 on the surface of the silicon wafer;
[0071] The oxidation step is as follows: hydrogen and oxygen are introduced in a volume ratio of 3:2 for oxidation, the temperature is set to 900°C, and the time is 8 hours.
[0072] S2, removing the primary oxide layer 1 in a partial area of the front side;
[0073] Specifically, a photolithography process is used, and the specific parameters of the photolithography are as follows: a photoresist with a thickness of 20,000 angstroms is applied, an exposure time of 10 seconds, a development time of 25 seconds, and finally the oxide layer is removed by rinsing with ammonium fluoride.
[0074] S3, doping phosphorus in the area where the primary oxide layer 1 is removed by a diffusion process to form a pre-doped area 5;
[0075] The diffusion process is as follows: placing the silicon wafer in a diffusion furnace, carrying liquid phosphorus oxychloride into the diffusion furnace by means of nitrogen, diffusing at a temperature of 1000°C for 3 hours, and finally the resistance value of the block resistor is 5Ω, and then high-temperature junction pushing is performed, with the highest junction pushing temperature being 1255°C, and the N+ junction depth of the pre-doped region 5 formed is 10μm.
[0076] S4, depositing a silicon nitride passivation layer 3 on the surface of the silicon wafer;
[0077] The steps are as follows: placing the silicon wafer in a low-pressure furnace tube at a temperature of 700° C., introducing NH3 and SiH2CL2 in a volume ratio of 3:1, forming a vacuum pressure at 300 mTorr, and depositing a SiN passivation layer with a thickness of 0.1 μm.
[0078] S5, removing the silicon nitride passivation layer 3 and the primary oxide layer 1 from a part of the front area of the silicon wafer, and performing etching to form an isolation zone 4, wherein the isolation zone 4 extends to the edge of the pre-doped area 5, and the depth of the isolation zone 4 is not less than the depth of the pre-doped area 5;
[0079] The silicon nitride passivation layer 3 and the primary oxide layer 1 in the corresponding area are removed by photolithography, and the photolithography process in step S2 can be used. The edge of the pre-doped area 5 is etched to form a part of the isolation zone 4, and the depth of the isolation zone 4 is 20 μm.
[0080] S6, performing a push-up process on the pre-doped region 5 through a diffusion process to form a doped region 5, so that the depth of the doped region 5 is greater than the depth of the isolation zone 4;
[0081] Specifically, the diffusion process of this step is to perform high-temperature push-in diffusion at a maximum push-in temperature of 1255° C. to form a doping region 5 with a depth of 60 μm.
[0082] S7, removing the silicon nitride passivation layer 3 and the primary oxide layer 1 on the surface of the silicon wafer;
[0083] The silicon nitride passivation layer 3 on the front and back surfaces is removed by dry etching, and the oxide layer is removed by ammonium fluoride.
[0084] S8, performing doping treatment on the back side of the silicon wafer, wherein the doping type is opposite to the doping type of the pre-doped region 5, to form a back side doped region 6;
[0085] Specifically, the latex source is evenly spread on the back of the chip through a glue spreader, diffused at a temperature of 850°C, and the final block resistance is 15Ω, forming P+ on the back of the chip.
[0086] S9, performing secondary oxidation on the surface of the silicon wafer and depositing a protective layer;
[0087] The secondary oxidation adopts the oxidation process in S1 to form a secondary oxidation layer 7;
[0088] The steps of depositing the protective layer include:
[0089] (1) Deposition of SIPOS layer 8: The chip is placed in a furnace tube, and SiH4 and N2O with a volume ratio of 3:1 are introduced at a temperature of 600°C. The vacuum pressure is formed at 100 mTorr, and the thickness of SIPOS layer 8 is 1 μm.
[0090] (2) Deposition of silicon nitride layer 9: The chip is placed in a low-pressure furnace tube at a temperature of 700° C. NH 3 and SiH 2 Cl 2 with a volume ratio of 3:1 are introduced. The vacuum pressure is formed at 300 mTorr. The thickness of the deposited SiN passivation layer is 0.1 μm.
[0091] (3) Deposition of silicon dioxide layer 10: The chip is placed in a furnace tube, and ethyl orthosilicate is introduced at a temperature of 700° C. The pressure is controlled at 200 mTorr to form a silicon dioxide layer 10 with a thickness of 0.8 μm.
[0092] S10 , removing the protective layer and the oxide layer on the back surface and the surface of the doped region 5 , and performing metallization treatment to form a metal layer 11 .
[0093] Among them, SIPOS is removed by rinsing with ammonium fluoride and hydrogen peroxide in a volume ratio of 5:1, the silicon nitride layer 9 is removed by dry etching, and the silicon dioxide and oxide layer are removed by rinsing with ammonium fluoride.
[0094] The metallization treatment is to perform metallization treatment on the back surface and the surface of the doped region 5, specifically:
[0095] (1) firstly, a nickel plating is performed, in which 0.6 μm of nickel is plated on the metal area in a nickel plating solution at 80° C., then a silicon-nickel alloy is formed at a temperature of 600° C., and then a secondary nickel plating is performed, that is, 0.8 μm of nickel is plated on the metal area in a nickel plating solution at 80° C.;
[0096] (2) Evaporating the metal is as follows: using an evaporation table to evaporate 5 μm of aluminum metal on the front side of the chip, etching the metal outside the active area by photolithography, and making a metal alloy at 600 °C, and then evaporating the metal on the back side of the chip to complete the metallization of the chip.
[0097] Example 2
[0098] The steps include:
[0099] S1, select a P-type silicon wafer with a resistivity of 20Ω·cm, use a thinning machine to thin the silicon wafer to a thickness of 200μm, perform a primary oxidation on the silicon wafer, and form a primary oxide layer 1 on the surface of the silicon wafer;
[0100] The oxidation step is as follows: hydrogen and oxygen with a volume ratio of 3:2 are introduced for oxidation, the temperature is set to 1100°C, and the time is 3 hours.
[0101] S2, removing the primary oxide layer 1 in a partial area of the front side;
[0102] Specifically, a photolithography process is used, and the specific parameters of the photolithography are as follows: a photoresist with a thickness of 10,000 angstroms is applied, the exposure time is 6 seconds, the development time is 20 seconds, and finally the oxide layer is removed by rinsing with ammonium fluoride.
[0103] S3, doping phosphorus in the area where the oxide layer is removed by a diffusion process to form a pre-doped area 5;
[0104] The diffusion process is as follows: placing the silicon wafer in a diffusion furnace, carrying liquid phosphorus oxychloride into the diffusion furnace by nitrogen, diffusing at 1100°C for 0.5h, and finally the resistance value of the block resistor is 1.2Ω. Then, high-temperature junction pushing is performed, and the highest junction pushing temperature is 1255°C. The N+ junction depth of the pre-doped area 5 formed is 20μm.
[0105] S4, depositing a silicon nitride passivation layer 3 on the surface of the silicon wafer;
[0106] The steps are as follows: placing the silicon wafer in a low-pressure furnace tube at a temperature of 750° C., introducing NH3 and SiH2CL2 in a volume ratio of 2:1, forming a vacuum pressure at 100 mTorr, and depositing a SiN passivation layer with a thickness of 0.2 μm.
[0107] S5, removing the silicon nitride passivation layer 3 and the oxide layer in a part of the front area of the silicon wafer, and performing etching to form an isolation zone 4, wherein the isolation zone 4 extends to the edge of the pre-doped area 5, and the depth of the isolation zone 4 is not less than the depth of the pre-doped area 5;
[0108] The silicon nitride passivation layer 3 and the oxide layer in the corresponding area are removed by photolithography, and the photolithography process in step S2 can be used. The edge of the pre-doped area 5 is etched to form a part of the isolation zone 4, and the depth of the isolation zone 4 is 30 μm.
[0109] S6, performing a push-up process on the pre-doped region 5 through a diffusion process to form a doped region 5, so that the depth of the doped region 5 is greater than the depth of the isolation zone 4;
[0110] Specifically, the diffusion process of this step is to perform high-temperature push-in diffusion at a maximum push-in temperature of 1255° C. to form a doping region 5 with a depth of 80 μm.
[0111] S7, removing the silicon nitride passivation layer 3 and the primary oxide layer 1 on the surface of the silicon wafer;
[0112] The silicon nitride passivation layer 3 on the front and back surfaces is removed by dry etching, and the oxide layer is removed by ammonium fluoride.
[0113] S8, performing doping treatment on the back side of the silicon wafer, wherein the doping type is opposite to the doping type of the pre-doped region 5, to form a back side doped region 6;
[0114] Specifically, the latex source is evenly spread on the back of the chip through a glue spreader, diffused at a temperature of 1100°C, and the final block resistance is 3Ω, forming P+ on the back of the chip.
[0115] S9, performing secondary oxidation on the surface of the silicon wafer and depositing a protective layer;
[0116] The secondary oxidation adopts the oxidation process in S1 to form a secondary oxidation layer 7;
[0117] The steps of depositing the protective layer include:
[0118] (1) Deposition of SIPOS layer 8: The chip was placed in a furnace tube, and SiH4 and N2O with a volume ratio of 2:1 were introduced at a temperature of 700°C. The vacuum pressure was formed at 500 mTorr, and the thickness of SIPOS layer 8 was 2 μm.
[0119] (2) Deposition of silicon nitride layer 9: The chip is placed in a low-pressure furnace tube at a temperature of 750° C. NH 3 and SiH 2 Cl 2 with a volume ratio of 2:1 are introduced. The vacuum pressure is formed at 500 mTorr. The thickness of the deposited SiN passivation layer is 0.3 μm.
[0120] (3) Deposition of silicon dioxide layer 10: The chip was placed in a furnace tube, and tetraethyl orthosilicate was introduced at a temperature of 600° C. The pressure was controlled at 350 mTorr to form a silicon dioxide layer 10 with a thickness of 1.2 μm.
[0121] S10 , removing the protective layer and the oxide layer on the back surface and the surface of the doped region 5 , and performing metallization treatment to form a metal layer 11 .
[0122] Among them, SIPOS is removed by rinsing with ammonium fluoride and hydrogen peroxide in a volume ratio of 5:1, the silicon nitride layer 9 is removed by dry etching, and the silicon dioxide and oxide layer are removed by rinsing with ammonium fluoride.
[0123] The metallization treatment is to perform metallization treatment on the back surface and the surface of the doped region 5, specifically:
[0124] (1) firstly, a nickel plating is performed, in which 1 μm of nickel is plated on the metal area in a nickel plating solution at 95° C., then a silicon-nickel alloy is formed at a temperature of 700° C., and then a secondary nickel plating is performed, that is, 1.5 μm of nickel is plated on the metal area in a nickel plating solution at 95° C.;
[0125] (2) Evaporating the metal is as follows: using an evaporation table to evaporate 3 μm of aluminum metal on the front side of the chip, etching the metal outside the active area by photolithography, and making a metal alloy at 300 °C, and then evaporating the metal on the back side of the chip to complete the metallization of the chip.
[0126] Example 3
[0127] The steps include:
[0128] S1, select a P-type silicon wafer with a resistivity of 40Ω·cm, use a thinning machine to thin the silicon wafer to a thickness of 270μm, perform a primary oxidation on the silicon wafer, and form a primary oxide layer 1 on the surface of the silicon wafer;
[0129] The oxidation step is as follows: hydrogen and oxygen with a volume ratio of 3:2 are introduced for oxidation, the temperature is set to 1000°C, and the time is 5 hours.
[0130] S2, removing the primary oxide layer 1 in a partial area of the front side;
[0131] Specifically, a photolithography process is used, and the specific parameters of the photolithography are as follows: a photoresist with a thickness of 40,000 angstroms is applied, an exposure time of 15 seconds, a development time of 40 seconds, and finally the oxide layer is removed by rinsing with ammonium fluoride.
[0132] S3, doping phosphorus in the area where the primary oxide layer 1 is removed by a diffusion process to form a pre-doped area 5;
[0133] The diffusion process is as follows: placing the silicon wafer in a diffusion furnace, carrying liquid phosphorus oxychloride into the diffusion furnace by nitrogen, diffusing at 1200°C for 5 hours, and finally the resistance value of the block resistor is 15Ω. Then, high-temperature junction pushing is performed, and the highest junction pushing temperature is 1255°C. The N+ junction depth of the pre-doped area 5 formed is 30μm.
[0134] S4, depositing a silicon nitride passivation layer 3 on the surface of the silicon wafer;
[0135] The steps are as follows: placing the silicon wafer in a low-pressure furnace tube at a temperature of 800° C., introducing NH3 and SiH2CL2 in a volume ratio of 1.5:1, forming a vacuum pressure at 500 mTorr, and depositing a SiN passivation layer with a thickness of 0.5 μm.
[0136] S5, removing the silicon nitride passivation layer 3 and the oxide layer in a part of the front area of the silicon wafer, and performing etching to form an isolation zone 4, wherein the isolation zone 4 extends to the edge of the pre-doped area 5, and the depth of the isolation zone 4 is not less than the depth of the pre-doped area 5;
[0137] The silicon nitride passivation layer 3 and the oxide layer in the corresponding area are removed by photolithography, and the photolithography process in step S2 can be used. The edge of the pre-doped area 5 is corroded to form a part of the isolation zone 4, and the depth of the isolation zone 4 is 60 μm.
[0138] S6, performing a push-up process on the pre-doped region 5 through a diffusion process to form a doped region 5, so that the depth of the doped region 5 is greater than the depth of the isolation zone 4;
[0139] Specifically, the diffusion process of this step is to perform high-temperature push-in diffusion at a maximum push-in temperature of 1255° C. to form a doping region 5 with a depth of 70 μm.
[0140] S7, removing the silicon nitride passivation layer 3 and the primary oxide layer 1 on the surface of the silicon wafer;
[0141] The silicon nitride passivation layer 3 on the front and back surfaces is removed by dry etching, and the oxide layer is removed by ammonium fluoride.
[0142] S8, performing doping treatment on the back side of the silicon wafer, wherein the doping type is opposite to the doping type of the pre-doped region 5, to form a back side doped region 6;
[0143] Specifically, the latex source is evenly spread on the back of the chip through a glue spreader, diffused at a temperature of 1000°C, and the final block resistance is 8Ω, forming P+ on the back of the chip.
[0144] S9, performing secondary oxidation on the surface of the silicon wafer and depositing a protective layer;
[0145] The secondary oxidation adopts the oxidation process in S1 to form a secondary oxidation layer 7;
[0146] The steps of depositing the protective layer include:
[0147] (1) Deposition of SIPOS layer 8: The chip was placed in a furnace tube, and SiH4 and N2O with a volume ratio of 1.5:1 were introduced at a temperature of 700°C. The vacuum pressure was formed at 500 mTorr, and the thickness of SIPOS layer 8 was 0.5 μm.
[0148] (2) Deposition of silicon nitride layer 9: The chip is placed in a low-pressure furnace tube at a temperature of 800° C. NH 3 and SiH 2 Cl 2 with a volume ratio of 1.5:1 are introduced. The vacuum pressure is formed at 100 mTorr. The thickness of the deposited SiN passivation layer is 0.5 μm.
[0149] (3) Deposition of silicon dioxide layer 10: The chip is placed in a furnace tube, and tetraethyl orthosilicate is introduced at a temperature of 800° C. The pressure is controlled at 500 mTorr to form a silicon dioxide layer 10 with a thickness of 1.5 μm.
[0150] S10 , removing the protective layer and the oxide layer on the back surface and the surface of the doped region 5 , and performing metallization treatment to form a metal layer 11 .
[0151] Among them, SIPOS is removed by rinsing with ammonium fluoride and hydrogen peroxide in a volume ratio of 5:1, the silicon nitride layer 9 is removed by dry etching, and the silicon dioxide and oxide layer are removed by rinsing with ammonium fluoride.
[0152] The metallization treatment is to perform metallization treatment on the back surface and the surface of the doped region 5, specifically:
[0153] (1) firstly, a nickel plating is performed, in which 0.8 μm of nickel is plated on the metal area in a nickel plating solution at 95° C., then a silicon-nickel alloy is formed at a temperature of 700° C., and then a secondary nickel plating is performed, that is, 1.5 μm of nickel is plated on the metal area in a nickel plating solution at 95° C.;
[0154] (2) Evaporating the metal is as follows: using an evaporation table to evaporate 8 μm of aluminum metal on the front side of the chip, etching the metal outside the active area by photolithography, and making a metal alloy at 500 °C, and then evaporating the metal on the back side of the chip to complete the metallization of the chip.
[0155] Although the disclosure is disclosed as above, the protection scope of the disclosure is not limited thereto. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the disclosure, and these changes and modifications will fall within the protection scope of this application.
Claims
1. A method for preparing a high-power planar deep passivation isolation chip, characterized in that: The steps include: S1, oxidizing the silicon wafer to form an oxide layer on the surface of the silicon wafer; S2, removing the oxide layer from part of the front area; S3, doping phosphorus or boron in the area where the oxide layer is removed by diffusion process to form a pre-doped area; S4, depositing a silicon nitride passivation layer on the surface of the silicon wafer; S5, removing the silicon nitride passivation layer and the oxide layer from a part of the front area of the silicon wafer, and performing etching to form an isolation zone, wherein the isolation zone extends to the edge of the pre-doped area, and the depth of the isolation zone is not less than the depth of the pre-doped area; S6, performing a push-up process on the pre-doped region through a diffusion process to form a doped region, so that the depth of the doped region is greater than the depth of the isolation zone; S7, removing the silicon nitride passivation layer and the oxide layer on the surface of the silicon wafer; S8, performing doping treatment on the back side of the silicon wafer, wherein the doping type is opposite to the doping type of the pre-doped area; S9, performing secondary oxidation on the surface of the silicon wafer and depositing a protective layer; S10, removing the protective layer and the oxide layer on the back side and the surface of the doped area, and performing metallization treatment.
2. The method for preparing a high-power planar deep passivation isolation chip according to claim 1, characterized in that: Before the silicon wafer is subjected to primary oxidation, the silicon wafer is subjected to thinning treatment or acid-base corrosion treatment to make the thickness of the silicon wafer 200-270 μm, and the resistivity of the silicon wafer is 0.002-50 Ω·cm.
3. The method for preparing a high-power planar deep passivation isolation chip according to claim 1, characterized in that: The depth of the pre-doped region formed in step S3 is 10-30 μm.
4. The method for preparing a high-power planar deep passivation isolation chip according to claim 1 or 3, characterized in that: The depth of the isolation zone in step S5 is 10-60 μm.
5. The method for preparing a high-power planar deep passivation isolation chip according to claim 1 or 3, characterized in that: In step S5, the edge of the pre-doped region is corroded to form a part of the isolation zone.
6. The method for preparing a high-power planar deep passivation isolation chip according to claim 1, characterized in that: The depth of the doped region in step S6 is 50-80 μm.
7. The method for preparing a high-power planar deep passivation isolation chip according to claim 1 or 6, characterized in that: In step S6, the pre-doped region is subjected to a push-in treatment by a diffusion process, and diffusion is performed at a push-in temperature of 1255°C.
8. The method for preparing a high-power planar deep passivation isolation chip according to claim 1, characterized in that: The step of depositing a protective layer in step S9 includes: (1) Deposition of SIPOS layer: placing the chip in a furnace tube, introducing SiH4 and N2O in a volume ratio of (1.5-3):1 at a temperature of 600-700°C, and forming a SIPOS layer at a vacuum pressure of 100-500 mTorr, with a thickness of 0.5-2 μm; (2) Deposition of silicon nitride layer: The chip is placed in a low-pressure furnace tube at a temperature of 650-800°C, and NH3 and SiH2CL2 are introduced in a volume ratio of (1.5-3):
1. The vacuum pressure is formed at 100-500 mTorr, and the thickness of the deposited SiN passivation layer is 0.1-0.5 μm; (3) Deposition of silicon dioxide layer: placing the chip in a furnace tube, introducing tetraethyl orthosilicate at a temperature of 600-800° C., and controlling the pressure at 200-500 mTorr to form a silicon dioxide layer with a thickness of 0.8-1.5 μm.