Manufacturing method of side wall
Linearly controllable, tilted sidewalls are formed through the oblique angle etching method, which solves the problem of difficulty in filling the dielectric layer after the chip device size is reduced, and effectively avoids void defects.
Patent Information
- Application Number
- CN202411312732.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-01-24
AI Technical Summary
As the size of the chip device decreases, the formation of side walls leads to difficulty in filling subsequent dielectric layers, which easily leads to void defects.
Using the oblique angle etching method, the top oxide layer is etched first, and then after the middle nitride layer is opened, the etching is maintained without difference, and the bottom oxide layer is used as the etching stop layer to form a linearly controllable, Sloping side walls.
By controlling the generation of inclined angle, a linear and controllable side wall with a linear and tilted angle can be formed, which improves the filling effect of the medium layer and avoids the generation of void defects.
Smart Images

Figure CN119361424A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a sidewall. Background Art
[0002] As the size of chip devices shrinks, the pitch formed by the width (line) and spacing (space) of the gate structure is further reduced. After the sidewalls (spacer) are formed, the smaller the spacing, the more difficult it is to fill the subsequent dielectric layer, which can easily cause void defects after filling. Summary of the invention
[0003] In order to solve the problems existing in the above-mentioned prior art, the present invention provides a new method for manufacturing a side wall, which is used to transform a traditional side wall into a linear controllable, inclined side wall, whose unique morphology is conducive to the subsequent filling of a dielectric layer and avoids the generation of void defects.
[0004] The present invention provides a method for manufacturing a side wall, comprising the following steps:
[0005] Step 1: forming a pattern structure on a semiconductor substrate where a sidewall is required;
[0006] Step 2, depositing an ONO layer, wherein the ONO layer includes a bottom oxide layer, an intermediate nitride layer and a top oxide layer;
[0007] Step three: first etch the top oxide layer by etching at an inclined angle, and then, after the middle nitride layer is opened, continue etching without distinction, and use the bottom oxide layer as an etching stop layer, thereby forming the sidewall.
[0008] Preferably, the semiconductor substrate in step one is a silicon substrate.
[0009] Preferably, the graphic structure in step 1 is a gate structure, and the gate structure comprises a gate dielectric layer and a gate conductive material layer stacked in sequence.
[0010] Preferably, the gate dielectric layer is a gate oxide layer, and the gate conductive material layer is polysilicon.
[0011] Preferably, the ONO layer in step 2 can be formed by a chemical vapor deposition method.
[0012] Preferably, when etching the intermediate nitride layer in step three, the top oxide layer is etched synchronously.
[0013] Preferably, the etching in step three is a low-frequency power-enhanced ion bombardment process.
[0014] Preferably, the gas used in the ion bombardment process in step three includes fluorine-based gas and argon gas.
[0015] Preferably, the tilt angle in step three depends on the energy and time of ion bombardment.
[0016] Preferably, in step three, when the step size is smaller, a lower frequency pulse can be used for etching to achieve the capability of continuous etching downwards.
[0017] The present invention changes the etching process of the side wall, adopts the method of etching at an inclined angle, etches the top oxide layer first, and then maintains indifferent etching after the middle nitride layer is opened, and uses the bottom oxide layer as the etching stop layer, thereby forming the side wall.
[0018] The present invention controls the generation of the tilt angle, increases the tilt angle, and maintains synchronous etching of the oxide layer and the nitride layer when etching the oxide layer and the nitride layer, thereby forming a side wall with controllable linearity and controllable tilt angle. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0020] Figure 1 Shown is a schematic diagram of a conventional side wall;
[0021] Figure 2 Shown is a flow chart of a method for manufacturing a sidewall according to an embodiment of the present invention;
[0022] Figure 3 to Figure 4 Shown are structural schematic diagrams of various steps in a method for manufacturing a sidewall according to an embodiment of the present invention;
[0023] Figure 5 Shown is a schematic diagram of a sidewall according to an embodiment of the present invention. DETAILED DESCRIPTION
[0024] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.
[0025] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.
[0026] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".
[0027] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.
[0028] The existing method for manufacturing the sidewall includes: etching the protective layer; performing ashing treatment; wet cleaning the groove and performing ion beam etching. However, the polymer generated after etching the protective layer remains at the bottom of the groove, resulting in reduced device performance and low product yield. Therefore, the present invention proposes a new method for manufacturing the sidewall to effectively clean the polymer residue at the bottom of the groove. The technical solution of the present invention is further explained below in conjunction with the accompanying drawings and through specific implementation methods.
[0029] Figure 2 Shown is a flow chart of a method for manufacturing a sidewall according to an embodiment of the present invention; Figure 3 to Figure 4 The structure diagram of each step of the method for manufacturing the sidewall of the embodiment of the present invention is shown. Figure 2 As shown, the method for manufacturing the sidewall of the embodiment of the present invention comprises the following steps:
[0030] Step 1: forming a graphic structure on which a sidewall is required to be formed on a semiconductor substrate.
[0031] The material of the substrate may be silicon, germanium, silicon germanium or silicon carbide, etc., or may be silicon on insulator (SOI) or germanium on insulator (GOI), or may be other materials, such as III and V group compounds such as gallium arsenide. The substrate in this embodiment is a silicon substrate, and further, it may be an undoped or lightly doped silicon substrate.
[0032] A graphic structure is formed on the surface of the silicon substrate, the graphic structure includes a gate structure, and the gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence. In a preferred embodiment, the gate dielectric layer is a gate oxide layer, and the gate conductive material layer is polysilicon. Of course, it can also be other graphic structures that need to form sidewalls, and there can also be multiple graphic structures.
[0033] Step 2: depositing an ONO layer, wherein the ONO layer includes a bottom oxide layer, a middle nitride layer and a top oxide layer.
[0034] In the embodiment of the present invention, the ONO layer can be formed by a chemical vapor deposition method. Specifically, a uniform silicon oxide layer is formed by a low-pressure chemical vapor deposition method, then a silicon nitride layer is formed on the silicon oxide layer by a low-pressure chemical vapor deposition method, and then another silicon oxide layer is formed by a low-pressure chemical vapor deposition method. Of course, other suitable methods can also be used.
[0035] Step 3: Etch the top oxide layer first by etching at an inclined angle, and then, after the middle nitride layer is opened, continue etching without distinction, and use the bottom oxide layer as an etching stop layer, thereby forming a side wall.
[0036] like Figure 3 and Figure 4 As shown, in the embodiment of the present invention, when the middle nitride layer is etched, the top oxide layer is etched synchronously. The method of etching with an inclined angle is a low-frequency power-enhanced ion bombardment process. The gas of the ion bombardment process includes fluorine-based gas and argon gas. The inclined angle depends on the energy and time of the ion bombardment. When the step is smaller, a lower frequency pulse can be used for etching to achieve the ability to etch continuously downward.
[0037] The method for manufacturing the side wall of the present invention can form a linearly controllable side wall with a controllable tilt angle by controlling the generation of the tilt angle, increasing the tilt angle, and maintaining the synchronous etching of OX and SIN during OX and SIN etching, thereby realizing the manufacturing of the traditional side wall into a linearly controllable, tilted side wall. Its unique morphology is conducive to the subsequent filling of the dielectric layer and avoids the generation of void defects.
[0038] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.
Claims
1. A method for manufacturing a side wall, characterized in that: The following steps are involved: Step 1: forming a pattern structure on a semiconductor substrate where a sidewall is required; Step 2, depositing an ONO layer, wherein the ONO layer includes a bottom oxide layer, a middle nitride layer and a top oxide layer; Step three: first etch the top oxide layer by etching at an inclined angle, and then, after the middle nitride layer is opened, continue etching without distinction, and use the bottom oxide layer as an etching stop layer, thereby forming the sidewall.
2. The method for manufacturing the side wall according to claim 1, characterized in that: The semiconductor substrate in step 1 is a silicon substrate.
3. The method for manufacturing the side wall according to claim 1, characterized in that: The graphic structure in step 1 is a gate structure, and the gate structure includes a gate dielectric layer and a gate conductive material layer stacked in sequence.
4. The method for manufacturing the side wall according to claim 3, characterized in that: The gate dielectric layer is a gate oxide layer, and the gate conductive material layer is polysilicon.
5. The method for manufacturing the side wall according to claim 1, characterized in that: The ONO layer in step 2 can be formed by a chemical vapor deposition method.
6. The method for manufacturing the side wall according to claim 1, characterized in that: When etching the intermediate nitride layer in step three, the top oxide layer is etched synchronously.
7. The method for manufacturing a side wall according to claim 1, characterized in that: The etching in step three is a low-frequency power-enhanced ion bombardment process.
8. The method for manufacturing the side wall according to claim 7, characterized in that: The gas used in the ion bombardment process in step three includes fluorine-based gas and argon gas.
9. The method for manufacturing the side wall according to claim 7, characterized in that: The tilt angle in step 3 depends on the energy and time of ion bombardment.
10. The method for manufacturing a side wall according to claim 7, characterized in that: In step 3, when the step size is smaller, a lower frequency pulse can be used for etching to achieve the ability to etch continuously downwards.
Citation Information
Patent Citations
Method of manufacturing semiconductor device
CN104183477A
Method for manufacturing semiconductor device
CN105097539A
Side wall etchback technology
CN106531629A
Manufacturing method of SONOS memory grid electrode structure
CN107833890A
Formation method of SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) device
CN110098125A