Semiconductor process chamber and semiconductor process apparatus

Abstract

The application discloses a semiconductor process chamber, which comprises a chamber body, a susceptor and a first inner liner, wherein the susceptor is arranged in the chamber body, the first inner liner is movably arranged in the chamber body, the first inner liner is arranged around the susceptor and between the susceptor and the chamber body; when a deposition process is performed in the semiconductor process chamber, the first inner liner is moved to a first position, at least a part of the first inner liner is higher than a bearing surface of the susceptor; when an etching process is performed in the semiconductor process chamber, the first inner liner is moved to a second position, the first inner liner is lower than the bearing surface or flush with the bearing surface. The above scheme can solve the problem that in the related art, when an etching process is performed in a process chamber, a film layer deposited on the inner wall of the chamber is easy to fall on a wafer, thereby causing pollution to the wafer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor equipment, in particular to a semiconductor process chamber and a semiconductor process equipment. BACKGROUND

[0002] With the rapid development of the semiconductor industry, etching machines are widely used in the manufacturing process of ICs (integrated circuits). As the semiconductor process is updated and iterated, the process requirements for etching machines are also increasing. As the thickness of the wafer is getting higher and higher, the thickness of the wafer to be etched is also getting thicker. In the process of etching the wafer to form an etching hole, due to the incomplete anisotropy in etching, the etching process will also cause a certain amount of lateral etching to the sidewall of the etching hole, thereby causing sidewall undercut. Under the premise of protecting the sidewall from excessive lateral etching, high aspect ratio etching hole etching process has a very important influence on the etching machine and semiconductor equipment.

[0003] In order to obtain a high aspect ratio etching hole when etching the wafer, the current method is mainly to combine etching process and atomic layer deposition process. During the atomic layer deposition process, the deposit is easy to adhere to the inner wall of the chamber and the components inside the chamber. After alternating etching and atomic layer deposition processes for multiple times, the film layer deposited on the inner wall of the chamber is easy to fall on the wafer during etching, thereby causing pollution to the wafer. SUMMARY

[0004] The present application discloses a semiconductor process chamber to solve the problem that the film layer deposited on the inner wall of the chamber is easy to fall on the wafer and cause pollution to the wafer during the etching process in the related art.

[0005] To solve the above technical problems, the present application is implemented as follows:

[0006] The present application discloses a semiconductor process chamber, which comprises a chamber body, a susceptor and a first inner liner. The susceptor is arranged in the chamber body, the first inner liner is movably arranged in the chamber body, and the first inner liner is arranged around the susceptor and between the susceptor and the chamber body. When the semiconductor process chamber performs a deposition process, the first inner liner moves to a first position, and at least a part of the first inner liner is higher than a bearing surface of the susceptor. When the semiconductor process chamber performs an etching process, the first inner liner moves to a second position, and the first inner liner is lower than the bearing surface or flush with the bearing surface.

[0007] The technical solution adopted by the present application can achieve the following technical effects:

[0008] The semiconductor process chamber disclosed by the embodiments of the present application is provided with a first inner liner, which is movably arranged in the chamber body and surrounds the susceptor, so that when the semiconductor process chamber performs a deposition process, the first inner liner is moved to be at least partially higher than the bearing surface of the susceptor, thereby avoiding the deposition of a film layer to the corresponding area of the chamber body which is shielded by the first inner liner. When the semiconductor process chamber performs an etching process, the first inner liner is moved to a position lower than or flush with the bearing surface, and the film layer deposited on the first inner liner is carried to a position below the bearing surface or flush with the bearing surface. Since the sidewall of the chamber body and the corresponding area of the first inner liner at the first position have no film layer or only a small amount of film layer (which can be ignored), when the semiconductor process chamber performs an etching process, there is no etching of the film layer on the corresponding area of the sidewall of the chamber body and the first inner liner at the first position, thereby avoiding or reducing the film layer falling on the wafer, and thereby alleviating the pollution to the wafer. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A sectional view of the semiconductor process chamber disclosed by the embodiments of the present application when the first inner liner is moved to the second position;

[0010] Figure 2 A sectional view of the semiconductor process chamber disclosed by the embodiments of the present application when the first inner liner is moved to the first position;

[0011] Figure 3 An enlarged schematic view of the driving mechanism disclosed by the embodiments of the present application;

[0012] Figure 4 A schematic view of the cooperation between the connecting block and the guide rod disclosed by the embodiments of the present application;

[0013] Figure 5 A partial enlarged schematic view of the semiconductor process chamber disclosed by the embodiments of the present application when the first inner liner is moved to the first position;

[0014] Figure 6 A partial enlarged schematic view of the semiconductor process chamber disclosed by the embodiments of the present application when the first inner liner is moved to the second position;

[0015] Figure 7 A structural schematic view of the first inner liner disclosed by the embodiments of the present application;

[0016] Figure 8 A structural schematic view of the semiconductor process equipment disclosed by the embodiments of the present application;

[0017] Figure 9 A schematic view of the semiconductor process chamber disclosed by the embodiments of the present application when performing an etching process;

[0018] Figure 10A schematic view of a semiconductor process chamber disclosed by embodiments of the present application performing a deposition process;

[0019] Figure 11 A schematic view of purging the second sub-pipe;

[0020] Figure 12 A schematic view of replenishing the source liquid device 740 with source liquid;

[0021] Figure 13 A schematic view of a semiconductor process apparatus disclosed by embodiments of the present application in a first sub-state;

[0022] Figure 14 A schematic view of a semiconductor process apparatus disclosed by embodiments of the present application in a second sub-state;

[0023] Figure 15 A schematic view of a semiconductor process apparatus disclosed by embodiments of the present application in a third sub-state;

[0024] Figure 16 A schematic view of a semiconductor process apparatus disclosed by embodiments of the present application in a fourth sub-state;

[0025] Figure 17 A schematic view of a semiconductor process apparatus disclosed by embodiments of the present application in a fifth sub-state;

[0026] Figure 18 A schematic view of a semiconductor process apparatus disclosed by embodiments of the present application in a sixth sub-state;

[0027] Figure 19 A schematic view of a bottom of a splash-proof box disclosed by embodiments of the present application in an open state;

[0028] Figure 20 A schematic view of a bottom of a splash-proof box disclosed by embodiments of the present application in a non-open state.

[0029] Explanation of reference numerals:

[0030] 100 - chamber body, 101 - first gap, 102 - second gap, 103 - third gap, 110 - top wall, 120 - side wall, 130 - exhaust device,

[0031] 200 - susceptor, 201 - bearing surface, 210 - susceptor body, 220 - flow uniforming member, 230 - cantilever,

[0032] 300 - first inner liner, 301 - first avoiding hole, 310 - body portion, 311 - strip-shaped hole, 320 - inclined portion, 330 - extension portion, 340 - connecting block, 341 - limiting protrusion, 350 - bolt, 360 - buffer pad,

[0033] 400-gas emitter,

[0034] 500-driving mechanism, 510-driving body, 520-guide rod, 521-thread hole, 522-limiting groove,

[0035] 600-second inner liner, 601-second avoiding hole,

[0036] 710-first gas source device, 720-second gas source device, 730-third gas source device, 740-first source liquid device, 750-vaporizer, 760-second source liquid device, 761-exhaust port, 770-fifth gas source device, 780-first flow controller, 790-second flow controller, 810-condenser, 820-pressure detection device, 840-anti-splashing box, 841-inner shell, 841a-first filter hole, 842-outer shell, 842a-second filter hole, 843-anti-splashing liquid level sensor, 844-liquid storage space,

[0037] 901-first pipeline, 902-second pipeline, 902a-third sub-pipeline, 902b-fourth sub-pipeline, 903-third pipeline, 903a-fifth sub-pipeline, 903b-sixth sub-pipeline, 904-fourth pipeline, 905-fifth pipeline, 905a-first sub-pipeline, 905b-second sub-pipeline, 906-sixth pipeline, 907-seventh pipeline, 908-eighth pipeline, 909-ninth pipeline, 9010-tenth pipeline, 9011-eleventh pipeline, 9012-twelfth pipeline, 9013-thirteenth pipeline, 9014-fourteenth pipeline,

[0038] 9020-first exhaust pipeline, 9021-second exhaust pipeline. DETAILED DESCRIPTION

[0039] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described below in connection with specific embodiments of the present application and corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0040] In order to facilitate the understanding of the technical solutions of the present application, the present application first describes the related content of the semiconductor process chamber, as follows:

[0041] In the process of forming etching holes on a wafer by etching in a semiconductor process chamber, due to the incomplete anisotropy in etching, the etching process will also cause a certain lateral etching to the sidewall of the etching hole, thereby causing the sidewall to be undercut. Under the premise of protecting the sidewall from being etched too much, the etching process of the etching hole with high aspect ratio has a very important influence on the etching machine and semiconductor equipment.

[0042] In order to obtain an etching hole with high aspect ratio when etching a wafer, a method combining etching process and atomic layer deposition process is used. First, the wafer is etched, and then a protective film layer is deposited on the sidewall of the wafer before the etching hole is etched to a certain depth and the sidewall is not undercut. Since the vertical etching speed is greater than the lateral etching speed when etching the etching hole, the film layer on the sidewall can be etched deeper in the vertical direction at the same time. By repeating the etching process and atomic layer deposition process, an etching hole with a specific high aspect ratio is formed on the wafer.

[0043] In order to obtain an etching hole with high aspect ratio, the related art uses a process chamber that can perform both etching process and atomic layer deposition process. Since the deposit is easy to adhere to the inner wall of the chamber and the components in the chamber during the atomic layer deposition process, after alternating etching and atomic layer deposition processes for multiple times, the film layer deposited on the inner wall of the chamber is easy to fall on the wafer during etching due to etching, thereby causing pollution to the wafer. The technical solution disclosed in the present application can alleviate the problem that the film layer deposited on the inner wall of the chamber is easy to fall on the wafer and cause pollution to the wafer during the etching process in the process chamber.

[0044] The technical solutions disclosed in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0045] Please refer to Figures 1 to 20 The semiconductor process chamber disclosed in the embodiments of the present application includes a chamber body 100, a susceptor 200, and a first inner liner 300.

[0046] The susceptor 200 is arranged in the chamber body 100 and is used to carry a wafer. The first inner liner 300 is movably arranged in the chamber body 100, surrounds the susceptor 200, and is located between the susceptor 200 and the chamber body 100. The first inner liner 300 can be a cylindrical body.

[0047] When the semiconductor process chamber performs a deposition process, the first inner liner 300 moves to a first position, and at least a part of the first inner liner 300 is higher than a carrying surface 201 of the susceptor 200. The first inner liner 300 can protect the area of the chamber body 100 opposite to it, so as to reduce the thickness of the film layer deposited on the inner wall of the chamber body 100.

[0048] When the semiconductor process chamber performs the etching process, the first inner liner 300 moves to the second position, and the first inner liner 300 is lower than or flush with the bearing surface 201, so that the film layer deposited on the first inner liner 300 is also carried to the lower side of the bearing surface 201 or flush with the bearing surface 201, and even if more film layers are deposited on the first inner liner 300, the film layers will not fall on the wafer located on the bearing surface 201.

[0049] The semiconductor process chamber disclosed by the embodiments of the present application sets the first inner liner 300, which is movably arranged in the chamber body 100 and surrounds the susceptor 200, so that when the semiconductor process chamber performs the deposition process, the first inner liner 300 moves to a position at least partially higher than the bearing surface 201 of the susceptor 200, so that the film layer is prevented from being deposited in the corresponding area of the chamber body 100 blocked by the first inner liner 300. When the semiconductor process chamber performs the etching process, the first inner liner 300 moves to a position lower than the bearing surface 201 or flush with the bearing surface 201, and the film layer deposited on the first inner liner 300 is also carried to the lower side of the bearing surface 201 or flush with the bearing surface 201. Since the sidewall 120 of the chamber body 100 and the area corresponding to the first position of the first inner liner 300 have no film layer or only a small amount of film layer (which can be ignored), when the semiconductor process chamber performs the etching process, there is no etching of the film layer on the area of the sidewall 120 corresponding to the first position of the first inner liner 300, thereby avoiding or reducing the film layer falling on the wafer, and thus alleviating the pollution to the wafer.

[0050] When the semiconductor process chamber performs the deposition process, in order to prevent the first precursor and the second precursor introduced into the chamber body 100 from reacting and depositing at the gas inlet hole before entering the chamber body 100, the top wall 110 of the chamber body 100 is optionally provided with a first gas inlet hole, the sidewall 120 of the chamber body 100 is provided with a second gas inlet hole higher than the bearing surface 201, and the first inner liner 300 is provided with a first avoiding hole 301. When the semiconductor process chamber performs the deposition process, the second gas inlet hole is opposite to the first avoiding hole 301, the first gas inlet hole is used to introduce the first precursor, and the second gas inlet hole is used to introduce the second precursor. The first precursor and the second precursor perform the deposition process in the chamber body 100 to make the semiconductor process chamber perform the deposition process. When the semiconductor process chamber performs the etching process, the first inner liner 300 is located below the second gas inlet hole, and the first gas inlet hole is used to introduce the etching gas to make the semiconductor process chamber perform the etching process.

[0051] The semiconductor process chamber disclosed by the embodiment of the present application comprises a first gas inlet hole in the top wall 110 of the chamber body 100 and a second gas inlet hole in the side wall 120 of the chamber body 100, which is higher than the bearing surface 201. When the semiconductor process chamber performs a deposition process, the second gas inlet hole is opposite to the first avoiding hole 301, the first gas inlet hole is connected to the first precursor, and the second gas inlet hole is connected to the second precursor. Thus, the deposition reaction of the first precursor and the second precursor at the gas inlet hole before entering the chamber body 100 can be avoided.

[0052] Optionally, the semiconductor process chamber can further comprise a gas emitter 400, and the first gas inlet hole and the second gas inlet hole can be provided with the gas emitter 400. The first precursor, the second precursor and the etching gas can be transported into the chamber body 100 through the corresponding gas emitter 400. When the semiconductor process chamber performs a deposition process, the first inner liner 300 moves to the first position, and the gas emitter 400 located at the second gas inlet hole has a first gap 101 between the hole opening on the side of the side wall 120 of the first avoiding hole 301.

[0053] The semiconductor process chamber disclosed by the embodiment of the present application comprises a gas emitter 400, and the first gas inlet hole and the second gas inlet hole can be provided with the gas emitter 400. The first precursor, the second precursor and the etching gas can be transported into the chamber body 100 through the corresponding gas emitter 400. When the semiconductor process chamber performs a deposition process, the first inner liner 300 moves to the first position, and the gas emitter 400 located at the second gas inlet hole has a first gap 101 between the hole opening on the side of the side wall 120 of the first avoiding hole 301.

[0054] In an optional embodiment, the first inner liner 300 can comprise a body part 310, an inclined part 320 and an extension part 330. The body part 310 can be a cylindrical structure, the inclined part 320 and the extension part 330 can be annular structures, the body part 310 can be sleeved on the susceptor 200, the first end of the inclined part 320 can be connected to the first port of the body part 310, the second end of the inclined part 320 can be connected to the first end of the extension part 330, the second end of the inclined part 320 can be inclined to the side of the central axis of the cylindrical structure, the second end of the extension part 330 can extend to the side of the central axis of the cylindrical structure, and the extension part 330 is parallel to the bearing surface 201. Specifically, the included angle between the inclined part 320 and the extension part 330 can be between 100° and 110°, including 100° and 110°. Thus, the ability of the film layer to adhere to the position between the inclined part 320 and the extension part 330 can be reduced. If the included angle is too small, the film layer is more likely to adhere to the position between the inclined part 320 and the extension part 330 (because the airflow through the position with a sharp corner is poor, the film layer is more likely to adhere to the position).

[0055] The semiconductor process chamber disclosed by the embodiments of the present application sets the first inner liner 300 to have a structure including a body part 310, an inclined part 320 and an extension part 330, so that the body part 310 can protect the sidewall 120 of the chamber body 100, and the extension part 330 can protect the edge area of the top wall 110 of the chamber body 100, to reduce the thickness of the deposited film layer in the edge area of the sidewall 120 and the top wall 110. The transition connection of the body part 310 and the extension part 330 through the inclined part 320 can alleviate the situation that a smaller included angle is formed at the connection of the body part 310 and the extension part 330, and a thicker film layer is easily deposited.

[0056] Optionally, when the semiconductor process chamber performs a deposition process, the extension part 330 and the top wall 110 of the chamber body 100 can have a second gap 102 therebetween. For example, the second gap 102 can be between 0.3mm-0.8mm, including 0.3mm and 0.8mm. When the semiconductor process chamber performs an etching process, the extension part 330 can be located below the bearing surface 201 or flush with the bearing surface 201.

[0057] The embodiments of the present application set the semiconductor process chamber to have the second gap 102 between the extension part 330 and the top wall 110 of the chamber body 100 when the semiconductor process chamber performs a deposition process, so that the situation that particles fall off due to friction between the extension part 330 and the top wall 110 of the chamber body 100 can be avoided.

[0058] Specifically, when the second gap 102 between the extension part 330 and the top wall 110 is maintained, the travel of the first inner liner 300 can be controlled, or the distance between the extension part 330 and the top wall 110 can be detected by a distance sensor. The technology of maintaining the second gap 102 between the extension part 330 and the top wall 110 belongs to the prior art, and will not be described in detail herein.

[0059] In order to make the airflow distribution in the chamber body 100 relatively uniform, the susceptor 200 can optionally include a susceptor body 210 and a flow uniformizing member 220. The susceptor body 210 can include a bearing surface 201 for bearing a wafer. The flow uniformizing member 220 can be annularly arranged on the susceptor body 210 and located below the bearing surface 201. The flow uniformizing member 220 can be provided with a plurality of flow uniformizing holes annularly arranged on the susceptor body 210, and the flow uniformizing holes can be strip-shaped grid holes. The chamber body 100 can be provided with an exhaust hole located below the flow uniformizing member 220. When the semiconductor process chamber performs an etching process, the extension part 330 and the flow uniformizing member 220 can have a third gap 103 therebetween.

[0060] The semiconductor process chamber disclosed by the embodiments of the present application is provided with the flow uniformizing member 220, which is arranged around the susceptor body 210 and below the bearing surface 201, and is provided with a plurality of flow uniformizing holes distributed around the susceptor body 210, so that the gas in the chamber body 100 can uniformly pass through the plurality of flow uniformizing holes and be discharged from the exhaust hole. Since the plurality of flow uniformizing holes are uniformly distributed around the susceptor body 210, the exhaust of each region in the chamber body 100 is relatively uniform, thereby improving the uniformity of the gas flow distribution in the chamber body 100. When the semiconductor process chamber performs etching process, the third gap 103 is reserved between the extension 330 and the flow uniformizing member 220, which can avoid the friction between the extension 330 and the flow uniformizing member 220 to cause more particles.

[0061] Optionally, in the radial direction of the bearing surface 201, the extension 330 can cover the edge region of the flow uniformizing hole. Since the extension 330 covers the edge region of the flow uniformizing hole, when the gas in the chamber body 100 is discharged through the flow uniformizing hole, the gas can converge to the central region of the chamber body 100, so that the gas in the chamber body 100 can converge to the position of the bearing surface 201, thereby improving the efficiency of the semiconductor process chamber when performing deposition process and etching process.

[0062] Specifically, the movement of the first inner liner 300 between the first position and the second position can be controlled manually. In order to improve the automation of the semiconductor process chamber, optionally, the semiconductor process chamber can further include a driving mechanism 500, which can be arranged in the chamber body 100 and connected with the first inner liner 300. The driving mechanism 500 can be used to drive the first inner liner 300 to switch between the first position and the second position, thereby improving the automation of the semiconductor process chamber.

[0063] Optionally, the driving mechanism 500 can be multiple, the base 200 can include a base body 210 and multiple cantilever arms 230, the multiple cantilever arms 230 can be circumferentially arranged on the base body 210, and can correspond to the multiple driving mechanisms 500 one by one. At least one cantilever arm 230 is connected to the chamber body 100, and the other cantilever arms 230 can be connected to the base body 210 at one end and suspended at the other end and spaced apart from the chamber body 100. The driving mechanism 500 can be arranged on the cantilever arm 230. The first inner liner 300 can be provided with a strip-shaped hole 311 extending along the direction of movement of the first inner liner 300 between the first position and the second position. The cantilever arm 230 connected to the chamber body 100 can be inserted into the strip-shaped hole 311. During the movement of the first inner liner 300 between the first position and the second position, the strip-shaped hole 311 can avoid the corresponding cantilever arm 230. Each driving mechanism 500 is arranged on the corresponding cantilever arm 230 and connected to the corresponding part of the first inner liner 300. When the number of multiple cantilever arms 230 is even, the multiple cantilever arms 230 can be symmetrically arranged. When the number of multiple cantilever arms 230 is odd, the angle between any two adjacent cantilever arms 230 in the circumferential direction of the base body 210 is equal.

[0064] The semiconductor process chamber disclosed in the embodiments of the present application sets the base 200 to include a base body 210 and multiple cantilever arms 230, so that the multiple cantilever arms 230 are circumferentially arranged on the base body 210. By arranging multiple driving mechanisms 500, the multiple driving mechanisms 500 correspond to the multiple cantilever arms 230 one by one, and then the driving mechanism 500 is arranged on the cantilever arm 230, so that the first inner liner 300 is driven to move between the first position and the second position by the multiple driving mechanisms 500, so that the movement of the first inner liner 300 is more stable. The cantilever arm 230 connected to the chamber body 100 can be used to fix and install the entire base 200. By providing a strip-shaped hole 311, the cantilever arm 230 connected to the chamber body 100 is inserted into the strip-shaped hole 311, so that the strip-shaped hole 311 can avoid the corresponding cantilever arm 230 during the movement of the first inner liner 300 between the first position and the second position.

[0065] It should be noted that the cantilever arm 230 in the multiple cantilever arms 230 has one end connected to the base body 210 and the other end suspended and spaced apart from the chamber body 100. The space between the cantilever arm 230 and the chamber body 100 can be used for the first inner liner 300 to extend into, and the cantilever arm 230 and the chamber body 100 will not contact the first inner liner 300.

[0066] Specifically, one of the plurality of cantilever arms 230 can be connected to the chamber body 100, and the other cantilever arms 230 can be spaced apart from the chamber body 100, so that more strip-shaped holes 311 do not need to be formed on the first inner liner 300, thereby facilitating the protection of the side wall 120 of the chamber body 100 by the first inner liner 300 to avoid the deposition of a thick film layer on the side wall 120.

[0067] Of course, two or three cantilever arms 230 can be connected to the chamber body 100, and the present application does not make specific limitations on this.

[0068] Specifically, the driving mechanism 500 can include a driving body 510 and a guide rod 520, the driving body 510 can be arranged on the cantilever arm 230, the driving body 510 can be connected to the first end of the guide rod 520, the second end of the guide rod 520 can be provided with a threaded hole 521 and a limiting groove 522 or a limiting protrusion 341 surrounding the threaded hole 521, the first inner liner 300 can have a connecting block 340 and a bolt 350, the connecting block 340 can have a limiting protrusion 341 or a limiting groove 522 matched with the limiting groove 522 or the limiting protrusion 341 of the guide rod 520, the limiting protrusion 341 and the limiting groove 522 can be matched in the direction perpendicular to the movement direction of the guide rod 520, the connecting block 340 can be provided with a connecting hole, and the bolt 350 can be screwed into the threaded hole 521 through the connecting hole, so that the second end of the guide rod 520 is connected to the connecting block 340.

[0069] The semiconductor process chamber disclosed in the embodiments of the present application sets the driving mechanism 500 to include a driving body 510 and a guide rod 520, so that the driving body 510 is arranged on the cantilever arm 230, the driving body 510 is connected to the first end of the guide rod 520, the second end of the guide rod 520 is connected to the connecting block 340 of the first inner liner 300 through the bolt 350, and the limiting groove 522 or the limiting protrusion 341 of the second end of the guide rod 520 is matched with the limiting protrusion 341 or the limiting groove 522 of the connecting block 340 in the direction perpendicular to the movement direction of the first inner liner 300, so that the connection between the first inner liner 300 and the guide rod 520 is more stable.

[0070] Optionally, a buffer pad 360 can be connected between the second end of the guide rod 520 and the connecting block 340, so that the impact between the first inner liner 300 and the guide rod 520 can be reduced when the driving mechanism 500 drives the first inner liner 300 to move, thereby protecting the first inner liner 300.

[0071] Optionally, the cantilever arm 230 can be provided with a protection space, and part of the driving body 510 can be located in the protection space, so that the driving body 510 can be protected, and a thick film layer can be avoided from being deposited on the driving body 510.

[0072] The first inner liner 300 can be composed of a plurality of first sub-liners spliced together, and the plurality of first sub-liners can have a gap therebetween, for example, the gap can be between 0.3 mm and 0.8 mm, and can include 0.3 mm and 0.8 mm, so as to digest the processing error and avoid interference fit, thereby facilitating the first inner liner 300 to be disposed in the chamber body 100.

[0073] To further protect the side wall 120 of the chamber body 100, optionally, the semiconductor process chamber can further include a second inner liner 600 disposed in the chamber body 100, and the second inner liner 600 is detachably disposed on the side wall 120. The second inner liner 600 can be provided with a second avoiding hole 601, and in the case that the first inner liner 300 moves to the first position, the second inner liner 600 can be located between the first inner liner 300 and the chamber body 100, and the center axis of the second gas inlet hole, the center axis of the first avoiding hole 301 and the center axis of the second avoiding hole 601 coincide.

[0074] The semiconductor process chamber disclosed in the embodiments of the present application sets the second inner liner 600, so that the second inner liner 600 is detachably disposed on the side wall 120, so that the second inner liner 600 can protect the side wall 120 to avoid the film layer being directly deposited on the side wall 120, so that in the case that the second inner liner 600 also has a large amount of film layer deposited thereon, the second inner liner 600 can be directly disassembled for cleaning or replacement, without the need to disassemble the chamber body 100, thereby avoiding the risk of damaging the chamber body 100 when disassembling the chamber body 100.

[0075] Specifically, the second inner liner 600 can be composed of a plurality of second sub-liners spliced together, thereby facilitating the installation of the second inner liner 600.

[0076] To reduce the deposition rate of the film layer at the two orifices of the first avoiding hole 301 and the two orifices of the second avoiding hole 601, optionally, the two orifices of the first avoiding hole 301 can be circular chamfer structures, and the two orifices of the second avoiding hole 601 can be circular chamfer structures, so as to reduce the deposition rate of the film layer at the two orifices of the first avoiding hole 301 and the two orifices of the second avoiding hole 601, thereby facilitating the reduction of the thickness of the film layer deposited at the two orifices of the first avoiding hole 301 and the two orifices of the second avoiding hole 601.

[0077] Please refer to Figure 8The application also discloses a semiconductor process equipment, which comprises the semiconductor process chamber disclosed in the above embodiments, a first pipeline 901 in communication with the first gas inlet hole and a fifth pipeline 905 in communication with the second gas inlet hole, the first pipeline 901 is used for selectively feeding the first precursor or etching gas into the first gas inlet hole, and the fifth pipeline 905 is used for feeding the second precursor. When the deposition process is performed in the semiconductor process chamber, the first pipeline 901 and the fifth pipeline 905 alternately feed the first precursor and the second precursor. When the etching process is performed in the semiconductor process chamber, the first pipeline 901 feeds the etching gas. The first precursor and the etching gas process the first pipeline 901.

[0078] The semiconductor process equipment disclosed in the embodiments of the application is provided with the semiconductor process chamber disclosed in the above embodiments, so that when the deposition process is performed in the semiconductor process chamber, the first inner liner 300 is moved to be at least partially higher than the bearing surface 201 of the susceptor 200, so that the film layer can be prevented from being deposited on the area of the chamber body 100 corresponding to the first inner liner 300. When the etching process is performed in the semiconductor process chamber, the first inner liner 300 is moved to a position lower than the bearing surface 201, and the film layer deposited on the first inner liner 300 is also carried to the lower side of the bearing surface 201. Since the sidewall 120 of the chamber body 100 and the area corresponding to the first position of the first inner liner 300 are free of the film layer or only have a small amount of film layer (which can be ignored), when the etching process is performed in the semiconductor process chamber, the film layer on the area of the sidewall 120 corresponding to the first position of the first inner liner 300 will not be etched, and thus the film layer falling on the wafer can be avoided or reduced, and the pollution to the wafer can be alleviated.

[0079] Specifically, the semiconductor process equipment can further include a first gas source device 710, a second gas source device 720, a third gas source device 730, a fourth gas source device, a first source liquid device 740, and a vaporizer 750. The second gas source device 720 can be in communication with the first source liquid device 740 through a second pipeline 902, the first source liquid device 740 can be in communication with the vaporizer 750 through a third pipeline 903, the third gas source device 730 can be in communication with the vaporizer 750 through a fourth pipeline 904, and the vaporizer 750 can be in communication with the second gas inlet through a fifth pipeline 905. When the semiconductor process chamber performs a deposition process, the first gas source device 710 can be in communication with the first gas inlet through the first pipeline 901, the first pipeline 901 and the fifth pipeline 905 can be alternately opened and closed, the second pipeline 902, the third pipeline 903, and the fourth pipeline 904 are all in an open state, and the first pipeline 901 and the fifth pipeline 905 can alternately introduce the first precursor and the second precursor into the chamber body 100. When the semiconductor process chamber performs an etching process, the fourth gas source device can be in communication with the first gas inlet through the first pipeline 901, the first pipeline 901 is in an open state, and the fifth pipeline 905 is in a closed state. The fourth gas source device can introduce the etching gas into the chamber body 100 through the first pipeline 901.

[0080] Please refer to Figure 9 and Figure 10 In order to improve the process efficiency of the semiconductor process equipment, the semiconductor process equipment can further include a first source liquid device 740, a vaporizer 750, a second source liquid device 760, and a condenser 810. The first source liquid device 740 can be connected with the vaporizer 750, and the first source liquid device 740 is vaporized into a gas after passing through the vaporizer 750. The vaporizer 750 and the second source liquid device 760 are connected in parallel to the fifth pipeline 905, and the condenser 810 is arranged between the vaporizer 750 and the second source liquid device 760.

[0081] When the semiconductor process chamber performs a deposition process, the vaporizer 750 is in communication with the fifth pipeline 905, and the vaporizer 750 is disconnected with the second source liquid device 760. The first pipeline 901 is used to transport the first precursor into the chamber body 100, the first source liquid device 740 is vaporized into a gas after passing through the vaporizer 750, and enters the chamber body 100 through the fifth pipeline 905. The first source liquid device 740 is at least part of the gas that constitutes the second precursor.

[0082] When the semiconductor process chamber performs an etching process, the vaporizer 750 is disconnected with the fifth pipeline 905, and the vaporizer 750 is in communication with the second source liquid device 760. The first pipeline 901 is used to transport the etching gas into the chamber body 100, the first source liquid device 740 is vaporized into a gas after passing through the vaporizer 750, and is liquefied into a liquid after passing through the condenser 810 and is stored in the second source liquid device 760.

[0083] The semiconductor process equipment disclosed by the embodiment of the present application is characterized in that the first source liquid device 740, the vaporizer 750, the second source liquid device 760 and the condenser 810 are arranged, so that when the deposition process is performed in the semiconductor process chamber, the first pipeline 901 transports the first precursor into the chamber body 100, the first source liquid device 740 is vaporized into gas after passing through the vaporizer 750, and enters the chamber body 100 through the fifth pipeline 905, so that the deposition process is performed in the chamber body 100. When the etching process is performed in the semiconductor process chamber, the vaporizer 750 is disconnected from the fifth pipeline 905, the vaporizer 750 is communicated with the second source liquid device 760, the first pipeline 901 transports the etching gas into the chamber body 100, so that the etching process is performed in the chamber body 100. Since the first source liquid device 740 is vaporized into gas after passing through the vaporizer 750 when the etching process is performed in the semiconductor process chamber, and is liquefied into liquid in the second source liquid device 760 after passing through the condenser 810, the first source liquid device 740 is always in the delivery state, so that the time for the first source liquid device 740 to start delivering source liquid can be reduced when the deposition process is performed after the etching process, and the process efficiency of the semiconductor process equipment can be improved, and the second source liquid device 760 can also recycle the source liquid.

[0084] Specifically, the second source liquid device 760 is communicated with the vaporizer 750 through the sixth pipeline 906, the condenser 810 is arranged in the sixth pipeline 906, and the second source liquid device 760 is communicated with the exhaust device 130 of the semiconductor process chamber through the second exhaust pipeline 9021. When the deposition process is performed in the semiconductor process chamber, the sixth pipeline 906, the first exhaust pipeline 9020 and the second exhaust pipeline 9021 are all in the closed state. When the etching process is performed in the semiconductor process chamber, the sixth pipeline 906 and the second exhaust pipeline 9021 are both in the open state, and the first exhaust pipeline 9020 is in the closed state.

[0085] Please refer to Figure 11 The semiconductor process equipment further comprises a fifth gas source device 770, the fifth pipeline 905 comprises a first sub-pipeline 905a and a second sub-pipeline 905b, the first end of the first sub-pipeline 905a is communicated with the vaporizer 750, the second end of the first sub-pipeline 905a is communicated with the first end of the second sub-pipeline 905b, the second end of the second sub-pipeline 905b is communicated with the second gas inlet hole, and the fifth gas source device 770 is communicated with the second sub-pipeline 905b through the seventh pipeline 907.

[0086] When the deposition process or the etching process is performed, the first pipeline 901 is always connected to the chamber body 100, and the fifth pipeline is only connected to the second precursor during the deposition process. Since the second sub-pipe 905b is close to the chamber body 100, the first precursor and the second precursor are easy to deposit at the second sub-pipe 905b, so that the second precursor cannot be connected to the chamber body 100, and the second sub-pipe 905b needs to be purged. When the second sub-pipe 905b is purged, the first pipeline 901 and the first exhaust pipeline 9020 are in a closed state, the second pipeline 902, the third pipeline 903, the fourth pipeline 904, the sixth pipeline 906 and the second exhaust pipeline 9021 are in an open state, the first sub-pipe 905a is in a closed state, and the seventh pipeline 907 and the second sub-pipe 905b are in an open state.

[0087] Please refer to Figure 12 In order to supplement the source liquid to the first source liquid device 740 and avoid overfilling of the second source liquid device 760, the semiconductor process equipment can optionally further include an eighth pipeline 908 and a ninth pipeline 909. The eighth pipeline 908 can be connected to the second source liquid device 760, and the second source liquid device 760 can be connected to the first source liquid device 740 through the ninth pipeline 909. When the semiconductor process equipment supplements the first source liquid device 740, the eighth pipeline 908 can be used to connect the gas to the second source liquid device 760, so as to drive the liquid in the second source liquid device 760 to enter the first source liquid device 740 through the ninth pipeline 909, thereby supplementing the source liquid to the first source liquid device 740 and avoiding overfilling of the second source liquid device 760.

[0088] Optionally, the first source liquid device 740 and the second source liquid device 760 can be provided with high liquid level sensors and low liquid level sensors. When the low liquid level sensor of the first source liquid device 740 is triggered or the high liquid level sensor of the second source liquid device 760 is triggered, the semiconductor process equipment enters a state of supplementing the first source liquid device 740.

[0089] Specifically, the semiconductor process equipment can further include a fifth gas source device 770. The fifth gas source device 770 can be connected to the second source liquid device 760 through the eighth pipeline 908, and the fifth gas source device 770 can connect the gas to the second source liquid device 760 through the eighth pipeline 908, so as to drive the liquid in the second source liquid device 760 to enter the first source liquid device 740 through the ninth pipeline 909.

[0090] Optionally, please refer to Figure 13 and Figure 14, the semiconductor process equipment can further include a first flow controller 780, which can be used to control the flow of gas in the third pipeline 903. The inlet of the first flow controller 780 can be in communication with the third pipeline 903, and the outlet of the first flow controller 780 is in communication with the vaporizer 750 through the tenth pipeline 9010, the eighth pipeline 908 is in communication with the tenth pipeline 9010, the fifth gas source device 770 is in communication with the third pipeline 903 through the eleventh pipeline 9011, and the eighth pipeline 908 is in communication with the second source liquid device 760 through the tenth pipeline 9010 and the twelfth pipeline 9012; the semiconductor process equipment has a first sub-state and a second sub-state.

[0091] When the semiconductor process equipment is in the first sub-state, the eighth pipeline 908, the tenth pipeline 9010, the fourth pipeline 904, the sixth pipeline 906 and the second exhaust pipeline 9021 are all in an open state, and the other pipelines are all in a closed state. The purge gas blown out by the fifth gas source device 770 passes through the eighth pipeline 908, the tenth pipeline 9010, and then reaches the vaporizer 750, and then passes through the fourth pipeline 904 together with the gas in the fourth pipeline 904, enters the second source liquid device 760 through the sixth pipeline 906, and is exhausted from the second exhaust pipeline 9021, so as to realize the purge of the pipeline behind the first flow controller 780.

[0092] When the semiconductor process equipment is in the second sub-state, the eleventh pipeline 9011, the third pipeline 903 and the first exhaust pipeline 9020 are all in an open state, and the other pipelines are all in a closed state. The purge gas blown out by the fifth gas source device 770 passes through the eleventh pipeline 9011 and the third pipeline 903 into the first source liquid device 740 and is exhausted from the first exhaust pipeline 9020, so as to purge the pipeline in front of the first flow controller 780.

[0093] It should be noted that when the first flow controller 780 is maintained or replaced, the residual second precursor in the pipeline on both sides of the first flow controller 780 needs to be purged clean to avoid harm to the human body, wherein the first sub-state is to purge the pipeline behind the first flow controller 780, and the second sub-state is to purge the pipeline in front of the first flow controller 780.

[0094] Please refer to Figure 15 and Figure 16 In order to maintain and replace the vaporizer 750, the pipeline in front of and behind the vaporizer 750 needs to be purged to avoid harm to the human body caused by residual gas. Alternatively, the fifth gas source device 770 can be in communication with the sixth pipeline 906 through the thirteenth pipeline 9013, and the semiconductor process equipment has a third sub-state and a fourth sub-state.

[0095] When the semiconductor processing apparatus is in the third sub-state, the thirteenth pipe 9013, the sixth pipe 906 and the second exhaust pipe 9021 are in the open state, and the other pipes are in the closed state. The purge gas blown by the fifth gas source device 770 is discharged after sequentially passing through the thirteenth pipe 9013, the sixth pipe 906, the second source liquid device 760 and the second exhaust pipe 9021, so as to purge the rear side pipe of the vaporizer 750.

[0096] When the semiconductor processing apparatus is in the fourth sub-state, the eighth pipe 908, the tenth pipe 9010, the twelfth pipe 9012 and the second exhaust pipe 9021 are in communication, and the other pipes are in the closed state. The purge gas blown by the fifth gas source device 770 is discharged after sequentially passing through the eighth pipe 908, the tenth pipe 9010, the twelfth pipe 9012, the second source liquid device 760 and the second exhaust pipe 9021, so as to purge the front side pipe of the vaporizer 750.

[0097] Please refer to Figure 17 and Figure 18 When the first source liquid device 740 is replenished, replaced or repaired, the gas in the second gas source device 720 needs to be prevented from entering the first source liquid device 740. In order to prevent the gas in the second gas source device 720 from entering the first source liquid device 740, the second pipe 902 can optionally include a third sub-pipe 902a and a fourth sub-pipe 902b, and the third pipe 903 can include a fifth sub-pipe 903a and a sixth sub-pipe 903b. The second gas source device 720 can be in communication with the first source liquid device 740 through the third sub-pipe 902a and the fourth sub-pipe 902b in sequence, and the first source liquid device 740 can be in communication with the first flow controller through the fifth sub-pipe 903a and the sixth sub-pipe 903b in sequence. The third sub-pipe 902a and the sixth sub-pipe 903b can be in communication through the fourteenth pipe 9014, and the semiconductor processing apparatus has a fifth sub-state.

[0098] When the semiconductor processing apparatus is in the fifth sub-state, the third sub-pipe 902a, the fourteenth pipe 9014, the sixth sub-pipe 903b, the tenth pipe 9010, the twelfth pipe 9012 and the second exhaust pipe 9021 are in the open state, and the other pipes are in the closed state, so that the gas in the second gas source device 720 can be prevented from entering the first source liquid device 740.

[0099] In another embodiment, when the semiconductor processing apparatus is in the sixth sub-state, the third sub-pipe 902a, the fourteenth pipe 9014, the sixth sub-pipe 903b, the tenth pipe 9010, the fourth pipe 904, the sixth pipe 906 and the second exhaust pipe 9021 are in the open state, and the other pipes are in the closed state, so that the gas in the second gas source device 720 can be prevented from entering the first source liquid device 740.

[0100] Optionally, the fourth pipeline 904 can be provided with a second flow controller 790, which can control the flow of gas in the fourth pipeline 904.

[0101] Optionally, the second exhaust pipeline 9021 can be provided with a pressure detection device 820, which can be closed in the case of abnormal pressure of the second exhaust pipeline 9021 detected by the pressure detection device 820, thereby protecting the exhaust device 130.

[0102] Optionally, the semiconductor process equipment can further include a heating member, which can be used to heat the fifth pipeline 905, thereby preventing the fifth pipeline 905 from being blocked due to the liquefaction of the gas before entering the chamber body 100.

[0103] Please refer to Figure 19 and Figure 20 , the semiconductor process equipment can include a splash-proof box 840, which can be provided in the second source liquid device 760, and the top of the second source liquid device 760 can have an exhaust port 761. The splash-proof box 840 can include an inner shell 841 and an outer shell 842, the inner shell 841 can be buckled on the exhaust port 761, the outer shell 842 can be buckled on the inner shell 841, and there is a liquid storage space 844 between the inner shell 841 and the outer shell 842, the side wall of the inner shell 841 adjacent to the exhaust port 761 is provided with a first filter hole 841a, the side wall of the outer shell 842 adjacent to the exhaust port 761 is provided with a second filter hole 842a, and the second filter hole 842a is located on the side of the inner shell 841 away from the first filter hole 841a, the second exhaust pipeline 9021 communicates with the exhaust port 761, so that the first filter hole 841a, the liquid storage space 844 and the second filter hole 842a form a labyrinth channel, thereby better preventing the liquid in the second source liquid device 760 from entering the exhaust device 130, thereby protecting the exhaust device 130.

[0104] Further, the bottom wall of the outer shell 842 opposite to the exhaust port 761 can be movably connected with the side wall of the outer shell 842, and a splash-proof liquid level sensor 843 can be arranged in the liquid storage space, in the case that the liquid level of the liquid storage space triggers the splash-proof liquid level sensor 843, the bottom wall of the outer shell 842 can move relative to the side wall of the outer shell 842, so that the liquid in the liquid storage space 844 flows back to the second source liquid device 760 through the side of the bottom wall of the outer shell 842, thereby avoiding that too much liquid in the liquid storage space 844 causes the gas to be unable to be discharged through the channel of the liquid storage space 844.

[0105] It should be noted that the opening and closing of the pipeline in the semiconductor process equipment disclosed in the embodiments of the present application can be controlled by the valve on the corresponding pipeline. The first precursor can be a Si element-containing compound, and the second precursor can be oxygen. Of course, the first precursor and the second precursor can also be other kinds, which can be selected according to different process requirements.

[0106] It should be noted that the carrier gas and the gas after the vaporizer 750 vaporizes the first source liquid device 740 together to form the second precursor. The fourth gas source device can be used to output the etching gas. The fifth gas source device 770 is used to output the purge gas, for example, the purge gas can be an inert gas such as nitrogen, which can be used to purge the pipeline.

[0107] The focus of the above embodiments of the present application is the difference between the various embodiments. The different optimization features of the various embodiments can be combined to form a more optimal embodiment without contradiction. In view of the brevity of the text, further description is omitted here.

[0108] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above specific embodiments. The above specific embodiments are only illustrative and not restrictive. Those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope of protection of the claims, which are all within the scope of protection of the present application.

Claims

1. A semiconductor process chamber, comprising: The chamber body (100), the base (200) and the first inner liner (300) are provided, wherein the base (200) is arranged in the chamber body (100), the first inner liner (300) is movably arranged in the chamber body (100), and the first inner liner (300) surrounds the base (200) and is located between the base (200) and the chamber body (100); When a deposition process is performed in the semiconductor process chamber, the first inner liner (300) is moved to a first position, and at least a part of the first inner liner (300) is higher than a bearing surface (201) of the base (200); When an etching process is performed in the semiconductor process chamber, the first inner liner (300) is moved to a second position, and the first inner liner (300) is lower than the bearing surface (201) or flush with the bearing surface (201).

2. The semiconductor process chamber of claim 1, wherein, A top wall (110) of the chamber body (100) is provided with a first gas inlet hole, a sidewall (120) of the chamber body (100) is provided with a second gas inlet hole which is higher than the bearing surface (201), and the first inner liner (300) is provided with a first avoiding hole (301); When the deposition process is performed in the semiconductor process chamber, the second gas inlet hole is opposite to the first avoiding hole (301), the first gas inlet hole is used for introducing a first precursor, the second gas inlet hole is used for introducing a second precursor, and the first precursor and the second precursor perform the deposition process in the chamber body (100); When the etching process is performed in the semiconductor process chamber, the first inner liner (300) is located below the second gas inlet hole, and the first gas inlet hole is used for introducing an etching gas.

3. The semiconductor process chamber of claim 2, wherein, The semiconductor process chamber further comprises a gas emitter (400), and the first gas inlet hole and the second gas inlet hole are both provided with the gas emitter (400); When the deposition process is performed in the semiconductor process chamber, the gas emitter (400) located at the second gas inlet hole has a first gap (101) between the gas emitter (400) and an orifice of the first avoiding hole (301) which faces a side of the sidewall (120).

4. The semiconductor process chamber of claim 1, wherein, The first inner liner (300) comprises a body part (310), an inclined part (320) and an extension part (330), the body part (310) is a cylindrical structure, a first end of the inclined part (320) is connected with a first port of the body part (310), a second end of the inclined part (320) is connected with a first end of the extension part (330), the second end of the inclined part (320) is inclined toward a side of a central axis of the cylindrical structure, a second end of the extension part (330) extends toward a side where the central axis of the cylindrical structure is located, and the extension part (330) is parallel to the bearing surface (201).

5. The semiconductor process chamber of claim 4, wherein, When the deposition process is performed in the semiconductor process chamber, the extension part (330) has a second gap (102) with the top wall (110) of the chamber body (100); The extension (330) is below the bearing surface (201) or flush with the bearing surface (201) when the etching process is performed in the semiconductor process chamber.

6. The semiconductor process chamber of claim 5, wherein, The susceptor (200) comprises a susceptor body (210) and a flow uniformizer (220), the flow uniformizer (220) is circumferentially arranged on the susceptor body (210) and below the bearing surface (201), the flow uniformizer (220) is provided with a plurality of flow uniformizing holes circumferentially distributed around the susceptor body (210), and the chamber body (100) is provided with an exhaust hole below the flow uniformizer (220). The extension (330) has a third gap (103) with the flow uniformizer (220) when the etching process is performed in the semiconductor process chamber.

7. The semiconductor process chamber of claim 6, wherein, In the radial direction of the bearing surface (201), the extension (330) covers the edge area of the flow uniformizing hole.

8. The semiconductor process chamber of claim 1, wherein, The semiconductor process chamber further comprises a driving mechanism (500) arranged in the chamber body (100) and connected with the first inner liner (300) for driving the first inner liner (300) to switch between the first position and the second position.

9. The semiconductor process chamber of claim 8, wherein, The driving mechanism (500) is a plurality of, the susceptor (200) comprises a susceptor body (210) and a plurality of cantilevers (230), a plurality of the cantilevers (230) are circumferentially arranged on the susceptor body (210) and one-to-one correspond to a plurality of the driving mechanisms (500), at least one of the cantilevers (230) is connected with the chamber body (100), and the other cantilevers (230) have one end connected with the susceptor body (210) and the other end suspended and spaced apart from the chamber body (100), and the driving mechanism (500) is arranged on the cantilever (230). The first inner liner (300) is provided with a strip-shaped hole (311) extending along the direction in which the first inner liner (300) moves between the first position and the second position, and the cantilever (230) connected with the chamber body (100) penetrates into the strip-shaped hole (311).

10. The semiconductor process chamber of claim 2, wherein, The semiconductor process chamber further comprises a second inner liner (600) arranged in the chamber body (100) and detachably arranged on the side wall (120), the second inner liner (600) is provided with a second avoiding hole (601), in the case that the first inner liner (300) moves to the first position, the second inner liner (600) is located between the first inner liner (300) and the chamber body (100), and the central axis of the second gas inlet hole, the central axis of the first avoiding hole (301) and the central axis of the second avoiding hole (601) coincide.

11. The semiconductor process chamber of claim 2, wherein, The two hole openings of the first avoiding hole (301) are circular chamfer structures.

12. The semiconductor process chamber of claim 10, wherein, The two hole openings of the second avoiding hole (601) are circular chamfer structures.

13. A semiconductor process apparatus characterized by comprising: The semiconductor processing chamber includes the semiconductor processing chamber according to any one of claims 1 to 12, a first pipeline (901) in communication with a first gas inlet hole formed in a top wall (110) of the chamber body (100), and a fifth pipeline (905) in communication with a second gas inlet hole formed in a side wall (120) of the chamber body (100), the first pipeline (901) being used for selectively introducing a first precursor or an etching gas into the first gas inlet hole, and the fifth pipeline (905) being used for introducing a second precursor; During the deposition process in the semiconductor processing chamber, the first pipeline (901) and the fifth pipeline (905) alternately introduce the first precursor and the second precursor; During the etching process in the semiconductor processing chamber, the first pipeline (901) introduces the etching gas.

14. The semiconductor process apparatus according to claim 13, wherein The semiconductor processing equipment further includes a first source liquid device (740), a vaporizer (750), a second source liquid device (760), and a condenser (810), the first source liquid device (740) being connected with the vaporizer (750), the vaporizer (750) and the second source liquid device (760) being connected in parallel to the fifth pipeline (905), and the condenser (810) being arranged between the vaporizer (750) and the second source liquid device (760); During the deposition process in the semiconductor processing chamber, the vaporizer (750) is in communication with the fifth pipeline (905), and the vaporizer (750) is disconnected from the second source liquid device (760); During the etching process in the semiconductor processing chamber, the vaporizer (750) is disconnected from the fifth pipeline (905), and the vaporizer (750) is in communication with the second source liquid device (760).

15. The semiconductor process apparatus according to claim 14, wherein The semiconductor processing equipment further includes an eighth pipeline (908) and a ninth pipeline (909), the eighth pipeline (908) being connected with the second source liquid device (760), and the second source liquid device (760) being connected with the first source liquid device (740) through the ninth pipeline (909); When the semiconductor processing equipment replenishes the first source liquid device (740), the eighth pipeline (908) is used for introducing a gas into the second source liquid device (760) to drive the liquid in the second source liquid device (760) to enter the first source liquid device (740) through the ninth pipeline (909).

16. The semiconductor process apparatus according to claim 14, wherein The semiconductor processing equipment includes a splash-proof box (840), the splash-proof box (840) being arranged in the second source liquid device (760), and a top portion of the second source liquid device (760) having an exhaust port (761); The splash-proof box (840) comprises an inner shell (841) and an outer shell (842), the inner shell (841) is buckled on the exhaust port (761), the outer shell (842) is buckled on the inner shell (841), and a liquid storage space (844) is formed between the inner shell (841) and the outer shell (842), a first filter hole (841a) is formed in the side wall of the inner shell (841) adjacent to the exhaust port (761), a second filter hole (842a) is formed in the side wall of the outer shell (842) adjacent to the exhaust port (761), and the second filter hole (842a) is located on the side of the inner shell (841) away from the first filter hole (841a), and a second exhaust pipeline (9021) is in communication with the exhaust port (761).

17. The semiconductor process apparatus according to claim 16, wherein The bottom wall of the outer shell (842) opposite to the exhaust port (761) is movably connected with the side wall of the outer shell (842), a splash-proof liquid level sensor (843) is arranged in the liquid storage space, and in the case that the liquid level of the liquid storage space triggers the splash-proof liquid level sensor (843), the bottom wall of the outer shell (842) moves relative to the side wall of the outer shell (842) to make the liquid in the liquid storage space (844) flow back to the second liquid source device (760) through the side of the bottom wall of the outer shell (842).

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