Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate; forming a gate structure on the substrate; forming an etching barrier layer, the etching barrier layer covering the gate structure and the substrate; using multiple rounds of processes to form a filling layer covering the etching barrier layer, each round of processes at least comprising: using a deposition process to form a filling sublayer, starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer; using an etching process to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer; wherein the process parameters of the etching process are the same or different between different rounds of processes. The embodiments of the present invention are conducive to improving the manufacturing yield of semiconductor devices.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] In advanced semiconductor devices, as the feature size continues to decrease, the semiconductor filling layer has become an indispensable part of the semiconductor structure. The filling layer is usually located between different semiconductor devices and can effectively prevent signal interference and leakage between different areas. By selecting a filling layer material with suitable insulation properties, an independent working environment can be provided for each functional area, thereby improving the reliability and performance of semiconductor devices.

[0003] However, the existing filling process of the semiconductor structure reduces the manufacturing yield of the semiconductor device. Therefore, how to provide a technical solution to improve the filling process of the semiconductor structure to improve the manufacturing yield of the semiconductor device has become a technical problem that those skilled in the art need to solve urgently. Summary of the invention

[0004] The technical problem solved by the present invention is to improve the manufacturing yield of semiconductor devices by providing a semiconductor structure and a forming method thereof.

[0005] In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising:

[0006] A substrate is provided; a gate structure is formed on the substrate; an etching barrier layer is formed, the etching barrier layer covers the gate structure and the substrate; a filling layer covering the etching barrier layer is formed by multiple rounds of processes, each round of processes at least comprising: a deposition process is used to form a filling sublayer, and starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer; an etching process is used to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer; wherein the process parameters of the etching process are the same or different between different rounds of processes.

[0007] Optionally, in the process of forming the etch stop layer, a top corner of the etch stop layer covering the gate structure is formed with a sharp corner;

[0008] In the first round of etching process, a portion of the sharp corner of the etch stop layer is removed from the surface of the current filling sub-layer to form a curved top corner.

[0009] Optionally, the etching gas of the first etching process is C x1 F y1 , the ratio of x1 to y1 is greater than or equal to 1 / 2.

[0010] Optionally, the number of rounds of the multi-round process is greater than or equal to 2, and the etching gas of the second round of etching process is C x2 F y2 ;

[0011] Among them, the C x1 F y1 The ratio of x1 to y1 is greater than that of C x2 F y2 The ratio of x2 to y2 in .

[0012] Optionally, the number of rounds of the multi-round process is greater than or equal to 3, and the etching gas of the third round of etching process is C x3 F y3 ;

[0013] Among them, the C x3 F y3 The ratio of x3 to y3 is greater than the C x2 F y2 The ratio of x2 to y2 in .

[0014] Optionally, the etching gas of the etching process includes a combination of one or more of the following: tetracarbon octafluoride C4F8, pentacarbon octafluoride C5F8, and tetracarbon hexafluoride C4F6.

[0015] Optionally, in each round of the process, the film thickness of the deposited current filling sublayer is recorded as the first film thickness, and the remaining film thickness after etching away the current filling sublayer is recorded as the second film thickness, and the ratio of the first film thickness to the second film thickness is less than or equal to 2:1.

[0016] Optionally, the material of the etch stop layer includes: silicon nitride;

[0017] The material of the filling layer includes silicon oxide.

[0018] Optionally, before forming the gate structure on the substrate, the forming method further includes:

[0019] forming a groove on the substrate;

[0020] forming a dielectric repair layer covering the sidewalls and bottom of the groove;

[0021] Filling the groove to form a dielectric isolation layer;

[0022] forming a well region on the substrate;

[0023] forming a gate dielectric layer on the well region;

[0024] Wherein, the gate structure is located on the gate dielectric layer.

[0025] Optionally, after forming the gate structure and before forming the etching stop layer, the forming method further includes:

[0026] forming a sidewall covering the sidewall of the gate structure;

[0027] forming source-drain doped layers in the well regions on both sides of the gate structure;

[0028] forming a pinning layer on the source-drain doped layer;

[0029] After forming the sidewalls and before forming the source-drain doping layers, a lightly doped source is formed between the source doping layer and the sidewalls, and a lightly doped drain is formed between the drain doping layer and the sidewalls.

[0030] Correspondingly, an embodiment of the present invention also provides a semiconductor structure, including: a substrate; a gate structure located on the substrate; an etch stop layer covering the gate structure and the substrate; and a filling layer including multiple filling sublayers covering the etch stop layer.

[0031] Optionally, the semiconductor structure further includes:

[0032] The top angle of the etching stop layer covering the gate structure is an arc-shaped top angle;

[0033] The first filling sublayer exposes the arc-shaped top corner.

[0034] Optionally, the number of the filling sublayers is greater than or equal to 2;

[0035] Among them, the arc-shaped vertex angle exposed by the first filling sublayer has a first arc and a first arc length, the arc-shaped vertex angle formed by the second filling sublayer has a second arc and a second arc length, the second arc is greater than or equal to the first arc, and the second arc length is greater than the first arc length.

[0036] Optionally, the number of filling sublayers is greater than or equal to 3;

[0037] Among them, the arc-shaped vertex angle exposed by the first filling sublayer has a first curvature and a first arc length, the arc-shaped vertex angle formed by the second filling sublayer has a second curvature and a second arc length, and the arc-shaped vertex angle formed by the third filling sublayer has a third curvature and a third arc length, the third curvature is greater than or equal to the second curvature, the second curvature is greater than or equal to the first curvature, the third arc length is greater than the second arc length, and the second arc length is greater than the first arc length.

[0038] Optionally, the material of the etch stop layer includes: silicon nitride;

[0039] The material of the filling layer includes silicon oxide.

[0040] Optionally, the semiconductor structure further includes:

[0041] A groove located on the substrate;

[0042] A dielectric repair layer, covering the sidewall and bottom of the groove;

[0043] A dielectric isolation layer is filled in the groove;

[0044] A well region, located on the substrate;

[0045] A gate dielectric layer, located on the well region;

[0046] Wherein, the gate structure is located on the gate dielectric layer;

[0047] A sidewall, covering a sidewall of the gate structure;

[0048] Source-drain doped layers, located in the well regions on both sides of the gate structure;

[0049] A pinning layer, located on the source and drain doping layer;

[0050] A lightly doped source electrode, located between the sidewall and the source doping layer;

[0051] The lightly doped drain is located between the sidewall and the drain doping layer.

[0052] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0053] The method for forming a semiconductor structure provided by an embodiment of the present invention includes: using multiple rounds of processes to form a filling layer covering the etching barrier layer, each round of processes at least includes: using a deposition process to form a filling sublayer, starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer; using an etching process to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer, that is, the filling layer formed by using multiple rounds of processes includes multiple layers of filling sublayers, and each filling sublayer is etched to remove a portion of its thickness, which can reduce the probability of generating voids in the filling layer, thereby improving the manufacturing yield of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0055] Figures 1 to 4 It is a schematic diagram of structures corresponding to each step in a method for forming a semiconductor structure;

[0056] Figures 5 to 14 It is a schematic diagram of the structures corresponding to each step in the method for forming a semiconductor structure according to the first embodiment of the present invention;

[0057] Figure 15 to Figure 16 It is a partial structural schematic diagram corresponding to each step in the semiconductor structure forming method of the second embodiment of the present invention. DETAILED DESCRIPTION

[0058] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0059] As can be seen from the background technology, the prior art has the problem of reduced yield rate of semiconductor device manufacturing. Figures 1 to 4 A method for forming a semiconductor structure is provided to analyze the reasons for the reduction in the yield of semiconductor device manufacturing. The method for forming a semiconductor structure mainly includes the following steps:

[0060] refer to Figure 1 and Figure 2 , providing a substrate 10 , on which a P-type well region 11 and an N-type well region 12 are formed.

[0061] refer to Figure 3 , forming a gate dielectric layer 13 covering the P-type well region 11 and the N-type well region 12 ; forming a gate structure 14 on the gate dielectric layer 13 ; and forming a sidewall 15 on the sidewall of the gate structure 14 .

[0062] refer to Figure 4 In the P-type well region 11, a P-type doping 16 and a P-type doping 18 are formed at the gate sidewall 15. In the N-type well region 12, an N-type doping 20 and an N-type doping 22 are formed at the gate sidewall 15.

[0063] A P-type doped source 17 and a drain 19 are formed in the P-type well region 11. A N-type doped source 21 and a drain 23 are formed in the N-type well region 12.

[0064] A filling layer 24 is formed on the substrate 10 at one time. The filling layer 24 covers and fills between the semiconductor device 25 and the semiconductor device 26 .

[0065] Continue to refer Figure 4In the existing semiconductor structure manufacturing process, when the filling layer 24 is formed between the semiconductor device 25 and the semiconductor device 26, a void Void will be generated in the film layer of the filling layer 24. For example, when the void 27 appears near the upper end of the gate structure 14, the probability of the semiconductor structure being damaged by static electricity during the manufacturing process is increased, the pressure resistance of the semiconductor device is reduced, and thus the manufacturing yield of the semiconductor device is reduced. For another example, when the void 28 appears between the gate structure 14 and the P-type source 17, there is a difference between the gate-source capacitance (i.e., the capacitance between the gate structure 14 and the source 17) and the gate-drain capacitance (i.e., the capacitance between the gate structure 14 and the drain 19) of the semiconductor structure, which reduces the uniformity of the performance of the semiconductor device, thereby reducing the manufacturing yield of the semiconductor device.

[0066] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure.

[0067] The formation method includes: providing a substrate; forming a gate structure on the substrate; forming an etch barrier layer, wherein the etch barrier layer covers the gate structure and the substrate; using multiple rounds of processes to form a filling layer covering the etch barrier layer, wherein each round of processes at least includes: using a deposition process to form a filling sublayer, wherein starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer; using an etching process to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer; wherein the process parameters of the etching process are the same or different between different rounds of processes.

[0068] In the method for forming a semiconductor structure, multiple rounds of processes are used to form a filling layer covering the etching barrier layer, and each round of processes at least includes: using a deposition process to form a filling sublayer, starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer; using an etching process to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer, that is, the filling layer formed by multiple rounds of processes includes multiple layers of filling sublayers, and each filling sublayer is etched to remove a portion of its thickness, which can reduce the probability of generating voids in the filling layer, thereby improving the manufacturing yield of semiconductor devices.

[0069] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0070] refer to Figures 5 to 14 , is a schematic structural diagram corresponding to each step in the semiconductor structure forming method of the first embodiment of the present invention.

[0071] refer to Figure 5 , providing a substrate 200.

[0072] The substrate 200 is used to provide a process platform for forming a semiconductor structure.

[0073] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium, and the substrate 200 can also be a silicon substrate 200 on an insulator or a germanium substrate 200 on an insulator, and other types of substrates 200. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 can also be formed on the surface of the substrate 200 to improve the quality of pattern transfer.

[0074] It should be noted that Figure 5 This is a schematic diagram, and the entire structure of the substrate 200 is not shown. For example, in the process of forming the substrate 200, other appropriate regions may be formed, such as an isolation layer, for example, a well region formed in the substrate 200, and the well region is located above the isolation layer.

[0075] Continue to refer Figure 5 The substrate 200 includes a first device region 201 and a second device region 202 for forming a semiconductor device.

[0076] refer to Figure 6 Before forming the well region on the substrate 200 , the forming method further includes: forming a groove 203 on the substrate 200 .

[0077] The groove 203 is located at the junction of the first device area 201 and the second device area 202, and is used to provide a position space for the subsequent formation of a dielectric repair layer and a dielectric isolation layer.

[0078] In this embodiment, the main process steps for forming the groove 203 include:

[0079] A photoresist (not shown) is coated on the substrate 200 , and the groove 203 is formed through an exposure, development and etching process.

[0080] Continue to refer Figure 6 , forming a dielectric repair layer 204 covering the sidewall and bottom of the groove 203.

[0081] During the process of forming the groove 203, the side wall of the groove 203 is rough. The dielectric repair layer 204 is used to make the side wall of the groove 203 smooth, providing a good contact interface for the subsequent formation of the dielectric isolation layer, thereby improving the isolation effect of the dielectric isolation layer between semiconductor devices.

[0082] The material of the dielectric repair layer 204 includes: one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon fluoride. The silicon nitride has a thermal expansion coefficient that matches that of silicon. In this embodiment, the material of the dielectric repair layer 204 is silicon oxide.

[0083] In this embodiment, the main process of forming the dielectric repair layer 204 covering the sidewall and bottom of the groove 203 includes:

[0084] The material of the dielectric repair layer 204 is formed on the substrate 200 by using a furnace tube process.

[0085] Through exposure, development and etching processes, a dielectric repair layer 204 is formed in the groove 203 .

[0086] Continue to refer Figure 6 , a dielectric isolation layer 205 is filled in the groove 203 to form.

[0087] The dielectric isolation layer 205 is used to physically or electrically isolate semiconductor devices to prevent electrical interference between semiconductor devices.

[0088] The material of the dielectric isolation layer 205 includes one or more of silicon oxide, silicon nitride and silicon fluoride. The silicon oxide has good insulation, coverage and stability. In this embodiment, the material of the dielectric isolation layer 205 is silicon oxide.

[0089] In this embodiment, the main process steps of filling the groove 203 to form the dielectric isolation layer 205 include:

[0090] The material of the dielectric isolation layer 205 is formed on the substrate 200 by using a chemical vapor deposition process. The material of the dielectric isolation layer 205 is also filled in the groove 203 .

[0091] The material of the dielectric isolation layer 205 is formed by filling the groove 203 with a chemical mechanical polishing process.

[0092] refer to Figure 7 , forming a well region on the substrate 200;

[0093] The well region is used, on the one hand, to change the conductivity type of a local area so as to realize different types of transistors on the substrate 200 , and on the other hand, to improve the threshold voltage of the semiconductor device.

[0094] In this embodiment, the first device region 201 is doped with, for example, boron to form a P-type well region 206 through an ion implantation process, and the second device region 202 is doped with, for example, phosphorus to form an N-type well region 207 through an ion implantation process, so as to form different types of semiconductor devices in the first device region 201 and the second device region 202. In other embodiments, the first device region 201 is doped with, for example, phosphorus to form an N-type well region through an ion implantation process; and the second device region 202 is doped with, for example, boron to form a P-type well region through an ion implantation process.

[0095] refer to Figure 8 , a gate dielectric layer 208 is formed on the well region.

[0096] The gate dielectric layer 208 has the following beneficial effects: First, electrical insulation. As an electrical insulating material, it electrically isolates the gate structure to be formed later from the source, drain and conduction channel of the transistor. Second, it facilitates the adjustment of the electric field distribution at the semiconductor channel in coordination with the gate structure.

[0097] The material of the gate dielectric layer 208 includes: one or more of silicon oxide, silicon nitride, silicon carbonitride, and carbon nitride silicon oxide. The silicon oxide has the following advantages: First, it has excellent insulation properties and can electrically isolate the gate structure, semiconductor channel, and source and drain. Second, it has excellent coverage and good contact with semiconductor materials, which can reduce semiconductor channel leakage current. Third, it has good stability and enhances the reliability of semiconductor devices. In this embodiment, the material of the gate dielectric layer 208 is silicon oxide.

[0098] A gate dielectric layer 208 is formed on the well region. In this embodiment, that is, in the same process step, the gate dielectric layer 208 is formed on the P-type well region 206 and the N-type well region 207. In other embodiments, the gate dielectric layer 208 may be formed on the P-type well region 206 and the N-type well region 207 in separate process steps.

[0099] In this embodiment, the main process steps for forming the gate dielectric layer 208 on the well region include:

[0100] The material of the gate dielectric layer 208 is formed on the substrate 200 by using a furnace process or an in-situ vapor deposition process.

[0101] The gate dielectric layer 208 is formed on the P-type well region 206 and the N-type well region 207 through exposure, development and etching processes.

[0102] Continue to refer Figure 8 , a gate structure 209 is formed on the substrate 200 . The gate structure 209 is located on the gate dielectric layer 208 .

[0103] The gate structure 209 is used to control the on and off of the semiconductor device.

[0104] The material of the gate structure 209 includes: polysilicon or amorphous silicon. In this embodiment, the material of the gate structure 209 is polysilicon.

[0105] In this embodiment, the main process steps of forming the gate structure 209 on the substrate 200 include: using a chemical vapor deposition process to form the material of the gate structure 209 on the substrate 200.

[0106] The gate structure 209 is formed on the P-type well region 206 and the N-type well region 207 through an exposure, development and etching process.

[0107] Continue to refer Figure 8 After forming the gate structure 209 and before forming the etching stop layer, the forming method further includes: forming a sidewall 210 covering the sidewall of the gate structure 209 .

[0108] The sidewall spacer 210 is used to protect the gate structure 209 to prevent it from being damaged during subsequent processes.

[0109] The material of the sidewall spacer 210 includes one or more of silicon nitride, silicon oxide and silicon fluoride. The silicon nitride has good coverage. In this embodiment, the material of the sidewall spacer 210 is silicon nitride.

[0110] In this embodiment, the main process steps of forming the sidewall spacer 210 covering the sidewall of the gate structure 209 include: using an atomic layer deposition process to form the material of the sidewall spacer 210 on the substrate 200 .

[0111] Through exposure, development and etching processes, a sidewall spacer 210 is formed on the sidewall of the gate structure 209 .

[0112] refer to Fig. 9 After forming the sidewall 210 and before forming the source-drain doped layer, a lightly doped source is formed between the source doped layer and the sidewall 210 , and a lightly doped drain is formed between the drain doped layer and the sidewall 210 .

[0113] The lightly doped source and the lightly doped drain, that is, the LDD (Lightly Doped Drain: LDD) in the semiconductor structure, have the following beneficial effects: First, the breakdown voltage is improved. The LDD structure helps to reduce the concentration of the electric field near the source and drain, thereby improving the voltage resistance of the device. Second, the leakage current is controlled. By introducing a lightly doped region near the source and drain, the impedance between the source and drain and the gate structure is increased, thereby reducing the leakage current of the semiconductor structure.

[0114] In this embodiment, the main process steps of forming a lightly doped source between the source doping layer and the sidewall 210 and forming a lightly doped drain between the drain doping layer and the sidewall 210 include:

[0115] A first hard mask (not shown) is formed on the substrate 200 . The hard mask has a first opening for defining an LDD doping region in the P-type well region 206 .

[0116] By ion implantation, in the P-type well region 206 , boron is doped between the source doping layer and the gate structure 209 to form a lightly doped source 211 , and boron is doped between the drain doping layer and the gate structure 209 to form a lightly doped drain 212 .

[0117] A second hard mask (not shown) is formed on the substrate 200 . The hard mask has a second opening for defining an LDD doping region in the N-type well region 207 .

[0118] By ion implantation, phosphorus is doped between the source doping layer and the gate structure 209 to form a lightly doped source 213 , and phosphorus is doped between the drain doping layer and the gate structure 209 to form a lightly doped drain 214 .

[0119] Continue to refer Fig. 9 , forming source and drain doping layers in the well regions on both sides of the gate structure 209 .

[0120] The source-drain doped layers, together with the gate structure 209 , control the flow of carriers in the semiconductor channel.

[0121] In this embodiment, the main process steps of forming the source-drain doping layer in the well regions on both sides of the gate structure 209 include:

[0122] A third hard mask (not shown) is formed on the substrate 200 . The hard mask has a third opening for defining source and drain doping regions in the P-type well region 206 .

[0123] By ion implantation, the P-type well region 206 is heavily doped with, for example, boron to form a source doping layer 215 in contact with the lightly doped source 211 and a drain doping layer 216 in contact with the lightly doped drain 212 .

[0124] A fourth hard mask (not shown) is formed on the substrate 200 . The hard mask has a fourth opening for defining a source-drain doping region in the N-type well region 207 .

[0125] By ion implantation, the N-type well region 207 is heavily doped with, for example, phosphorus, to form a source doping layer 217 in contact with the lightly doped source 213 and a drain doping layer 218 in contact with the lightly doped drain 214 .

[0126] It should be noted that, in other embodiments, the LDD doped region defined in the P-type well region 206 and the source-drain doped region defined in the P-type well region 206 may share the same mask, such as the fifth hard mask, to save manufacturing steps. The LDD doped region defined in the N-type well region 207 and the source-drain doped region defined in the N-type well region 207 may share the same hard mask, such as the sixth hard mask, to save manufacturing steps.

[0127] In this embodiment, after the source-drain doping layers are formed in the well regions on both sides of the gate structure 209 , an annealing process is performed to activate the doped elements in the doping process.

[0128] Continue to refer Fig. 9 , a pinning layer 219 is formed on the source-drain doping layer.

[0129] The pinning layer 219 has the following beneficial effects: First, it improves the interface characteristics of semiconductor materials. There are usually defects on the surface of doped semiconductor materials, and the surface state of semiconductor materials is improved by forming a pinning layer 219. Second, it reduces contact resistance. By forming a pinning layer 219 on the source-drain doping layer and the gate structure, the contact resistance between the source-drain doping layer and the gate structure and the metal electrode can be reduced. Third, it improves the reliability of the device. The pinning layer 219 can reduce the mutual diffusion between the metal electrode and the semiconductor material, thereby improving the stability of the device in harsh environments such as high temperature and high humidity.

[0130] The material of the pinning layer 219 includes: metal or metal nitride, and the metal includes titanium and copper. In this embodiment, the material of the pinning layer 219 is metal copper.

[0131] In this embodiment, a sputtering process in physical vapor deposition is used to form the material of the pinning layer 219 on the substrate 200, and an exposure, development and etching process is used to form the pinning layer 219 on the source and drain doping layer. The pinning layer 219 also covers the top of the gate structure 209.

[0132] refer to Fig.10 , forming an etch stop layer 220 , wherein the etch stop layer 220 covers the gate structure 209 and the substrate 200 .

[0133] The etching stop layer 220 has the following beneficial effects: first, it protects the gate structure 209; the first filling sublayer subsequently formed at the sharp corner 221 on the gate structure 209 has a poor film quality, and the first filling sublayer at the sharp corner 221 will be etched away, causing the gate structure 209 at the sharp corner 221 to also be etched, affecting the characteristics of the semiconductor device. Therefore, the etching stop layer 220 is formed to protect the gate structure 209. Second, it protects the substrate 200; when the first filling sublayer is formed, there may be voids in the first filling sublayer, resulting in the exposure of the substrate 200 at the voids. When the first filling sublayer is etched, the exposed substrate 200 is also etched. The exposed area of ​​the substrate 200 may be, for example, a P-type well region and / or an N-type well region.

[0134] The material of the etching stop layer 220 includes silicon nitride.

[0135] In this embodiment, the etch stop layer 220 is formed by a chemical vapor deposition process. The etch stop layer 220 covers the gate structure 209 and the substrate 200 .

[0136] Continue to refer Fig.10 In the process of forming the etching stop layer 220 , a sharp corner 221 is formed at the top corner of the etching stop layer 220 covering the gate structure 209 , which increases the probability that the film quality of the subsequently formed filling sublayer will deteriorate at the sharp corner 221 .

[0137] By making the film thickness of the etch stop layer 220 greater than or equal to 100 angstroms, the gate structure 209 and the substrate 200 can be well protected; by making the film thickness of the etch stop layer 220 less than or equal to 300 angstroms, the process manufacturing cycle can be reduced. The film thickness of the etch stop layer 220 is within the range of greater than or equal to 100 angstroms and less than or equal to 300 angstroms.

[0138] A filling layer covering the etching stop layer is formed by adopting multiple rounds of processes, and each round of processes at least includes: adopting a deposition process to form a filling sublayer, and starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer; adopting an etching process to remove a part of the thickness of the filling sublayer from the surface of the current filling sublayer; wherein the process parameters of the etching process are the same or different between different rounds of processes.

[0139] In each round of the process, the thickness of the deposited current filling sublayer is recorded as the first film thickness, and the remaining film thickness after etching away the current filling sublayer is recorded as the second film thickness. The ratio of the first film thickness to the second film thickness is less than or equal to 2:1.

[0140] The filling layer formed by the multi-round process includes multiple filling sub-layers, and each filling sub-layer is etched to remove a portion of its thickness, which can reduce the probability of generating voids in the filling layer, thereby improving the manufacturing yield of the semiconductor device.

[0141] The filling layer has the following beneficial effects: First, as an isolation layer; the filling layer is used to isolate semiconductor devices, prevent electrical interference between different areas, and ensure stable operation of the device. Second, stress buffering; the filling layer can be used to relieve the stress caused by the different thermal expansion coefficients of different materials, and prevent the performance degradation of semiconductor devices due to long-term operation. Third, protective effect; the filling layer can also serve as a protective layer to prevent the surface of the semiconductor device from being contaminated or physically damaged, thereby extending the service life of the device.

[0142] The material of the filling layer includes silicon oxide.

[0143] refer to Figures 11 to 14 , is a schematic diagram of the process steps for forming two filling sub-layers in this embodiment.

[0144] The number of rounds of the multi-round process is greater than or equal to 2. In this embodiment, a two-round process is used to form a filling layer covering the etching stop layer 220. The two-round process includes:

[0145] First round of process: adopting the first round of deposition process to form a first filling sub-layer; adopting the first round of etching process to remove a part of the thickness of the first filling sub-layer.

[0146] refer to Fig.11 , a first round of deposition process is used to form a first filling sub-layer 222 .

[0147] In this embodiment, the material of the first filling sub-layer 222 includes silicon oxide.

[0148] The first filling sublayer 222 is formed by using an atomic layer deposition process or a chemical vapor deposition process.

[0149] That is, the material forming the first filling sublayer 222. The first filling sublayer 222 covers the surface of the etching stop layer 220. The film layer formed by the atomic layer deposition method is thin and uniform, has a dense structure, has no pinholes, and has good adhesion to the etching stop layer 220. In this embodiment, the atomic layer deposition process is used to form the first filling sublayer 222.

[0150] refer to Fig.12 , an etching process is used to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer. In the present embodiment, that is, a first round of etching process is used to remove a portion of the thickness of the first filling sublayer 222.

[0151] A dry etching process is used to remove a portion of the thickness of the first filling sub-layer 222 .

[0152] It should be noted that, in the first round of etching process, a portion of the sharp corner 221 of the etch stop layer 220 is removed from the surface of the current first filling sub-layer 222 to form an arc-shaped top corner 223 .

[0153] In this embodiment, the etching gas of the first etching process is C x1 F y1 , the ratio of x1 to y1 is greater than or equal to 1 / 2, that is, in the etching gas C x1 F y1 Increasing the carbon content to dilute the fluorine content has the following beneficial effects: first, it can reduce the etching loss of the etching barrier layer 220 in the first round of etching process, reduce the risk of gate structure exposure near the top corner of the etching barrier layer 220, and improve the manufacturing yield of the semiconductor device; second, it can make the transition of the arc-shaped top corner 223 formed at the top corner of the etching barrier layer 220 smoother, which not only improves the coverage characteristics of the second filling sublayer at the arc-shaped top corner 223, but also improves the pressure resistance of the semiconductor device, such as anti-static ability.

[0154] The etching gas of the etching process includes one or more of the following combinations: tetracarbon octafluoride C4F8, pentacarbon octafluoride C5F8, tetracarbon hexafluoride C4F6. In this embodiment, the etching gas is tetracarbon hexafluoride C4F6.

[0155] In each round of the process, the thickness of the deposited current filling sublayer is recorded as the first film thickness, the remaining film thickness after etching away the current filling sublayer is recorded as the second film thickness, and the ratio of the first film thickness to the second film thickness is less than or equal to 2:1. In the present embodiment, in the first round of the process, the thickness of the deposited current first filling sublayer 222 is recorded as the first film thickness, the remaining film thickness after etching away the current first filling sublayer 222 is recorded as the second film thickness, and the ratio of the first film thickness to the second film thickness is less than or equal to 2:1, which has the following beneficial effects: the voids in the first filling sublayer 222 can be removed and / or the voids in the first filling sublayer 222 can be exposed, and the subsequently formed filling sublayer fills the exposed voids, thereby reducing the probability of voids in the filling layer and improving the manufacturing yield of semiconductor devices.

[0156] Second round of process: adopting a second round of deposition process to form a second filling sub-layer; adopting a second round of etching process to remove a part of the thickness of the second filling sub-layer.

[0157] refer to Fig.13 , a second round of deposition process is used to form a second filling sub-layer 224 .

[0158] In this embodiment, the material of the second filling sub-layer 224 includes silicon oxide.

[0159] A deposition process is used to form a filling sublayer. Starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer. In this embodiment, that is, an atomic layer deposition process or a chemical vapor deposition process is used to form the second filling sublayer 224, that is, the material of the second filling sublayer 224 is formed. The second filling sublayer 224 covers the previous first filling sublayer 222. The film layer formed by the atomic layer deposition method has the advantages of being thin and uniform, having a dense structure, no pinholes, and having good adhesion with the first filling sublayer 222. In this embodiment, the atomic layer deposition process is used to form the second filling sublayer 224.

[0160] refer to Fig.14 , an etching process is used to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer. In this embodiment, that is, a second round of etching process is used to remove a portion of the thickness of the second filling sublayer 224 from the surface of the current second filling sublayer 224.

[0161] A dry etching process is used to remove a portion of the thickness of the second filling sub-layer 224 .

[0162] It should be noted that, in the second round of etching process, the second filling sub-layer 224 is etched so that the second filling sub-layer 224 forms an arc-shaped top corner 225 .

[0163] In this embodiment, the etching gas of the second etching process is C x2 F y2 ; wherein, the C x1 F y1 The ratio of x1 to y1 is greater than that of C x2 F y2 The ratio of x2 to y2, that is, relative to the first etching process, the etching gas in the second etching process has a high fluorine content, which has the following beneficial effects: first, the arc-shaped top angle 225 formed by the second filling sublayer 224 is made smoother; second, the etching rate of the second filling sublayer 224 is increased, saving the process production cycle.

[0164] The etching gas of the etching process includes one or more of the following combinations: tetracarbon octafluoride C4F8, pentacarbon octafluoride C5F8, tetracarbon hexafluoride C4F6. In this embodiment, the etching gas is tetracarbon octafluoride C4F8.

[0165] In each round of the process, the thickness of the deposited current filling sublayer is recorded as the first film thickness, the remaining film thickness after etching away the current filling sublayer is recorded as the second film thickness, and the ratio of the first film thickness to the second film thickness is less than or equal to 2: 1. In the present embodiment, in the second round of the process, the thickness of the deposited current second filling sublayer 224 is recorded as the first film thickness, the remaining film thickness after etching away the current second filling sublayer 224 is recorded as the second film thickness, and the ratio of the first film thickness to the second film thickness is less than or equal to 2: 1, which has the following beneficial effects: the voids in the second filling sublayer 224 can be removed and / or the voids in the second filling sublayer 224 can be exposed, and other dielectric layers formed subsequently can fill the exposed voids, thereby reducing the probability of voids in the filling layer and improving the manufacturing yield of semiconductor devices.

[0166] It should be noted that the process parameters of the etching process may be the same or different between different rounds of processes. In this embodiment, the process parameters of the first round of etching process and the second round of etching process are different, that is, the carbon and fluorine content in the etching gas are different.

[0167] refer to Figure 15 to Figure 16 , is a schematic diagram of the structure corresponding to some steps in the method for forming a semiconductor structure in the second embodiment of the present invention. Fig.16 and Fig.14 It can be seen from the comparison that the difference between this embodiment and the above-mentioned embodiment is only that a third filling sub-layer 226 is formed covering the second filling sub-layer 224 .

[0168] The number of rounds of the multi-round process is greater than or equal to 3. In this embodiment, a three-round process is used to form a filling layer covering the etching stop layer 220. The three-round process includes: a first round process, a second round process, and a third round process. The process methods of the first round process and the second round process can refer to the specific description of the above-mentioned embodiment, which will not be repeated here. In this embodiment, the third round process steps are mainly described.

[0169] refer to Fig.15 , a third round of deposition process is used to form a third filling sub-layer 226 .

[0170] In this embodiment, the material of the third filling sub-layer 226 includes silicon oxide.

[0171] A deposition process is used to form a filling sublayer. Starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer. In this embodiment, that is, an atomic layer deposition process or a chemical vapor deposition process is used to form the third filling sublayer 226, that is, the material of the third filling sublayer 226 is formed. The third filling sublayer 226 covers the previous second filling sublayer 224. The film layer formed by the atomic layer deposition method has the advantages of being thin and uniform, having a dense structure, having no pinholes, and having good adhesion with the second filling sublayer 224. In this embodiment, the atomic layer deposition process is used to form the third filling sublayer 226.

[0172] refer to Fig.16 , an etching process is used to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer. In this embodiment, that is, a third round of etching process is used to remove a portion of the thickness of the third filling sublayer 226 from the surface of the current third filling sublayer 226.

[0173] A dry etching process is used to remove a portion of the thickness of the third filling sub-layer 226 .

[0174] It should be noted that, in the third round of etching process, the third filling sub-layer 226 is etched so that the third filling sub-layer 226 forms an arc-shaped top corner 227 .

[0175] In this embodiment, the etching gas of the third etching process is C x3 F y3 ; wherein, the C x3 F y3 The ratio of x3 to y3 is greater than the C x2 F y2 The ratio of x2 to y2 in the etching process, relative to the second etching process, increases the carbon content in the etching gas of the third etching process to dilute the fluorine content, which has the following beneficial effects: the arc-shaped top corner 227 formed at the top corner of the third filling sublayer 226 can be made smoother, thereby improving the pressure resistance of the semiconductor device, such as the anti-static ability, and improving the manufacturing yield of the semiconductor device.

[0176] The etching gas of the etching process includes one or more of the following combinations: tetracarbon octafluoride C4F8, pentacarbon octafluoride C5F8, tetracarbon hexafluoride C4F6. In this embodiment, the etching gas is pentacarbon octafluoride C5F8.

[0177] In each round of the process, the film thickness of the deposited current filling sublayer is recorded as the first film thickness, and the remaining film thickness after etching away the current filling sublayer is recorded as the second film thickness, and the ratio of the first film thickness to the second film thickness is less than or equal to 2:1. In the present embodiment, in the third round of the process, the film thickness of the deposited current third filling sublayer 226 is recorded as the first film thickness, and the remaining film thickness after etching away the current third filling sublayer 226 is recorded as the second film thickness, and the ratio of the first film thickness to the second film thickness is less than or equal to 2:1, which has the following beneficial effects: the voids in the third filling sublayer 226 can be removed and / or the voids in the third filling sublayer 226 can be exposed, and the subsequently formed film layers fill the exposed voids, thereby reducing the probability of voids in the filling layer and improving the manufacturing yield of semiconductor devices.

[0178] It should be noted that the process parameters of the etching process are the same or different between different rounds of processes. In this embodiment, the process parameters of the first round of etching process and the second round of etching process are different, and the process parameters of the second round of etching process and the third round of etching process are different. In other embodiments, the process parameters of the first round of etching process, the second round of etching process and the third round of etching process are the same.

[0179] It should be noted that the number of rounds of the multi-round process involved in the present invention includes 2 rounds or 3 rounds, but this does not limit the present invention, and the number of rounds of the multi-round process can be selected according to actual needs.

[0180] In order to solve the technical problem, the present invention also provides a semiconductor structure corresponding to the formation method.

[0181] Fig.14 It is a schematic diagram of a semiconductor structure corresponding to the first embodiment of the semiconductor structure of the present invention.

[0182] refer to Fig.14 The semiconductor structure of this embodiment includes: a substrate 200; a gate structure 209 located on the substrate 200; an etch stop layer 220 covering the gate structure 209 and the substrate 200; and a filling layer including multiple filling sublayers covering the etch stop layer 220.

[0183] In the semiconductor structure of this embodiment, the filling layer includes multiple filling sub-layers, which have the following beneficial effects in the process of forming the semiconductor structure: first, the probability of generating voids in the filling layer can be reduced, thereby improving the manufacturing yield and reliability of the semiconductor device. Second, the risk of over-etching of the etching stop layer 220 can be reduced.

[0184] The substrate 200 is used to provide a process platform for forming a semiconductor structure.

[0185] In this embodiment, the substrate 200 is a silicon substrate 200, and the material of the substrate 200 is single crystal silicon. In other embodiments, the material of the substrate 200 can also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium, and the substrate 200 can also be a silicon substrate 200 on an insulator or a germanium substrate 200 on an insulator, and other types of substrates 200. In other embodiments, an epitaxial layer (not shown) having the same crystal structure as the substrate 200 can also be formed on the surface of the substrate 200 to improve the quality of pattern transfer.

[0186] It should be noted that Fig.14 This is a schematic diagram, and the entire structure of the substrate 200 is not shown. For example, in the process of forming the substrate 200, other appropriate regions may be formed, such as an isolation layer, for example, a well region formed in the substrate 200, and the well region is located above the isolation layer.

[0187] The substrate 200 includes a first device region 201 and a second device region 202 for forming a semiconductor device.

[0188] The gate structure 209 is located on the substrate 200. The gate structure 209 is used to control the opening and closing of the semiconductor device.

[0189] The material of the gate structure 209 includes: polysilicon or amorphous silicon. In this embodiment, the material of the gate structure 209 is polysilicon.

[0190] The etching stop layer 220 covers the gate structure 209 and the substrate 200 .

[0191] The etching stop layer 220 has the following beneficial effects: first, it protects the gate structure 209. Fig.11 The first filling sublayer (as shown in the figure) has poor film quality, and the first filling sublayer at the sharp corner 221 will be etched away, causing the gate structure 209 at the sharp corner 221 to be etched as well, affecting the characteristics of the semiconductor device. Therefore, an etching stop layer 220 is formed to protect the gate structure 209. Second, the substrate 200 is protected. When the first filling sublayer 222 is formed, there may be voids in the first filling sublayer 222, causing the substrate 200 at the voids to be exposed. When the first filling sublayer 222 is etched, the exposed substrate 200 is also etched. The exposed area of ​​the substrate 200 may be, for example, a P-type well region and / or an N-type well region.

[0192] The material of the etching stop layer 220 includes silicon nitride.

[0193] Continue to refer Fig.14, the top corner of the etching stop layer 220 covering the gate structure 209 is an arc-shaped top corner 223, wherein the first filling sublayer 222 exposes the arc-shaped top corner 223, such as Fig.12 The arc-shaped top corner 223 improves the coverage characteristics of the second filling sublayer at the arc-shaped top corner 223, and improves the pressure resistance of the semiconductor device, such as the anti-static ability.

[0194] The filling layer, including multiple filling sub-layers, covers the etching stop layer 220 .

[0195] The filling layer has the following beneficial effects: First, as an isolation layer. The filling layer is used to isolate between semiconductor devices, prevent electrical interference between different areas, and ensure the stable operation of the device. Second, stress buffering. The filling layer can be used to relieve the stress caused by the different thermal expansion coefficients of different materials, and prevent the performance degradation of semiconductor devices due to long-term operation. Third, protective effect. The filling layer can also serve as a protective layer to prevent the surface of the semiconductor device from being contaminated or physically damaged, thereby extending the service life of the device.

[0196] The material of the filling layer includes silicon oxide.

[0197] Continue to refer Fig.14 , the filling layer includes multiple filling sub-layers, and the number of filling sub-layers is greater than or equal to 2 layers; in this embodiment, the number of filling sub-layers is equal to 2 layers, and the filling layer includes a first filling sub-layer 222 and a second filling sub-layer 224.

[0198] The material of the first filling sub-layer 222 is silicon oxide, and the material of the second filling sub-layer 224 is silicon oxide.

[0199] Continue to refer Fig.12 and Fig.14 , the arc-shaped top angle 223 exposed by the first filling sublayer 222 has a first curvature and a first arc length, and the arc-shaped top angle 225 formed by the second filling sublayer 224 has a second curvature and a second arc length, the second curvature is greater than or equal to the first curvature, and the second arc length is greater than the first arc length, which has the following beneficial effects: First, the arc-shaped top angle of the second filling sublayer 224 at the etching barrier layer 220 can be made smoother, that is, the arc-shaped top angle 223 of the second filling sublayer 224 at the etching barrier layer 220 is avoided, which reduces the risk of the semiconductor device being damaged by static electricity at the sharp corner, and improves the anti-static ability of the semiconductor device. Second, the electric field of the gate structure 209 can be reduced. The concentration at the sharp corner reduces the risk of the semiconductor device being broken down at the sharp corner when the semiconductor device is working at high voltage, and improves the high-voltage resistance of the semiconductor device.

[0200] Continue to refer Fig.14 , the semiconductor structure further comprises:

[0201] The groove 203 is located on the substrate 200. The groove 203 is located at the junction of the first device area 201 and the second device area 202, and is used to provide a position space for forming a dielectric repair layer 204 and a dielectric isolation layer 205.

[0202] The dielectric repair layer 204 covers the sidewalls and bottom of the groove 203. The dielectric repair layer 204 is used to make the sidewalls of the groove 203 smooth, provide a good contact interface for forming the dielectric isolation layer 205, and improve the isolation effect of the dielectric isolation layer 205 between semiconductor devices.

[0203] The material of the dielectric repair layer 204 includes: one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon fluoride. The silicon nitride has a thermal expansion coefficient that matches that of silicon. In this embodiment, the material of the dielectric repair layer 204 is silicon nitride.

[0204] The dielectric isolation layer 205 is filled in the groove 203. The dielectric isolation layer 205 is used to physically or electrically isolate the semiconductor devices to prevent electrical interference between the semiconductor devices.

[0205] The material of the dielectric isolation layer 205 includes one or more of silicon oxide, silicon nitride and silicon fluoride. The silicon oxide has good insulation, coverage and stability. In this embodiment, the material of the dielectric isolation layer 205 is silicon oxide.

[0206] The well region is located on the substrate 200 .

[0207] The well region is used, on the one hand, to change the conductivity type of a local area so as to realize different types of transistors on the substrate 200 , and on the other hand, to improve the threshold voltage of the semiconductor device.

[0208] In this embodiment, the well region includes: a P-type well region 206 formed by doping elements such as boron in the first device region 201 , and an N-type well region 207 formed by doping elements such as phosphorus in the second device region 202 .

[0209] The gate dielectric layer 208 is located on the well region, wherein the gate structure 209 is located on the gate dielectric layer 208 .

[0210] The gate dielectric layer 208 has the following beneficial effects: First, electrical insulation. As an electrical insulating material, the gate structure 209 is electrically isolated from the source, drain and conduction channel of the transistor. Second, it is convenient to cooperate with the gate structure 209 to adjust the electric field distribution at the semiconductor channel.

[0211] The material of the gate dielectric layer 208 includes: one or more of silicon oxide, silicon nitride, silicon carbonitride, and carbon nitride silicon oxide. The silicon oxide has the following advantages: First, it has excellent insulation properties and can electrically isolate the gate structure, semiconductor channel, and source and drain. Second, it has excellent coverage and good contact with semiconductor materials, which can reduce semiconductor channel leakage current. Third, it has good stability and enhances the reliability of semiconductor devices. In this embodiment, the material of the gate dielectric layer 208 is silicon oxide.

[0212] The sidewall spacer 210 covers the sidewall of the gate structure 209 .

[0213] The sidewall spacer 210 is used to protect the gate structure 209 from being damaged.

[0214] The material of the sidewall spacer 210 includes one or more of silicon nitride, silicon oxide and silicon fluoride. The silicon nitride has good coverage. In this embodiment, the material of the sidewall spacer 210 is silicon nitride.

[0215] The lightly doped source is located between the side wall and the source doping layer; the lightly doped drain is located between the side wall and the drain doping layer. The lightly doped source and the lightly doped drain, that is, the LDD (Lightly Doped Drain: LDD) in the semiconductor structure, have the following beneficial effects: First, the breakdown voltage is improved. The LDD structure helps to reduce the electric field concentration near the source and drain, thereby improving the voltage resistance of the device. Second, the leakage current is controlled. By introducing a lightly doped region near the source and drain, the impedance between the source and drain and the gate structure is increased, thereby reducing the leakage current of the semiconductor structure.

[0216] The lightly doped source includes: a lightly doped source 211 located in the P-type well region 206 and in contact with the source doping layer 215 , and a lightly doped source 213 located in the N-type well region 207 and in contact with the source doping layer 217 .

[0217] The lightly doped drain includes: a lightly doped drain 212 located in the P-type well region 206 and in contact with the drain doping layer 216 , and a lightly doped drain 214 located in the N-type well region 207 and in contact with the drain doping layer 218 .

[0218] The source-drain doped layers are located in the well regions on both sides of the gate structure 209 .

[0219] The source-drain doped layers, together with the gate structure 209 , control the flow of carriers in the semiconductor channel.

[0220] The source-drain doping layer includes: a source doping layer 215 located in the P-type well region 206 and in contact with the lightly doped source 211, and a drain doping layer 216 in contact with the lightly doped drain 212. A source doping layer 217 located in the N-type well region 207 and in contact with the lightly doped source 213, and a drain doping layer 218 in contact with the lightly doped drain 214.

[0221] The pinning layer 219 is located on the source-drain doping layer.

[0222] The pinning layer 219 has the following beneficial effects: First, it improves the interface characteristics of semiconductor materials. There are usually defects on the surface of doped semiconductor materials, and the surface state of semiconductor materials is improved by forming a pinning layer 219. Second, it reduces contact resistance. By forming a pinning layer 219 on the semiconductor source and drain doping layer and the gate structure, the contact resistance between the source and drain doping layer and the gate structure and the metal electrode can be reduced. Third, it improves the reliability of the device. The pinning layer 219 can reduce the mutual diffusion between the metal electrode and the semiconductor material, thereby improving the stability of the device in harsh environments such as high temperature and high humidity.

[0223] The material of the pinning layer 219 includes: metal or metal nitride, and the metal includes titanium and copper. In this embodiment, the material of the pinning layer is copper.

[0224] Fig.16 Schematic diagram of a semiconductor structure corresponding to the second embodiment of the semiconductor structure of the present invention. Fig.16 and Fig.14 It can be seen from the comparison that the difference between this embodiment and the previous embodiment is only that the third filling sub-layer 226 covers the second filling sub-layer 224 .

[0225] The number of filling sub-layers is greater than or equal to 3. Fig.12 , Fig.14 and Fig.16In this embodiment, the number of filling sublayers is equal to 3 layers, wherein the arc-shaped vertex angle 223 exposed by the first filling sublayer 222 has a first curvature and a first arc length, the arc-shaped vertex angle 225 formed by the second filling sublayer 224 has a second curvature and a second arc length, and the arc-shaped vertex angle 227 formed by the third filling sublayer 226 has a third curvature and a third arc length, the third curvature is greater than or equal to the second curvature, the second curvature is greater than or equal to the first curvature, the third arc length is greater than the second arc length, and the second arc length is greater than the first arc length, which has the following beneficial effects: first, the arc-shaped vertex angle 225 of the third filling sublayer 226 can be made smoother at the arc-shaped vertex angle 225 of the second filling sublayer 224, that is, the arc-shaped vertex angle 225 of the third filling sublayer 226 is avoided from forming a sharp corner at the arc-shaped vertex angle 225 of the second filling sublayer 224, thereby reducing the risk of semiconductor devices being damaged by static electricity at sharp corners and improving the anti-static ability of semiconductor devices. Second, the electric field concentration of the gate structure 209 at the sharp corners can be reduced, thereby reducing the risk of the semiconductor device being broken down at the sharp corners when working at high voltage, and improving the high voltage resistance of the semiconductor device.

[0226] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make possible changes, modifications and combinations to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a gate structure on the substrate; forming an etch stop layer, wherein the etch stop layer covers the gate structure and the substrate; A filling layer covering the etching stop layer is formed by using multiple rounds of processes, each round of processes at least comprising: A deposition process is used to form filling sublayers, and starting from the second filling sublayer, each filling sublayer covers the previous filling sublayer; Using an etching process to remove a portion of the thickness of the filling sublayer from the surface of the current filling sublayer; Among them, the process parameters of the etching process are the same or different between different rounds of processes; In the process of forming the etching stop layer, a top corner of the etching stop layer covering the gate structure is formed with a sharp corner; In the first etching process, a portion of the sharp corner of the etching stop layer is removed from the surface of the current filling sub-layer to form an arc-shaped top corner; The number of the filling sublayers is equal to 3; The arc-shaped vertex angle exposed by the first filling sublayer has a first arc and a first arc length, the arc-shaped vertex angle formed by the second filling sublayer has a second arc and a second arc length, the arc-shaped vertex angle formed by the third filling sublayer has a third arc and a third arc length, the third arc is greater than or equal to the second arc, the second arc is greater than or equal to the first arc, the third arc length is greater than the second arc length, and the second arc length is greater than the first arc length; The etching gas used to remove a portion of the thickness of the first filling sublayer is C4F6, the etching gas used to remove a portion of the thickness of the second filling sublayer is C4F8, and the etching gas used to remove a portion of the thickness of the third filling sublayer is C5F8.

2. The forming method according to claim 1, characterized in that: The etching gas of the first etching process is C x1 F y1 , the ratio of x1 to y1 is greater than or equal to 1 / 2.

3. The forming method according to claim 2, characterized in that: The number of rounds of the multi-round process is greater than or equal to 2, and the etching gas of the second round of etching process is C x2 F y2 ; Among them, the C x1 F y1 The ratio of x1 to y1 is greater than that of C x2 F y2 The ratio of x2 to y2 in .

4. The forming method according to claim 3, characterized in that: The number of rounds of the multi-round process is greater than or equal to 3, and the etching gas of the third round of etching process is C x3 F y3 ; Among them, the C x3 F y3 The ratio of x3 to y3 is greater than the C x2 F y2 The ratio of x2 to y2 in .

5. The forming method according to claim 2, characterized in that: The etching gas of the etching process includes one or more of the following combinations: tetracarbon octafluoride C4F8, pentacarbon octafluoride C5F8, and tetracarbon hexafluoride C4F6.

6. The forming method according to claim 1, characterized in that: In each round of the process, the thickness of the deposited current filling sublayer is recorded as the first film thickness, and the remaining film thickness after etching away the current filling sublayer is recorded as the second film thickness. The ratio of the first film thickness to the second film thickness is less than or equal to 2:

1.

7. The forming method according to claim 1, characterized in that: The material of the etching stop layer includes: silicon nitride; The material of the filling layer includes silicon oxide.

8. The forming method according to claim 1, characterized in that: Before forming the gate structure on the substrate, the forming method further includes: forming a groove on the substrate; forming a dielectric repair layer covering the sidewalls and bottom of the groove; Filling the groove to form a dielectric isolation layer; forming a well region on the substrate; forming a gate dielectric layer on the well region; Wherein, the gate structure is located on the gate dielectric layer.

9. The forming method according to claim 8, characterized in that: After forming the gate structure and before forming the etching stop layer, the forming method further comprises: forming a sidewall covering the sidewall of the gate structure; forming source-drain doped layers in the well regions on both sides of the gate structure; forming a pinning layer on the source-drain doped layer; After forming the sidewalls and before forming the source-drain doping layers, a lightly doped source is formed between the source doping layer and the sidewalls, and a lightly doped drain is formed between the drain doping layer and the sidewalls.

10. A semiconductor structure, characterized in that: include: substrate; A gate structure, located on the substrate; An etching stop layer, covering the gate structure and the substrate; A filling layer, comprising a plurality of filling sub-layers, covering the etching stop layer; The semiconductor structure further comprises: The top angle of the etching stop layer covering the gate structure is an arc-shaped top angle; Wherein, the first filling sublayer exposes the arc-shaped top corner; The number of the filling sublayers is equal to 3; The arc-shaped vertex angle exposed by the first filling sublayer has a first arc and a first arc length, the arc-shaped vertex angle formed by the second filling sublayer has a second arc and a second arc length, the arc-shaped vertex angle formed by the third filling sublayer has a third arc and a third arc length, the third arc is greater than or equal to the second arc, the second arc is greater than or equal to the first arc, the third arc length is greater than the second arc length, and the second arc length is greater than the first arc length; The etching gas used to remove a portion of the thickness of the first filling sublayer is C4F6, the etching gas used to remove a portion of the thickness of the second filling sublayer is C4F8, and the etching gas used to remove a portion of the thickness of the third filling sublayer is C5F8.

11. The semiconductor structure according to claim 10, characterized in that The material of the etching stop layer includes: silicon nitride; The material of the filling layer includes silicon oxide.

12. The semiconductor structure according to claim 10, wherein: Also includes: a groove located on the substrate; A dielectric repair layer, covering the sidewall and bottom of the groove; A dielectric isolation layer is filled in the groove; A well region, located on the substrate; A gate dielectric layer, located on the well region; Wherein, the gate structure is located on the gate dielectric layer; A sidewall, covering a sidewall of the gate structure; Source-drain doped layers, located in the well regions on both sides of the gate structure; A pinning layer, located on the source and drain doping layer; A lightly doped source electrode, located between the sidewall and the source doping layer; The lightly doped drain is located between the sidewall and the drain doping layer.

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