A semiconductor structure and a method of manufacturing the same

Abstract

The present disclosure relates to the field of semiconductor, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: an interposer, the interposer comprising a deep trench capacitor array and an isolation structure arranged between the deep trench capacitor array; wherein the deep trench capacitor array comprises a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitors at the edge side of the deep trench capacitor array.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and particularly relates to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] With the development of semiconductor technology, different types of chips are packaged together through an interposer, which gradually becomes a development trend of packaging technology. In the related art, a deep trench capacitor (DTC) is usually arranged in the interposer as a decoupling capacitor, which is used to reduce signal noise and leakage between adjacent semiconductor devices coupled to the interposer.

[0003] However, since the deep trench capacitor array on the interposer does not have an isolation structure, the deep trench capacitor array has a large keep-out-zone (KOZ), and there is a large parasitic capacitance between the deep trench capacitor array and other devices on the interposer, which is easy to interfere with other devices. SUMMARY

[0004] Therefore, the embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof to solve the technical problems in the background art.

[0005] The embodiments of the present disclosure provide a semiconductor structure, comprising: an interposer, the interposer comprising a deep trench capacitor array and an isolation structure arranged between the deep trench capacitor array; wherein the deep trench capacitor array comprises a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitor at the edge side of the deep trench capacitor array.

[0006] In some embodiments, the deep trench capacitor comprises: a first electrode layer, a capacitor dielectric layer, a second electrode layer and a conductive layer; wherein the first electrode layer covers the inner wall of the deep trench in the interposer and extends to the upper surface of the interposer; the capacitor dielectric layer covers the first electrode layer; the second electrode layer covers the capacitor dielectric layer; and the conductive layer covers the second electrode layer.

[0007] In some embodiments, the isolation structure includes a first isolation structure, an isolation trench is provided in an interposer between the deep trench capacitor arrays, and the first isolation structure is located in the isolation trench; for a deep trench capacitor array, on a side away from the first isolation structure, the end portions of the first electrode layer, the capacitor dielectric layer, the second electrode layer and the conductive layer on the upper surface of the interposer of the outermost side deep trench capacitor completely coincide; on a side close to the first isolation structure, the outermost side deep trench capacitor exposes part of the first electrode layer, the end portions of the capacitor dielectric layer, the second electrode layer and the conductive layer on the upper surface of the interposer of the outermost side deep trench capacitor completely coincide, and the remaining part of the first electrode layer on the upper surface of the interposer is covered by the capacitor dielectric layer.

[0008] In some embodiments, the semiconductor structure further includes a dielectric material layer covering the conductive layer in the deep trench and completely filling the deep trench.

[0009] In some embodiments, the semiconductor structure further includes an insulating layer between the deep trench capacitor array and the interposer, and the interposer is exposed on a side of the outermost side deep trench capacitor away from the first isolation structure.

[0010] In some embodiments, the isolation structure further includes a second isolation structure covering the deep trench capacitor array, the first isolation structure and the exposed insulating layer.

[0011] In some embodiments, in a cross section in a vertical first direction, the cross-sectional shape of the first isolation structure is rectangular, trapezoidal, inverted trapezoidal or elliptical; and the first direction is perpendicular to the vertical direction.

[0012] In some embodiments, the aspect ratio of the isolation trench is 2-10.

[0013] In some embodiments, the projections of the plurality of deep trench capacitors on the upper surface of the interposer in the vertical direction are arranged in a regular hexagon.

[0014] The embodiment of the present disclosure further provides a manufacturing method of a semiconductor structure, comprising: providing an interposer; forming an initial deep trench capacitor array structure in the interposer, the initial deep trench capacitor array structure comprising a plurality of initial deep trench capacitor structures; performing first etching on the initial deep trench capacitor array structure to expose a first electrode layer at a periphery of an initial deep trench capacitor structure at an edge side of the initial deep trench capacitor array structure, and form an intermediate deep trench capacitor array structure; performing second etching on the intermediate deep trench capacitor array structure to form an isolation trench by etching the exposed first electrode layer away from a side of the initial deep trench capacitor structure at the edge side, and cut off adjacent capacitor units in the intermediate deep trench capacitor array structure to form a deep trench capacitor array, the isolation trench being located in the interposer between the deep trench capacitor array; and filling an isolation material in the isolation trench to form an isolation structure, the isolation structure at least partially surrounding a deep trench capacitor at the edge side of the deep trench capacitor array.

[0015] In some embodiments, forming the initial deep trench capacitor array structure in the interposer comprises: forming a deep trench array in the interposer, the deep trench array comprising a plurality of deep trenches; depositing an insulating material in the deep trenches and on an upper surface of the interposer to form an insulating layer covering inner walls of the deep trenches and extending to the upper surface of the interposer; and sequentially depositing the first electrode layer, a capacitor dielectric layer, a second electrode layer and a conductive layer on the insulating layer to form the initial deep trench capacitor array structure, wherein the first electrode layer covers the insulating material layer, the capacitor dielectric layer covers the first electrode layer, the second electrode layer covers the capacitor dielectric layer, and the conductive layer covers the second electrode layer.

[0016] In some embodiments, after forming the initial deep trench capacitor array structure in the interposer, the method further comprises: depositing a dielectric material on the conductive layer, the dielectric material covering the conductive layer in the deep trenches and completely filling the deep trenches to form a dielectric material layer.

[0017] In some embodiments, the first etching on the initial deep trench capacitor array structure comprises: forming a patterned first mask layer on the initial deep trench capacitor array structure; and performing the first etching on the initial deep trench capacitor array structure according to the patterned first mask layer to form a first trench at a periphery of an initial deep trench capacitor structure at an edge side of the initial deep trench capacitor array structure, the first trench exposing the first electrode layer; and the remaining initial deep trench capacitor array structure serving as the intermediate deep trench capacitor array structure.

[0018] In some embodiments, the second etching of the intermediate deep trench capacitor array structure comprises: forming a patterned second mask layer on the intermediate deep trench capacitor array structure; etching the intermediate deep trench capacitor array structure according to the patterned second mask layer to form the isolation trench on a side of the first trench away from the initial deep trench capacitor structure of the most edge side; and cutting off adjacent capacitor units in the intermediate deep trench capacitor array structure to expose part of the insulating layer; the isolation trench extends into the interposer; and the remaining intermediate deep trench capacitor array structure serves as the deep trench capacitor array.

[0019] In some embodiments, the isolation structure formed by filling the isolation trench with isolation material comprises: depositing isolation material on the interposer in which the deep trench capacitor array is formed, wherein part of the isolation material fills the isolation trench to form a first isolation structure; and part of the isolation material covers the deep trench capacitor array, the first isolation structure, and the exposed insulating layer to form a second isolation structure, the first isolation structure and the second isolation structure constituting the isolation structure.

[0020] Therefore, the semiconductor structure and the manufacturing method thereof are provided in the embodiments of the present disclosure. The semiconductor structure comprises: an interposer comprising a deep trench capacitor array and an isolation structure arranged between the deep trench capacitor array; wherein the deep trench capacitor array comprises a plurality of deep trench capacitors, and the isolation structure at least partially surrounds the deep trench capacitor on the most edge side of the deep trench capacitor array.

[0021] In the embodiments of the present disclosure, the isolation structure is arranged between the deep trench capacitor array, and the isolation structure at least partially surrounds the deep trench capacitor on the most edge side of the deep trench capacitor array. In this way, the deep trench capacitor array can be isolated from other devices on the interposer, which is conducive to reducing the parasitic capacitance between the deep trench capacitor array and the other devices on the interposer, thereby reducing the interference of the deep trench capacitor array on the other devices and improving the electrical performance of the semiconductor structure.

[0022] Details of one or more embodiments of the present disclosure are presented in the following drawings and description. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] Figure 1A vertical sectional view of a semiconductor structure provided by an embodiment of the present disclosure Figure 1 ;

[0025] Figure 2 A plan view of a semiconductor structure provided by an embodiment of the present disclosure

[0026] Figure 3 An enlarged view of the dashed box region in Figure 2 ;

[0027] Figure 4 A microscopic image of a semiconductor structure provided by an embodiment of the present disclosure

[0028] Figure 5 A vertical sectional view of a semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;

[0029] Figure 6 A flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure

[0030] Figure 7 A structure schematic of a semiconductor structure provided by an embodiment of the present disclosure in a manufacturing process Figure 1 ;

[0031] Figure 8 A structure schematic of a semiconductor structure provided by an embodiment of the present disclosure in a manufacturing process Figure 2 ;

[0032] Figure 9 A structure schematic of a semiconductor structure provided by an embodiment of the present disclosure in a manufacturing process Figure 3 ;

[0033] Figure 10 A structure schematic of a semiconductor structure provided by an embodiment of the present disclosure in a manufacturing process Figure 4 ;

[0034] Figure 11 A structure schematic of a semiconductor structure provided by an embodiment of the present disclosure in a manufacturing process Figure 5 ;

[0035] Figure 12 A structure schematic of a semiconductor structure provided by an embodiment of the present disclosure in a manufacturing process Figure 6 ;

[0036] Figure 13 A structure schematic of a semiconductor structure provided by an embodiment of the present disclosure in a manufacturing process Figure 7 ;

[0037] Figure 14 A structure schematic of a semiconductor structure provided by an embodiment of the present disclosure in a manufacturing processFigure 8

[0038] Figure 15 Structure schematic of a semiconductor structure in a manufacturing process provided for embodiments of the present disclosure Figure 9

[0039] Figure 16 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 1

[0040] Figure 17 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 2

[0041] Figure 18 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 3

[0042] Figure 19 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 4

[0043] Figure 20 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 5

[0044] Figure 21 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 6

[0045] Figure 22 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 7

[0046] Figure 23 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 8

[0047] Figure 24 Structure schematic of a semiconductor structure in a manufacturing process provided for related art Figure 9 DETAILED DESCRIPTION

[0048] Example embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. While example embodiments of the present disclosure are shown in the drawings, it is understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0049] ​​​​​​​​​​​In the following description, numerous specific details are given to provide a thorough understanding of the disclosure. However, it will be apparent that the disclosure can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the disclosure. Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation including modifi cations and variants thereof. For example, the terms "including" and "comprising" should be given their broadest interpretative meanings, that is, "including", but not limited to.

[0050] In the drawings, the size of layers, regions, elements, and the like, can be exaggerated for clarity. Like reference numerals in different drawings denote like elements.

[0051] It is to be understood that the terms "on", "adjacent", "connected to", or "coupled to" as used herein refer to an arrangement in which an element, layer, or the like is directly on, adjacent to, connected or coupled to another element, layer or the like, or an intervening element, layer or the like can be present. Conversely, the terms "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" as used herein refer to an arrangement in which no intervening element, layer or the like is present. It will be appreciated that, although terms such as first, second, third etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the disclosure. Conversely, a second element, component, region, layer or section discussed need not necessarily exist.

[0052] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items. All numerical ranges herein include endpoint values.

[0054] With the development of semiconductor technology, traditional two-dimensional packaging can no longer meet the industry's needs. Therefore, vertical interconnect stacked packaging based on through silicon via (TSV) technology packages different types of chips together through a silicon interposer. This packaging method has key technological advantages such as short-distance interconnection and high-density integration, and has gradually led the development of packaging technology.

[0055] In related technologies, deep trench capacitors (DTCs) are typically placed in the interposer as decoupling capacitors to reduce signal noise and leakage between adjacent semiconductor devices coupled to the interposer. However, because the deep trench capacitor array on the interposer lacks an isolation structure, it has a large exclusion region (the exclusion region refers to the area around the deep trench capacitor array where no circuit elements such as transistors are placed). This results in significant parasitic capacitance between the deep trench capacitor array and other devices on the interposer (including between deep trench capacitor arrays themselves), which can easily cause interference to other devices.

[0056] Based on this, the present disclosure proposes the following technical solutions:

[0057] This disclosure provides a semiconductor structure, with attached... Figure 1 This is a schematic vertical cross-sectional view of a semiconductor structure provided in an embodiment of this disclosure; (See attached diagram) Figure 2 This is a top view schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure; (See attached diagram) Figure 3 For the appendix Figure 2 Enlarged view of the area within the dashed box.

[0058] See appendix Figure 1 The semiconductor structure includes: an interposer 10, the interposer 10 including a deep trench capacitor array 11 (as shown in the attached diagram). Figure 2 (as shown) and the isolation structure 12 disposed between the deep trench capacitor array 11.

[0059] The deep trench capacitor array 11 includes a plurality of deep trench capacitors 110, and the isolation structure 12 at least partially surrounds the deep trench capacitors 110 at the edge of the deep trench capacitor array 11 (i.e., the periphery of the deep trench capacitor array).

[0060] It should be noted that the first direction x and the vertical direction z shown in the drawings are perpendicular to the paper surface. In addition, in order to clearly show the content in the embodiment, the drawings only show the positional relationship between the deep trench capacitors 110 at the edge of the deep trench capacitor array 11 and the isolation structure 12. The subsequent description will not be repeated. Figure 1 Figure 2 The vertical direction z shown in the drawings is perpendicular to the paper surface. In addition, in order to clearly show the content in the embodiment, the drawings only show the positional relationship between the deep trench capacitors 110 at the edge of the deep trench capacitor array 11 and the isolation structure 12. The subsequent description will not be repeated. Figure 1

[0061] In the embodiment of the present disclosure, referring to FIG. 1, the interposer 10 is a pipeline for transmitting electrical signals among multiple chips in the package. The interposer 10 can realize the interconnection between chips, and can also realize the interconnection with the package substrate, serving as a bridge between multiple dies and a circuit board. For example, the interposer 10 can connect a memory chip (for example, a dynamic random access memory (DRAM)) and a logic chip (for example, a central processing unit (CPU) or a graphics processing unit (GPU)). The material of the interposer 10 can be silicon, polysilicon, germanium, germanium silicon, silicon carbide, etc. Figure 1 In some embodiments of the present disclosure, referring to FIG. 2, the projections of the plurality of deep trench capacitors 110 on the upper surface of the interposer 10 are arranged in a regular hexagon. Specifically, the projections of the six adjacent deep trench capacitors 110 on the plane of the interposer 10 are arranged in a regular hexagon, each vertex of the regular hexagon is provided with a deep trench capacitor 110, and the center of the regular hexagon is provided with a deep trench capacitor 110. That is, the arrangement of the deep trench capacitors 110 is a hexagonal closest packed (HCP) structure.

[0062] Figure 2 It can be understood that the arrangement of the plurality of deep trench capacitors 110 in a hexagonal closest packed structure can obtain a closely arranged deep trench capacitor array 11, and thus the capacitance value of the deep trench capacitor array 11 can be improved.

[0063] In some embodiments of the present disclosure, referring to FIG. 3, the deep trench capacitor 110 includes a first electrode layer 111, a capacitor dielectric layer 112, a second electrode layer 113, and a conductive layer 114. The first electrode layer 111 covers the inner wall of the deep trench T0 in the interposer 10 and extends to the upper surface of the interposer 10. The capacitor dielectric layer 112 covers the first electrode layer 111. The second electrode layer 113 covers the capacitor dielectric layer 112. The conductive layer 114 covers the second electrode layer 113.

[0064] In some embodiments of the present disclosure, referring to FIG. 3, the deep trench capacitor 110 includes a first electrode layer 111, a capacitor dielectric layer 112, a second electrode layer 113, and a conductive layer 114. The first electrode layer 111 covers the inner wall of the deep trench T0 in the interposer 10 and extends to the upper surface of the interposer 10. The capacitor dielectric layer 112 covers the first electrode layer 111. The second electrode layer 113 covers the capacitor dielectric layer 112. The conductive layer 114 covers the second electrode layer 113. Figure 1 In some embodiments of the present disclosure, referring to FIG. 3, the deep trench capacitor 110 includes a first electrode layer 111, a capacitor dielectric layer 112, a second electrode layer 113, and a conductive layer 114. The first electrode layer 111 covers the inner wall of the deep trench T0 in the interposer 10 and extends to the upper surface of the interposer 10. The capacitor dielectric layer 112 covers the first electrode layer 111. The second electrode layer 113 covers the capacitor dielectric layer 112. The conductive layer 114 covers the second electrode layer 113.​​​

[0065] In some other embodiments, the deep trench capacitor can include a plurality of electrode layers and a plurality of capacitor dielectric layers stacked alternately, for example, the deep trench capacitor can be a double-sided deep trench capacitor. In this way, the capacitance of the deep trench capacitor can be improved.

[0066] It should be noted that the deep trench T0 refers to the trench in which the deep trench capacitor 110 in the interposer 10 is located, and the deep trench T0 has a high aspect ratio. For example, the aspect ratio of the deep trench T0 can be 10, 15 or 20.

[0067] In the embodiments of the present disclosure, referring to FIG. 1, the deep trench capacitor array 11 includes a plurality of deep trench capacitors 110 arranged in an array. Figure 1 The materials of the first electrode layer 111, the second electrode layer 113 and the conductive layer 114 can be at least one of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride and other conductive materials. Specifically, the materials of the first electrode layer 111 and the second electrode layer 113 are titanium nitride, and the material of the conductive layer 114 is polysilicon. The material of the capacitor dielectric layer 112 can be at least one of aluminum oxide (Al2O3), zirconium oxide (ZrO) and other insulating materials. The capacitor dielectric layer 112 can also include other insulating materials with high dielectric constant (high-k), for example, materials with a dielectric constant greater than 3.9.

[0068] In the embodiments of the present disclosure, referring to FIG. 1, the deep trench capacitor array 11 includes a plurality of deep trench capacitors 110 arranged in an array. Figure 1 The isolation structure 12 at least partially surrounds the deep trench capacitors 110 at the edge of the deep trench capacitor array 11. That is, the isolation structure 12 can partially surround the deep trench capacitors 110 at the edge of the deep trench capacitor array 11, or can completely surround the deep trench capacitors 110 at the edge of the deep trench capacitor array 11. In the following, the isolation structure 12 completely surrounding the deep trench capacitors 110 at the edge of the deep trench capacitor array 11 is taken as an example for description.

[0069] In some embodiments of the present disclosure, referring to FIG. 1, the isolation structure 12 includes a first isolation structure 13, and an isolation trench T1 is arranged in the interposer 10 between the deep trench capacitor array 11, and the first isolation structure 13 is located in the isolation trench T1. Figure 1 In some embodiments of the present disclosure, referring to FIG. 1, the isolation structure 12 includes a first isolation structure 13, and an isolation trench T1 is arranged in the interposer 10 between the deep trench capacitor array 11, and the first isolation structure 13 is located in the isolation trench T1.

[0070] Figure 1 In some embodiments of the present disclosure, referring to FIG. 1, the isolation structure 12 includes a first isolation structure 13, and an isolation trench T1 is arranged in the interposer 10 between the deep trench capacitor array 11, and the first isolation structure 13 is located in the isolation trench T1.

[0071] ​It should be noted that the size of the isolation trench T1 can be determined according to actual needs, and the main factors include the number, size and layout of the deep trench capacitors, the capacitance value, the operating voltage, the range of the peripheral circuit, and the distance between the device to be isolated and the deep trench capacitor array, etc. For example, the closer the distance between the device to be isolated and the deep trench capacitor array 11, the deeper and wider the isolation trench T1 can be set.

[0072] In some embodiments of the present disclosure, referring to the accompanying drawings Figure 1 In the cross section in the first vertical direction x, the cross-sectional shape of the first isolation structure 13 can be rectangular, trapezoidal, inverted trapezoidal or elliptical; the first direction x is perpendicular to the vertical direction z. For the cross-sectional shape of the first isolation structure 13, no specific limitation is made here. In the following, the cross-sectional shape of the first isolation structure 13 is taken as an example for description.

[0073] In the embodiments of the present disclosure, referring to the accompanying drawings Figure 1 The material of the first isolation structure 13 can include an insulating material such as oxide, nitride or oxynitride, and the first isolation structure 13 can also adopt an oxide-nitride-oxide (ONO) stacked structure. Specifically, the material of the first isolation structure 13 is silicon oxide.

[0074] It can be understood that by arranging the isolation structure between the deep trench capacitor arrays 11, and the isolation structure 12 at least partially surrounds the deep trench capacitors 110 at the edge side of the deep trench capacitor array 11, the deep trench capacitor array 11 can be isolated from other devices on the interlayer 10, which is beneficial to reduce the parasitic capacitance between the deep trench capacitor array 11 and other devices on the interlayer 10, and further reduce the interference of the deep trench capacitor array 11 on other devices, and improve the electrical performance of the semiconductor structure.

[0075] The accompanying drawings Figure 4 A microscopic image of a semiconductor structure provided in the embodiments of the present disclosure.

[0076] In the embodiments of the present disclosure, referring to the accompanying drawings Figure 4 The isolation trench T1 is located in the etching overlap region 120. Here, the etching overlap region 120 is a region partially overlapping the first etching region 121 and the second etching region 122. The first etching region 121 and the second etching region 122 are respectively obtained by first etching and second etching to form the deep trench capacitor array 11.

[0077] In the embodiments of the present disclosure, referring to the accompanying drawings Figure 2 and the accompanying drawings Figure 3In the cross section in the vertical direction z, the first etching area 121, the second etching area 122 and the etching overlap area 120 are rectangular ring structures. That is, in the cross section in the vertical direction z, the first isolation structure 13 is a rectangular ring structure, so that the first isolation structure 13 can completely surround the deep trench capacitors 110 at the edge side of the deep trench capacitor array 11.

[0078] It should be noted that the first etching area 121, the second etching area 122 and the etching overlap area 120 herein refer to a region divided on the plane of the interposer 10, rather than an actual region formed when etching in the interposer 10. That is, the first etching area 121, the second etching area 122 and the etching overlap area 120 are regions occupying part of the area of the interposer 10. Details are not repeated hereinafter.

[0079] It can be understood that the etching overlap area 120 is a partially overlapping area of the first etching area 121 and the second etching area 122 obtained by the first etching and the second etching for forming the deep trench capacitor array 11. That is, when preparing the first isolation structure 13, the original two masks required for preparing the deep trench capacitor array 11 can be used. The process of preparing the first isolation structure 13 does not need to use a new mask, nor does it need to increase a new process. The preparation process is simple and the production cost is low.

[0080] In some embodiments of the present disclosure, referring to FIG. 1, the first etching area 121, the second etching area 122 and the etching overlap area 120 are rectangular ring structures. Figure 1 For a deep trench capacitor array 11, the end portions of the first electrode layer 111, the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 on the upper surface of the interposer 10 of the deep trench capacitor 110 at the edge side completely coincide on the side far from the first isolation structure 13;

[0081] On the side close to the first isolation structure 13, the deep trench capacitor 110 exposes part of the first electrode layer 111, and the end portions of the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 on the upper surface of the interposer 10 of the deep trench capacitor 110 at the edge side completely coincide, and the remaining part of the first electrode layer 111 on the upper surface of the interposer 10 is covered by the capacitor dielectric layer 112.

[0082] It can be understood that, on the one hand, by setting the end of the first electrode layer 111, the capacitor dielectric layer 112, the conductive layer 114 and the second electrode layer 113 on the interlayer 10 in the deep trench capacitor 110 to be completely or partially overlapped, the uniformity of the electrode extraction in the deep trench capacitor 110 can be improved, and thus the parasitic resistance can be reduced and the performance of the deep trench capacitor 110 can be improved. On the other hand, on the side close to the first isolation structure 13, the deep trench capacitor 110 at the most edge side exposes part of the first electrode layer 111, so that subsequent electrical connection with the conductive plug can be facilitated.

[0083] In some embodiments of the present disclosure, referring to the accompanying drawings Figure 1 The semiconductor structure further includes a dielectric material layer 16 covering the conductive layer 114 in the deep trench T0 and completely filling the deep trench T0. Here, the dielectric material layer 16 can completely fill the deep trench T0, which can improve the situation that the deep trench is not completely filled and voids are easily caused by filling the deep trench with polysilicon in the related art.

[0084] In the embodiments of the present disclosure, the material of the dielectric material layer 16 can be at least one of silicon oxide, silicon nitride and silicon oxynitride. Specifically, the material of the dielectric material layer 16 is silicon oxide.

[0085] In some embodiments of the present disclosure, referring to the accompanying drawings Figure 1 The semiconductor structure further includes an insulating layer 15 located between the deep trench capacitor array 11 and the interlayer 10, and the interlayer 10 exposed on the side of the deep trench capacitor 110 at the most edge side away from the first isolation structure 13. Here, the insulating layer 15 is located between the deep trench capacitor array 11 and the interlayer 10, and is used to provide electrical isolation between the deep trench capacitor 110 and the interlayer 10.

[0086] In the embodiments of the present disclosure, the material of the insulating layer 15 can be at least one of silicon oxide, silicon nitride, silicon oxynitride and other insulating materials. Specifically, the material of the insulating layer 15 is silicon oxide.

[0087] The accompanying drawings Figure 5 provide another vertical sectional view of a semiconductor structure according to an embodiment of the present disclosure;

[0088] In some embodiments of the present disclosure, referring to the accompanying drawings Figure 5 The isolation structure 12 further includes a second isolation structure 14 covering the deep trench capacitor array 11, the first isolation structure 13 and the exposed insulating layer 15. In this way, the second isolation structure 14 can isolate the deep trench capacitor array 11 from the outside and play a role in protecting the deep trench capacitor array 11.

[0089] In the embodiments of the present disclosure, referring to the accompanying drawings Figure 5The material of the second isolation structure 14 can include oxide, nitride, or oxynitride, etc. The second isolation structure 14 can also adopt an oxide-nitride-oxide (ONO) stacked structure. The material of the second isolation structure 14 and the first isolation structure 13 can be the same or different. Specifically, the material of the second isolation structure 14 is silicon oxide.

[0090] The embodiments of the present disclosure further provide a manufacturing method of a semiconductor structure. Figure 6 A flowchart of a manufacturing method of a semiconductor structure provided by the embodiments of the present disclosure is shown in FIG. 10. The method includes the following steps. Figure 6 As shown in FIG. 10, the method includes the following steps:

[0091] Step S101: providing an interposer 10.

[0092] Step S102: forming an initial deep trench capacitor array structure 23 in the interposer 10, the initial deep trench capacitor array structure 23 including a plurality of initial deep trench capacitor structures 230.

[0093] Step S103: performing a first etching on the initial deep trench capacitor array structure 23 to expose a first electrode layer 111 at the periphery of the initial deep trench capacitor structure 230 at the most edge side of the initial deep trench capacitor array structure 23, and form an intermediate deep trench capacitor array structure 24.

[0094] Step S104: performing a second etching on the intermediate deep trench capacitor array structure 24 to etch the exposed first electrode layer 111 away from one side of the initial deep trench capacitor structure 230 at the most edge side and form an isolation trench T1, and cut off adjacent capacitor units in the intermediate deep trench capacitor array structure 24 to form a deep trench capacitor array 11, the isolation trench T1 being located in the interposer 10 between the deep trench capacitor arrays 11.

[0095] Step S105: filling an isolation material in the isolation trench T1 to form an isolation structure 12; the isolation structure 12 at least partially surrounding a deep trench capacitor 110 at the most edge side of the deep trench capacitor array 11.

[0096] FIG. 11 shows a structure of the semiconductor structure provided by the embodiments of the present disclosure in the manufacturing process. Figure 7 FIG. 12 shows a structure of the semiconductor structure provided by the embodiments of the present disclosure in the manufacturing process. Figure 15 FIG. 13 shows a structure of the semiconductor structure provided by the embodiments of the present disclosure in the manufacturing process. Figure 7 FIG. 14 shows a structure of the semiconductor structure provided by the embodiments of the present disclosure in the manufacturing process. Figure 15 The manufacturing method of the semiconductor structure provided by the embodiments of the present disclosure is further described.

[0097] First, referring to FIG. 10, the method includes the following steps: Figure 7 FIG. 11 shows a structure of the semiconductor structure provided by the embodiments of the present disclosure in the manufacturing process. Figure 10Step S101: Provide an intermediary layer 10; Step S102: Form an initial deep trench capacitor array structure 23 in the intermediary layer 10, the initial deep trench capacitor array structure 23 including a plurality of initial deep trench capacitor structures 230.

[0098] In this embodiment of the disclosure, see Appendix Figure 7 Interposer 10 serves as a conduit for transmitting electrical signals between multiple chips within the package. Interposer 10 enables interconnection between chips and with the package substrate, acting as a bridge between multiple dies and the circuit board. For example, interposer 10 can connect memory chips (e.g., Dynamic Random Access Memory (DRAM)) and logic chips (e.g., Central Processing Unit (CPU), Graphics Processing Unit (GPU)). The material of interposer 10 can be silicon, polysilicon, germanium, silicon germanium, or silicon carbide, among others.

[0099] In some embodiments of this disclosure, see the appendix. Figure 7 To be continued Figure 10 An initial deep trench capacitor array structure 23 is formed in the intermediate layer 10, including:

[0100] A deep trench array is formed within the intermediate layer 10, the deep trench array comprising multiple deep trenches T0;

[0101] An insulating material is deposited on the upper surface of the intermediary layer 10 and in the deep trench T0 to form an insulating layer 15, which covers the inner wall of the deep trench T0 and extends to the upper surface of the intermediary layer 10.

[0102] A first electrode layer 111, a capacitor dielectric layer 112, a second electrode layer 113, and a conductive layer 114 are sequentially deposited on the insulating layer 15 to form an initial deep trench capacitor array structure 23; wherein, the first electrode layer 111 covers the insulating material layer; the capacitor dielectric layer 112 covers the first electrode layer 111; the second electrode layer 113 covers the capacitor dielectric layer 112; and the conductive layer 114 covers the second electrode layer 113.

[0103] In this embodiment of the present disclosure, the specific steps for forming a deep trench array within the interposer layer 10 include forming a patterned deep trench mask layer 20 (as shown in the attached figure) on the interposer layer 10. Figure 7 As shown in the figure, the intermediate layer 10 is etched according to the patterned deep trench mask layer 20 to form multiple deep trenches T0 (as shown in the figure). Figure 8 As shown, deep trenches T0 form an array. Here, the deep trenches T0 have a high aspect ratio. For example, the aspect ratio of the deep trenches T0 can be 10, 15, or 20.

[0104] In this embodiment of the disclosure, see Appendix Figure 9The material of the insulating layer 15 can be at least one of silicon oxide, silicon nitride, silicon oxynitride. Specifically, the material of the insulating layer 15 is silicon oxide. Here, the insulating layer 15 formed by depositing an insulating material can be used to provide electrical isolation between the interposer 10 and the subsequently formed deep trench capacitors.

[0105] In the embodiments of the present disclosure, referring to FIG. 1, the method further includes the following steps. Figure 10 The material of the first electrode layer 111, the second electrode layer 113 and the conductive layer 114 can be at least one of doped silicon, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, and other conductive materials. Specifically, the material of the first electrode layer 111 and the second electrode layer 113 is titanium nitride, and the material of the conductive layer 114 is polysilicon. The material of the capacitor dielectric layer 112 can be at least one of aluminum oxide (Al2O3), zirconium oxide (ZrO), and other insulating materials. The capacitor dielectric layer 112 can also include other high-k insulating materials, such as materials with a dielectric constant greater than 3.9.

[0106] In the embodiments of the present disclosure, the deposition of the insulating layer 15, the first electrode layer 111, the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 can use one or more of the following processes: chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0107] In some embodiments of the present disclosure, referring to FIG. 1, the method further includes the following steps. Figure 10 After forming the initial deep trench capacitor array structure 23 in the interposer 10, the method further includes the following steps: depositing a dielectric material on the conductive layer 114, the dielectric material covering the conductive layer 114 in the deep trench T0 and completely filling the deep trench T0 to form a dielectric material layer 16.

[0108] Here, the dielectric material layer 16 can completely fill the deep trench T0, which can improve the situation that the deep trench is not completely filled and voids are easily caused when polysilicon is used to fill the deep trench in the related art.

[0109] The material of the dielectric material layer 16 can be at least one of silicon oxide, silicon nitride, silicon oxynitride. Specifically, the material of the dielectric material layer 16 is silicon oxide.

[0110] Then, step S103 is performed: performing a first etching on the initial deep trench capacitor array structure 23 to expose the first electrode layer 111 at the periphery of the initial deep trench capacitor structure 230 at the edge of the initial deep trench capacitor array structure 23, and form an intermediate deep trench capacitor array structure 24.

[0111] In some embodiments of the present disclosure, referring to FIG. 1, the method further includes the following steps. Figure 11 and FIG. 2.Figure 12 The first etching of the initial deep trench capacitor array structure 23 includes:

[0112] A patterned first mask layer 21 is formed on the initial deep trench capacitor array structure 23.

[0113] The first etching of the initial deep trench capacitor array structure 23 is performed according to the patterned first mask layer 21, a first trench T2 is formed at the periphery of the initial deep trench capacitor structure 230 at the most edge side of the initial deep trench capacitor array structure 23, the first trench T2 exposes the first electrode layer 111; the remaining initial deep trench capacitor array structure 23 serves as an intermediate deep trench capacitor array structure 24. Here, the exposed part of the first electrode layer 111 through the first trench T2 is conducive to electrical connection with the subsequently formed conductive plug.

[0114] It should be noted that the periphery of the initial deep trench capacitor structure 230 at the most edge side of the initial deep trench capacitor array structure 23 refers to the side of the initial deep trench capacitor structure 230 away from the initial deep trench capacitor array structure 23, and located in the region on the interposer 10 where the initial deep trench capacitor structure 230 is located.

[0115] In the embodiments of the present disclosure, the etching of the initial deep trench capacitor array structure 23 can adopt plasma etching, and can also adopt other dry etching processes, such as reactive ion etching, sputtering etching, magnetic field enhanced reactive ion etching, reactive ion beam etching or high-density plasma etching.

[0116] In the embodiments of the present disclosure, the first etching of the initial deep trench capacitor array structure 23 can be performed by using the first mask layer 21, and the second etching of the intermediate deep trench capacitor array structure 24 can be performed by using the second mask layer 22. Figure 12 The first etching of the initial deep trench capacitor array structure 23 can be performed by using the first mask layer 21, and the second etching of the intermediate deep trench capacitor array structure 24 can be performed by using the second mask layer 22.

[0117] Next, step S104 is performed: the second etching of the intermediate deep trench capacitor array structure 24 is performed to etch the exposed first electrode layer 111 away from the side of the initial deep trench capacitor structure 230 at the most edge side to form an isolation trench T1, and the adjacent capacitor units in the intermediate deep trench capacitor array structure 24 are cut off to form a deep trench capacitor array 11, and the isolation trench T1 is located in the interposer 10 between the deep trench capacitor arrays 11.

[0118] In some embodiments of the present disclosure, referring to the accompanying drawings Figure 13 and Figure 14 The second etching of the intermediate deep trench capacitor array structure 24 includes:

[0119] A patterned second mask layer 22 is formed on the intermediate deep trench capacitor array structure 24.

[0120] According to the patterned second mask layer 22, the intermediate deep trench capacitor array structure 24 is etched a second time to form an isolation trench T1 on the side of the initial deep trench capacitor structure 230 away from the outermost edge of the first trench T2; and, adjacent capacitor cells in the intermediate deep trench capacitor array structure 24 are cut off to expose part of the insulating layer 15; the isolation trench T1 extends into the interposer layer 10; the remaining intermediate deep trench capacitor array structure 24 serves as the deep trench capacitor array 11.

[0121] It should be noted that a second etching is performed on the intermediate deep trench capacitor array structure 24 to cut off adjacent capacitor units in the intermediate deep trench capacitor array structure 24, forming a deep trench capacitor array 11 including multiple deep trench capacitors 110. In some other embodiments, the second etching can also be used to cut off the connection between the deep trench capacitor array 11 and other devices, which is not specifically limited here.

[0122] In this embodiment of the disclosure, see Appendix Figure 13 The patterned second mask layer 22 covers a portion of the first trench T2. That is, the opening of the first photomask used to form the patterned first mask layer 21 partially overlaps with the opening of the second photomask used to form the patterned second mask layer 22. This results in a partial overlap between the second etched region 122 obtained through the second etching and the first etched region 121, forming an etch overlap region 120. (See Appendix) Figure 14 The isolation trench T1 is located in the etched overlap area 120.

[0123] In this embodiment of the disclosure, the aspect ratio of the isolation trench T1 is 2-10, including the endpoint values. For example, the aspect ratio of the isolation trench T1 can be 2, 5, 7, or 10.

[0124] Appendix Figure 16 To be continued Figure 24 This is a schematic diagram illustrating the semiconductor structure during the manufacturing process, as provided for related technologies. As shown in the diagram, the fabrication steps of the deep trench capacitor array 11 in related technologies are as follows:

[0125] First, an initial capacitor structure 27 is formed on the intermediate layer 10 (as shown in the attached diagram). Figure 16 To be continued Figure 19 (as shown); then, a patterned third mask layer 25 is formed on the initial capacitor structure 27 using a second photomask, and the initial capacitor structure 27 is etched to form an intermediate capacitor structure 28 (as shown in the attached image); Figure 20 , 21 (As shown); Next, a patterned fourth mask layer 26 is formed on the intermediate capacitor structure 28 using a first photomask, the intermediate capacitor structure 28 is etched, exposing part of the first electrode layer 111 located on the upper surface of the interposer layer 10, forming a deep trench capacitor array (as shown in the attached diagram); Figure 22 , 23(as shown); Finally, a protective layer 29 is formed on the deep trench capacitor array 11 (as shown in the attached diagram). Figure 24 (As shown).

[0126] Here, the two photomasks used in the fabrication of the deep trench capacitor array 11 in this disclosure are the same as the two photomasks used in the fabrication of the deep trench capacitor 110 in related technologies. However, by adjusting the opening positions of the first and second photomasks so that their opening portions overlap, this disclosure allows the original two photomasks required for fabricating the deep trench capacitor array 11 to be used simultaneously with the fabrication of the deep trench capacitor array 11 to etch isolation trenches T1 for subsequent formation of the first isolation structure 13. Thus, trench isolation of the deep trench capacitor array 11 can be established without adding additional processes.

[0127] It is understandable that by partially overlapping the first and second photomasks required for fabricating the deep trench capacitor array 11 in related technologies, the existing two photomasks can be used to complete the fabrication of the deep trench capacitor array 11 and the subsequent first isolation structure 13. The process of fabricating the first isolation structure 13 does not require the use of new photomasks or the addition of new process steps, which can simplify the process steps, save production costs, and improve production efficiency.

[0128] Furthermore, in related technologies, when performing two etching processes on the initial capacitor structure 27, the electrodes in the capacitor structure are first cut off before the first electrode layer 111, which is to be used for connection with the conductive plug, is exposed. The openings of the photomasks used for these two etching processes do not overlap; that is, the two etching processes do not overlap, and the electrode cutting process is completed in a single etching operation.

[0129] In the two etching processes disclosed herein, the first etching process first exposes a portion of the first electrode layer 111 (as shown in the attached image). Figure 12 (as shown); then, during the second etching, the exposed portion of the first electrode layer 111 is cut off (as shown in the attached diagram). Figure 14 (As shown). In this way, the first electrode layer 111 can be cut off in two steps of etching, which can reduce the difficulty of electrode cutting process.

[0130] In this embodiment of the disclosure, see Appendix Figure 2 The projections of multiple deep trench capacitors 110 onto the upper surface of the interposer 10 along the vertical direction z form a regular hexagonal arrangement. In other words, the deep trench capacitors 110 are arranged in a hexagonal close-packed structure. In this way, a tightly packed deep trench capacitor array 11 can be obtained, thereby increasing the capacitance value of the deep trench capacitor array 11.

[0131] In this embodiment of the disclosure, see Appendix Figure 14For the deep trench capacitor array 11, on the side far away from the isolation trench T1, the end of the first electrode layer 111, the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the most edge-side deep trench capacitor 110 on the upper surface of the interposer 10 completely coincide; on the side close to the isolation trench T1, the most edge-side deep trench capacitor 110 exposes part of the first electrode layer 111, the end of the capacitor dielectric layer 112, the second electrode layer 113 and the conductive layer 114 of the most edge-side deep trench capacitor 110 on the upper surface of the interposer 10 completely coincide, and the remaining part of the first electrode layer 111 on the upper surface of the interposer 10 is covered by the capacitor dielectric layer 112.

[0132] It can be understood that, by setting the end of the first electrode layer 111, the capacitor dielectric layer 112, the conductive layer 114 and the second electrode layer 113 on the interposer 10 in the deep trench capacitor 110 to completely or partially coincide, the uniformity of electrode extraction in the deep trench capacitor 110 can be improved, and thus the parasitic resistance can be reduced and the performance of the deep trench capacitor 110 can be improved.

[0133] Finally, step S105 is performed: filling the isolation material in the isolation trench T1 to form the isolation structure 12; the isolation structure 12 at least partially surrounds the most edge-side deep trench capacitor 110 of the deep trench capacitor array 11.

[0134] In some embodiments of the present disclosure, referring to the accompanying drawings Figure 15 Filling the isolation material in the isolation trench T1 to form the isolation structure 12 includes:

[0135] Depositing the isolation material on the interposer 10 in which the deep trench capacitor array 11 is formed, wherein part of the isolation material fills the isolation trench T1 to form the first isolation structure 13; and part of the isolation material covers the deep trench capacitor array 11, the first isolation structure 13 and the exposed insulating layer 15 to form the second isolation structure 14, and the first isolation structure 13 and the second isolation structure 14 constitute the isolation structure 12.

[0136] It can be understood that, by depositing the isolation material on the interposer 10 to form the first isolation structure 13 and the second isolation structure 14 at the same time, thus, it is beneficial to simplify the process, reduce the preparation difficulty and production cost.

[0137] In the embodiments of the present disclosure, the isolation structure 12 can partially surround the most edge-side deep trench capacitor 110 of the deep trench capacitor array 11, or can completely surround the most edge-side deep trench capacitor 110 of the deep trench capacitor array 11.

[0138] In some embodiments of the present disclosure, referring to the accompanying drawings Figure 15In the cross section in the first direction x, the cross section shape of the first isolation structure 13 can be rectangular, trapezoidal, inverted trapezoidal or elliptical. No specific limitation is made herein.

[0139] In the embodiments of the present disclosure, referring to the accompanying drawings Figure 15 The material of the first isolation structure 13 and the second isolation structure 14 can include oxide, nitride or oxynitride and the like. Specifically, the material of the first isolation structure 13 and the second isolation structure 14 is silicon oxide.

[0140] It should be noted that in some other embodiments, the first isolation structure 13 and the second isolation structure 14 can also be formed by twice deposition process, and the material of the first isolation structure 13 and the second isolation structure 14 can be selected according to actual needs.

[0141] It should be noted that the semiconductor structure and the manufacturing method thereof provided by the embodiments of the present disclosure can be applied to DRAM structure or other semiconductor devices, and no more limitation is made herein. The embodiments of the semiconductor structure provided by the present disclosure and the embodiments of the manufacturing method thereof belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be combined arbitrarily without conflict.

[0142] The above merely describes the preferred embodiments of the present disclosure but not for limiting the protection scope of the present disclosure, and any modification, equivalent replacement and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Provide an intermediary layer; An initial deep trench capacitor array structure is formed in the interposer layer, the initial deep trench capacitor array structure comprising a plurality of initial deep trench capacitor structures; The initial deep trench capacitor array structure is etched for the first time, exposing the first electrode layer on the periphery of the initial deep trench capacitor structure at the outermost edge of the initial deep trench capacitor array structure, forming an intermediate deep trench capacitor array structure. The intermediate deep trench capacitor array structure is etched a second time to form an isolation trench on the side of the exposed first electrode layer away from the outermost edge of the initial deep trench capacitor structure. Furthermore, adjacent capacitor cells in the intermediate deep trench capacitor array structure are cut off to form a deep trench capacitor array. The isolation trench is located in the intermediary layer between the deep trench capacitor arrays. The isolation trench is filled with isolation material to form an isolation structure; The isolation structure at least partially surrounds the deep trench capacitors on the outermost edge of the deep trench capacitor array.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Forming an initial deep trench capacitor array structure in the interposer layer includes: A deep trench array is formed within the intermediate layer, the deep trench array comprising a plurality of deep trenches; An insulating material is deposited on the upper surface of the intermediate layer and in the deep trench to form an insulating layer that covers the inner wall of the deep trench and extends to the upper surface of the intermediate layer. A first electrode layer, a capacitor dielectric layer, a second electrode layer, and a conductive layer are sequentially deposited on the insulating layer to form the initial deep trench capacitor array structure; wherein, the first electrode layer covers the insulating material layer; the capacitor dielectric layer covers the first electrode layer; the second electrode layer covers the capacitor dielectric layer; and the conductive layer covers the second electrode layer.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, After forming the initial deep trench capacitor array structure in the intermediate layer, the following steps are included: A dielectric material is deposited on the conductive layer, the dielectric material covering the conductive layer in the deep trench and completely filling the deep trench to form a dielectric material layer.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, The initial deep trench capacitor array structure is etched for the first time, including: A patterned first mask layer is formed on the initial deep trench capacitor array structure; According to the patterned first mask layer, the initial deep trench capacitor array structure is etched for the first time, forming a first trench around the outermost edge of the initial deep trench capacitor array structure, and the first trench exposes the first electrode layer; the remaining initial deep trench capacitor array structure serves as the intermediate deep trench capacitor array structure.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, The second etching of the intermediate deep trench capacitor array structure includes: A patterned second mask layer is formed on the intermediate deep trench capacitor array structure; According to the patterned second mask layer, the intermediate deep trench capacitor array structure is etched a second time to form the isolation trench on the side of the initial deep trench capacitor structure away from the outermost edge of the first trench; and, adjacent capacitor cells in the intermediate deep trench capacitor array structure are cut off to expose part of the insulating layer; the isolation trench extends into the interposer layer; the remaining intermediate deep trench capacitor array structure serves as the deep trench capacitor array.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The isolation trench is filled with isolation material to form an isolation structure, including: An isolation material is deposited on an interlayer on which the deep trench capacitor array is formed, wherein a portion of the isolation material fills the isolation trench to form a first isolation structure; a portion of the isolation material covers the deep trench capacitor array, the first isolation structure, and the exposed insulating layer to form a second isolation structure, wherein the first isolation structure and the second isolation structure constitute an isolation structure.

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