Intermetallic dielectric layer structure and preparation method thereof

Abstract

The invention provides an intermetallic dielectric layer structure and a preparation method thereof. The intermetallic dielectric layer structure is composed of a first silicon-rich oxide layer, a fluorine-silicon glass layer, a second silicon-rich oxide layer and a non-doped silicon glass layer. On one hand, the first silicon-rich oxide layer is used for preventing the fluorine element of the fluorosilicone glass layer from diffusing towards the first metal layer, and the second silicon-rich oxide layer is used for preventing the fluorine element of the fluorosilicone glass layer from diffusing towards the second metal layer, so that the probability that the fluorosilicone glass layer diffuses to the metal layer and the device dielectric layer in the later process can be effectively reduced; the defects of generation of metal holes and falling of the dielectric layer can be effectively avoided; and on the other hand, due to the enhancement of the fluorine diffusion barrier capability, more fluorine elements can be doped into the fluorosilicone glass layer, so that the dielectric K value of the fluorosilicone glass layer is effectively reduced, the overall parasitic capacitance of the device is reduced, and the propagation delay of the device is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to an intermetallic dielectric layer structure and a preparation method thereof. Background Art

[0002] Inside the IC, due to the existence of interlayer dielectrics (ILD&IMD (inter layer dielectric and intermetal dielectric)), there is inevitably distributed (parasitic) capacitance between the wires. Distributed capacitance not only affects the chip speed, but also affects the reliability. The speed of the integrated circuit is determined by the gate delay of the transistor and the propagation delay of the signal. The shorter the delay time, the higher the signal frequency. The gate delay is mainly determined by the gate material of the transistor. The propagation delay is also called RC delay. R is the resistance of the metal wire, and C is the capacitance formed by the internal dielectric. The expression of propagation delay is: T RC =ρε(L 2 / TD), where ρ is the metal resistivity, ε is the dielectric constant of the dielectric layer, L is the wire length, T is the dielectric thickness, and D is the metal wire thickness. The dielectric constant ε of the dielectric layer is related to the size of the capacitor C. Reducing the dielectric constant ε of the dielectric layer can reduce the capacitance value, thereby reducing the propagation delay.

[0003] For the IC back-end process, in order to reduce the propagation delay, a layer of fluorinated silica glass (FSG) insulating layer dielectric formed by chemical vapor deposition (CVD) is added to reduce the K value (ε / ε0, where ε represents the dielectric constant of the material and ε0 represents the dielectric constant of vacuum or air). The purpose of adjusting the K value can be achieved by adjusting the fluorine content in the fluorine silica glass. The higher the fluorine content, the better the gap fill and step coverage of the fluorine silica glass. However, due to the thermal instability of fluorine ions in the insulating layer dielectric and the easy diffusion, the process conditions and process windows of the fluorine content are limited. If fluorine diffuses into the device or metal, it will cause the dielectric layer to peel off (Peeling Defect), such as Figure 1 to Figure 3 As shown in Figure 2, and the generation of metal voids, such as Figure 4-5 As shown, this will eventually cause device failure.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a metal interlayer dielectric structure and a preparation method thereof, so as to solve the problem in the prior art that fluorine diffuses into the device or metal, causing the dielectric layer to fall off and metal holes to form.

[0006] To achieve the above-mentioned purpose and other related purposes, the present invention provides an intermetallic dielectric layer structure, which includes: a first silicon-rich oxide layer covering the surface of a first metal layer; a fluorosilicate glass layer disposed on the first silicon-rich oxide layer; a second silicon-rich oxide layer disposed on the fluorosilicate glass layer; an undoped silicon glass layer disposed on the second silicon-rich oxide layer, and a second metal layer is disposed on the undoped silicon glass layer; the first silicon-rich oxide layer is used to block the fluorine element of the fluorosilicate glass layer from diffusing toward the first metal layer, and the second silicon-rich oxide layer is used to block the fluorine element of the fluorosilicate glass layer from diffusing toward the second metal layer.

[0007] Optionally, the first silicon-rich oxide layer has a thickness of 250 angstroms to 400 angstroms.

[0008] Optionally, the fluorosilicate glass layer is formed by forming a first fluorosilicate glass layer based on a high-density plasma chemical vapor deposition process and a second fluorosilicate glass layer based on a plasma enhanced chemical vapor deposition process, and then performing chemical mechanical polishing, wherein the thickness of the first fluorosilicate glass layer is 5000 angstroms to 7000 angstroms, and the thickness of the second fluorosilicate glass layer is 7000 angstroms to 9000 angstroms.

[0009] Optionally, the thickness of the fluorosilicate glass layer is 5000 angstroms to 6500 angstroms.

[0010] Optionally, the mass fraction of fluorine in the fluorine-silicate glass layer is 4.5% to 8%.

[0011] Optionally, the second silicon-rich oxide layer has a thickness of 300 angstroms to 800 angstroms.

[0012] Optionally, the thickness of the undoped silicon glass layer is 1500 angstroms to 2500 angstroms.

[0013] The present invention also provides a method for preparing an intermetallic dielectric layer structure, the preparation method comprising the steps of: forming a first silicon-rich oxide layer on the surface of a first metal layer; forming a fluorine silicon glass layer on the first silicon-rich oxide layer; forming a second silicon-rich oxide layer on the fluorine silicon glass layer; forming an undoped silicon glass layer on the second silicon-rich oxide layer, wherein a second metal layer is disposed on the undoped silicon glass layer; the first silicon-rich oxide layer is used to block the fluorine element of the fluorine silicon glass layer from diffusing toward the first metal layer, and the second silicon-rich oxide layer is used to block the fluorine element of the fluorine silicon glass layer from diffusing toward the second metal layer.

[0014] Optionally, the first silicon-rich oxide layer and the second silicon-rich oxide layer are formed by a chemical vapor deposition process, wherein the reaction gas includes SiH4 and N2O, and the ratio of Si and O in the first silicon-rich oxide layer and the second silicon-rich oxide layer is adjusted by controlling the ratio of SiH4 and N2O.

[0015] Optionally, during the deposition process of the first silicon-rich oxide layer and the second silicon-rich oxide layer, N2 gas is also introduced to dilute the reaction gas and adjust the glow discharge to improve the blocking ability of the first silicon-rich oxide layer and the second silicon-rich oxide layer to the fluorine element, wherein the volume ratio of N2 to N2O is 1:1 to 3:1.

[0016] Optionally, forming a fluorosilicate glass layer on the first silicon-rich oxide layer includes: forming a first fluorosilicate glass layer by a high-density plasma chemical vapor deposition process; forming a second fluorosilicate glass layer on the first fluorosilicate glass layer by a plasma enhanced chemical vapor deposition process; forming a final fluorosilicate glass layer by a chemical mechanical polishing process; reaction gases during the deposition of the first fluorosilicate glass layer and the second fluorosilicate glass layer include SiH4, N2O, SiF4 and C2F6.

[0017] Optionally, during the deposition process of the first fluorosilicate glass layer and the second fluorosilicate glass layer, N2 gas is introduced to increase the mass fraction of fluorine in the reaction gas, and the fluorine content in the reaction gas is increased to increase the K value of the first fluorosilicate glass layer and the second fluorosilicate glass layer. The N2 gas is introduced to dilute the reaction gas and adjust the glow discharge, thereby improving the thermal stability of the fluorine element in the first fluorosilicate glass layer and the second fluorosilicate glass layer.

[0018] Optionally, the mass fraction of fluorine in the fluorine-silicate glass layer is 4.5% to 8%.

[0019] As described above, the intermetallic dielectric layer structure and the preparation method thereof of the present invention have the following beneficial effects:

[0020] The intermetallic dielectric layer structure of the present invention is composed of a first silicon-rich oxide layer, a fluorosilicate glass layer, a second silicon-rich oxide layer and an undoped silicon glass layer. On the one hand, the first silicon-rich oxide layer is used to block the fluorine element of the fluorosilicate glass layer from diffusing toward the first metal layer, and the second silicon-rich oxide layer is used to block the fluorine element of the fluorosilicate glass layer from diffusing toward the second metal layer, thereby effectively reducing the probability of the fluorosilicate glass layer diffusing to the metal layer and the device dielectric layer in the back-end process, and effectively avoiding the generation of metal holes and the shedding defects of the dielectric layer; on the other hand, due to the enhanced fluorine diffusion blocking ability, the present invention can dope more fluorine elements into the fluorosilicate glass layer, thereby more effectively reducing the dielectric K value of the fluorosilicate glass layer, thereby reducing the overall parasitic capacitance of the device and reducing the propagation delay of the device.

[0021] In the deposition process of the first silicon-rich oxide layer and the second silicon-rich oxide layer of the present invention, N2 gas is introduced to dilute the reaction gas and adjust the glow discharge, so as to achieve fine adjustment of the Si / O ratio in the silicon-rich oxide layer and improve the quality of the silicon-rich oxide layer, thereby improving the blocking ability of the first silicon-rich oxide layer and the second silicon-rich oxide layer to the fluorine element; in the deposition process of the fluorosilicate glass layer of the present invention, N2 gas is introduced to increase the mass fraction of fluorine in the reaction gas, thereby effectively increasing the fluorine content in the reaction gas to increase the K value of the first fluorosilicate glass layer and the second fluorosilicate glass layer, and at the same time, the N2 gas is introduced to dilute the reaction gas and adjust the glow discharge, thereby improving the thermal stability of the fluorine element in the first fluorosilicate glass layer and the second fluorosilicate glass layer.

[0022] The present invention can add more fluorine elements to the fluorosilicate glass layer, thereby more effectively reducing the dielectric K value of the fluorosilicate glass layer, thereby reducing the overall parasitic capacitance of the device, reducing the propagation delay of the device, and avoiding the shedding of the device dielectric layer and the generation of holes in the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0024] Figure 1 to Figure 3 Schematic diagram showing the peeling defect of the dielectric layer caused by fluorine diffusion into the device.

[0025] Figure 4-5 Schematic diagram showing the formation of metal voids due to the diffusion of fluorine into metal.

[0026] Figure 6 to Figure 11It is a schematic diagram showing the structure of each step of the method for preparing the intermetallic dielectric layer structure according to an embodiment of the present invention, wherein: Fig.11 Shown is a schematic structural diagram of an intermetallic dielectric layer structure according to an embodiment of the present invention.

[0027] Component number description

[0028] 101 Base

[0029] 102 Gate Structure

[0030] 103 Isolation dielectric layer

[0031] 104 First Metal Layer

[0032] 105 first silicon-rich oxide layer

[0033] 106 Fluorosilicate glass layer

[0034] 107 Second silicon-rich oxide layer

[0035] 108 Undoped silica glass layer

[0036] 204 Second Metal Layer

[0037] 205 Second layer First silicon-rich oxide layer

[0038] 206 Second fluorine silicon glass layer

[0039] 207 Second layer Second silicon-rich oxide layer

[0040] 208 Second undoped silica glass layer DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0043] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0044] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0045] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0046] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0047] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] The parasitic capacitance can be reduced by using fluorine-silicon glass, but the diffusion of fluorine into the device or metal will cause peeling defect of the dielectric layer and the formation of metal voids. The reaction formula is: Si-F+H2O=>SiOH+HF. The F ions produced by the reaction are easy to combine with Al-Cu to form Al-F and Cu-F. Al-F and Cu-F are very easy to dissolve in aqueous solution. Under high temperature conditions, the presence of F will form more voids in the metal material.

[0049] To solve the above problems, Fig.11 As shown, this embodiment provides an intermetallic dielectric layer structure, which includes a first silicon-rich oxide layer 105 , a fluorosilicate glass layer 106 , a second silicon-rich oxide layer 107 and an undoped silicon glass layer 108 .

[0050] like Fig.11As shown, an application example of the intermetallic dielectric layer structure of this embodiment is used for a MOS device structure, and the MOS device structure includes a substrate 101, and the substrate 101 can be a silicon substrate, a silicon germanium substrate, a germanium substrate, an SOI substrate, a silicon carbide substrate, a III-V compound substrate, etc. The substrate 101 can contain various doping (including P-type conductive doping, N-type conductive doping, etc.), such as body region doping, source and drain region doping, etc. A gate structure 102 is formed on the substrate 101, and the substrate 101 on both sides of the gate structure 102 is a source region and a drain region (not shown). The substrate 101 is covered with an isolation dielectric layer 103 for isolating the device below and the metal layer above. The isolation dielectric layer 103 can be, for example, silicon dioxide, silicon nitride, silicon oxynitride, or a stack of the above materials. A first metal layer 104 is disposed on the isolation dielectric layer 103. The first metal layer 104 can be electrically connected to the gate structure 102, the source region and the drain region respectively through through holes formed in the isolation dielectric layer 103. The first metal layer 104 is patterned according to the required electrical function to form a corresponding wiring structure.

[0051] like Fig.11 As shown, the first silicon-rich oxide layer 105 covers the surface of the first metal layer 104. The first silicon-rich oxide layer 105 is used to prevent damage to the first metal layer 104 during the formation of the fluorosilicate glass layer 106. It also prevents HF generated when the fluorosilicate glass layer 106 comes into contact with water vapor from diffusing into the first metal layer 104 and then corroding the metal to affect electron migration. It can also increase the content of fluorine in the fluorosilicate glass layer 106 and reduce the K value of the fluorosilicate glass layer 106.

[0052] In a specific example, the first silicon-rich oxide layer 105 extends along a surface profile of the first metal layer 104 (eg, an upper surface, a sidewall, etc. of the first metal layer 104 ) to completely cover the surface of the first metal layer 104 .

[0053] In one embodiment, the thickness of the first silicon-rich oxide layer 105 may be 250 angstroms to 400 angstroms. In a specific example, the thickness of the first silicon-rich oxide layer 105 is 300 angstroms.

[0054] like Fig.11 As shown, the fluorine silicon glass layer 106 is disposed on the first silicon-rich oxide layer 105 .

[0055] In one embodiment, the fluorosilicate glass layer 106 is formed by forming a first fluorosilicate glass layer based on a high-density plasma chemical vapor deposition process and a second fluorosilicate glass layer based on a plasma enhanced chemical vapor deposition process, and then performing chemical mechanical polishing (CMP). The first fluorosilicate glass layer formed based on the high-density plasma chemical vapor deposition process has a strong filling capacity and a high density, which can effectively improve the stability of the fluorosilicate glass, and the second fluorosilicate glass layer formed based on the plasma enhanced chemical vapor deposition process can effectively compensate for the unevenness of the protrusions and depressions on the surface of the first fluorosilicate glass layer, and then performing chemical mechanical polishing, finally forming a fluorosilicate glass layer 106 with high filling capacity, high density and high flatness.

[0056] In one embodiment, the thickness of the first fluorosilicate glass layer is 5000 angstroms to 7000 angstroms, and the thickness of the second fluorosilicate glass layer is 7000 angstroms to 9000 angstroms. In a specific example, the thickness of the first fluorosilicate glass layer is 6000 angstroms, and the thickness of the second fluorosilicate glass layer is 8000 angstroms. In one embodiment, the thickness of the fluorosilicate glass layer is 5000 angstroms to 6500 angstroms. In a specific example, the thickness of the fluorosilicate glass layer is 5500 angstroms.

[0057] In one embodiment, the mass fraction of fluorine in the fluorine silicate glass layer 106 is 4.5% to 8%. Compared with the conventional fluorine silicate glass with a lower mass fraction of fluorine, the mass fraction of fluorine in the fluorine silicate glass layer 106 of this embodiment is 4.5% to 8%, such as 7%, which can effectively reduce the K value of the fluorine silicate glass, thereby reducing the final parasitic capacitance value.

[0058] like Fig.11 As shown, the second silicon-rich oxide layer 107 is disposed on the fluorosilicate glass layer 106. The second silicon-rich oxide layer 107 is used to prevent HF generated when the fluorosilicate glass layer 106 contacts water vapor from diffusing into the second metal layer 204, thereby corroding the metal and affecting electron migration, and can further increase the content of fluorine in the fluorosilicate glass layer 106 and reduce the K value of the fluorosilicate glass layer 106.

[0059] In one embodiment, the second silicon-rich oxide layer 107 has a thickness of 300 angstroms to 800 angstroms. In a specific example, the second silicon-rich oxide layer 107 may have a thickness of 600 angstroms.

[0060] like Fig.11 As shown, the non-doped silicon glass layer 108 is disposed on the second silicon-rich oxide layer 107 to further prevent the diffusion of F element, and a second metal layer 204 is disposed on the non-doped silicon glass layer 108 .

[0061] In one embodiment, the thickness of the non-doped silica glass layer 108 is 1500 angstroms to 2500 angstroms. In a specific example, the thickness of the non-doped silica glass layer 108 may be 2000 angstroms. In this example, the thickness of the fluorosilicate glass layer 106 is set to be much greater than the non-doped silica glass layer 108, and a second silicon-rich oxide layer 107 is provided between the fluorosilicate glass layer 106 and the non-doped silica glass layer 108, which effectively prevents the fluorine element in the fluorosilicate glass layer 106 from diffusing into the second metal layer 204 while greatly reducing the overall K value of the intermetallic dielectric layer structure.

[0062] like Fig.11 As shown, of course, more wiring metal layers can be made on the MOS device structure as needed. For example, a second first silicon-rich oxide layer 205, a second fluorosilicate glass layer 206, a second second silicon-rich oxide layer 207, a second non-doped silicon glass layer 208 and a third metal layer can be formed on the second metal layer 204, and the examples listed here are not limited to them.

[0063] like Figure 6 to Figure 11 As shown, this embodiment also provides a method for preparing an intermetallic dielectric layer structure, the preparation method comprising the following steps:

[0064] like Figure 6 As shown, step 1) is first performed to form a first silicon-rich oxide layer 105 on the surface of the first metal layer 104 .

[0065] In one embodiment, the first silicon-rich oxide layer 105 is formed by a chemical vapor deposition process, wherein the reaction gas includes SiH 4 and N 2 O, and the ratio of Si to O in the first silicon-rich oxide layer 105 is adjusted by controlling the ratio of SiH 4 to N 2 O.

[0066] In one embodiment, during the deposition process of the first silicon-rich oxide layer 105, N2 gas is introduced to dilute the reaction gas and adjust the glow discharge to improve the blocking ability of the first silicon-rich oxide layer 105 to the fluorine element, wherein the volume ratio of N2 to N2O is 1:1 to 3:1.

[0067] like Figure 7 As shown, step 2) is then performed to form a fluorine silicon glass layer 106 on the first silicon-rich oxide layer 105 .

[0068] In one embodiment, forming the fluorosilicate glass layer 106 on the first silicon-rich oxide layer 105 includes:

[0069] Step 2-1), forming a first fluorosilicate glass layer by a high-density plasma chemical vapor deposition process;

[0070] Step 2-2), forming a second fluorosilicate glass layer on the first fluorosilicate glass layer by a plasma enhanced chemical vapor deposition process; the reaction gas during the deposition of the first fluorosilicate glass layer and the second fluorosilicate glass layer includes SiH4, N2O, SiF4 and C2F6;

[0071] Step 2-3), forming the final fluorosilicate glass layer through a chemical mechanical polishing process.

[0072] The first fluorosilicate glass layer formed based on the high-density plasma chemical vapor deposition process has a strong filling ability and a high density, which can effectively improve the stability of the fluorosilicate glass. The second fluorosilicate glass layer formed based on the plasma enhanced chemical vapor deposition process can effectively compensate for the unevenness of the protrusions and depressions on the surface of the first fluorosilicate glass layer. Chemical mechanical polishing is then performed to finally form a fluorosilicate glass layer 106 with high filling ability, high density and high flatness.

[0073] In one embodiment, during the deposition of the first fluorosilicate glass layer and the second fluorosilicate glass layer, N2 gas is introduced and the mass fraction of fluorine in the reaction gas is increased, and the fluorine content in the reaction gas is increased to increase the K value of the first fluorosilicate glass layer and the second fluorosilicate glass layer, and N2 gas is introduced to dilute the reaction gas and adjust the glow discharge to improve the thermal stability of the fluorine element in the first fluorosilicate glass layer and the second fluorosilicate glass layer. In a specific example, the mass fraction of fluorine in the fluorosilicate glass layer 106 is 4.5% to 8%, which can effectively reduce the K value of the fluorosilicate glass, thereby reducing the final parasitic capacitance value.

[0074] like Figure 8 As shown, step 3) is then performed to form a second silicon-rich oxide layer 107 on the fluorine silicon glass layer 106 .

[0075] like Figure 9-10 As shown, step 4 is then performed to form an undoped silicon glass layer 108 on the second silicon-rich oxide layer 107, and a second metal layer 204 is provided on the undoped silicon glass layer 108; the first silicon-rich oxide layer 105 is used to block the fluorine element of the fluorine silicon glass layer 106 from diffusing toward the first metal layer 104, and the second silicon-rich oxide layer 107 is used to block the fluorine element of the fluorine silicon glass layer 106 from diffusing toward the second metal layer 204.

[0076] In one embodiment, the second silicon-rich oxide layer 107 is formed by a chemical vapor deposition process, wherein the reaction gas includes SiH 4 and N 2 O, and the ratio of Si to O in the second silicon-rich oxide layer 107 is adjusted by controlling the ratio of SiH 4 to N 2 O.

[0077] In one embodiment, during the deposition process of the second silicon-rich oxide layer 107, N2 gas is introduced to dilute the reaction gas and adjust the glow discharge to improve the blocking ability of the second silicon-rich oxide layer 107 to the fluorine element, wherein the volume ratio of N2 to N2O is 1:1 to 3:1.

[0078] like Fig.11 As shown, the preparation method may further include forming a second first silicon-rich oxide layer 205 , a second fluorine silicon glass layer 206 , a second second silicon-rich oxide layer 207 , a second undoped silicon glass layer 208 and a third metal layer on the second metal layer 204 .

[0079] In order to verify the ability of the metal interlayer structure of the present application to inhibit the diffusion of fluorine, the present embodiment also conducted the following two groups of experiments:

[0080] The first set of experiments:

[0081] Step 1), preparing 4 groups of different structures, including:

[0082] S1, depositing a 5500 angstrom thick fluorine silicon glass layer (mass fraction of fluorine is 6%) and a 2000 angstrom thick polyethylene oxide (PEOX) layer on the surface of a silicon substrate in sequence;

[0083] S2, depositing a 5500 angstrom thick fluorine silicon glass layer (mass fraction of fluorine is 6%) and a 2000 angstrom thick silicon nitride (SIN) layer on the surface of the silicon substrate in sequence;

[0084] S3, depositing a 5500 angstrom thick fluorine silicon glass layer (mass fraction of fluorine is 6%) and a 2000 angstrom thick silicon oxynitride (SION) layer on the surface of the silicon substrate in sequence;

[0085] S4, depositing a first silicon-rich oxide layer (SRO) with a thickness of 2000 angstroms, a fluorine-silicon glass layer (with a mass fraction of fluorine of 6%) with a thickness of 5500 angstroms, and a second silicon-rich oxide layer (SRO) with a thickness of 2000 angstroms on the surface of the silicon substrate in sequence;

[0086] Step 2), annealing at 400 degrees Celsius for 3 hours to fully diffuse the fluorine element in the fluorine-silicon glass layer;

[0087] Step 3), the diffusion depth profile of F in the medium is analyzed by secondary ion mass spectrometry (SIMS), thereby obtaining the fluorine diffusion barrier capabilities of S1, S2, S3, and S4. The analysis results are shown in the following table:

[0088] Material Fluorine diffusion inhibition ability Blistering Defect S1:PEOX fail none S2:SIN qualified have S3:SION qualified have S4:SRO most none

[0089] From the experiment, it can be seen that the fluorine diffusion inhibition ability of material S1 failed, and materials S2 and S3 had blistering defects. Material S4 showed good fluorine diffusion inhibition ability compared with the other three groups of materials S1, S2, and S3, and there was no blistering defect problem caused by F aggregation.

[0090] The second set of experiments:

[0091] Step 1), preparing 3 groups of different structures, including:

[0092] T1, depositing a first silicon-rich oxide layer (SRO) with a thickness of 300 angstroms, a fluorine-silicon glass layer (with a mass fraction of fluorine of 6%) with a thickness of 5500 angstroms, a second silicon-rich oxide layer (SRO) with a thickness of 600 angstroms, and a non-doped silicon glass layer with a thickness of 2000 angstroms on the surface of a silicon substrate in sequence;

[0093] T2, depositing a first silicon-rich oxide layer (SRO) with a thickness of 300 angstroms, a fluorine-silicon glass layer with a thickness of 5500 angstroms (the mass fraction of fluorine is 6%), and a non-doped silicon glass layer with a thickness of 2000 angstroms on the surface of the silicon substrate in sequence;

[0094] T3, a first silicon-rich oxide layer (SRO) with a thickness of 300 angstroms, a fluorine-silicon glass layer (with a fluorine mass fraction of 6%) with a thickness of 5500 angstroms, and a second silicon-rich oxide layer (SRO) with a thickness of 600 angstroms are sequentially deposited on the surface of the silicon substrate.

[0095] Step 2), annealing at 400 degrees Celsius for 3 hours to fully diffuse the fluorine element in the fluorine-silicon glass layer;

[0096] Step 3), the diffusion depth profile of F in the medium is analyzed by secondary ion mass spectrometry (SIMS), so as to obtain the barrier capacity of fluorine diffusion of the two structures. The analysis results are shown in the following table:

[0097] structure Fluorine diffusion inhibition ability Blistering Defect T1 qualified none T2 fail slight T3 fail have

[0098] As described above, the intermetallic dielectric layer structure and the preparation method thereof of the present invention have the following beneficial effects:

[0099] The intermetallic dielectric layer structure of the present invention is composed of a first silicon-rich oxide layer, a fluorosilicate glass layer, a second silicon-rich oxide layer and an undoped silicon glass layer. On the one hand, the first silicon-rich oxide layer is used to block the fluorine element of the fluorosilicate glass layer from diffusing toward the first metal layer 104, and the second silicon-rich oxide layer is used to block the fluorine element of the fluorosilicate glass layer from diffusing toward the second metal layer 204, thereby effectively reducing the probability of the fluorosilicate glass layer diffusing to the metal layer and the device dielectric layer in the back-end process, and effectively avoiding the generation of metal holes and the shedding defects of the dielectric layer; on the other hand, due to the enhanced fluorine diffusion blocking ability, the present invention can dope more fluorine elements into the fluorosilicate glass layer, thereby more effectively reducing the dielectric K value of the fluorosilicate glass layer, thereby reducing the overall parasitic capacitance of the device and reducing the propagation delay of the device.

[0100] In the deposition process of the first silicon-rich oxide layer and the second silicon-rich oxide layer of the present invention, N2 gas is introduced to dilute the reaction gas and adjust the glow discharge, so as to achieve fine adjustment of the Si / O ratio in the silicon-rich oxide layer and improve the quality of the silicon-rich oxide layer, thereby improving the blocking ability of the first silicon-rich oxide layer and the second silicon-rich oxide layer to the fluorine element; in the deposition process of the fluorosilicate glass layer of the present invention, N2 gas is introduced to increase the mass fraction of fluorine in the reaction gas, thereby effectively increasing the fluorine content in the reaction gas to increase the K value of the first fluorosilicate glass layer and the second fluorosilicate glass layer, and at the same time, the N2 gas is introduced to dilute the reaction gas and adjust the glow discharge, thereby improving the thermal stability of the fluorine element in the first fluorosilicate glass layer and the second fluorosilicate glass layer.

[0101] The present invention can add more fluorine elements to the fluorosilicate glass layer, thereby more effectively reducing the dielectric K value of the fluorosilicate glass layer, thereby reducing the overall parasitic capacitance of the device, reducing the propagation delay of the device, and avoiding the shedding of the device dielectric layer and the generation of holes in the metal layer.

[0102] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A metal interlayer structure, characterized in that: The intermetallic dielectric layer structure comprises: A first silicon-rich oxide layer covering the surface of the first metal layer; a fluorine-silicon glass layer, disposed on the first silicon-rich oxide layer; A second silicon-rich oxide layer is disposed on the fluorosilicate glass layer; an undoped silicon glass layer, disposed on the second silicon-rich oxide layer, wherein a second metal layer is disposed on the undoped silicon glass layer; The first silicon-rich oxide layer is used to block the fluorine element of the fluorine silicon glass layer from diffusing toward the first metal layer, and the second silicon-rich oxide layer is used to block the fluorine element of the fluorine silicon glass layer from diffusing toward the second metal layer.

2. The intermetallic dielectric layer structure according to claim 1, characterized in that: The thickness of the first silicon-rich oxide layer is 250 angstroms to 400 angstroms.

3. The intermetallic dielectric layer structure according to claim 1, characterized in that: The fluorosilicate glass layer is formed by forming a first fluorosilicate glass layer based on a high-density plasma chemical vapor deposition process and a second fluorosilicate glass layer based on a plasma enhanced chemical vapor deposition process, and then performing chemical mechanical polishing. The thickness of the first fluorosilicate glass layer is 5000 angstroms to 7000 angstroms, and the thickness of the second fluorosilicate glass layer is 7000 angstroms to 9000 angstroms.

4. The intermetallic dielectric layer structure according to claim 3, characterized in that: The thickness of the fluorosilicate glass layer is 5000 angstroms to 6500 angstroms.

5. The intermetallic dielectric layer structure according to claim 1, characterized in that: The mass fraction of fluorine in the fluorine-silicon glass layer is 4.5% to 8%.

6. The intermetallic dielectric layer structure according to claim 1, characterized in that: The second silicon-rich oxide layer has a thickness of 300 angstroms to 800 angstroms.

7. The intermetallic dielectric layer structure according to claim 1, characterized in that: The thickness of the non-doped silicon glass layer is 1500 angstroms to 2500 angstroms.

8. A method for preparing an intermetallic dielectric layer structure, characterized in that: The preparation method comprises the steps of: forming a first silicon-rich oxide layer on the surface of the first metal layer; forming a fluorine silicon glass layer on the first silicon-rich oxide layer; forming a second silicon-rich oxide layer on the fluorosilicate glass layer; forming a non-doped silicon glass layer on the second silicon-rich oxide layer, wherein a second metal layer is disposed on the non-doped silicon glass layer; The first silicon-rich oxide layer is used to block the fluorine element of the fluorine silicon glass layer from diffusing toward the first metal layer, and the second silicon-rich oxide layer is used to block the fluorine element of the fluorine silicon glass layer from diffusing toward the second metal layer.

9. The method for preparing the intermetallic dielectric layer structure according to claim 8, characterized in that: The first silicon-rich oxide layer and the second silicon-rich oxide layer are formed by a chemical vapor deposition process, wherein the reaction gas includes SiH4 and N2O, and the ratio of Si and O in the first silicon-rich oxide layer and the second silicon-rich oxide layer is adjusted by controlling the ratio of the SiH4 and N2O.

10. The method for preparing the intermetallic dielectric layer structure according to claim 9, characterized in that: The deposition process of the first silicon-rich oxide layer and the second silicon-rich oxide layer also includes introducing N2 gas to dilute the reaction gas and adjust the glow discharge to improve the blocking ability of the first silicon-rich oxide layer and the second silicon-rich oxide layer to the fluorine element, wherein the volume ratio of N2 to N2O is 1:1 to 3:

1.

11. The intermetallic dielectric layer structure according to claim 8, characterized in that: Forming a fluorine silicon glass layer on the first silicon-rich oxide layer comprises: forming a first fluorosilicate glass layer by a high density plasma chemical vapor deposition process; a second fluorosilicate glass layer formed on the first fluorosilicate glass layer by a plasma enhanced chemical vapor deposition process; The final fluorosilicate glass layer is formed by a chemical mechanical polishing process.

12. The method for preparing an intermetallic dielectric layer structure according to claim 11, characterized in that: The deposition process of the first fluorosilicate glass layer and the second fluorosilicate glass layer also includes introducing N2 gas and increasing the mass fraction of fluorine in the reaction gas, increasing the fluorine content in the reaction gas to increase the K value of the first fluorosilicate glass layer and the second fluorosilicate glass layer, introducing the N2 gas to dilute the reaction gas and adjust the glow discharge, and improve the thermal stability of the fluorine element in the first fluorosilicate glass layer and the second fluorosilicate glass layer.

13. The method for preparing an intermetallic dielectric layer structure according to claim 11, characterized in that: The mass fraction of fluorine in the fluorine-silicon glass layer is 4.5% to 8%.

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