Semiconductor structure and preparation method thereof, and method for measuring etched rate of semiconductor

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and a method for measuring the etching rate of a semiconductor, and the semiconductor structure is used for measuring the etching rate and comprises a semiconductor layer and a contrast material layer which are made of different materials. The first surface of the semiconductor layer comprises at least one groove, the groove is filled with a contrast material layer, and the contrast material layer is flush with the surface of the semiconductor layer. The high-precision etching rate ratio of the contrast material layer to the semiconductor layer is obtained through the semiconductor structure, the etching rate of the semiconductor is obtained by measuring the etching depth of the contrast material layer, the etching rate with higher accuracy of the semiconductor is obtained, and the operation is convenient; meanwhile, the material of the hard mask layer is arranged, so that the integrity of the first opening and the second opening in the etching process is ensured, and the accuracy of the obtained etching rate is further improved; in addition, the grooves are formed through the shallow trench isolation structures, so that the uniformity of the shapes and the sizes of the grooves is improved; finally, the thickness of the contrast material layer is measured through the reflection spectrum, the method is simple, and operation is convenient.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a semiconductor structure and a preparation method thereof, and a method for measuring a semiconductor etching rate. Background Art

[0002] In the semiconductor production process, a mixed solution of HF and HNO3 of different concentrations is often used to clean the back of the wafer to remove particles and metal contamination that may exist on the back of the wafer. However, the etching effect of the mixed solution on silicon wafers is too significant, resulting in a rough contact surface and aggravated scratches on the back of the etched wafer, which may cause the wafer to break in severe cases. Therefore, it is necessary to accurately measure the etching rate and etching characteristics of the etching solution on silicon in order to reasonably control the concentration of the mixed solution and the process time.

[0003] At present, due to the thick wafer thickness, it is difficult to obtain reflected light passing through the bottom surface of the wafer, so it is impossible to use the method of measuring the reflection spectrum to directly measure the thickness change of the wafer before and after etching; at the same time, because the etching depth is too small compared to the wafer thickness, the wafer thickness change obtained by using other thickness measurement methods has a large error.

[0004] Therefore, in the prior art, the weighing method is generally used to measure the etching rate of silicon by the mixed solution of HF and HNO3, that is, the wafer before the reaction is weighed first, and then the mixed solution of HF and HNO3 is sprayed onto the surface of the wafer to react with silicon, and the weight of the wafer is weighed again after a period of reaction; the difference between the two weights is the part of silicon etched away, so the etching rate of silicon by the mixed solution of HF and HNO3 can be calculated. However, this method has obvious disadvantages. The weight reduction cannot accurately reflect the changes in the thickness and surface morphology of the wafer, and the etching rate of silicon by the mixed solution of HF and HNO3 cannot be accurately calculated.

[0005] Therefore, there is an urgent need for a method that can accurately measure the etching rate of silicon wafers.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology part of the present application. Summary of the invention

[0007] In view of the above shortcomings of the prior art, an object of the present invention is to provide a semiconductor structure and a method for preparing the same, and a method for measuring the etching rate of a semiconductor, so as to solve the problem of low accuracy in measuring the etching rate of a wafer in the prior art.

[0008] To achieve the above object, the present invention provides a semiconductor structure, which is used for etching rate measurement, and comprises: a semiconductor layer and a reference material layer; the reference material layer is made of a different material from the semiconductor layer;

[0009] The first surface of the semiconductor layer comprises at least one groove, the groove is filled with the contrast material layer, and the surface of the contrast material layer is flush with the surface of the semiconductor layer.

[0010] Optionally, the semiconductor structure further comprises a hard mask layer;

[0011] The hard mask layer is arranged on the first surface of the semiconductor layer, and the hard mask layer covers the surfaces of the reference material layer and the semiconductor layer; the hard mask layer includes a first opening and a second opening penetrating the hard mask layer, the first opening and the second opening have the same diameter, the reference material layer is exposed below the first opening, and the semiconductor layer in the semiconductor structure where the reference material layer is not provided is exposed below the second opening.

[0012] Optionally, the material of the semiconductor layer is silicon; and / or the material of the reference material layer is silicon dioxide; and / or when a hard mask layer is provided, the material of the hard mask layer is a silicon nitride film doped with silicon carbide.

[0013] The present invention also provides a method for preparing a semiconductor structure, wherein the method is used to prepare the above-mentioned semiconductor structure, and the method comprises:

[0014] A silicon oxide film is disposed on the first surface of the semiconductor layer, a silicon nitride layer is disposed on the silicon oxide film, a patterned photoresist is disposed on the silicon nitride layer, the silicon nitride layer, the silicon oxide film and the semiconductor layer are etched by the patterned photoresist to obtain a groove on the first surface of the semiconductor layer, and the photoresist is removed;

[0015] A contrast material layer is disposed in the groove, and the exposed surface of the contrast material layer is flush with the first surface of the wafer to form a flush surface, and the silicon nitride layer and the silicon oxide film are removed.

[0016] The present invention also provides a method for preparing a semiconductor structure, wherein the method is used to prepare the above-mentioned semiconductor structure, and the method comprises:

[0017] Disposing at least one groove on the first surface of the semiconductor layer;

[0018] A contrast material layer is disposed in the groove, wherein the exposed surface of the contrast material layer is flush with the first surface of the wafer to form a flush surface;

[0019] Disposing a hard mask layer on the first surface of the semiconductor layer, the hard mask layer covering a flush surface of the contrast material layer and the semiconductor layer;

[0020] The hard mask layer is patterned to obtain a first opening and a second opening, wherein the first opening and the second opening penetrate the hard mask layer, the first opening is located above the contrast material layer, and the second opening is located above the semiconductor layer where the contrast material layer is not disposed.

[0021] The present invention also provides a method for measuring a semiconductor etching rate, the method comprising:

[0022] Providing a semiconductor structure, wherein the semiconductor structure is the semiconductor structure described above;

[0023] measuring an original thickness L1 of the reference material layer in the semiconductor structure;

[0024] The etching solution etches the surfaces of the contrast material layer and the semiconductor layer;

[0025] The thickness L2 of the reference material layer after etching is measured to obtain the etching time t, and the etching rate V1 of the reference material layer is calculated to be V1=(L1-L2) / t;

[0026] The etching rate ratio X between the reference material layer and the semiconductor layer is obtained, and the etching rate V2 = V1 / X of the semiconductor layer is calculated.

[0027] Optionally, the etching rate ratio X of the reference material layer to the semiconductor layer is obtained by:

[0028] The surface height difference ΔL between the reference material layer and the semiconductor layer after etching is measured, and the etching rate ratio X=(L1-L2) / (L1-L2+ΔL) of the reference material layer and the semiconductor layer is calculated.

[0029] The present invention also provides a method for measuring a semiconductor etching rate, the method comprising:

[0030] Providing a semiconductor structure, wherein the semiconductor structure is the semiconductor structure described above;

[0031] The etching solution etches the contrast material layer through the first opening to form a first etching hole, and the etching solution etches the semiconductor layer through the second opening to form a second etching hole;

[0032] The depth X1 of the first etching hole is measured, the etching time t is obtained, and the etching rate V1=X1 / t of the etching solution on the reference material layer is calculated;

[0033] The etching rate ratio X between the reference material layer and the semiconductor layer is obtained, and the etching rate V2 = V1 / X of the semiconductor layer is calculated.

[0034] Optionally, the etching rate ratio X of the reference material layer to the semiconductor layer is obtained by:

[0035] The ratio X of the depth of the first etched hole to the depth of the second etched hole after etching is measured, where X is the ratio of the etching rates of the reference material layer to the semiconductor layer.

[0036] Optionally, the method for measuring the depth ratio of the first etched hole to the second etched hole after etching is: slicing the semiconductor structure along a cross section perpendicular to the first surface; respectively measuring the depth of the first etched hole and the depth of the second etched hole obtained by slicing, and calculating the depth ratio X of the first etched hole to the second etched hole;

[0037] Or the method for measuring the ratio of the depth of the first etched hole and the depth of the second etched hole after etching is: emitting detection light to the bottom of the first etched hole and the second etched hole from the height of the first surface; receiving the reflection spectra reflected from the bottom of the first etched hole and the second etched hole respectively, and obtaining the depths of the first etched hole and the second etched hole by corresponding analysis of the reflection spectra.

[0038] As described above, the semiconductor structure and the method for preparing the same, as well as the method for measuring the etching rate of the semiconductor of the present invention have the following beneficial effects:

[0039] The present invention provides a groove filling reference material layer in the semiconductor layer as an etching rate measurement structure, places the etching positions of the reference material layer and the semiconductor layer in one structure, and can calculate the etching rate of the semiconductor layer by calculating the etched size ratio of the reference material layer and the semiconductor layer and combining the etching rate of the reference material layer that can directly measure the etching rate, and can measure a more accurate value by the size ratio, so that the etching rate of the semiconductor layer can be obtained with higher accuracy compared with the prior art;

[0040] The present invention sets the reference material layer to be silicon dioxide whose etching rate can be directly measured, and both silicon dioxide and silicon can be etched by the same etching solution, and the etching rates are also at a similar order of magnitude, so that the etching rate of the semiconductor layer with higher accuracy can be obtained;

[0041] The present invention arranges the groove by arranging a shallow trench isolation structure, thereby improving the uniformity of the shape and size of the groove, which is beneficial to obtaining a more uniform etching rate when sampling at multiple positions using the semiconductor structure, and further improving the accuracy of measuring the etching rate of the semiconductor layer using the semiconductor structure;

[0042] The present invention obtains the etching rate of the reference material layer by measuring the thickness difference of the reference material layer before and after etching, and can directly measure without setting a hard mask layer, and the method is simple and direct;

[0043] The present invention uses the height difference after etching to obtain the adjacent material layer and the semiconductor layer, thereby calculating the etched height of the semiconductor layer, and the method is simple;

[0044] The present invention provides a hard mask layer with a first opening and a second opening, so that during the etching of the reference material layer and the semiconductor layer, only the areas below the first opening and the second opening can be etched, and the etching area can be better controlled. The present invention also reduces the etching time required, thereby improving the measurement efficiency and the measurement accuracy.

[0045] The present invention uses a silicon carbide-doped silicon nitride film as the material of the hard mask layer, which can further improve the blocking effect and the control of the etching area and etching time;

[0046] The present invention etches the reference material layer and the semiconductor layer through the first opening and the second opening of the hard mask layer, and can effectively control the etching area, so that the obtained etching depth ratio can more accurately reflect the etching rates of the two compared with the measurement method in Example 3;

[0047] The present invention can obtain a more accurate etched depth ratio by measuring the etched depth ratio in a slicing manner;

[0048] The present invention obtains the ratio of the etched depth by measuring the reflection spectrum of the etched hole, so that the sample can be used twice, the cost is low and the measurement efficiency is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It shows a schematic structural diagram of the semiconductor structure in Example 1 of the present invention.

[0050] Figure 2 It is a schematic diagram of the structure presented by setting a silicon oxide film and a silicon nitride layer in step A1 of the method for preparing a semiconductor structure in embodiment 2 of the present invention.

[0051] Figure 3 It is a schematic diagram of the structure presented by setting the photoresist in step A2 of the method for preparing the semiconductor structure of embodiment 2 of the present invention.

[0052] Figure 4 It is a schematic diagram showing the structure of the groove obtained in step A3 of the method for preparing the semiconductor structure of embodiment 2 of the present invention.

[0053] Figure 5 It is a schematic structural diagram showing the setting of a reference material layer in step A4 in the method for preparing a semiconductor structure according to embodiment 2 of the present invention.

[0054] Figure 6 It is a schematic diagram showing the structure presented by etching the reference material layer and the semiconductor layer in step M4 in the method for measuring the etching rate of a semiconductor according to embodiment 3 of the present invention.

[0055] Figure 7 It shows a schematic structural diagram of the semiconductor structure in Example 4 of the present invention.

[0056] Figure 8 It is a schematic diagram of the structure presented by setting the groove in step B1 in the method for preparing the semiconductor structure of embodiment 5 of the present invention.

[0057] Fig. 9 It is a schematic diagram showing the structure presented by setting a reference material layer in step B2 in the method for preparing a semiconductor structure in embodiment 5 of the present invention.

[0058] Fig.10 It is a schematic structural diagram of setting a hard mask layer in step B3 of the method for preparing a semiconductor structure in embodiment 5 of the present invention.

[0059] Fig.11 It is a schematic diagram showing the structure of the patterned hard mask layer in step B4 of the method for preparing the semiconductor structure in embodiment 5 of the present invention.

[0060] Fig.12 Shown is a schematic diagram of the structure presented by setting a graphic photoresist in step B4 in an optional example of a method for preparing a semiconductor structure in embodiment 5 of the present invention.

[0061] Fig.13 It is a schematic diagram showing the structure presented by etching the reference material layer and the semiconductor layer in step N2 in the method for measuring the etching rate of a semiconductor according to Example 6 of the present invention.

[0062] Component number description

[0063] 10. Semiconductor layer; 11. Groove; 12. Silicon oxide film; 13. Silicon nitride layer; 14. Photoresist; 15. Second etching hole; 20. Reference material layer; 21. First etching hole; 30. Hard mask layer; 31. First opening; 32. Second opening. DETAILED DESCRIPTION

[0064] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0065] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the schematic diagrams showing the device structure will not be partially enlarged according to the general scale, and the schematic diagrams are only examples, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0066] For convenience of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0067] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0068] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0069] Embodiment 1:

[0070] like Figure 1 As shown, this embodiment provides a semiconductor structure, the semiconductor structure is used for etching rate measurement, the semiconductor structure comprises: a semiconductor layer and a reference material layer; the reference material layer is made of a different material from the semiconductor layer;

[0071] The first surface of the semiconductor layer comprises at least one groove, the groove is filled with the contrast material layer, and the surface of the contrast material layer is flush with the surface of the semiconductor layer.

[0072] In the prior art, it is difficult to directly measure the etching rate of the wafer by measuring the reflection spectrum because the wafer itself is too thick. At the same time, the etching depth on the wafer is too small compared to the wafer itself, resulting in a large error in the etching rate of the wafer obtained using other direct measurement methods. The existing weighing method can only reflect the overall reaction rate of the wafer, but cannot reflect the changes in the surface morphology of the wafer. Therefore, it is impossible to measure the precise etching rate of a specific position on the wafer.

[0073] The present invention sets a groove filling reference material layer in the semiconductor layer as a structure for measuring the etching rate, and places the etching positions of the reference material layer and the semiconductor layer in one structure. The etching rate of the semiconductor layer can be obtained by calculating the etched size ratio of the reference material layer and the semiconductor layer and combining the etching rate of the reference material layer that can directly measure the etching rate. A more accurate value can be measured by the size ratio. Therefore, compared with the prior art, the structure of the present invention can obtain the etching rate of the semiconductor layer with higher accuracy.

[0074] In one embodiment, the material of the semiconductor layer is silicon; and / or the material of the contrast material layer is silicon dioxide.

[0075] The present invention sets the reference material layer to be silicon dioxide whose etching rate can be directly measured, and both silicon dioxide and silicon can be etched by the same etching solution, and the etching rates are also at a similar order of magnitude, thereby obtaining an etching rate of the semiconductor layer with higher accuracy.

[0076] Specifically, the materials of the semiconductor layer and the contrast material layer can be other materials suitable for the requirements.

[0077] Embodiment 2:

[0078] This embodiment provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure is used to prepare the semiconductor structure in Embodiment 1. The method comprises:

[0079] The present invention provides a method for preparing a semiconductor structure, the preparation method comprising:

[0080] Step A1: disposing a silicon oxide film on the first surface of the semiconductor layer, and disposing a silicon nitride layer on the silicon oxide film;

[0081] Step A2: Disposing a patterned photoresist on the silicon nitride layer;

[0082] Step A3: etching the silicon nitride layer, the silicon oxide film and the semiconductor layer through the patterned photoresist to obtain a groove on the first surface of the semiconductor layer, and removing the photoresist;

[0083] Step A4: a contrast material layer is disposed in the groove, the exposed surface of the contrast material layer is flush with the first surface of the wafer to form a flush surface, and the silicon nitride layer and the silicon oxide film are removed.

[0084] The method for preparing the semiconductor structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the semiconductor structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0085] First, if Figure 2 As shown, step A1 is performed to dispose a silicon oxide film on the first surface of the semiconductor layer, and to dispose a silicon nitride layer on the silicon oxide film.

[0086] The present invention sets a groove by setting a shallow trench isolation structure, thereby improving the uniformity of the shape and size of the groove, which is beneficial for obtaining a more uniform etching rate when using the semiconductor structure for sampling at multiple positions, and further improving the accuracy of measuring the etching rate of the semiconductor layer using the semiconductor structure.

[0087] Then, step A2 is performed to dispose a patterned photoresist on the silicon nitride layer.

[0088] In one embodiment, a method for providing a patterned photoresist includes: Figure 3 As shown, a photoresist is disposed on the silicon nitride layer; the photoresist is exposed, developed and etched to obtain the patterned photoresist.

[0089] Then, if Figure 4 As shown, step A3 is performed to etch the silicon nitride layer, the silicon oxide film and the semiconductor layer through the patterned photoresist to obtain a groove on the first surface of the semiconductor layer, and remove the photoresist.

[0090] Finally, if Figure 5 As shown, step A4 is performed to set a contrast material layer in the groove, the exposed surface of the contrast material layer is flush with the first surface of the wafer to form a flush surface, and the silicon nitride layer and the silicon oxide film are removed.

[0091] In one embodiment, the flush surface is obtained by chemical mechanical polishing.

[0092] Embodiment 3:

[0093] This embodiment provides a method for measuring a semiconductor etching rate, the method comprising:

[0094] Step M1: providing a semiconductor structure, wherein the semiconductor structure is the semiconductor structure in Embodiment 1;

[0095] Step M2: measuring the original thickness L1 of the reference material layer in the semiconductor structure;

[0096] Step M3: etching the surfaces of the reference material layer and the semiconductor layer with an etching solution;

[0097] Step M4: measuring the thickness L2 of the reference material layer after etching, obtaining the etching time t, and calculating the etching rate V1 of the reference material layer = (L1-L2) / t;

[0098] Step M5: obtaining an etching rate ratio X between the reference material layer and the semiconductor layer, and calculating an etching rate V2 = V1 / X of the semiconductor layer.

[0099] The semiconductor etching rate measuring method of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the semiconductor etching rate measuring method protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0100] First, step M1 is performed to provide a semiconductor structure. The semiconductor structure is as follows: Figure 1 The semiconductor structure in Embodiment 1 is shown.

[0101] Then, step M2 is performed to measure the original thickness L1 of the reference material layer in the semiconductor structure.

[0102] Then, if Figure 6 As shown, step M3 is performed, and the etching solution etches the surfaces of the reference material layer and the semiconductor layer.

[0103] In one embodiment, the etching solution is a mixed solution of hydrofluoric acid and nitric acid.

[0104] Then, step M4 is performed to measure the thickness L2 of the reference material layer after etching, obtain the etching time t, and calculate the etching rate V1 = (L1-L2) / t of the reference material layer.

[0105] Finally, step M5 is performed to obtain the etching rate ratio X between the reference material layer and the semiconductor layer, and the etching rate V2 = V1 / X of the semiconductor layer is calculated.

[0106] The present invention obtains the etching rate of the reference material layer by measuring the thickness difference of the reference material layer before and after etching, and can directly measure without setting a hard mask layer. The method is simple and direct.

[0107] Specifically, the etching rate of the semiconductor layer obtained by the method of the present invention can be used as a calibration value of the etching rate of the semiconductor layer in the process.

[0108] In one embodiment, the etching rate ratio X of the reference material layer to the semiconductor layer is obtained as follows:

[0109] The surface height difference ΔL between the reference material layer and the semiconductor layer after etching is measured, and the etching rate ratio X=(L1-L2) / (L1-L2+ΔL) of the reference material layer to the semiconductor layer is calculated.

[0110] The invention uses the fact that the reference material layer and the semiconductor layer are adjacent after etching to obtain the height difference after etching, thereby calculating the etched height of the semiconductor layer, and the method is simple.

[0111] Specifically, the material etching in the present invention is isotropic etching, so only the etching thickness is measured here to obtain the etching rate in any direction, but the method of the present invention can also be applied to anisotropic etching methods, as long as the etching depth is measured in the etching direction for measuring the etching rate, which is within the protection scope of this application.

[0112] Embodiment 4:

[0113] This embodiment provides a semiconductor structure, and other features of the semiconductor structure are the same as those in Embodiment 1, except that:

[0114] like Figure 7 As shown, the semiconductor structure further includes a hard mask layer;

[0115] The hard mask layer is arranged on the first surface of the semiconductor layer, and the hard mask layer covers the surfaces of the reference material layer and the semiconductor layer; the hard mask layer includes a first opening and a second opening penetrating the hard mask layer, the first opening and the second opening have the same diameter, the reference material layer is exposed below the first opening, and the semiconductor layer in the semiconductor structure where the reference material layer is not provided is exposed below the second opening.

[0116] The present invention provides a hard mask layer with a first opening and a second opening, so that during the etching of the reference material layer and the semiconductor layer, only the areas below the first opening and the second opening can be etched, thereby achieving better control over the etched area during the etching process and reducing the etching time required, thereby improving measurement efficiency and accuracy.

[0117] In one embodiment, when a hard mask layer is provided, the material of the hard mask layer is a silicon nitride film doped with silicon carbide.

[0118] The present invention uses a silicon carbide-doped silicon nitride film as the material of the hard mask layer, thereby further improving the blocking effect and the control over the etching area and etching time.

[0119] Specifically, the distance between the center of the first opening and the center of the second opening is greater than the width of the contrast material layer before being etched, so as to avoid mutual interference between the etching of the contrast material layer and the semiconductor layer.

[0120] Specifically, the thickness of the reference material layer before etching is greater than the depth of the first etching hole.

[0121] Embodiment 5:

[0122] This embodiment provides a method for preparing a semiconductor structure. The method for preparing a semiconductor structure is used to prepare the semiconductor structure in Embodiment 4. The method comprises:

[0123] The present invention provides a method for preparing a semiconductor structure, the preparation method comprising:

[0124] Step B1: Disposing at least one groove on the first surface of the semiconductor layer;

[0125] Step B2: disposing a contrast material layer in the groove, wherein the exposed surface of the contrast material layer is flush with the first surface of the wafer to form a flush surface;

[0126] Step B3: disposing a hard mask layer on the first surface of the semiconductor layer, wherein the hard mask layer covers a flush surface of the contrast material layer and the semiconductor layer;

[0127] Step B4: Patterning the hard mask layer to obtain a first opening and a second opening, wherein the first opening and the second opening penetrate the hard mask layer, the first opening is located above the reference material layer, and the second opening is located above the semiconductor layer where the reference material layer is not set.

[0128] The method for preparing the semiconductor structure of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the method for preparing the semiconductor structure protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0129] First, if Figure 8 As shown, step B1 is performed, and at least one groove is provided on the first surface of the semiconductor layer.

[0130] In one embodiment, the method for forming the groove is as described in Example 2.

[0131] Then, if Fig. 9As shown, step B2 is performed to set a contrast material layer in the groove, and the exposed surface of the contrast material layer is flush with the first surface of the wafer to form a flush surface.

[0132] In one embodiment, the flush surface is obtained by chemical mechanical polishing.

[0133] Then, if Fig.10 As shown, step B3 is performed to dispose a hard mask layer on the first surface of the semiconductor layer, wherein the hard mask layer covers the surface of the contrast material layer and the semiconductor layer that is flush with each other.

[0134] Finally, if Fig.11 As shown, step B4 is performed to graph the hard mask layer to obtain a first opening and a second opening, wherein the first opening and the second opening penetrate the hard mask layer, the first opening is located above the reference material layer, and the second opening is located above the semiconductor layer where the reference material layer is not set.

[0135] In one embodiment, the method of patterning the hard mask layer is dry etching.

[0136] In one embodiment, the method of patterning the hard mask layer is as follows: Fig.12 As shown, a patterned photoresist is disposed on the hard mask layer; the hard mask layer is etched using the photoresist as a mask to obtain a patterned hard mask layer; and the photoresist is removed.

[0137] Embodiment 6:

[0138] This embodiment provides a method for measuring a semiconductor etching rate, the method comprising:

[0139] Step N1: providing a semiconductor structure, wherein the semiconductor structure is the semiconductor structure in Embodiment 2;

[0140] Step N2: etching the reference material layer through the first opening with an etching solution to form a first etching hole, and etching the semiconductor layer through the second opening with an etching solution to form a second etching hole;

[0141] Step N3: measuring the depth X1 of the first etching hole, obtaining the etching time t, and calculating the etching rate V1=X1 / t of the etching solution on the reference material layer;

[0142] Step N4: obtaining an etching rate ratio X between the reference material layer and the semiconductor layer, and calculating an etching rate V2 = V1 / X of the semiconductor layer.

[0143] The semiconductor etching rate measuring method of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the semiconductor etching rate measuring method protected by the present invention, and those skilled in the art may change it according to the actual preparation steps.

[0144] First, step N1 is performed to provide a semiconductor structure. The semiconductor structure is as follows: Figure 7 The semiconductor structure in Example 2 is shown.

[0145] Then, if Fig.13 As shown, step N2 is performed, the etching solution etches the reference material layer through the first opening to form a first etching hole, and the etching solution etches the semiconductor layer through the second opening to form a second etching hole.

[0146] In one embodiment, the etching solution is a mixed solution of hydrofluoric acid and nitric acid.

[0147] Next, step N3 is performed to measure the depth X1 of the first etching hole, obtain the etching time t, and calculate the etching rate V1=X1 / t of the etching solution on the reference material layer.

[0148] Finally, step N4 is performed to obtain the etching rate ratio X between the reference material layer and the semiconductor layer, and the etching rate V2 = V1 / X of the semiconductor layer is calculated.

[0149] In the present invention, the reference material layer and the semiconductor layer are etched through the first opening and the second opening of the hard mask layer, so that the etching area can be effectively controlled, so that the obtained etching depth ratio can more accurately reflect the etching rates of the two compared with the measurement method in Example 3.

[0150] Specifically, the etching rate of the semiconductor layer obtained by the method of the present invention can be used as a calibration value of the etching rate of the semiconductor layer in the process.

[0151] In one embodiment, the etching rate ratio X of the reference material layer to the semiconductor layer is obtained as follows:

[0152] The ratio X of the depth of the first etched hole to the depth of the second etched hole after etching is measured, where X is the ratio of the etching rates of the reference material layer to the semiconductor layer.

[0153] In one embodiment, a method for measuring the depth ratio of the first etched hole to the second etched hole after etching is: slicing the semiconductor structure along a cross section perpendicular to the first surface; respectively measuring the depth of the first etched hole and the depth of the second etched hole obtained by slicing, and calculating the depth ratio X of the first etched hole to the second etched hole.

[0154] The present invention measures the etched depth ratio by slicing, and this method can obtain a more accurate etched depth ratio, but the semiconductor structure after slicing cannot be used a second time, and the measurement cost is relatively high.

[0155] In one embodiment, a method for measuring the ratio of the depth of the first etched hole to the depth of the second etched hole after etching is: emitting detection light to the bottom of the first etched hole and the second etched hole from the height of the first surface; receiving reflection spectra reflected from the bottom of the first etched hole and the second etched hole respectively, and obtaining the depths of the first etched hole and the second etched hole by corresponding analysis of the reflection spectra.

[0156] The present invention obtains the ratio of the etched depth by measuring the reflection spectrum of the etched hole, so that the sample can be used twice, the cost is low and the measurement efficiency is higher.

[0157] Specifically, the material etching in the present invention is isotropic etching, so only the etching thickness is measured here to obtain the etching rate in any direction, but the method of the present invention can also be applied to anisotropic etching methods, as long as the etching depth is measured in the etching direction for measuring the etching rate, which is within the protection scope of this application.

[0158] In summary, the semiconductor structure and its preparation method, and the semiconductor etching rate measurement method of the present invention can obtain a high-precision etching rate ratio of the reference material layer and the semiconductor layer through the semiconductor structure, and obtain the semiconductor etching rate by measuring the etching depth of the reference material layer, so as to obtain a semiconductor etching rate with higher accuracy, and the operation is convenient; at the same time, by setting the material of the hard mask layer, the integrity of the first opening and the second opening during the etching process is guaranteed to further improve the accuracy of the obtained etching rate; in addition, a groove is set through a shallow trench isolation structure to improve the uniformity of the shape and size of the groove; finally, the thickness of the reference material layer is measured by reflective spectroscopy, and the method is simple and easy to operate.

[0159] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0160] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure is used for etching rate measurement, and the semiconductor structure comprises: a semiconductor layer and a reference material layer; the reference material layer is made of a material different from that of the semiconductor layer; The first surface of the semiconductor layer comprises at least one groove, the groove is filled with the contrast material layer, and the surface of the contrast material layer is flush with the surface of the semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor structure also includes a hard mask layer; the hard mask layer is arranged on the first surface of the semiconductor layer, and the hard mask layer covers the surface of the reference material layer and the semiconductor layer; the hard mask layer includes a first opening and a second opening penetrating the hard mask layer, the first opening and the second opening have the same diameter, the reference material layer is exposed below the first opening, and the semiconductor layer in the semiconductor structure where the reference material layer is not provided is exposed below the second opening.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The material of the semiconductor layer is silicon; and / or the material of the reference material layer is silicon dioxide; and / or when a hard mask layer is provided, the material of the hard mask layer is a silicon nitride film doped with silicon carbide.

4. A method for preparing a semiconductor structure, characterized in that: The preparation method is used to prepare the semiconductor structure described in claim 1, and the preparation method comprises: A silicon oxide film is disposed on the first surface of the semiconductor layer, a silicon nitride layer is disposed on the silicon oxide film, a patterned photoresist is disposed on the silicon nitride layer, the silicon nitride layer, the silicon oxide film and the semiconductor layer are etched by the patterned photoresist to obtain a groove on the first surface of the semiconductor layer, and the photoresist is removed; A contrast material layer is disposed in the groove, and the exposed surface of the contrast material layer is flush with the first surface of the wafer to form a flush surface, and the silicon nitride layer and the silicon oxide film are removed.

5. A method for preparing a semiconductor structure, characterized in that: The preparation method is used to prepare the semiconductor structure described in claim 2, and the preparation method comprises: Disposing at least one groove on the first surface of the semiconductor layer; A contrast material layer is disposed in the groove, wherein the exposed surface of the contrast material layer is flush with the first surface of the wafer to form a flush surface; Disposing a hard mask layer on the first surface of the semiconductor layer, the hard mask layer covering a flush surface of the contrast material layer and the semiconductor layer; The hard mask layer is patterned to obtain a first opening and a second opening, wherein the first opening and the second opening penetrate the hard mask layer, the first opening is located above the contrast material layer, and the second opening is located above the semiconductor layer where the contrast material layer is not disposed.

6. A method for measuring a semiconductor etching rate, characterized in that: The measuring method comprises: Providing a semiconductor structure, wherein the semiconductor structure is the semiconductor structure as claimed in claim 1; measuring an original thickness L1 of the reference material layer in the semiconductor structure; The etching solution etches the surfaces of the contrast material layer and the semiconductor layer; The thickness L2 of the reference material layer after etching is measured to obtain the etching time t, and the etching rate V1 of the reference material layer is calculated to be V1=(L1-L2) / t; The etching rate ratio X between the reference material layer and the semiconductor layer is obtained, and the etching rate V2 = V1 / X of the semiconductor layer is calculated.

7. The method for measuring the semiconductor etching rate according to claim 6, characterized in that: The method of obtaining the etching rate ratio X of the reference material layer and the semiconductor layer is: The surface height difference ΔL between the reference material layer and the semiconductor layer after etching is measured, and the etching rate ratio X=(L1-L2) / (L1-L2+ΔL) of the reference material layer to the semiconductor layer is calculated.

8. A method for measuring a semiconductor etching rate, characterized in that: The measuring method comprises: Providing a semiconductor structure, wherein the semiconductor structure is the semiconductor structure as claimed in claim 2; The etching solution etches the contrast material layer through the first opening to form a first etching hole, and the etching solution etches the semiconductor layer through the second opening to form a second etching hole; The depth X1 of the first etching hole is measured, the etching time t is obtained, and the etching rate V1=X1 / t of the etching solution on the reference material layer is calculated; The etching rate ratio X between the reference material layer and the semiconductor layer is obtained, and the etching rate V2 = V1 / X of the semiconductor layer is calculated.

9. The method for measuring the semiconductor etching rate according to claim 8, characterized in that: The method of obtaining the etching rate ratio X of the reference material layer and the semiconductor layer is: The ratio X of the depth of the first etched hole to the depth of the second etched hole after etching is measured, where X is the ratio of the etching rates of the reference material layer to the semiconductor layer.

10. The method for measuring the semiconductor etching rate according to claim 8, characterized in that: The method for measuring the ratio of the depth of the first etched hole to the depth of the second etched hole after etching is: slicing the semiconductor structure along a cross section perpendicular to the first surface; Respectively measuring the depth of the first etched hole and the depth of the second etched hole obtained by slicing, and calculating a depth ratio X between the first etched hole and the second etched hole; Or the method for measuring the ratio of the depth of the first etched hole to the depth of the second etched hole after etching is: irradiating the bottom of the first etched hole and the second etched hole with a detection light from the height of the first surface; Reflection spectra reflected from the bottom of the first etched hole and the second etched hole are received respectively, and the depths of the first etched hole and the second etched hole are obtained by corresponding analysis of the reflection spectra.

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