Device test structure and test method

Abstract

The invention discloses a device testing structure and a testing method, the device testing structure comprises at least three testing substructures, each testing substructure comprises a first metal line with a repeated turning shape, and in other second testing substructures except for one first testing substructure in the testing substructures, the first metal line is provided with a first metal line with a repeated turning shape, and the second metal line is provided with a second metal line with a repeated turning shape. A plurality of isolated metal patterns distributed along the single side or double sides of the first metal lines according to different first densities are further arranged, and whether gap defects caused by temperature fluctuation of the preparation process of the dielectric layer on the first metal lines exist or not is judged by performing resistance detection on the first metal lines in the test sub-structures. According to the method, the fluctuation of the process temperature can be better observed, the risk can be predicted in advance, the occurrence risk of the gap defect can be reasonably evaluated, and the stability of the dielectric layer preparation process can be effectively monitored.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit technology, and in particular to a device testing structure and a testing method. Background Art

[0002] With the iteration of chip technology, the requirements for integrated circuit manufacturing processes are increasing. Due to the long manufacturing cycle and high manufacturing cost of integrated circuits, it is particularly important to improve the quality of the manufacturing process and the efficiency of testing. In the process of integrated circuit manufacturing, the industry usually arranges the chip electrical test (WAT) structure on the cutting path around each integrated circuit chip on the wafer, and tests the WAT structure after manufacturing is completed to monitor the corresponding manufacturing process. If the WAT structure is subjected to various tests such as electrical testing after wafer manufacturing is completed, and it is found that the WAT structure has failures such as short circuits, open circuits or leakage, then the cause of the failure can be confirmed by performing failure analysis on the WAT structure, so that the process can be adjusted and improved accordingly.

[0003] In the existing BCD (Bipolar-CMOS-DMOS, bipolar transistor-complementary metal oxide semiconductor-double diffused metal oxide semiconductor) process, a high-density plasma deposition process is usually used to prepare fluorine-doped silicon glass as a metal interlayer dielectric layer. Due to the influence of high temperature fluctuations during deposition, when the local temperature is too high, the Ti material and the Al material in the metal plate line composition (including TiN / Ti layer, AlCu layer and TiN / Ti layer) often react to form compounds, resulting in gaps in the corners of the side walls of the metal lines. As a result, during electrical testing, the overall volume of the electrode metal is reduced, resulting in an increase in the square resistance of the metal, which poses a reliability risk to the product.

[0004] Metal electrical testing is a basic method for testing the reliability of integrated circuit manufacturing processes. However, for BCD products, the existing metal sheet resistance test structure cannot eliminate the influence of metal plate line thickness and key dimension fluctuations, so it is impossible to accurately detect the presence of the above-mentioned metal void defects based on the fluctuation of sheet resistance values.

[0005] Therefore, it is necessary to provide a new WAT test structure to solve the above problems existing in the prior art. Summary of the invention

[0006] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and to provide a device testing structure and a testing method.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] The present invention provides a device testing structure, comprising:

[0009] at least three test substructures disposed on the substrate and located in the dielectric layer;

[0010] Each of the test substructures comprises a first metal line having a repeated turning shape, and each of the second test substructures other than one of the first test substructures among the test substructures is further provided with a plurality of isolated metal patterns distributed along one side or both sides of the first metal line at different first densities;

[0011] By performing resistance detection on the first metal lines in each of the test substructures, it is determined whether there are gap defects on the first metal lines caused by temperature fluctuations in the preparation process of the dielectric layer.

[0012] Furthermore, the first metal line includes a plurality of first conductive film layers of different materials, and the metal pattern is used to weaken the heat dissipation performance of the area where the second test substructure is located, so as to induce a chemical reaction between metal elements in the materials of at least two adjacent first conductive film layers in the first metal line in the second test substructure at a high temperature during the preparation of the dielectric layer, and generate the void defect, so that the resistance detection value increases suddenly, so as to monitor the stability of the dielectric layer preparation process by the number of the test substructures that generate the void defects; wherein, the ability of the metal pattern to weaken the heat dissipation performance is proportional to the first density of the metal pattern distributed in the second test substructure.

[0013] Furthermore, among the materials of the at least two adjacent first conductive film layers, the material of one includes Ti element, and the material of the other includes Al.

[0014] Furthermore, the dielectric layer includes a front dielectric layer and a metal interlayer dielectric layer which are sequentially arranged on the substrate, the test substructure is protruding on the surface of the front dielectric layer, and the metal interlayer dielectric layer completely covers the test substructure, and by performing resistance detection on the first metal line in each of the test substructures, it is determined whether there is the gap defect on the first metal line caused by temperature fluctuations in the preparation process of the metal interlayer dielectric layer.

[0015] Furthermore, the test substructure also includes two second metal lines, which are in a forked-finger shape. The two second metal lines are arranged on both sides of the first metal line, and their respective forked fingers extend into the concave area of ​​the repeated turning shape of the first metal line. The metal pattern is located within the test structure area surrounded by the first metal line and the second metal line.

[0016] Furthermore, the second metal line includes a plurality of second conductive film layers made of different materials, and the material of each of the second conductive film layers in the second metal line corresponds to the material of each of the first conductive film layers in the first metal line.

[0017] Furthermore, the repeated turning shape includes a rectangular repeated turning shape or a serpentine bending shape.

[0018] Furthermore, the test substructures are isolated from each other, and two ends of the first metal line of each test substructure are respectively connected to a resistance test Pad.

[0019] Furthermore, both ends of the first metal line of each test substructure are respectively connected to a resistance test Pad, and the test substructures are connected in series in sequence through the Pad at one end of each first metal line, and the connection ends of the first metal lines of two adjacent test substructures share the same Pad.

[0020] Further, a ratio of the sum of the areas of the first metal line, the second metal line and the metal pattern to the area of ​​the test structure region is defined as a second density for mapping the first density, and the range of the second density is 51-99%.

[0021] The present invention also provides a testing method based on the above device testing structure, comprising:

[0022] Performing resistance detection on the first metal lines in each test substructure respectively, and obtaining corresponding first resistance detection values;

[0023] Calculate the difference between each of the first resistance detection values ​​and the reference resistance value to obtain each first resistance difference;

[0024] Each of the first resistance differences is compared with a threshold value, and when the difference exceeds a threshold value, it is determined that a gap defect exists on the first metal line of the corresponding test substructure.

[0025] Furthermore, before performing resistance detection on the first metal lines in each of the test substructures, firstly, performing overall resistance detection on the first metal lines of each of the test substructures connected in series in sequence to obtain a second resistance detection value, performing a difference calculation between the second resistance detection value and the reference resistance value to obtain a second resistance difference, and comparing the second resistance difference with the threshold value; when it exceeds the threshold value, performing resistance detection on the first metal lines in each of the test substructures to obtain corresponding first resistance detection values, performing a difference calculation between the first resistance detection values ​​and the reference resistance value to obtain the first resistance difference, and comparing the first resistance difference with the threshold value; when it exceeds the threshold value, it is determined that there is a gap defect on the first metal line of the corresponding test substructure.

[0026] Furthermore, it also includes: establishing a resistance difference control chart for separately collecting the first resistance differences obtained from test structures on different wafers, and setting a control limit as a threshold in the resistance difference control chart to trigger an alarm when the first resistance difference exceeds the control limit.

[0027] Furthermore, the reference resistance value is determined by collecting the third resistance detection value of the first metal line of the first test substructure of the test structure on different wafers when no void defect occurs, and calculating the average value to obtain the average resistance value, and the threshold value is determined by collecting the fourth resistance detection value of the first metal line of the first test substructure of the test structure on different wafers when a void defect occurs, and calculating the difference between each of the fourth resistance detection values ​​and the average value of the third resistance detection value, and obtaining the average value of at least 5 minimum values ​​of each fourth resistance difference.

[0028] Furthermore, it also includes: evaluating the risk of void defects occurring on the chip based on the number of the test substructures with void defects, so as to monitor the stability of the dielectric layer preparation process, wherein the stability of the dielectric layer preparation process is inversely proportional to the number of the test substructures with void defects.

[0029] Furthermore, the method further includes: testing a breakdown voltage between a first metal line and a second metal line of the first test substructure.

[0030] As can be seen from the above technical scheme, the present invention sets at least three test substructures with first metal lines, and respectively adds metal patterns distributed at different densities (first densities) in each of the other second test substructures other than one first test substructure, so as to weaken the heat dissipation performance of the area where the second test substructure is located to different degrees according to the characteristic that the density of the metal pattern is negatively correlated with the heat dissipation. When high temperature fluctuation occurs during the preparation of the dielectric layer, the metal pattern can be used to induce the first metal line in the second test substructure to generate a void defect. In this way, when performing metal electrical testing, the number of test substructures generating void defects can be effectively detected according to the principle that as the density of the metal pattern in the test substructure increases, the probability of the first metal line in the test substructure generating a void defect will also increase, so that the resistance detection value will also increase accordingly. The influence level of the temperature fluctuation of the dielectric layer preparation process on the reliability of the product (chip) can be judged accordingly. Therefore, the fluctuation of the process temperature can be better observed, the risk can be predicted in advance under the premise that the product is not affected, and the risk of the occurrence of the void defect actually caused by the process temperature fluctuation on the product can be reasonably evaluated in time, thereby realizing effective monitoring of the stability of the dielectric layer preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A schematic diagram of an existing test structure.

[0032] Figure 2-Figure 3 A schematic diagram of a device testing structure according to a preferred embodiment of the present invention.

[0033] Figure 4-Figure 5 The present invention is a flowchart of a testing method for a device testing structure according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0035] refer to Figure 1An existing test structure is arranged on a cutting path around a chip on a wafer, and the test structure includes a first metal line 1 in a serpentine shape, and two second metal lines 2 in a forked shape, and the two ends of the first metal line 1 are respectively connected to the first Pad 3 (pad) and the second Pad 4, one end of one second metal line 2 is connected to the first Pad, and the other end of the second metal line 2 is connected to the third Pad 5. The test structure is used to test the square resistance of the first metal line 1 through the first Pad 3 and the second Pad 4, and to test the breakdown voltage between the first metal line 1 and the second metal line 2 through the first Pad 3 and the third Pad 5.

[0036] Since the sizes of the first metal lines 1 in the test structures on different wafers are not consistent during production, for BCD products, when the first metal line 1 (metal plate line) in the test structure on a certain wafer undergoes normal size fluctuations during production, the existing metal block resistance test structure will not be able to eliminate the impact of the first metal line 1 thickness and key size fluctuations on the block resistance value, so it is impossible to accurately determine whether a corresponding gap defect has occurred on the first metal line 1 based on the detected block resistance value fluctuations. Therefore, when troubleshooting anomalies, it is usually necessary to first check whether the thickness and key size of the first metal line 1 are abnormal, and this process consumes a relatively long time.

[0037] In order to solve the above problems, the present invention provides a device test structure and a test method. The present invention sets at least three test substructures with first metal lines, and respectively adds metal patterns distributed at different densities (first densities) in each second test substructure other than one first test substructure, so as to weaken the heat dissipation performance of the area where the second test substructure is located to different degrees according to the characteristic that the density of the metal pattern is negatively correlated with the heat dissipation. When high temperature fluctuations occur during the preparation of the dielectric layer (metal interlayer dielectric layer), the metal pattern can be used to induce the first metal line in the second test substructure to produce a gap defect. In this way, when performing metal electrical property testing, the number of test substructures that produce gap defects can be effectively detected based on the principle that as the density of the metal pattern in the test substructure increases, the probability of the first metal line in the test substructure producing a gap defect will also increase, so that the resistance detection value will also increase accordingly. Based on this, it is possible to determine the level of impact of temperature fluctuations in the dielectric layer preparation process on product (chip) reliability. Therefore, the fluctuations in process temperature can be better observed, and risks can be predicted in advance without affecting the product. This allows for a timely and reasonable assessment of the risk of void defects actually caused by process temperature fluctuations in the product, thereby achieving effective monitoring of the stability of the dielectric layer preparation process.

[0038] The specific implementation modes of the present invention are further described in detail below in conjunction with the accompanying drawings.

[0039] refer to Figure 2 A device testing structure of the present invention includes at least three testing substructures 10 .

[0040] Each test substructure 10 is arranged on the surface of the substrate and is located in the dielectric layer. Each test substructure 10 includes a first metal line 101 with a repeated turning shape. Among them, each test substructure 10 includes a first test substructure 11 and a plurality of second test substructures 12. The difference between the second test substructure 12 and the first test substructure 11 is that in each second test substructure 12, in addition to the first metal line 101, a plurality of dummy metal patterns 102 are also respectively provided. In addition, the metal pattern 102 is arranged along one side or both sides of the first metal line 101, and the first density of the metal patterns 102 distributed in different second test substructures 12 is different. At the same time, the metal pattern 102 is an isolated metal pattern 102, that is, the metal pattern 102 is insulated and isolated from all metal lines in the second test substructure 12 including the first metal line 101.

[0041] The device test structure of the present invention is used to determine whether there is a gap defect on the first metal line 101 caused by temperature fluctuation in the preparation process of the dielectric layer by performing resistance detection on the first metal line 101 in each test substructure 10 (the first test substructure 11 and the second test substructure 12).

[0042] refer to Figure 2 In some embodiments, the first metal line 101 includes a plurality of first conductive film layers of different materials. The metal pattern 102 is used to weaken the heat dissipation performance of the area where the second test substructure 12 is located, so as to induce a chemical reaction between the metal elements in the materials of at least two adjacent first conductive film layers of the first metal line 101 of the second test substructure 12 at a high temperature during the preparation of the dielectric layer, and generate a gap defect. In this way, when the resistance (for example, the sheet resistance) is detected, the volume of the first metal line 101 is reduced due to the generation of the compound, so that the resistance detection value increases suddenly correspondingly, and it can be determined that there is a gap on the first metal line 101 of the second test substructure 12 where the resistance detection value increases suddenly (of course, if the temperature fluctuates and the temperature is too high to a certain extent, the first metal line 101 of the first test substructure 11 may also generate a gap, and the resistance detection value of the first metal line 101 can be detected to increase suddenly accordingly). Therefore, the stability of the dielectric layer preparation process can be monitored by the number of test substructures 10 that generate gap defects.

[0043] Among them, the ability of the metal pattern 102 to weaken the heat dissipation performance is proportional to the distribution density of the metal pattern 102 in the second test substructure 12. That is, under the same process temperature fluctuation range, the higher the distribution density of the metal pattern 102, the lower the heat dissipation performance of the first metal line 101 of the second test substructure 12, and the more likely it is to produce gaps. It can be understood that since the metal pattern 102 is not added to the first test substructure 11, the heat dissipation performance of the first metal line 101 of the first test substructure 11 will be higher than the heat dissipation performance of the first metal line 101 of each second test substructure 12, and under the same temperature conditions, the probability of generating gaps is also the smallest. Therefore, by utilizing the different probabilities of generating voids in each second test substructure 12 having metal patterns 102 with different first densities, which are all greater than those of the first test substructure 11, the temperature fluctuation in the dielectric layer preparation process can be better observed. When it is determined through resistance detection that a void is generated on the second test substructure 12, it can serve as an early warning before the void defect actually occurs in the chip on the wafer, thereby significantly reducing the reliability risk of the chip and fully ensuring the safe production of the chip.

[0044] In some embodiments, among the materials of at least two adjacent first conductive film layers in the first metal line 101 , the material of one includes Ti element, and the material of the other includes Al.

[0045] Taking the BCD product as an example, the first metal line 101 is used as a metal plate, and its composition from top to bottom includes a TiN / Ti layer, an AlCu layer and a TiN / Ti layer. The dielectric layer includes a front dielectric layer disposed on the surface of the substrate, and a metal interlayer dielectric layer disposed on the front dielectric layer, and the material of the metal interlayer dielectric layer is generally fluorine-doped silicon glass. The first metal line 101 (test substructure 10) is protruding on the surface of the front dielectric layer and is completely covered by the metal interlayer dielectric layer, so it is located in the metal interlayer dielectric layer, that is, in the entire dielectric layer including the front dielectric layer and the metal interlayer dielectric layer. Due to the influence of the process temperature fluctuation when the fluorine-doped silicon glass used as the metal interlayer dielectric layer is deposited by high-density plasma, when the local temperature is too high, the Ti element in the first metal line 101 often reacts with the Al element to form a compound, resulting in a gap problem at the corner position of the side wall of the first metal line 101. Therefore, when performing electrical testing, the overall volume of the first metal line 101 is reduced, resulting in an increase in the detected square resistance. Through the novel device testing structure of the present invention, it is possible to accurately judge whether there may be gaps by detecting the square resistance of the first metal line 101 of each test substructure 10, so that the reliability risk of the chip product can be controlled to the minimum.

[0046] In some embodiments, taking the device test structure of the present invention as an example of the lowest metal plate (M1) corresponding to the BCD product, the dielectric layer includes a front dielectric layer and a metal interlayer dielectric layer located above the front dielectric layer, and the test substructure 10 is protruding on the surface of the front dielectric layer and located in the metal interlayer dielectric layer. After each test substructure 10 is prepared on the surface of the front dielectric layer, and the metal interlayer dielectric layer covering each test substructure 10 is continuously deposited on the front dielectric layer, the resistance of the first metal line 101 in each test substructure 10 is detected to determine whether there is a gap defect on the first metal line 101 caused by the temperature fluctuation of the preparation process of the metal interlayer dielectric layer.

[0047] refer to Figure 2 In some embodiments, the test substructure 10 further includes two second metal lines 103. The second metal lines 103 are in the shape of interdigitated fingers, and the two second metal lines 103 are disposed on both sides of the first metal line 101, and their interdigitated fingers extend into the concave region of the repeated turning shape of the first metal line 101. The metal pattern 102 is located within the test structure region surrounded by the first metal line 101 and the second metal line 103. No metal pattern 102 is disposed outside the test structure region.

[0048] In some embodiments, the second metal line 103 includes a plurality of second conductive film layers of different materials, and the material of each second conductive film layer in the second metal line 103 corresponds to the material of each first conductive film layer in the first metal line 101. For example, in a BCD product, the material composition of the second metal line 103 is consistent with that of the first metal line 101, and it also includes a TiN / Ti layer, an AlCu layer, and a TiN / Ti layer from top to bottom. Since the material composition of the second metal line 103 is consistent with that of the first metal line 101, it is no longer necessary to test the square resistance of the second metal line 103.

[0049] In some embodiments, the repeated turning shape of the first metal line 101 includes a rectangular repeated turning shape, such as Figure 2 As shown, both ends of the first metal line 101 are led out from the ends of the rectangular repeated turning shapes located on the outermost two sides.

[0050] In some other embodiments, the repeated turning shape of the first metal line includes a serpentine bending shape, or other shapes consistent with a corresponding structure in the chip.

[0051] In some embodiments, each test substructure 10 is isolated from each other and disposed in a dielectric layer, and both ends of the first metal line 101 of each test substructure 10 are respectively connected to a first Pad 104 and a second Pad 105 for resistance testing. The first metal line 101 of each test substructure 10 is independently tested for resistance through the first Pad 104 and the second Pad 105 at both ends of the first metal line 101 of each test substructure 10.

[0052] refer to Figure 3 In some embodiments, the two ends of the first metal line 101 of each test substructure 10 are respectively connected to a Pad, and the test substructures 10 are connected in series through the Pads at one end of their first metal lines 101, and the connection ends of the first metal lines 101 of two adjacent test substructures 10 share the same Pad. For example, two ends of the first metal line 101 of the first test substructure 11 are connected to a fourth Pad 107 and a fifth Pad 108 respectively, one end of the first metal line 101 of the first second test substructure 12 closest to the first test substructure 11 is connected to the fifth Pad 108, that is, the first test substructure 11 shares the same fifth Pad 108, and the other end of the first metal line 101 of the first second test substructure 12 is connected to a sixth Pad 109, and so on, one end of the first metal line 101 of the Nth second test substructure 12 farthest from the first test substructure 11 is connected to the (N+4)th Pad, that is, the first test substructure 12 shares the same (N+4)th Pad (shown as sharing the sixth Pad 109 in the figure), and the other end of the first metal line 101 of the Nth second test substructure 12 is connected to the (N+5)th Pad 110. N is a positive integer not less than 2. In this way, a new metal square resistance test structure is formed. The fourth Pad 107 and the (N+5)th Pad 110 can be used to perform overall resistance detection on all first metal lines 101 connected in series in the test structure; or, through the Pads at both ends of the first metal line 101 of each test substructure 10, individual resistance detection can be performed on the first metal line 101 of each test substructure 10. Figure 2 Embodiment: This embodiment saves the occupied area of ​​the Pad to a certain extent.

[0053] In this way, the resistance detection process of the device test structure of the present invention can be simplified. If no voids are generated, the resistance detection value of all the first metal lines 101 between the fourth Pad 107 and the (N+5)th Pad 110 will be a relatively fixed value; if voids are generated, the overall resistance detection value of all the first metal lines 101 between the fourth Pad 107 and the (N+5)th Pad 110 will be significantly increased. At this time, by further testing the resistance of the first metal line 101 between the fourth Pad 107 and the fifth Pad 108, or / and the resistance of the first metal line 101 between the fifth Pad 108 and the sixth Pad 109, or / and the resistance of the first metal line 101 up to the (N+4)th Pad and the (N+5)th Pad 110, the hot spot position can be found. According to the first density of the metal pattern 102 in the test substructure 10 where the hot spot position is located, the process stability of the high-temperature deposition process of the metal interlayer dielectric layer can be monitored by evaluating the risk of the occurrence of voids. In large-scale production, using the device testing structure in this embodiment can significantly save electrical testing time.

[0054] In some embodiments, the ratio of the sum of the areas of the first metal line 101, the second metal line 103, and the metal pattern 102 to the area of ​​the test structure area is defined as the second density, which is used to reflect the area ratio of all metal structures in the test structure area, and the first density is mapped with the second density. Since the areas of the first metal line 101 and the second metal line 103 are fixed values, when the number of metal patterns 102 distributed in the second test substructure 12 increases, the second density and the first density will also increase accordingly.

[0055] It is worth noting that, since the metal pattern 102 is not provided in the first test substructure 11 , it is equivalent to that the first density of the metal pattern 102 in the first test substructure 11 is zero.

[0056] In some embodiments, the second density ranges from 51% to 99%. In this embodiment, the first test substructure 11 is not provided with the metal pattern 102, the second density is 51.6%, the second density of the first second test substructure 12 is 60%, the second density of the Nth second test substructure 12 is 99%, and the second density of the other second test substructures 12 between the first second test substructure 12 and the Nth second test substructure 12 is between 60% and 99%. However, this example is only an example.

[0057] In some embodiments, in order to prevent the addition of the metal pattern 102 from affecting the size of the first metal line 101 during fabrication, optical proximity correction (OPC) may be used to ensure that the size of the first metal line 101 meets the requirements of the design rules.

[0058] In some embodiments, the shape of the metal pattern 102 is not limited. For example, the metal pattern 102 may include a polygon (rectangle), a circle, an ellipse, a bar, a ring, a turning shape, a curve shape, an irregular shape, etc.

[0059] In some embodiments, the line width of the metal pattern 102 is the same as or different from the line width of the first metal line 101 .

[0060] In some embodiments, the metal patterns 102 are evenly distributed in the second test substructure 12 .

[0061] The following further describes in detail a testing method for a device testing structure of the present invention through specific implementation modes and in conjunction with the accompanying drawings.

[0062] In some embodiments, a device test structure test method of the present invention uses the above-mentioned Figure 2 or Figure 3 A device test structure implementation of the present invention is shown.

[0063] refer to Figure 4 and Figure 2 In some embodiments, a device test structure testing method of the present invention includes:

[0064] First, resistance detection is performed on the first metal lines 101 in each test substructure 10 (the first test substructure 11 and each second test substructure 12 ) to obtain corresponding first resistance detection values.

[0065] Then, the difference between each first resistance detection value and the reference resistance value is calculated to obtain each first resistance difference.

[0066] Finally, each first resistance difference is compared with a threshold value. When the first resistance difference (one or more) exceeds the threshold value, it is determined that a void defect exists on the first metal line 101 of the test substructure 10 corresponding to the first resistance difference exceeding the tolerance. On the contrary, when the first resistance difference does not exceed the threshold value (0), it is determined that no void defect exists on the first metal line 101 of all the test substructures 10.

[0067] refer to Figure 5 and Figure 3 In some embodiments, a device test structure testing method of the present invention includes:

[0068] First, the first metal lines 101 of the test substructures 10 connected in series are subjected to an overall resistance detection to obtain a second resistance detection value.

[0069] Then, a difference is calculated between the second resistance detection value and the reference resistance value to obtain a second resistance difference.

[0070] Next, the second resistance difference is compared with a threshold value. When the second resistance difference does not exceed the threshold value, it is determined that there is no gap defect on the first metal line 101 connected in series.

[0071] On the contrary, when the second resistance difference exceeds the threshold, it is determined that there is a gap defect on the first metal line 101 connected in series. At this time, the resistance detection of the first metal line 101 in each test substructure 10 is continued, and each first resistance detection value is obtained accordingly. Then, the difference between each first resistance detection value and the reference resistance value is calculated to obtain each first resistance difference. Finally, each first resistance difference is compared with the threshold again. When the first resistance difference exceeding the threshold is found, it is determined that there is a gap defect on the first metal line 101 of the corresponding test substructure 10. In this way, the hot spot position can be accurately checked. According to the first density of the metal pattern 102 in the test substructure 10 where the hot spot position is located (actually according to the second density), the process stability of the high-temperature deposition process of the metal interlayer dielectric layer can be monitored by judging the risk of the occurrence of gaps. Therefore, when the temperature fluctuation of the metal interlayer dielectric layer deposition process is small, the electrical test time can be significantly saved.

[0072] In some embodiments, a resistance difference control chart is further included to collect the first resistance differences obtained from the test structures on each wafer, monitor the magnitude of the first resistance differences by setting a control limit as a threshold in the resistance difference control chart, and set a trigger alarm when the first resistance difference exceeds the control limit.

[0073] In some embodiments, the reference resistance value is determined by collecting third resistance detection values ​​of the first metal line 101 of the first test substructure 11 of the test structures on different wafers without void defects and performing average value calculation to obtain a resistance average value.

[0074] In some embodiments, the threshold is determined by collecting the fourth resistance detection value of the first metal line 101 of the first test substructure 11 of the test structure on different wafers when a void defect occurs, and calculating the difference between each fourth resistance detection value and the average value of the third resistance detection value, and obtaining the average value of at least 5 minimum values ​​of each fourth resistance difference.

[0075] In some embodiments, the risk of void defects occurring on the wafer chips is evaluated based on the number of the test substructures 10 with void defects, so as to monitor the stability of the dielectric layer preparation process. The stability of the dielectric layer preparation process is inversely proportional to the number of the test substructures 10 with void defects.

[0076] Experiments show that the test method of the present invention can locate hot spots more quickly when troubleshooting anomalies. Figure 1 The test structure shown, when troubleshooting abnormalities, usually needs to first check the thickness and line width of the metal lines, and this process will take a long time. Using the test method of the present invention, the influence of the above dimensions can be directly eliminated from the resistance value detection data. At the same time, the test method of the present invention has higher accuracy and can better observe the fluctuations in the process, so that the risk can be predicted in advance before the chip is actually affected by the temperature, and it plays a role in timely reminding of abnormal process fluctuations. For example, when the temperature difference suddenly fluctuates by 10°C compared to the temperature reference value, the first test substructure 11 used as a comparison with the second test substructure 12 may not have a significant change in the resistance detection value, but if a sudden change in the resistance detection value occurs in the second test substructure 12, a reminder can be issued to the control system in advance so that targeted preventive measures can be taken. Of course, the chip quality at this time is still in a safe state, thus ensuring the stability of large-scale production.

[0077] In some embodiments, the breakdown voltage between the first metal line 101 and the second metal line 103 of the first test substructure 11 is tested. Figure 2 For example, one end of a second metal line 103 located on the left side of the first metal line 101 in the figure is also connected to the first Pad 104, and one end of another second metal line 103 located on the right side of the first metal line 101 is connected to the third Pad 106. The breakdown voltage between the first metal line 101 and the second metal line 103 can be tested through the first Pad 104 and the third Pad 106.

[0078] In summary, the present invention uses the above-mentioned device test structure to perform resistance electrical testing, so as to determine the level of influence of temperature fluctuations in the dielectric layer preparation process on chip reliability, better observe fluctuations in process temperature, predict risks in advance without affecting the product, and timely and reasonably evaluate the risk of occurrence of void defects actually caused by process temperature fluctuations in the product, thereby achieving effective monitoring of the stability of the dielectric layer preparation process.

[0079] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A device testing structure, characterized in that: include: at least three test substructures disposed on the substrate and located in the dielectric layer; Each of the test substructures comprises a first metal line having a repeated turning shape, and each of the second test substructures other than one of the first test substructures among the test substructures is further provided with a plurality of isolated metal patterns distributed along one side or both sides of the first metal line at different first densities; By performing resistance detection on the first metal lines in each of the test substructures, it is determined whether there are gap defects on the first metal lines caused by temperature fluctuations in the preparation process of the dielectric layer.

2. The device test structure according to claim 1, characterized in that: The first metal line includes a plurality of first conductive film layers of different materials, and the metal pattern is used to weaken the heat dissipation performance of the area where the second test substructure is located, so as to induce a chemical reaction between metal elements in the materials of at least two adjacent first conductive film layers in the first metal line in the second test substructure at a high temperature during the preparation of the dielectric layer, and generate the void defect, so that the resistance detection value increases suddenly, so as to monitor the stability of the dielectric layer preparation process by the number of the test substructures that generate the void defect; wherein, the ability of the metal pattern to weaken the heat dissipation performance is proportional to the first density of the metal pattern distributed in the second test substructure.

3. The device test structure according to claim 2, characterized in that: Among the materials of the at least two adjacent first conductive film layers, the material of one includes Ti element, and the material of the other includes Al.

4. The device test structure according to claim 2, characterized in that: The dielectric layer includes a front dielectric layer and an intermetallic dielectric layer which are sequentially arranged on the substrate, the test substructure is protruding on the surface of the front dielectric layer, and the intermetallic dielectric layer completely covers the test substructure. By performing resistance detection on the first metal line in each of the test substructures, it is determined whether there is a gap defect on the first metal line caused by temperature fluctuations in the preparation process of the intermetallic dielectric layer.

5. The device test structure according to claim 2, characterized in that: The test substructure also includes two second metal lines, which are in a forked-finger shape. The two second metal lines are arranged on both sides of the first metal line, and their respective forked fingers extend into the concave area of ​​the repeated turning shape of the first metal line. The metal pattern is located within the test structure area surrounded by the first metal line and the second metal line.

6. The device test structure according to claim 5, characterized in that: The second metal line includes a plurality of second conductive film layers made of different materials, and the material of each of the second conductive film layers in the second metal line corresponds to the material of each of the first conductive film layers in the first metal line.

7. The device testing structure according to claim 1, characterized in that: The repeated turning shape includes a rectangular repeated turning shape or a serpentine bending shape.

8. The device testing structure according to claim 1, characterized in that: The test substructures are isolated from each other, and two ends of the first metal line of each test substructure are respectively connected to a resistance test Pad.

9. The device testing structure according to claim 1, characterized in that: Both ends of the first metal line of each test substructure are connected to a resistance test Pad respectively, and the test substructures are connected in series in sequence through the Pad at one end of each first metal line, and the connection ends of the first metal lines of two adjacent test substructures share the same Pad.

10. The device testing structure according to claim 5, characterized in that: The ratio of the sum of the areas of the first metal line, the second metal line and the metal pattern to the area of ​​the test structure region is defined as a second density for mapping the first density, and the range of the second density is 51-99%.

11. A testing method based on the device testing structure according to any one of claims 1 to 10, comprising: Performing resistance detection on the first metal lines in each test substructure respectively, and obtaining corresponding first resistance detection values; Calculate the difference between each of the first resistance detection values ​​and the reference resistance value to obtain each first resistance difference; Each of the first resistance differences is compared with a threshold value, and when the difference exceeds a threshold value, it is determined that a gap defect exists on the first metal line of the corresponding test substructure.

12. The testing method according to claim 11, characterized in that: Before performing resistance detection on the first metal lines in each of the test substructures, first perform overall resistance detection on the first metal lines of each of the test substructures connected in series to obtain a second resistance detection value, perform difference calculation between the second resistance detection value and the reference resistance value to obtain a second resistance difference, compare the second resistance difference with the threshold value, and when it exceeds the threshold value, perform resistance detection on the first metal lines in each of the test substructures to obtain corresponding first resistance detection values, perform difference calculation between the first resistance detection values ​​and the reference resistance value to obtain the first resistance difference, compare the first resistance difference with the threshold value, and when it exceeds the threshold value, determine that there is a gap defect on the first metal line of the corresponding test substructure.

13. The testing method according to claim 11 or 12, characterized in that: Also includes: A resistance difference control chart is established to collect the first resistance differences obtained from the test structures on different wafers respectively, and a control limit as a threshold is set in the resistance difference control chart to trigger an alarm when the first resistance difference exceeds the control limit.

14. The testing method according to claim 11 or 12, characterized in that: The reference resistance value is determined by collecting the third resistance detection values ​​of the first metal lines of the first test substructures of the test structures on different wafers when no void defects occur, and calculating the average value to obtain the average resistance value. The threshold value is determined by collecting the fourth resistance detection values ​​of the first metal lines of the first test substructures of the test structures on different wafers when a void defect occurs, and calculating the difference between each of the fourth resistance detection values ​​and the average value of the third resistance detection values, to obtain the average value of at least 5 minimum values ​​of each fourth resistance difference.

15. The testing method according to claim 13, characterized in that: Also includes: Based on the number of the test substructures with void defects, the risk of void defects occurring on the chip is evaluated, so as to monitor the stability of the dielectric layer preparation process, wherein the stability of the dielectric layer preparation process is inversely proportional to the number of the test substructures with void defects.

16. The testing method according to claim 11, characterized in that: Also includes: A breakdown voltage between a first metal line and a second metal line of the first test substructure is tested.

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