ASK (Amplitude Shift Keying) modulation circuit, method and chip for wireless charging receiving end

Abstract

The invention provides an ASK modulation circuit, method and chip for a wireless charging receiving end, the circuit comprises a logic control circuit and a rectification circuit, the rectification circuit comprises a first rectification branch and a second rectification branch, the first rectification branch comprises a first power tube and a fourth power tube, and the second rectification branch comprises a second power tube and a third power tube; in a modulation mode, the logic control circuit controls the fourth power tube or the first power tube to be switched from the first state to the second state after a first preset duration in the process that the first rectification branch is switched from the first state to the second state; and in the process that the first rectification branch is switched from the second state to the first state, the second power tube or the third power tube is controlled to be switched from the first state to the second state after a second preset duration, the first state is the on state, and the second state is the off state. The power tube is controlled to be turned off in a delayed mode, off-chip capacitance, on-chip switch tubes and chip pins are reduced, and meanwhile the ASK modulation effect is not affected.

Description

Technical Field

[0001] The present application relates to the field of wireless charging technology, and in particular to an ASK modulation circuit, method and chip for a wireless charging receiving end. Background Art

[0002] In a wireless charging system, it usually includes a wireless charging transmitter and a wireless charging receiver. Figure 1 and Figure 2 In the related technology of wireless charging system, the capacitors C1-C6 are usually connected or connected between the nodes AC1_1 and AC2_1 by controlling the switch tubes S1-S6. Through the capacitance modulation, the current waveforms of the receiving end and the transmitting end are affected, so that the peak voltage of VCOIL changes, and the amplitude shift keying (ASK) modulation function is realized. Summary of the invention

[0003] The present application provides an ASK modulation circuit, method and chip for a wireless charging receiving end, which can reduce or remove off-chip capacitors, on-chip switch tubes and chip pins without affecting the ASK modulation effect.

[0004] In a first aspect, the present application provides an ASK modulation circuit for a wireless charging receiving end, the circuit comprising: a logic control circuit and a rectifier circuit, the rectifier circuit comprising a first power tube, a second power tube, a third power tube and a fourth power tube, the first power tube is connected in series with the second power tube, the third power tube is connected in series with the fourth power tube, the first power tube and the second power tube are connected in parallel with the third power tube and the fourth power tube, the rectifier circuit comprises a first rectifier branch and a second rectifier branch, wherein the first rectifier branch comprises the first power tube and the fourth power tube, and the second rectifier branch comprises the second power tube and the third power tube;

[0005] A logic control circuit is used to control, in a modulation mode, during the process of switching the first rectifier branch from the first state to the second state, the fourth power tube or the first power tube to switch from the first state to the second state after a first preset time period; during the process of switching the first rectifier branch from the second state to the first state, the second power tube or the third power tube to switch from the first state to the second state after a second preset time period, wherein the first state is an on state and the second state is an off state.

[0006] In the modulation mode, the power tube is controlled to delay shutdown during the state switching of the rectifier branch, forming a short current loop, causing the current of the receiving coil to change, which in turn causes the current of the transmitting coil and the VCOIL peak voltage to change, thereby realizing the ASK modulation function. It can reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0007] In one possible design, the logic control circuit is specifically used to, in the modulation mode, control the fourth power tube or the first power tube to switch from the first state to the second state when the second power tube or the third power tube switches from the second state to the first state during the process of the first rectifier branch switching from the first state to the first state; and control the second power tube or the third power tube to switch from the first state to the second state when the fourth power tube or the first power tube switches from the second state to the first state during the process of the first rectifier branch switching from the second state to the first state.

[0008] In one possible design, the logic control circuit is specifically used to, in the modulation mode, when the first rectifier branch is switching from the first state to the second state, when the current of the fourth power tube or the first power tube passes through zero, control the fourth power tube or the first power tube to switch from the first state to the second state after a first preset time period; when the first rectifier branch is switching from the second state to the first state, when the current of the second power tube or the third power tube passes through zero, control the second power tube or the third power tube to switch from the first state to the second state after a second preset time period.

[0009] In a possible design, the logic control circuit is further used to control the first rectifying branch and the second rectifying branch to switch between the first state and the second state in the unmodulated mode.

[0010] In one possible design, the logic control circuit is specifically used to control the first rectifier branch or the second rectifier branch to switch from the second state to the first state in an unmodulated mode when it is detected that the body diodes of the first power tube and the fourth power tube or the third power tube and the second power tube are turned on; and control the first rectifier branch or the second rectifier branch to switch from the first state to the second state when it is detected that the current of the first power tube and the fourth power tube or the third power tube and the second power tube passes through zero.

[0011] In a second aspect, the present application provides an ASK modulation method for a wireless charging receiving end, which is applied to the ASK modulation circuit for a wireless charging receiving end in the first aspect above, and the method includes:

[0012] In the modulation mode, during the process of the first rectifying branch switching from the first state to the second state, the fourth power tube or the first power tube is controlled to switch from the first state to the second state after a first preset time period;

[0013] During the process of the first rectifying branch switching from the second state to the first state, the second power tube or the third power tube is controlled to switch from the first state to the second state after a second preset time, wherein the first state is the on state and the second state is the off state.

[0014] In a possible design, the method includes: in a modulation mode, during a process in which a first rectifier branch switches from a first state to a second state, when a second power tube or a third power tube switches from a second state to a first state, controlling a fourth power tube or a first power tube to switch from a first state to a second state;

[0015] During the process of the first rectifying branch switching from the second state to the first state, when the fourth power tube or the first power tube switches from the second state to the first state, the second power tube or the third power tube is controlled to switch from the first state to the second state.

[0016] In a possible design, the method includes: in the modulation mode, during the process of switching the first rectifier branch from the first state to the second state, when the current of the fourth power tube or the first power tube passes through zero, controlling the fourth power tube or the first power tube to switch from the first state to the second state after a first preset time period;

[0017] During the process of the first rectifying branch switching from the second state to the first state, when the current of the second power tube or the third power tube passes through zero, the second power tube or the third power tube is controlled to switch from the first state to the second state after a second preset time.

[0018] In a third aspect, the present application provides a chip, which includes the ASK modulation circuit for a wireless charging receiving end in the first aspect.

[0019] In a fourth aspect, the present application provides an electronic device, which includes the chip in the fourth aspect above.

[0020] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 An ASK modulation circuit provided in the related art;

[0022] Figure 2 A waveform diagram of an ASK modulation circuit provided in the related art;

[0023] Figure 3 An ASK modulation circuit for a wireless charging receiving end provided in an embodiment of the present application;

[0024] Figure 4 A circuit control schematic diagram provided for Embodiment 1 of the present application;

[0025] Figure 5 A timing diagram provided for Embodiment 1 of the present application;

[0026] Figure 6 A logic control circuit provided in Embodiment 1 of the present application;

[0027] Figure 7 A circuit control schematic diagram provided for Embodiment 2 of the present application;

[0028] Figure 8 A timing diagram provided for Embodiment 2 of the present application;

[0029] Fig. 9 A logic control circuit provided in Embodiment 2 of the present application;

[0030] Fig.10 A circuit control schematic diagram provided for Embodiment 3 of the present application;

[0031] Fig.11 A logic control circuit provided in Embodiment 3 of the present application;

[0032] Fig.12 A circuit control schematic diagram provided for Embodiment 4 of the present application;

[0033] Fig.13 A logic control circuit provided in Embodiment 4 of the present application;

[0034] Fig.14 An ASK modulation method for a wireless charging receiving end is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0036] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0037] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] See also Figure 1 In the related technology of wireless charging system, by controlling the switch tubes S1-S6, the capacitors C1-C6 are connected or connected between the nodes AC1_1 and AC2_1, and the current waveforms of the receiving end and the transmitting end are affected by the capacitor modulation, so that the peak voltage of VCOIL changes, see Figure 2 , realize ASK modulation function.

[0039] See also Figure 1 At the receiving end, the rectifier circuit includes a first transistor Q1_1, a second transistor Q2_1, a third transistor Q3_1 and a fourth transistor Q4_1, the first rectifier branch includes Q1_1 and Q4_1, and the second rectifier branch includes Q2_1 and Q3_1. At different phases of the AC signal, the first rectifier branch or the second rectifier branch is controlled to be turned on, and the AC signal induced by the receiving end coil is converted into a DC signal VRECT through the rectifier circuit.

[0040] Capacitors C1-C6 are off-chip capacitors, which are connected to the outside of the ASK modulation chip by the user during use. Switch tubes S1-S6 are on-chip switch tubes, which are set inside the ASK modulation chip. It is necessary to set corresponding chip pins in the ASK modulation chip to connect the off-chip capacitors to the outside of the ASK modulation chip to realize the ASK modulation function.

[0041] For the specific waveform diagram of the ASK modulation process, see Figure 2 , by detecting the voltage values ​​of AC1_1 and AC2_1 and the current flowing through the receiving end coil, the switching states of Q1_1, Q2_1, Q3_1, and Q4_1 are controlled.

[0042] In order to ensure the effect of ASK modulation, the related technology usually needs to use multiple off-chip capacitors, on-chip switches and chip pins, which increases the area of ​​the ASK modulation chip and the cost of the overall circuit. If the area of ​​the ASK modulation chip is reduced and the cost of the overall circuit is reduced by reducing the number of off-chip capacitors, on-chip switches and chip pins, the ASK modulation effect in some application scenarios will be poor.

[0043] In view of the shortcomings in the related art, the embodiments of the present application provide an ASK modulation circuit, method, chip and electronic device for a wireless charging receiving end, which can reduce or remove off-chip capacitors, on-chip switching tubes and chip pins without affecting the ASK modulation effect.

[0044] Among them, the ASK modulation circuit used for the wireless charging receiving end can be a chip or a circuit module.

[0045] Among them, the ASK modulation circuit used for the wireless charging receiving end can be integrated in the same chip or in different chips, and the embodiment of the present application does not make specific limitations on this.

[0046] In the present application, electronic devices may include, but are not limited to: smartphones with wireless charging function, smart watches, wireless headphones, and electric toothbrushes.

[0047] See also Figure 3 The embodiment of the present application provides an ASK modulation circuit 1000 for a wireless charging receiving end. The circuit may include a logic control circuit 100 and a rectifier circuit 200. The rectifier circuit 200 includes a first power tube Q1, a second power tube Q2, a third power tube Q3 and a fourth power tube Q4. The first power tube Q1 is connected in series with the second power tube Q2, the third power tube Q3 is connected in series with the fourth power tube Q4, the first power tube Q1 and the second power tube Q2 are connected in parallel with the third power tube Q3 and the fourth power tube Q4, and the rectifier circuit 200 includes a first rectifier branch 201 and a second rectifier branch 202, wherein the first rectifier branch 201 includes the first power tube Q1 and the fourth power tube Q4, and the second rectifier branch 202 includes the second power tube Q2 and the third power tube Q3.

[0048] The logic control circuit 100 is used for, in the modulation mode, controlling the fourth power tube Q4 or the first power tube Q1 to switch from the first state to the second state after a first preset time period when the first rectifying branch switches from the first state to the second state; and controlling the second power tube Q2 or the third power tube Q3 to switch from the first state to the second state after a second preset time period when the first rectifying branch switches from the second state to the first state, wherein the first state is an on state and the second state is an off state.

[0049] The rectifier circuit 200 includes a first rectifier branch 201 and a second rectifier branch 202, a node AC1 is between Q1 and Q2, and a node AC2 is between Q3 and Q4. By controlling the first rectifier branch (Q1, Q4) and the second rectifier branch (Q3, Q2) to be turned on alternately, the AC signal induced by the receiving end coil is converted into a DC signal VRECT. Normally, the power tubes (Q1, Q4) in the first rectifier branch are turned on or off at the same time, and the power tubes (Q3, Q2) in the second rectifier branch are turned on or off at the same time.

[0050] In the modulation mode, the related technology uses capacitor modulation to affect the current waveform of the receiving end and the transmitting end by connecting or disconnecting the capacitor C1-C6 between the node AC1_1 and the node AC2_1, so that the VCOIL peak voltage changes, and ASK modulation is realized. However, the present application uses a logic control circuit to adjust the timing of the power tubes Q1 to Q4 in the rectifier circuit, so that Q1 and Q4 are not turned on or off at the same time, and Q3 and Q2 are not turned on or off at the same time, thereby affecting the current waveform of the receiving end and the transmitting end, and realizing ASK modulation.

[0051] Specifically, in the modulation mode, the logic control circuit controls Q4 or Q1 to switch from the on state to the off state after a first preset time period when the first rectifier branch (Q1, Q4) switches from the on state to the off state; controls Q2 or Q3 to switch from the on state to the off state after a second preset time period when the first rectifier branch (Q1, Q4) switches from the off state to the on state. That is, by controlling the power tube to delay shutoff during the rectifier branch state switching process, a short current loop is formed, so that the current of the receiving end coil changes, and then causes the current of the transmitting end coil to change, thereby realizing the ASK modulation function.

[0052] The first preset time length and the second preset time length can be set as needed. In an example, the first preset time length and the second preset time length can be tens of nanoseconds (ns).

[0053] In the embodiment of the present application, in the modulation mode, the power tube is controlled to be turned off delayed during the state switching of the rectifier branch, forming a short current loop, so that the current of the receiving coil changes, and then the current of the transmitting coil changes, thereby realizing the ASK modulation function. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0054] In a possible embodiment, the logic control circuit controls the first rectifying branch and the second rectifying branch to switch between a first state and a second state in the unmodulated mode.

[0055] Specifically, in the unmodulated mode, the logic control circuit controls the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) to switch between the on state and the off state, and converts the AC signal sensed by the receiving end coil into a DC signal.

[0056] In a possible embodiment, in the unmodulated mode, when the logic control circuit detects that the body diodes of the first power tube and the fourth power tube or the third power tube and the second power tube are turned on, the first rectifier branch or the second rectifier branch is controlled to switch from the second state to the first state; when the current of the first power tube and the fourth power tube or the third power tube and the second power tube is detected to pass through zero, the first rectifier branch or the second rectifier branch is controlled to switch from the first state to the second state.

[0057] Specifically, the logic control circuit detects AC1 and AC2 in the unmodulated mode, and when it detects that the body diodes of Q1 and Q4 or Q3 and Q2 are turned on, controls the power tube corresponding to the first rectifier branch or the second rectifier branch to be turned on; when it detects that the current of Q1 and Q4 or Q3 and Q2 passes through zero, controls the power tube corresponding to the first rectifier branch or the second rectifier branch to be turned off. Those skilled in the art can understand that the state of the power tube is detected by detecting the voltage values ​​of nodes AC1 and AC2, which will not be described in detail here.

[0058] In a possible embodiment, in the modulation mode, the logic control circuit controls the fourth power tube Q4 or the first power tube Q1 to switch from the on state to the off state when the second power tube Q2 or the third power tube Q3 switches from the off state to the on state during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state; and controls the second power tube Q2 or the third power tube Q3 to switch from the on state to the off state when the fourth power tube Q4 or the first power tube Q1 switches from the off state to the on state during the process of the first rectifier branch (Q1, Q4) switching from the off state to the on state.

[0059] The embodiments of the present application may include two specific embodiments.

[0060] Embodiment 1:

[0061] See also Figure 4 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0062] See also Figure 4, in the modulation mode (Q2 / Q4 modulation), during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state, when Q2 in the second rectifier branch (Q3, Q2) switches from the off state to the on state, Q4 in the first rectifier branch (Q1, Q4) is controlled to switch from the on state to the off state; during the process of the first rectifier branch (Q1, Q4) switching from the off state to the on state, when Q4 in the first rectifier branch (Q1, Q4) switches from the off state to the on state, Q2 in the second rectifier branch (Q3, Q2) is controlled to switch from the on state to the off state. That is, during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state, when it is detected that Q2 is turned on, Q4 is turned off, so that Q4 is delayed to turn off (that is, it is turned off after the first preset time length). During this period, Q2, Q4 and the coil form a short current loop, see Figure 4 (a1) in the circuit makes the current loop not pass through the load, and Figure 4 Compared with the loop (a) in FIG. 1 , the load impedance in the current loop of the receiving end coil is greatly reduced in a short time, so that the current of the receiving end coil changes, which in turn causes the current of the transmitting end coil to change, thereby realizing the ASK modulation function; when the first rectifier branch (Q1, Q4) switches from the off state to the on state, when it is detected that Q4 is turned on, Q2 is turned off, so that Q2 is turned off with a delayed turn-off (i.e., turned off after a second preset time). During this period, Q2, Q4 and the coil form a short current loop, see Figure 4 (b1) in the circuit makes the current loop not pass through the load, and Figure 4 Compared with the (b) loop in the figure, the load impedance in the current loop of the receiving coil is greatly reduced in a short time, causing the current of the receiving coil to change, which in turn causes the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0063] The first embodiment is to modulate Q2 and Q4 to realize the ASK modulation function. Specifically, by detecting the conduction state of the body diodes of the power tubes Q2 and Q4, the power tubes Q4 and Q2 are turned off in a delayed manner, and Q2, Q4 and the coil are introduced to form a short current loop to realize the ASK modulation function. Figure 4 , that is, (a1) and (b1) are added between (a) and (b) to realize the ASK modulation function.

[0064] It should be noted that Figure 4 In (a1), when Q2 is about to turn on, the current will first flow through the parasitic capacitance of Q2 and form a current loop with Q4, and then flow through the channel of Q2 and form a current loop with Q4 at the moment Q2 is turned on; Figure 4In (b1), when Q4 is about to be turned on, the current will first flow through the parasitic capacitance of Q4 and form a current loop with Q2, and then flow through the channel of Q4 and form a current loop with Q2 at the moment Q4 is turned on.

[0065] The timing diagram of the modulation mode and the unmodulation mode in the first embodiment can be found in Figure 5 , in the unmodulated mode, the timing of Q1~Q4 is: when the body diodes of Q1~Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on; when the current flowing through the power tubes Q1~Q4 is detected to be zero-crossing, the corresponding power tubes are controlled to be turned off. In the modulated mode, the timing of Q1 and Q3 is: when the body diodes of Q1 and Q3 are detected to be turned on, Q1 and Q3 are controlled to be turned on; when the current flowing through Q1 and Q3 is detected to be zero-crossing, Q1 and Q3 are controlled to be turned off; the timing of Q2 is: when the body diode of Q2 is detected to be turned on, Q2 is controlled to be turned on; when the body diode of Q4 is detected to be turned on, Q2 is controlled to be turned off; the timing of Q4 is: when the body diode of Q4 is detected to be turned on, Q4 is controlled to be turned on; when the body diode of Q2 is detected to be turned on, Q4 is controlled to be turned off. It can be understood that, Figure 5 The high level in the Q1~Q4 timing corresponds to the on state, and the low level corresponds to the off state.

[0066] For the first embodiment, the present application provides a logic control circuit 100, see Figure 6 The circuit 100 includes: a first comparator A1, a second comparator A2, a third comparator A3, a fourth comparator A4, a fifth comparator A5, a sixth comparator A6, a seventh comparator A7, an eighth comparator A8, a first NOR gate B1, a second NOR gate B2, a third NOR gate B3, a fourth NOR gate B4, a fifth NOR gate B5, a sixth NOR gate B6, a seventh NOR gate B7, an eighth NOR gate B8, a first NOR gate D1, a second NOR gate D2, a first NAND gate E1, a second NAND gate E2, a third NAND gate E3, a fourth NAND gate E4, a fifth NAND gate E5, and a sixth NAND gate E6.

[0067] A positive terminal of the first comparator A1 is electrically connected to -300mV, a negative terminal of the first comparator A1 is electrically connected to AC1, and an output terminal of the first comparator A1 is electrically connected to a first input terminal of the first NOR gate B1.

[0068] The positive terminal of the second comparator A2 is electrically connected to AC1, the negative terminal of the second comparator A2 is electrically connected to 0mV, and the output terminal of the second comparator A2 is electrically connected to the second input terminal of the second NOR gate B2.

[0069] The positive terminal of the third comparator A3 is electrically connected to -300mV, the negative terminal of the third comparator A3 is electrically connected to AC2, and the output terminal of the third comparator A3 is electrically connected to the first input terminal of the third NOR gate B3.

[0070] A positive terminal of the fourth comparator A4 is electrically connected to -300 mV, a negative terminal of the fourth comparator A4 is electrically connected to AC1, and an output terminal of the fourth comparator A4 is electrically connected to a second input terminal of a fourth NOR gate B4.

[0071] The second input terminal of the first NOR gate B1 is electrically connected to the output terminal of the second NOR gate B2 and the first input terminal of the first NAND gate E1 respectively, and the output terminal of the first NOR gate B1 is electrically connected to the first input terminal of the second NOR gate B2.

[0072] The second input terminal of the third NOR gate B3 is electrically connected to the output terminal of the fourth NOR gate B4. The output terminal of the third NOR gate B3 is electrically connected to the first input terminal of the fourth NOR gate B4 and the second input terminal of the second NAND gate E2.

[0073] The input end of the first NOT gate D1 is electrically connected to the first modulation enable signal EN_DEMOD_1 and the first input end of the second NAND gate E2 , respectively. The output end of the first NOT gate D1 is electrically connected to the second input end of the first NAND gate E1 .

[0074] The output end of the first NAND gate E1 is electrically connected to the first input end of the third NAND gate E3, the output end of the second NAND gate E2 is electrically connected to the second input end of the third NAND gate E3, and the output end of the third NAND gate E3 serves as the control signal end S-Q2 of Q2.

[0075] A positive terminal of the fifth comparator A5 is electrically connected to -300 mV, a negative terminal of the fifth comparator A5 is electrically connected to AC2, and an output terminal of the fifth comparator A5 is electrically connected to a first input terminal of a fifth NOR gate B5.

[0076] A positive terminal of the sixth comparator A6 is electrically connected to AC2, a negative terminal of the sixth comparator A6 is electrically connected to 0mV, and an output terminal of the sixth comparator A6 is electrically connected to a second input terminal of the sixth NOR gate B6.

[0077] A positive terminal of the seventh comparator A7 is electrically connected to -300 mV, a negative terminal of the seventh comparator A7 is electrically connected to AC1, and an output terminal of the seventh comparator A7 is electrically connected to a first input terminal of a seventh NOR gate B7.

[0078] The positive terminal of the eighth comparator A8 is electrically connected to -300mV, the negative terminal of the eighth comparator A8 is electrically connected to AC2, and the output terminal of the eighth comparator A8 is electrically connected to the second input terminal of the eighth NOR gate B8.

[0079] The second input terminal of the fifth NOR gate B5 is electrically connected to the output terminal of the sixth NOR gate B6 and the first input terminal of the fourth NAND gate E4 respectively, and the output terminal of the fifth NOR gate B5 is electrically connected to the first input terminal of the sixth NOR gate B6.

[0080] The second input terminal of the seventh NOR gate B7 is electrically connected to the output terminal of the eighth NOR gate B8. The output terminal of the seventh NOR gate B7 is electrically connected to the first input terminal of the eighth NOR gate B8 and the second input terminal of the fifth NAND gate E5.

[0081] The input end of the second NOT gate D2 is electrically connected to the second modulation enable signal EN_DEMOD_2 and the first input end of the fifth NAND gate E5 respectively, and the output end of the second NOT gate D2 is electrically connected to the second input end of the fourth NAND gate E4.

[0082] The output end of the fourth NAND gate E4 is electrically connected to the first input end of the sixth NAND gate E6. The output end of the fifth NAND gate E5 is electrically connected to the second input end of the sixth NAND gate E6. The output end of the sixth NAND gate E6 serves as the control signal end S-Q4 of Q4.

[0083] In the first embodiment, the first modulation enable signal EN_DEMOD_1 and the second modulation enable signal EN_DEMOD_2 in the logic control circuit are used to select the modulation mode and the unmodulated mode. The control signals of Q2 and Q4 are output through the logic control circuit to control the timing of Q2 and Q4, so that Q2 and Q4 are delayed to turn off to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0084] Embodiment 2:

[0085] See also Figure 7 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0086] See also Figure 7 , in the modulation mode (Q1 / Q3 modulation), when the first rectifying branch (Q1, Q4) switches from the on state to the off state, when Q3 in the second rectifying branch (Q3, Q2) switches from the off state to the on state, Q1 in the first rectifying branch (Q1, Q4) is controlled to switch from the on state to the off state; when the first rectifying branch (Q1, Q4) switches from the off state to the on state, when Q1 in the first rectifying branch (Q1, Q4) switches from the off state to the on state, Q3 in the second rectifying branch (Q3, Q2) is controlled to switch from the on state to the off state. That is, when the first rectifying branch (Q1, Q4) switches from the on state to the off state, when it is detected that Q3 is turned on, Q1 is turned off, so that Q1 is turned off with a delay (that is, it is turned off after a first preset time period). During this period, Q1, Q3 and the coil form a short current loop, see Figure 7 (a1) in the circuit makes the current loop not pass through the load, and Figure 7Compared with the loop (a) in FIG. 1 , the load impedance in the current loop of the receiving end coil is greatly reduced in a short time, so that the current of the receiving end coil changes, which in turn causes the current of the transmitting end coil to change, thereby realizing the ASK modulation function; when the first rectifier branch (Q1, Q4) switches from the off state to the on state, when it is detected that Q1 is turned on, Q3 is turned off, so that Q3 is turned off with a delayed turn-off (i.e., turned off after a second preset time). During this period, Q1, Q3 and the coil form a short current loop, see Figure 7 (b1) in the circuit makes the current loop not pass through the load, and Figure 7 Compared with the (b) loop in the figure, the load impedance in the current loop of the receiving coil is greatly reduced in a short time, causing the current of the receiving coil to change, which in turn causes the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0087] The second embodiment is to modulate Q1 and Q3 to realize the ASK modulation function. Specifically, by detecting the conduction state of the body diode of the power tube Q3 and the power tube Q1, the power tube Q1 and the power tube Q3 are turned off in a delayed manner, and Q1, Q3 and the coil are introduced to form a short current loop to realize the ASK modulation function. Figure 7 , that is, (a1) and (b1) are added between (a) and (b) to realize the ASK modulation function.

[0088] It should be noted that Figure 7 In (a1), when Q3 is about to turn on, the current will first flow through the parasitic capacitance of Q3 and form a current loop with Q1, and then flow through the channel of Q3 and form a current loop with Q1 at the moment Q3 is turned on; Figure 7 In (b1), when Q1 is about to be turned on, the current will first flow through the parasitic capacitance of Q1 and form a current loop with Q3, and then flow through the channel of Q1 and form a current loop with Q3 at the moment Q1 is turned on.

[0089] The timing diagram of the modulation mode and the unmodulation mode in the second embodiment can be found in Figure 8 , in the unmodulated mode, the timing of Q1~Q4 is: when the body diodes of Q1~Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on; when the current flowing through the power tubes Q1~Q4 is detected to be zero-crossing, the corresponding power tubes are controlled to be turned off. In the modulated mode, the timing of Q2 and Q4 is: when the body diodes of Q2 and Q4 are detected to be turned on, Q2 and Q4 are controlled to be turned on; when the current flowing through Q2 and Q4 is detected to be zero-crossing, Q2 and Q4 are controlled to be turned off; the timing of Q1 is: when the body diode of Q1 is detected to be turned on, Q1 is controlled to be turned on; when the body diode of Q3 is detected to be turned on, Q1 is controlled to be turned off; the timing of Q3 is: when the body diode of Q3 is detected to be turned on, Q3 is controlled to be turned on; when the body diode of Q1 is detected to be turned on, Q3 is controlled to be turned off. It can be understood that, Figure 8 The high level in the Q1~Q4 timing corresponds to the on state, and the low level corresponds to the off state.

[0090] For the second embodiment, the present application provides a logic control circuit 100, see Fig. 9 The circuit 100 includes: a ninth comparator A9, a tenth comparator A10, an eleventh comparator A11, a twelfth comparator A12, a thirteenth comparator A13, a fourteenth comparator A14, a fifteenth comparator A15, a sixteenth comparator A16, a ninth NOR gate B9, a tenth NOR gate B10, an eleventh NOR gate B11, a twelfth NOR gate B12, a thirteenth NOR gate B13, a fourteenth NOR gate B14, a fifteenth NOR gate B15, a sixteenth NOR gate B16, a third NOR gate D3, a fourth NOR gate D4, a seventh NAND gate E7, an eighth NAND gate E8, a ninth NAND gate E9, a tenth NAND gate E10, an eleventh NAND gate E11, and a twelfth NAND gate E12.

[0091] A positive terminal of the ninth comparator A9 is electrically connected to AC1, a negative terminal of the ninth comparator A9 is electrically connected to VRECT+200mV, and an output terminal of the ninth comparator A9 is electrically connected to a first input terminal of a ninth NOR gate B9.

[0092] A positive terminal of the tenth comparator A10 is electrically connected to VRECT, a negative terminal of the tenth comparator A10 is electrically connected to AC1, and an output terminal of the tenth comparator A10 is electrically connected to a second input terminal of a tenth NOR gate B10.

[0093] A positive terminal of the eleventh comparator A11 is electrically connected to AC1, a negative terminal of the eleventh comparator A11 is electrically connected to VRECT+200mV, and an output terminal of the eleventh comparator A11 is electrically connected to a first input terminal of an eleventh NOR gate B11.

[0094] A positive terminal of the twelfth comparator A12 is electrically connected to AC2, a negative terminal of the twelfth comparator A12 is electrically connected to VRECT+200mV, and an output terminal of the twelfth comparator A12 is electrically connected to a second input terminal of the twelfth NOR gate B12.

[0095] The second input terminal of the ninth NOR gate B9 is electrically connected to the output terminal of the tenth NOR gate B10 and the first input terminal of the seventh NAND gate E7 respectively, and the output terminal of the ninth NOR gate B9 is electrically connected to the first input terminal of the tenth NOR gate B10.

[0096] The second input terminal of the eleventh NOR gate B11 is electrically connected to the output terminal of the twelfth NOR gate B12. The output terminal of the eleventh NOR gate B11 is electrically connected to the first input terminal of the twelfth NOR gate B12 and the second input terminal of the eighth NAND gate E8 respectively.

[0097] An input terminal of the third NOT gate D3 is electrically connected to the third modulation enable signal EN_DEMOD_3 and a first input terminal of the eighth NAND gate E8 , respectively. An output terminal of the third NOT gate D3 is electrically connected to a second input terminal of the seventh NAND gate E7 .

[0098] The output end of the seventh NAND gate E7 is electrically connected to the first input end of the ninth NAND gate E9, the output end of the eighth NAND gate E8 is electrically connected to the second input end of the ninth NAND gate E9, and the output end of the ninth NAND gate E9 serves as the control signal end S-Q1 of Q1.

[0099] A positive terminal of the thirteenth comparator A13 is electrically connected to AC2, a negative terminal of the thirteenth comparator A13 is electrically connected to VRECT+200mV, and an output terminal of the thirteenth comparator A13 is electrically connected to a first input terminal of a thirteenth NOR gate B13.

[0100] A positive terminal of the fourteenth comparator A14 is electrically connected to VRECT, a negative terminal of the fourteenth comparator A14 is electrically connected to AC2, and an output terminal of the fourteenth comparator A14 is electrically connected to a second input terminal of a fourteenth NOR gate B14.

[0101] A positive terminal of the fifteenth comparator A15 is electrically connected to AC2, a negative terminal of the fifteenth comparator A15 is electrically connected to VRECT+200mV, and an output terminal of the fifteenth comparator A15 is electrically connected to a first input terminal of a fifteenth NOR gate B15.

[0102] A positive terminal of the sixteenth comparator A16 is electrically connected to AC1, a negative terminal of the sixteenth comparator A16 is electrically connected to VRECT+200mV, and an output terminal of the sixteenth comparator A16 is electrically connected to a second input terminal of a sixteenth NOR gate B16.

[0103] The second input terminal of the thirteenth NOR gate B13 is electrically connected to the output terminal of the fourteenth NOR gate B14 and the first input terminal of the tenth NAND gate E10 respectively. The output terminal of the thirteenth NOR gate B13 is electrically connected to the first input terminal of the fourteenth NOR gate B14.

[0104] The second input terminal of the fifteenth NOR gate B15 is electrically connected to the output terminal of the sixteenth NOR gate B16. The output terminal of the fifteenth NOR gate B15 is electrically connected to the first input terminal of the sixteenth NOR gate B16 and the second input terminal of the eleventh NAND gate E11 respectively.

[0105] An input terminal of the fourth NOT gate D4 is electrically connected to the fourth modulation enable signal EN_DEMOD_4 and a first input terminal of the eleventh NAND gate E11 , respectively. An output terminal of the fourth NOT gate D4 is electrically connected to a second input terminal of the tenth NAND gate E10 .

[0106] The output end of the tenth NAND gate E10 is electrically connected to the first input end of the twelfth NAND gate E12, the output end of the eleventh NAND gate E11 is electrically connected to the second input end of the twelfth NAND gate E12, and the output end of the twelfth NAND gate E12 serves as the control signal end S-Q3 of Q3.

[0107] In the second embodiment, the third modulation enable signal EN_DEMOD_3 and the fourth modulation enable signal EN_DEMOD_4 in the logic control circuit are used to select the modulation mode and the unmodulated mode. The control signals of Q1 and Q3 are output through the logic control circuit to control the timing of Q1 and Q3, so that Q1 and Q3 are delayed to turn off to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0108] In a possible embodiment, in the modulation mode, the logic control circuit controls the fourth power tube Q4 or the first power tube Q1 to switch from the on state to the off state after a first preset time period when the current of the fourth power tube Q4 or the first power tube Q1 passes through zero during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state, and controls the second power tube Q2 or the third power tube Q3 to switch from the on state to the off state after a second preset time period when the current of the second power tube Q2 or the third power tube Q3 passes through zero during the process of the first rectifier branch (Q1, Q4) switching from the off state to the on state.

[0109] The embodiments of the present application may include two specific embodiments.

[0110] Embodiment three:

[0111] See also Fig.10 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0112] See also Fig.10, in the modulation mode (Q2 / Q4 modulation), during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state, when the current of Q4 in the first rectifier branch (Q1, Q4) passes through zero, the first rectifier branch (Q1, Q4) is controlled to switch from the on state to the off state after the first preset time length; during the process of the first rectifier branch (Q1, Q4) switching from the off state to the on state, when the current of Q2 in the second rectifier branch (Q3, Q2) passes through zero, the second rectifier branch (Q3, Q2) is controlled to switch from the on state to the off state after the second preset time length. That is, during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state, when it is detected that the current of Q4 passes through zero, Q4 is delayed to be turned off (that is, it is turned off after the first preset time length). During this period, Q2, Q4 and the coil form a short current loop, see Fig.10 (a1) in the circuit makes the current loop not pass through the load, and Fig.10 Compared with the loop (a) in FIG. 1 , the load impedance in the current loop of the receiving end coil is greatly reduced in a short time, so that the current of the receiving end coil changes, which in turn causes the current of the transmitting end coil to change, thereby realizing the ASK modulation function; when the first rectifier branch (Q1, Q4) is switched from the off state to the on state, when it is detected that the current of Q2 crosses zero, Q2 is turned off with a delay (i.e., it is turned off after a second preset time). During this period, Q2, Q4 and the coil form a short current loop, see Fig.10 (b1) in the circuit makes the current loop not pass through the load, and Fig.10 Compared with the (b) loop in the figure, the load impedance in the current loop of the receiving coil is greatly reduced in a short time, causing the current of the receiving coil to change, which in turn causes the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0113] The third embodiment is to modulate Q2 and Q4 to realize the ASK modulation function. Specifically, by inserting a configurable shutdown delay module at the driver of the circuit, when the current of the power tube Q2 and the power tube Q4 is detected to be zero, the power tube Q2 and the power tube Q4 are shut down in a corresponding manner with a delay, and Q2, Q4 and the coil are introduced to form a short current loop to realize the ASK modulation function. Fig.10 , that is, (a1) and (b1) are added between (a) and (b) to realize the ASK modulation function.

[0114] It should be noted that there are two cases where Q4 is turned off with delay: Q4 can be turned off before Q2 is turned on or after Q2 is turned on. Fig.10As shown in (a1), the current flows through the parasitic capacitance of Q2 and forms a current loop with Q4; when Q4 is turned off after Q2 is turned on, when Q2 is about to be turned on, the current will first flow through the parasitic capacitance of Q2 and form a current loop with Q4, and at the moment Q2 is turned on, it flows through the channel of Q2 and forms a current loop with Q4. The situation of delayed turn-off of Q2 can also be divided into two types. Q2 can be turned off before Q4 is turned on or after Q4 is turned on. When Q2 is turned off before Q4 is turned on, as shown in Fig.10 As shown in (b1), the current flows through the parasitic capacitance of Q4 and forms a current loop with Q2; when Q2 is turned off after Q4 is turned on, when Q4 is about to be turned on, the current will first flow through the parasitic capacitance of Q4 and form a current loop with Q2, and at the moment Q4 is turned on, the current flows through the channel of Q4 and forms a current loop with Q2.

[0115] The timing diagram of the modulation mode and the unmodulation mode in the third embodiment can be found in Figure 5 , in the unmodulated mode, the timing of Q1~Q4 is: when the body diodes of Q1~Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on; when the current flowing through the power tubes Q1~Q4 is detected to be zero-crossing, the corresponding power tubes are controlled to be turned off. In the modulated mode, the timing of Q1 and Q3 is: when the body diodes of Q1 and Q3 are detected to be turned on, Q1 and Q3 are controlled to be turned on; when the current flowing through Q1 and Q3 is detected to be zero-crossing, Q1 and Q3 are controlled to be turned off; the timing of Q2 is: when the body diode of Q2 is detected to be turned on, Q2 is controlled to be turned on; when the current of Q2 is detected to be zero-crossing, Q2 is controlled to be turned off after a first preset time; the timing of Q4 is: when the body diode of Q4 is detected to be turned on, Q4 is controlled to be turned on; when the current of Q4 is detected to be zero-crossing, Q4 is controlled to be turned off after a second preset time. It can be understood that, Figure 5 The high level in the Q1~Q4 timing corresponds to the on state, and the low level corresponds to the off state.

[0116] For the third embodiment, the present application provides a logic control circuit 100, see Fig.11 The circuit 100 includes: a seventeenth comparator A17, an eighteenth comparator A18, a nineteenth comparator A19, a twentieth comparator A20, a seventeenth NOR gate B17, an eighteenth NOR gate B18, a nineteenth NOR gate B19, a twentieth NOR gate B20, a thirteenth NAND gate E13, a fourteenth NAND gate E14, a fifteenth NAND gate E15, a sixteenth NAND gate E16, a seventeenth NAND gate E17, an eighteenth NAND gate E18, a fifth NAND gate D5, a sixth NAND gate D6, a first turn-off delay device F1, and a second turn-off delay device F2.

[0117] A positive terminal of the seventeenth comparator A17 is electrically connected to -300 mV, a negative terminal of the seventeenth comparator A17 is electrically connected to AC1, and an output terminal of the seventeenth comparator A17 is electrically connected to a first input terminal of a seventeenth NOR gate B17.

[0118] A positive terminal of the eighteenth comparator A18 is electrically connected to AC1, a negative terminal of the eighteenth comparator A18 is electrically connected to 0mV, and an output terminal of the eighteenth comparator A18 is electrically connected to a second input terminal of the eighteenth NOR gate B18.

[0119] The second input terminal of the seventeenth NOR gate B17 is electrically connected to the output terminal of the eighteenth NOR gate B18, the second input terminal of the fourteenth NAND gate E14 and the input terminal of the first turn-off delayer F1 respectively, and the output terminal of the seventeenth NOR gate B17 is electrically connected to the first input terminal of the eighteenth NOR gate B18.

[0120] A first input terminal of the thirteenth NAND gate E13 is electrically connected to the output terminal of the first turn-off delayer F1 , and a second input terminal of the thirteenth NAND gate E13 is electrically connected to the fifth modulation enable signal EN_DEMOD_5 and the input terminal of the fifth NOT gate D5 , respectively.

[0121] The output terminal of the fifth NOT gate D5 is electrically connected to the first input terminal of the fourteenth NAND gate E14.

[0122] The output end of the thirteenth NAND gate E13 is electrically connected to the first input end of the fifteenth NAND gate E15, the output end of the fourteenth NAND gate E14 is electrically connected to the second input end of the fifteenth NAND gate E15, and the output end of the fifteenth NAND gate E15 serves as the control signal end S-Q2 of Q2.

[0123] The positive terminal of the nineteenth comparator A19 is electrically connected to -300mV, the negative terminal of the nineteenth comparator A19 is electrically connected to AC2, and the output terminal of the nineteenth comparator A19 is electrically connected to the first input terminal of the nineteenth NOR gate B19.

[0124] A positive terminal of the twentieth comparator A20 is electrically connected to AC2, a negative terminal of the twentieth comparator A20 is electrically connected to 0mV, and an output terminal of the twentieth comparator A20 is electrically connected to a second input terminal of the twentieth NOR gate B20.

[0125] The second input terminal of the nineteenth NOR gate B19 is electrically connected to the output terminal of the twentieth NOR gate B20, the second input terminal of the seventeenth NAND gate E17 and the input terminal of the second turn-off delayer F2 respectively, and the output terminal of the nineteenth NOR gate B19 is electrically connected to the first input terminal of the twentieth NOR gate B20.

[0126] A first input terminal of the sixteenth NAND gate E16 is electrically connected to the output terminal of the second turn-off delayer F2 , and a second input terminal of the sixteenth NAND gate E16 is electrically connected to the sixth modulation enable signal EN_DEMOD_6 and the input terminal of the sixth NOT gate D6 , respectively.

[0127] The output terminal of the sixth NOT gate D6 is electrically connected to the first input terminal of the seventeenth NAND gate E17.

[0128] The output end of the sixteenth NAND gate E16 is electrically connected to the first input end of the eighteenth NAND gate E18, the output end of the seventeenth NAND gate E17 is electrically connected to the second input end of the eighteenth NAND gate E18, and the output end of the eighteenth NAND gate E18 serves as the control signal end S-Q4 of Q4.

[0129] In the third embodiment, the fifth modulation enable signal EN_DEMOD_5 and the sixth modulation enable signal EN_DEMOD_6 in the logic control circuit are used to select the modulation mode and the unmodulated mode. The first turn-off delay F1 and the second turn-off delay F2 delay the turn-off of Q2 and Q4 to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0130] Embodiment 4:

[0131] See also Fig.12 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0132] See also Fig.12 , in the modulation mode (Q1 / Q3 modulation), during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state, when the current of Q1 in the first rectifier branch (Q1, Q4) passes through zero, the Q1 in the first rectifier branch (Q1, Q4) is controlled to switch from the on state to the off state after the first preset time; during the process of the first rectifier branch (Q1, Q4) switching from the off state to the on state, when the current of Q3 in the second rectifier branch (Q3, Q2) passes through zero, the Q3 in the second rectifier branch (Q3, Q2) is controlled to switch from the on state to the off state after the second preset time. That is, during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state, when it is detected that the current of Q1 passes through zero, Q1 is delayed to be turned off (that is, it is turned off after the first preset time). During this period, Q1, Q3 and the coil form a short current loop, see Fig.12 (a1) in the circuit makes the current loop not pass through the load, and Fig.12Compared with the loop (a) in FIG. 1 , the load impedance in the current loop of the receiving end coil is greatly reduced in a short time, so that the current of the receiving end coil changes, which in turn causes the current of the transmitting end coil to change, thereby realizing the ASK modulation function; when the first rectifier branch (Q1, Q4) is switched from the off state to the on state, when it is detected that the current of Q3 crosses zero, Q3 is turned off with a delay (i.e., turned off after a second preset time). During this period, Q1, Q3 and the coil form a short current loop, see Fig.12 (b1) in the circuit makes the current loop not pass through the load, and Fig.12 Compared with the (b) loop in the figure, the load impedance in the current loop of the receiving coil is greatly reduced in a short time, causing the current of the receiving coil to change, which in turn causes the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0133] Embodiment 4 is to modulate Q1 and Q3 to realize the ASK modulation function. Specifically, by inserting a configurable shutdown delay module at the driver of the circuit, when the current of the power tube Q1 and the power tube Q3 is detected to be zero, the power tube Q1 and the power tube Q3 are shut down in a corresponding manner with a delay, and Q1, Q3 and the coil are introduced to form a short current loop to realize the ASK modulation function. Fig.12 , that is, (a1) and (b1) are added between (a) and (b) to realize the ASK modulation function.

[0134] It should be noted that there are two cases where Q1 is turned off with delay: Q1 can be turned off before Q3 is turned on or after Q3 is turned on. Fig.12 As shown in (a1), the current flows through the parasitic capacitance of Q3 and forms a current loop with Q1; when Q1 is turned off after Q3 is turned on, when Q3 is about to be turned on, the current will first flow through the parasitic capacitance of Q3 and form a current loop with Q1, and at the moment Q3 is turned on, it will flow through the channel of Q3 and form a current loop with Q1. The situation of delayed shutdown of Q3 can also be divided into two types. Q3 can be turned off before Q1 is turned on or after Q1 is turned on. When Q3 is turned off before Q1 is turned on, as shown in Fig.12 As shown in (b1), the current flows through the parasitic capacitance of Q1 and forms a current loop with Q3; when Q3 is turned off after Q1 is turned on, when Q1 is about to be turned on, the current will first flow through the parasitic capacitance of Q1 and form a current loop with Q3, and at the moment Q1 is turned on, the current will flow through the channel of Q1 and form a current loop with Q3.

[0135] The timing diagram of the modulation mode and the unmodulation mode in the fourth embodiment can be found in Figure 8, in the unmodulated mode, the timing of Q1~Q4 is: when the body diodes of Q1~Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on; when the current flowing through the power tubes Q1~Q4 is detected to be zero-crossing, the corresponding power tubes are controlled to be turned off. In the modulated mode, the timing of Q2 and Q4 is: when the body diodes of Q2 and Q4 are detected to be turned on, Q2 and Q4 are controlled to be turned on; when the current flowing through Q2 and Q4 is detected to be zero-crossing, Q2 and Q4 are controlled to be turned off; the timing of Q1 is: when the body diode of Q1 is detected to be turned on, Q1 is controlled to be turned on; when the current of Q1 is detected to be zero-crossing, Q1 is controlled to be turned off after a first preset time; the timing of Q3 is: when the body diode of Q3 is detected to be turned on, Q3 is controlled to be turned on; when the current of Q3 is detected to be zero-crossing, Q3 is controlled to be turned off after a second preset time. It can be understood that, Figure 8 The high level in the Q1~Q4 timing corresponds to the on state, and the low level corresponds to the off state.

[0136] For the fourth embodiment, the present application provides a logic control circuit 100, see Fig.13 The circuit 100 includes: a twenty-first comparator A21, a twenty-second comparator A22, a twenty-third comparator A23, a twenty-fourth comparator A24, a twenty-first NOR gate B21, a twenty-second NOR gate B22, a twenty-third NOR gate B23, a twenty-fourth NOR gate B24, a nineteenth NAND gate E19, a twentieth NAND gate E20, a twenty-first NAND gate E21, a twenty-second NAND gate E22, a twenty-third NAND gate E23, a twenty-fourth NAND gate E24, a seventh NAND gate D7, an eighth NAND gate D8, a third turn-off delay device F3, and a fourth turn-off delay device F4.

[0137] A positive terminal of the twenty-first comparator A21 is electrically connected to AC1, a negative terminal of the twenty-first comparator A21 is electrically connected to VRECT+200mV, and an output terminal of the twenty-first comparator A21 is electrically connected to a first input terminal of a twenty-first NOR gate B21.

[0138] A positive terminal of the twenty-second comparator A22 is electrically connected to VRECT, a negative terminal of the twenty-second comparator A22 is electrically connected to AC1, and an output terminal of the twenty-second comparator A22 is electrically connected to a second input terminal of the twenty-second NOR gate B22.

[0139] The second input terminal of the twenty-first NOR gate B21 is electrically connected to the output terminal of the twenty-second NOR gate B22, the second input terminal of the twentieth NAND gate E20 and the input terminal of the third turn-off delayer F3 respectively, and the output terminal of the twenty-first NOR gate B21 is electrically connected to the first input terminal of the twenty-second NOR gate B22.

[0140] A first input terminal of the nineteenth NAND gate E19 is electrically connected to the output terminal of the third turn-off delayer F3 , and a second input terminal of the nineteenth NAND gate E19 is electrically connected to the seventh modulation enable signal EN_DEMOD_7 and the input terminal of the seventh NOT gate D7 , respectively.

[0141] An output terminal of the seventh NOT gate D7 is electrically connected to a first input terminal of the twentieth NAND gate E20.

[0142] The output end of the nineteenth NAND gate E19 is electrically connected to the first input end of the twenty-first NAND gate E21, the output end of the twentieth NAND gate E20 is electrically connected to the second input end of the twenty-first NAND gate E21, and the output end of the twenty-first NAND gate E21 serves as the control signal end S-Q1 of Q1.

[0143] A positive end of the twenty-third comparator A23 is electrically connected to AC2, a negative end of the twenty-third comparator A23 is electrically connected to VRECT+200mV, and an output end of the twenty-third comparator A23 is electrically connected to a first input end of a twenty-third NOR gate B23.

[0144] A positive terminal of the twenty-fourth comparator A24 is electrically connected to VRECT, a negative terminal of the twenty-fourth comparator A24 is electrically connected to AC1, and an output terminal of the twenty-fourth comparator A24 is electrically connected to a second input terminal of a twenty-fourth NOR gate B24.

[0145] The second input terminal of the twenty-third NOR gate B23 is electrically connected to the output terminal of the twenty-fourth NOR gate B24, the second input terminal of the twenty-third NAND gate E23 and the input terminal of the fourth turn-off delayer F4 respectively, and the output terminal of the twenty-third NOR gate B23 is electrically connected to the first input terminal of the twenty-fourth NOR gate B24.

[0146] A first input terminal of the twenty-second NAND gate E22 is electrically connected to the output terminal of the fourth turn-off delayer F4 , and a second input terminal of the twenty-second NAND gate E22 is electrically connected to the eighth modulation enable signal EN_DEMOD_8 and the input terminal of the eighth NOT gate D8 , respectively.

[0147] An output terminal of the eighth NOT gate D8 is electrically connected to a first input terminal of the twenty-third NAND gate E23 .

[0148] The output end of the twenty-second NAND gate E22 is electrically connected to the first input end of the twenty-fourth NAND gate E24, the output end of the twenty-third NAND gate E23 is electrically connected to the second input end of the twenty-fourth NAND gate E24, and the output end of the twenty-fourth NAND gate E24 serves as the control signal end S-Q3 of Q3.

[0149] In the fourth embodiment, the seventh modulation enable signal EN_DEMOD_7 and the eighth modulation enable signal EN_DEMOD_8 in the logic control circuit are used to select the modulation mode and the unmodulated mode. The third turn-off delay F3 and the fourth turn-off delay F4 delay the turn-off of Q1 and Q3 to achieve the purpose of ASK modulation. It is possible to reduce or remove the off-chip capacitor, the on-chip switch tube and the chip pin while not affecting the ASK modulation effect.

[0150] The four embodiments in the present application control the power tube to delay shutdown during the state switching of the rectifier branch to form a short current loop, so that the current of the receiving coil changes, and then causes the current of the transmitting coil to change, thereby realizing the ASK modulation function. In the specific implementation method, embodiment one and embodiment two control the power tube to delay shutdown by detecting the body diode state of the power tube at the symmetrical position in the rectifier circuit; embodiment three and embodiment four control the power tube to delay shutdown by inserting a configurable shutdown delay module at the driver of the circuit, and both can form a short current loop to realize the ASK modulation function. It can reduce or remove off-chip capacitors, on-chip switching tubes, and chip pins without affecting the ASK modulation effect.

[0151] The present application embodiment provides an ASK modulation method for a wireless charging receiving end, see Fig.14 The method is applied to the above-mentioned ASK modulation circuit for the wireless charging receiving end, and the method comprises:

[0152] S1, in the modulation mode, during the process of the first rectifying branch switching from the first state to the second state, the fourth power tube or the first power tube is controlled to switch from the first state to the second state after a first preset time period.

[0153] S2, during the process of the first rectifier branch switching from the second state to the first state, the second power tube or the third power tube is controlled to switch from the first state to the second state after a second preset time period, wherein the first state is the on state and the second state is the off state.

[0154] In a possible implementation, S1 includes: in the modulation mode, when the first rectifier branch switches from the first state to the second state, when the second power tube or the third power tube switches from the second state to the first state, controlling the fourth power tube or the first power tube to switch from the first state to the second state;

[0155] S2 includes: during the process of the first rectifying branch switching from the second state to the first state, when the fourth power tube or the first power tube switches from the second state to the first state, controlling the second power tube or the third power tube to switch from the first state to the second state.

[0156] In a possible implementation, S1 includes: in the modulation mode, when the first rectifier branch switches from the first state to the second state, when the current of the fourth power tube or the first power tube passes through zero, controlling the fourth power tube or the first power tube to switch from the first state to the second state after a first preset time period;

[0157] S2 includes: during the process of switching the first rectifier branch from the second state to the first state, when the current of the second power tube or the third power tube passes through zero, controlling the second power tube or the third power tube to switch from the first state to the second state after a second preset time period.

[0158] An embodiment of the present application provides a chip, including the above-mentioned ASK modulation circuit for a wireless charging receiving end.

[0159] An embodiment of the present application provides an electronic device, comprising the above-mentioned chip.

[0160] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An ASK modulation circuit for a wireless charging receiving end, characterized in that: The circuit comprises: a logic control circuit and a rectifier circuit, the rectifier circuit comprises a first power tube, a second power tube, a third power tube and a fourth power tube, the first power tube is connected in series with the second power tube, the third power tube is connected in series with the fourth power tube, the first power tube and the second power tube are connected in parallel with the third power tube and the fourth power tube, the rectifier circuit comprises a first rectifier branch and a second rectifier branch, wherein the first rectifier branch comprises the first power tube and the fourth power tube, and the second rectifier branch comprises the second power tube and the third power tube; The logic control circuit is used to, in the modulation mode, control the fourth power tube or the first power tube to switch from the first state to the second state after a first preset time period when the first rectifier branch switches from the first state to the second state; and control the second power tube or the third power tube to switch from the first state to the second state after a second preset time period when the first rectifier branch switches from the second state to the first state, wherein the first state is an on state and the second state is an off state.

2. The ASK modulation circuit for a wireless charging receiving end according to claim 1, characterized in that: The logic control circuit is specifically used for controlling the fourth power tube or the first power tube to switch from the first state to the second state when the second power tube or the third power tube switches from the second state to the first state during the process of the first rectifier branch switching from the first state to the second state in the modulation mode; and controlling the second power tube or the third power tube to switch from the first state to the second state when the fourth power tube or the first power tube switches from the second state to the first state during the process of the first rectifier branch switching from the second state to the first state.

3. The ASK modulation circuit for a wireless charging receiving end according to claim 1, characterized in that: The logic control circuit is specifically used for, in the modulation mode, when the first rectifier branch switches from the first state to the second state, when the current of the fourth power tube or the first power tube passes through zero, controlling the fourth power tube or the first power tube to switch from the first state to the second state after a first preset time period; when the first rectifier branch switches from the second state to the first state, when the current of the second power tube or the third power tube passes through zero, controlling the second power tube or the third power tube to switch from the first state to the second state after a second preset time period.

4. The ASK modulation circuit for a wireless charging receiving end according to any one of claims 1 to 3, characterized in that: The logic control circuit is further used to control the first rectifying branch and the second rectifying branch to switch between the first state and the second state in the unmodulated mode.

5. The ASK modulation circuit for a wireless charging receiving end according to claim 4, characterized in that: The logic control circuit is specifically used to control the first rectifier branch or the second rectifier branch to switch from the second state to the first state when it is detected that the body diodes of the first power tube and the fourth power tube or the third power tube and the second power tube are turned on in the unmodulated mode; When it is detected that the current of the first power tube and the fourth power tube or the third power tube and the second power tube passes through zero, the first rectifying branch or the second rectifying branch is controlled to switch from the first state to the second state.

6. An ASK modulation method for a wireless charging receiving end, characterized in that: The method is applied to the ASK modulation circuit for a wireless charging receiving end according to any one of claims 1 to 3, and the method comprises: In the modulation mode, during the process of the first rectifying branch switching from the first state to the second state, the fourth power tube or the first power tube is controlled to switch from the first state to the second state after a first preset time period; During the process of the first rectifier branch switching from the second state to the first state, the second power tube or the third power tube is controlled to switch from the first state to the second state after a second preset time, wherein the first state is the on state and the second state is the off state.

7. The ASK modulation method for a wireless charging receiving end according to claim 6, characterized in that: The method is applied to the ASK modulation circuit for a wireless charging receiving end as claimed in claim 2, and the method comprises: In the modulation mode, when the first rectifier branch switches from the first state to the second state, when the second power tube or the third power tube switches from the second state to the first state, the fourth power tube or the first power tube is controlled to switch from the first state to the second state; During the process of the first rectifying branch switching from the second state to the first state, when the fourth power tube or the first power tube switches from the second state to the first state, the second power tube or the third power tube is controlled to switch from the first state to the second state.

8. The ASK modulation method for a wireless charging receiving end according to claim 6, characterized in that: The method is applied to the ASK modulation circuit for a wireless charging receiving end as claimed in claim 3, and the method comprises: In the modulation mode, when the first rectifier branch switches from the first state to the second state, when the current of the fourth power tube or the first power tube passes through zero, the fourth power tube or the first power tube is controlled to switch from the first state to the second state after a first preset time period; During the process of switching the first rectifier branch from the second state to the first state, when the current of the second power tube or the third power tube passes through zero, the second power tube or the third power tube is controlled to switch from the first state to the second state after a second preset time.

9. A chip, characterized in that: include: An ASK modulation circuit for a wireless charging receiving end as described in any one of claims 1 to 5.

10. An electronic device, characterized in that: include: The chip as claimed in claim 9.

Images