ASK (Amplitude Shift Keying) modulation circuit, method and chip for wireless charging receiving end

Abstract

The invention provides an ASK modulation circuit, method and chip for a wireless charging receiving end, the circuit comprises a logic control circuit and a rectification circuit, and the rectification circuit comprises a first rectification branch and a second rectification branch; the logic control circuit controls the first rectification branch circuit or the second rectification branch circuit to be switched from the first state to the second state after a preset duration in the process that the first rectification branch circuit or the second rectification branch circuit is switched from the first state to the second state in the modulation mode, the first state is the on state, and the second state is the off state. The first rectification branch circuit or the second rectification branch circuit is controlled to be turned off in a delayed manner, so that a transient discharge current loop of the first rectification branch circuit or the second rectification branch circuit to the VRECT is formed, the current of the receiving end coil is changed, then the current of the transmitting end coil is changed, and the ASK modulation function is achieved. According to the invention, off-chip capacitors, on-chip switch tubes and chip pins can be reduced or removed, and the ASK modulation effect is not affected.

Description

Technical Field

[0001] The present application relates to the field of wireless charging technology, and in particular to an ASK modulation circuit, method and chip for a wireless charging receiving end. Background Art

[0002] In a wireless charging system, a wireless charging transmitter and a wireless charging receiver are usually included. For circuit diagrams and waveform diagrams of wireless charging systems in related technologies, see Figure 1 and Figure 2 In a wireless charging system, the capacitors C1-C6 are usually connected or connected between the nodes AC1_1 and AC2_1 by controlling the switch tubes S1-S6. Through capacitor modulation, the current waveforms at the receiving and transmitting ends are affected, so that the peak voltage of VCOIL changes, thereby realizing the amplitude shiftkeying (ASK) modulation function. Summary of the invention

[0003] The present application provides an ASK modulation circuit, method and chip for a wireless charging receiving end, which can reduce or remove off-chip capacitors, on-chip switch tubes and chip pins without affecting the ASK modulation effect.

[0004] In a first aspect, the present application provides an ASK modulation circuit for a wireless charging receiving end, the circuit comprising: a logic control circuit and a rectifier circuit, the rectifier circuit comprising a first power tube, a second power tube, a third power tube and a fourth power tube, the first power tube is connected in series with the second power tube, the third power tube is connected in series with the fourth power tube, the first power tube and the second power tube are connected in parallel with the third power tube and the fourth power tube, the rectifier circuit comprises a first rectifier branch and a second rectifier branch, wherein the first rectifier branch comprises the first power tube and the fourth power tube, and the second rectifier branch comprises the second power tube and the third power tube;

[0005] A logic control circuit is used to control the first rectifier branch or the second rectifier branch to switch from the first state to the second state after a preset time period during the process of switching from the first state to the second state in the modulation mode, wherein the first state is the on state and the second state is the off state.

[0006] In the embodiment of the present application, in the modulation mode, the first rectifier branch or the second rectifier branch is controlled to delay shutting down during the state switching process, so as to form a short discharge current loop of the first rectifier branch or the second rectifier branch to VRECT, so that the current of the receiving end coil changes, and then causes the current of the transmitting end coil to change, thereby realizing the ASK modulation function. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0007] In one possible design, the logic control circuit is specifically used to control the first rectifier branch or the second rectifier branch to switch from the first state to the second state after a preset time period when the current in the first rectifier branch or the second rectifier branch passes through zero in the modulation mode.

[0008] In one possible design, the logic control circuit is specifically used to control the first rectifier branch or the second rectifier branch to switch from the first state to the second state in the modulation mode, when the current of the first rectifier branch or the second rectifier branch is a preset threshold.

[0009] In one possible design, the logic control circuit is specifically used for, in a modulation mode, when the first rectifier branch is switching from a first state to a second state, when the current in the first rectifier branch passes through zero, controlling the first rectifier branch to switch from the first state to the second state after a preset time period; and when the second rectifier branch is switching from a first state to a second state, when the current in the second rectifier branch passes through zero, controlling the second rectifier branch to switch from the first state to the second state after a preset time period.

[0010] In one possible design, the logic control circuit is specifically used to, in a modulation mode, control the first rectifier branch to switch from the first state to the second state when the current of the first rectifier branch is a preset threshold value during the process of switching the first rectifier branch from the first state to the second state; and control the second rectifier branch to switch from the first state to the second state when the current of the second rectifier branch is a preset threshold value during the process of switching the second rectifier branch from the first state to the second state.

[0011] In a possible design, the logic control circuit is further used to control the first rectifying branch and the second rectifying branch to switch between the first state and the second state in the unmodulated mode.

[0012] In a second aspect, the present application provides an ASK modulation method for a wireless charging receiving end, which is applied to the ASK modulation circuit for a wireless charging receiving end in the first aspect above, and the method includes:

[0013] In the modulation mode, when the first rectifier branch or the second rectifier branch switches from the first state to the second state, the first rectifier branch or the second rectifier branch is controlled to switch from the first state to the second state after a preset time period, wherein the first state is the on state and the second state is the off state.

[0014] In one possible design, the method includes: in a modulation mode, when the first rectifier branch or the second rectifier branch is switching from a first state to a second state, when the current in the first rectifier branch or the second rectifier branch passes through zero, controlling the first rectifier branch or the second rectifier branch to switch from the first state to the second state after a preset time period.

[0015] In one possible design, the method includes: in a modulation mode, during the process of switching the first rectifier branch or the second rectifier branch from a first state to a second state, when the current of the first rectifier branch or the second rectifier branch is a preset threshold, controlling the first rectifier branch or the second rectifier branch to switch from the first state to the second state.

[0016] In one possible design, the method includes: in a modulation mode, during the process of switching the first rectifier branch from the first state to the second state, when the current in the first rectifier branch passes through zero, controlling the first rectifier branch to switch from the first state to the second state after a preset time period; during the process of switching the second rectifier branch from the first state to the second state, when the current in the second rectifier branch passes through zero, controlling the second rectifier branch to switch from the first state to the second state after a preset time period.

[0017] In one possible design, the method includes: in a modulation mode, during a process in which a first rectifier branch switches from a first state to a second state, when a current of the first rectifier branch is a preset threshold, controlling the first rectifier branch to switch from the first state to the second state; during a process in which a second rectifier branch switches from a first state to a second state, when a current of the second rectifier branch is a preset threshold, controlling the second rectifier branch to switch from the first state to the second state.

[0018] In one possible design, the method includes: in an unmodulated mode, controlling a first rectifying branch and a second rectifying branch to switch between a first state and a second state.

[0019] In a third aspect, the present application provides a chip, which includes the ASK modulation circuit for a wireless charging receiving end in the first aspect.

[0020] In a fourth aspect, the present application provides an electronic device, which includes the chip in the fourth aspect above.

[0021] The beneficial effects provided in the above-mentioned second aspect and various possible designs of the above-mentioned second aspect can refer to the beneficial effects brought about by the above-mentioned first aspect and various possible implementation methods of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 An ASK modulation circuit provided in the related art;

[0023] Figure 2 A waveform diagram of an ASK modulation circuit provided in the related art;

[0024] Figure 3 An ASK modulation circuit for a wireless charging receiving end provided in an embodiment of the present application;

[0025] Figure 4 A circuit control schematic diagram provided for Embodiment 1 of the present application;

[0026] Figure 5 A logic control circuit provided in Embodiment 1 of the present application;

[0027] Figure 6 A circuit control schematic diagram provided for Embodiment 2 of the present application;

[0028] Figure 7 A logic control circuit provided in Embodiment 2 of the present application;

[0029] Figure 8 A logic control circuit provided in Embodiment 3 of the present application;

[0030] Fig. 9 A logic control circuit provided in Embodiment 4 of the present application;

[0031] Fig.10 A circuit control schematic diagram provided for Embodiment 5 of the present application;

[0032] Fig.11 A logic control circuit provided in Embodiment 5 of the present application;

[0033] Fig.12 A logic control circuit provided in Embodiment 6 of the present application;

[0034] Fig.13 An ASK modulation method for a wireless charging receiving end is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0036] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0037] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] See also Figure 1 In the related technology of wireless charging system, by controlling the switch tubes S1-S6, the capacitors C1-C6 are connected or connected between the node AC1_1 and the node AC2_1, and the current waveforms of the receiving end and the transmitting end are affected by the capacitor modulation, see Figure 2 , which changes the VCOIL peak voltage and realizes the ASK modulation function.

[0039] See also Figure 1 ,like Figure 1As shown, in the receiving end, the rectifier circuit includes a first transistor Q1_1, a second transistor Q2_1, a third transistor Q3_1 and a fourth transistor Q4_1, wherein the first rectifier branch includes Q1_1 and Q4_1, and the second rectifier branch includes Q2_1 and Q3_1. For different phases of the AC signal, the first rectifier branch or the second rectifier branch is controlled to be turned on respectively, and the AC signal induced by the receiving end coil is converted into a DC signal VRECT through the rectifier circuit.

[0040] Capacitors C1-C6 are off-chip capacitors, which are usually connected to the outside of the ASK modulation chip during use; switch tubes S1-S6 are on-chip switch tubes, which are arranged inside the ASK modulation chip. It is necessary to set chip pins corresponding to each on-chip switch tube in the ASK modulation chip to connect the off-chip capacitors to the outside of the ASK modulation chip through the chip pins, thereby realizing the ASK modulation function.

[0041] For the specific waveform diagram of the ASK modulation process, see Figure 2 By detecting the voltage values ​​of nodes AC1_1 and AC2_1 and the current flowing through the receiving coil, the switch states of Q1_1, Q2_1, Q3_1, and Q4_1 are controlled. By controlling the switch tubes S1-S6, the VCOIL peak voltage changes, realizing ASK modulation.

[0042] In order to ensure the effect of ASK modulation, the related technology usually needs to use multiple off-chip capacitors, on-chip switches and chip pins, which increases the area of ​​the ASK modulation chip and the cost of the overall circuit. If the area of ​​the ASK modulation chip is reduced and the cost of the overall circuit is reduced by reducing the number of off-chip capacitors, on-chip switches and chip pins, the ASK modulation effect in some application scenarios will be poor.

[0043] In view of the shortcomings in the related art, the embodiments of the present application provide an ASK modulation circuit, method, chip and electronic device for a wireless charging receiving end, which can reduce or remove off-chip capacitors, on-chip switching tubes and chip pins without affecting the ASK modulation effect.

[0044] Among them, the ASK modulation circuit used for the wireless charging receiving end can be a chip or a circuit module.

[0045] Among them, the ASK modulation circuit used for the wireless charging receiving end can be integrated in the same chip or in different chips, and the embodiment of the present application does not make specific limitations on this.

[0046] In the present application, electronic devices may include, but are not limited to: smartphones with wireless charging function, smart watches, wireless headphones, and electric toothbrushes.

[0047] See also Figure 3 The embodiment of the present application provides an ASK modulation circuit 1000 for a wireless charging receiving end. The circuit may include a logic control circuit 100 and a rectifier circuit 200. The rectifier circuit 200 includes a first power tube Q1, a second power tube Q2, a third power tube Q3 and a fourth power tube Q4. The first power tube Q1 is connected in series with the second power tube Q2, the third power tube Q3 is connected in series with the fourth power tube Q4, the first power tube Q1 and the second power tube Q2 are connected in parallel with the third power tube Q3 and the fourth power tube Q4, and the rectifier circuit 200 includes a first rectifier branch 201 and a second rectifier branch 202, wherein the first rectifier branch 201 includes the first power tube Q1 and the fourth power tube Q4, and the second rectifier branch 202 includes the second power tube Q2 and the third power tube Q3.

[0048] The logic control circuit 100 is used to control the first rectifier branch 201 or the second rectifier branch 202 to switch from the first state to the second state after a preset time period in the modulation mode, wherein the first state is the on state and the second state is the off state.

[0049] like Figure 3 As shown, the rectifier circuit 200 includes a first rectifier branch 201 and a second rectifier branch 202. The first rectifier branch 201 includes Q1 and Q4, and the second rectifier branch 202 includes Q3 and Q2. A node AC1 is between Q1 and Q2, and a node AC2 is between Q3 and Q4. By controlling the first rectifier branch (Q1, Q4) and the second rectifier branch (Q3, Q2) to be alternately turned on, the AC signal induced by the receiving end coil is converted into a DC signal VRECT.

[0050] In the related art, in the modulation mode, the switch tubes S1-S6 are controlled to connect or disconnect the capacitors C1-C6 between the nodes AC1_1 and AC2_1, and the capacitor modulation is used to affect the current waveforms of the receiving end and the transmitting end, so that the VCOIL peak voltage changes, and ASK modulation is realized. However, the present application controls the first rectifier circuit or the second rectifier circuit through a logic control circuit, and introduces a short discharge loop by adjusting the switching logic timing of the power tubes Q1~Q4, thereby affecting the current waveforms of the receiving end and the transmitting end, and realizing ASK modulation.

[0051] Specifically, in the modulation mode, the logic control circuit controls the first rectifier branch (Q1, Q4) or the second rectifier branch (Q2, Q3) to switch from the on state to the off state after a preset time period during the process of switching the first rectifier branch (Q1, Q4) or the second rectifier branch (Q2, Q3) from the on state to the off state. That is, by controlling the first rectifier branch or the second rectifier branch to delay shutting off during the state switching process of the first rectifier branch or the second rectifier branch, a short-term discharge current loop of the first rectifier branch or the second rectifier branch to VRECT is formed, so that the current of the receiving end coil changes, and then causes the current of the transmitting end coil to change, thereby realizing the ASK modulation function.

[0052] The preset duration can be set by the user according to the needs of the actual project application. In an example, the preset duration can be tens of nanoseconds (ns).

[0053] In the embodiment of the present application, in the modulation mode, the first rectifier branch or the second rectifier branch is controlled to delay shutting down during the state switching process, so as to form a short discharge current loop of the first rectifier branch or the second rectifier branch to VRECT, so that the current of the receiving end coil changes, and then causes the current of the transmitting end coil to change, thereby realizing the ASK modulation function. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0054] In a possible embodiment, the logic control circuit controls the first rectifying branch and the second rectifying branch to switch between a first state and a second state in the unmodulated mode.

[0055] Specifically, in the unmodulated mode, the logic control circuit controls the first rectifier branch (Q1, Q4) and the second rectifier branch (Q3, Q2) to switch between the on state and the off state, and converts the AC signal sensed by the receiving end coil into a DC signal. Figure 3 The state of the power tube is detected by detecting the voltage values ​​of the nodes AC1 and AC2. When it is detected that the body diodes of Q1 to Q4 are turned on, the corresponding power tube is controlled to be turned on. When it is detected that the current flowing through the power tubes Q1 to Q4 passes through zero, the corresponding power tube is controlled to be turned off. Those skilled in the art can understand that the state of the power tube is detected by detecting the voltage values ​​of the nodes AC1 and AC2, and it will not be repeated here.

[0056] In a possible embodiment, the logic control circuit is in a modulation mode, and when the current in the first rectifier branch or the second rectifier branch passes through zero during the process of switching from the first state to the second state in the first rectifier branch or the second rectifier branch, the logic control circuit controls the first rectifier branch or the second rectifier branch to switch from the first state to the second state after a preset time period.

[0057] Specifically, in the modulation mode, the logic control circuit controls the first rectifier branch (Q1, Q4) or the second rectifier branch (Q3, Q2) to switch from the on state to the off state when the current in the first rectifier branch (Q1, Q4) or the second rectifier branch (Q3, Q2) passes through zero, and then controls the first rectifier branch (Q1, Q4) or the second rectifier branch (Q3, Q2) to switch from the on state to the off state after a preset delay.

[0058] According to the control of the first rectifying branch and the second rectifying branch respectively, the embodiment of the present application may include two specific embodiments.

[0059] Embodiment 1:

[0060] See also Figure 4 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0061] See also Figure 4 In the modulation mode, when the first rectifying branch (Q1, Q4) switches from the on state to the off state, when the current in the first rectifying branch (Q1, Q4) crosses zero, the first rectifying branch (Q1, Q4) is controlled to switch from the on state to the off state after a preset time. That is, when the first rectifying branch (Q1, Q4) switches from the on state to the off state, when it is detected that the current in Q1, Q4 crosses zero, Q1, Q4 are turned off with a delay (i.e., turned off after a preset time), such as Figure 4 As shown, when switching between (a) and (b), the first rectifier branch is turned off due to delay, forming (a1), see Figure 4 In (a1), during this period, the current flows out from Cload, which is equivalent to the discharge of Cload, forming a short-term discharge current loop for VRECT in the first rectifier branch, causing the current of the receiving coil to change, and then causing the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0062] Embodiment 1 is to perform unilateral modulation on Q1 and Q4 to realize the function of ASK modulation. Specifically, by inserting a configurable shutdown delay module at the driver of the circuit, when it is detected that the current of Q1 and Q4 is zero-crossing, the shutdown delay module is used to delay the shutdown of Q1 and Q4, and introduce a short-term discharge current loop of VRECT of the first rectifier branch to realize the ASK modulation function. Figure 4 , that is, (a1) is added between (a) and (b) to realize the ASK modulation function.

[0063] The control timing of the power tubes Q1-Q4 in the modulation mode and the unmodulation mode in the first embodiment is as follows: in the unmodulation mode, the timing of Q1-Q4 is: when the body diodes of Q1-Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on, and when the current flowing through the power tubes Q1-Q4 is detected to be zero-crossing, the corresponding power tubes are controlled to be turned off. In the modulation mode, the timing of Q2 and Q3 is: when the body diodes of Q2 and Q3 are detected to be turned on, Q2 and Q3 are controlled to be turned on, and when the current flowing through Q2 and Q3 is detected to be zero-crossing, Q2 and Q3 are controlled to be turned off; the timing of Q1 is: when the body diode of Q1 is detected to be turned on, Q1 is controlled to be turned on, and when the current of Q1 is detected to be zero-crossing, Q1 is controlled to be turned off after a preset time; the timing of Q4 is: when the body diode of Q4 is detected to be turned on, Q4 is controlled to be turned on, and when the current of Q4 is detected to be zero-crossing, Q4 is controlled to be turned off after a preset time.

[0064] For the first embodiment, the present application provides a logic control circuit 100, see Figure 5 The circuit 100 includes: a first comparator A1, a second comparator A2, a third comparator A3, a fourth comparator A4, a first NOR gate B1, a second NOR gate B2, a third NOR gate B3, a fourth NOR gate B4, a first NAND gate E1, a second NAND gate E2, a third NAND gate E3, a fourth NAND gate E4, a fifth NAND gate E5, a sixth NAND gate E6, a first NAND gate D1, a second NAND gate D2, a first turn-off delay F1 and a second turn-off delay F2.

[0065] A positive terminal of the first comparator A1 is electrically connected to AC1, a negative terminal of the first comparator A1 is electrically connected to VRECT+200mV, and an output terminal of the first comparator A1 is electrically connected to a first input terminal of the first NOR gate B1.

[0066] A positive terminal of the second comparator A2 is electrically connected to VRECT, a negative terminal of the second comparator A2 is electrically connected to AC1, and an output terminal of the second comparator A2 is electrically connected to a second input terminal of the second NOR gate B2.

[0067] The second input terminal of the first NOR gate B1 is electrically connected to the output terminal of the second NOR gate B2, the second input terminal of the third NAND gate E3 and the input terminal of the first turn-off delayer F1 respectively, and the output terminal of the first NOR gate B1 is electrically connected to the first input terminal of the second NOR gate B2.

[0068] A first input terminal of the first NAND gate E1 is electrically connected to an output terminal of the first turn-off delayer F1 , and a second input terminal of the first NAND gate E1 is electrically connected to a first modulation enable signal EN_MOD_1 and an input terminal of the first NOT gate D1 , respectively.

[0069] The output terminal of the first NOT gate D1 is electrically connected to the first input terminal of the third NAND gate E3 .

[0070] The output end of the first NAND gate E1 is electrically connected to the first input end of the second NAND gate E2, the output end of the third NAND gate E3 is electrically connected to the second input end of the second NAND gate E2, and the output end of the second NAND gate E2 serves as the control signal end S-Q1 of Q1.

[0071] The positive terminal of the third comparator A3 is electrically connected to -300mV, the negative terminal of the third comparator A3 is electrically connected to AC2, and the output terminal of the third comparator A3 is electrically connected to the first input terminal of the third NOR gate B3.

[0072] A positive terminal of the fourth comparator A4 is electrically connected to AC2, a negative terminal of the fourth comparator A4 is electrically connected to 0mV, and an output terminal of the fourth comparator A4 is electrically connected to a second input terminal of the fourth NOR gate B4.

[0073] The second input terminal of the third NOR gate B3 is electrically connected to the output terminal of the fourth NOR gate B4, the second input terminal of the sixth NAND gate E6 and the input terminal of the second turn-off delayer F2 respectively, and the output terminal of the third NOR gate B3 is electrically connected to the first input terminal of the fourth NOR gate B4.

[0074] A first input terminal of the fourth NAND gate E4 is electrically connected to the output terminal of the second turn-off delayer F2 , and a second input terminal of the fourth NAND gate E4 is electrically connected to the second modulation enable signal EN_MOD_2 and the input terminal of the second NOT gate D2 .

[0075] The output terminal of the second NOT gate D2 is electrically connected to the first input terminal of the sixth NAND gate E6.

[0076] The output end of the fourth NAND gate E4 is electrically connected to the first input end of the fifth NAND gate E5, the output end of the sixth NAND gate E6 is electrically connected to the second input end of the fifth NAND gate E5, and the output end of the fifth NAND gate E5 serves as the control signal end S-Q4 of Q4.

[0077] In the first embodiment, the first modulation enable signal EN_MOD_1 and the second modulation enable signal EN_MOD_2 in the logic control circuit are used to select the modulation mode and the unmodulated mode. The first turn-off delay F1 and the second turn-off delay F2 delay the turn-off of Q1 and Q4 to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0078] Embodiment 2:

[0079] See also Figure 6 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0080] See also Figure 6 In the modulation mode, when the second rectifying branch (Q2, Q3) switches from the on state to the off state, when the current in the second rectifying branch (Q2, Q3) crosses zero, the second rectifying branch (Q2, Q3) is controlled to switch from the on state to the off state after a preset time. That is, when the second rectifying branch (Q2, Q3) switches from the on state to the off state, when it is detected that the current in Q2, Q3 crosses zero, Q2, Q3 are turned off with a delay (i.e., turned off after a preset time), such as Figure 6 As shown, when switching between (a) and (b), the second rectifier branch is turned off due to delay, forming (a1), see Figure 6 In (a1), during this period, the current flows out from Cload, which is equivalent to the discharge of Cload, forming a short-term discharge current loop for VRECT in the second rectifier branch, causing the current of the receiving coil to change, and then causing the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0081] Embodiment 2 is to perform unilateral modulation on Q2 and Q3 to realize the function of ASK modulation. Specifically, by inserting a configurable shutdown delay module at the driver of the circuit, when it is detected that the current of Q2 and Q3 crosses zero, the shutdown delay module correspondingly delays the shutdown of Q2 and Q3, introduces a short-term discharge current loop of VRECT of the first rectifier branch, and realizes the ASK modulation function. Figure 6 , that is, (a1) is added after (a) and (b) to realize the ASK modulation function.

[0082] The control timing of the power tubes Q1 to Q4 in the modulation mode and the unmodulation mode in the second embodiment is as follows: in the unmodulation mode, the timing of Q1 to Q4 is: when the body diodes of Q1 to Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on, and when the current flowing through the power tubes Q1 to Q4 is detected to be zero-crossing, the corresponding power tubes are controlled to be turned off. In the modulation mode, the timing of Q1 and Q4 is: when the body diodes of Q1 and Q4 are detected to be turned on, Q1 and Q4 are controlled to be turned on, and when the current flowing through Q1 and Q4 is detected to be zero-crossing, Q1 and Q4 are controlled to be turned off; the timing of Q2 is: when the body diode of Q2 is detected to be turned on, Q2 is controlled to be turned on, and when the current of Q2 is detected to be zero-crossing, Q2 is controlled to be turned off after a preset time; the timing of Q3 is: when the body diode of Q3 is detected to be turned on, Q3 is controlled to be turned on, and when the current of Q3 is detected to be zero-crossing, Q3 is controlled to be turned off after a preset time.

[0083] For the second embodiment, the present application provides a logic control circuit 100, see Figure 7The circuit 100 includes: a fifth comparator A5, a sixth comparator A6, a seventh comparator A7, an eighth comparator A8, a fifth NOR gate B5, a sixth NOR gate B6, a seventh NOR gate B7, an eighth NOR gate B8, a seventh NAND gate E7, an eighth NAND gate E8, a ninth NAND gate E9, a tenth NAND gate E10, an eleventh NAND gate E11, a twelfth NAND gate E12, a third NAND gate D3, a fourth NAND gate D4, a third turn-off delay F3 and a fourth turn-off delay F4.

[0084] A positive terminal of the fifth comparator A5 is electrically connected to AC2, a negative terminal of the fifth comparator A5 is electrically connected to VRECT+200mV, and an output terminal of the fifth comparator A5 is electrically connected to a first input terminal of a fifth NOR gate B5.

[0085] A positive terminal of the sixth comparator A6 is electrically connected to VRECT, a negative terminal of the sixth comparator A6 is electrically connected to AC2, and an output terminal of the sixth comparator A6 is electrically connected to a second input terminal of a sixth NOR gate B6.

[0086] The second input terminal of the fifth NOR gate B5 is electrically connected to the output terminal of the sixth NOR gate B6, the second input terminal of the ninth NAND gate E9 and the input terminal of the third turn-off delayer F3 respectively, and the output terminal of the fifth NOR gate B5 is electrically connected to the first input terminal of the sixth NOR gate B6.

[0087] A first input terminal of the seventh NAND gate E7 is electrically connected to the output terminal of the third turn-off delayer F3 , and a second input terminal of the seventh NAND gate E7 is electrically connected to the third modulation enable signal EN_MOD_3 and the input terminal of the third NOT gate D3 , respectively.

[0088] An output terminal of the third NOT gate D3 is electrically connected to a first input terminal of the ninth NAND gate E9.

[0089] The output end of the seventh NAND gate E7 is electrically connected to the first input end of the eighth NAND gate E8, the output end of the ninth NAND gate E9 is electrically connected to the second input end of the eighth NAND gate E8, and the output end of the eighth NAND gate E8 serves as the control signal end S-Q3 of Q3.

[0090] A positive terminal of the seventh comparator A7 is electrically connected to -300 mV, a negative terminal of the seventh comparator A7 is electrically connected to AC1, and an output terminal of the seventh comparator A7 is electrically connected to a first input terminal of a seventh NOR gate B7.

[0091] A positive terminal of the eighth comparator A8 is electrically connected to AC1, a negative terminal of the eighth comparator A8 is electrically connected to 0mV, and an output terminal of the eighth comparator A8 is electrically connected to a second input terminal of the eighth NOR gate B8.

[0092] The second input terminal of the seventh NOR gate B7 is electrically connected to the output terminal of the eighth NOR gate B8, the second input terminal of the twelfth NAND gate E12 and the input terminal of the fourth turn-off delayer F4 respectively, and the output terminal of the seventh NOR gate B7 is electrically connected to the first input terminal of the eighth NOR gate B8.

[0093] A first input terminal of the tenth NAND gate E10 is electrically connected to the output terminal of the fourth turn-off delayer F4 , and a second input terminal of the tenth NAND gate E10 is electrically connected to the fourth modulation enable signal EN_MOD_4 and the input terminal of the fourth NOT gate D4 , respectively.

[0094] The output terminal of the fourth NOT gate D4 is electrically connected to the first input terminal of the twelfth NAND gate E12.

[0095] The output end of the tenth NAND gate E10 is electrically connected to the first input end of the eleventh NAND gate E11, the output end of the twelfth NAND gate E12 is electrically connected to the second input end of the eleventh NAND gate E11, and the output end of the eleventh NAND gate E11 serves as the control signal end S-Q2 of Q2.

[0096] In the second embodiment, the third modulation enable signal EN_MOD_3 and the fourth modulation enable signal EN_MOD_4 in the logic control circuit are used to select the modulation mode and the unmodulated mode. The third turn-off delay F3 and the fourth turn-off delay F4 delay the turn-off of Q3 and Q2 to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes, and chip pins without affecting the ASK modulation effect.

[0097] In a possible embodiment, in the modulation mode, the logic control circuit controls the first rectifier branch or the second rectifier branch to switch from the first state to the second state when the current of the first rectifier branch or the second rectifier branch is a preset threshold value.

[0098] Specifically, in the modulation mode, the logic control circuit controls the first rectifier branch (Q1, Q4) or the second rectifier branch (Q3, Q2) to switch from the on state to the off state when the current of the first rectifier branch (Q1, Q4) or the second rectifier branch (Q3, Q2) is a preset threshold value.

[0099] The preset threshold can be set by the user according to the needs of the actual project application. The current can be selected as the preset threshold, or the voltage can be selected as the preset threshold. When the voltage is selected, the value range of the preset threshold can be (0mV) ~ (5mV). In one example, the preset threshold is 3mV; when the current is selected, the value range of the preset threshold can be (-200mA) ~ (-400mA). In one example, the preset threshold is -300mA. In the related art, when it is detected that the current of the power tube passes through zero, the corresponding power tube is turned off. In the present application, a preset threshold of a certain negative value is set. Since it takes time for the current to increase from zero to a certain negative value, when it is detected that the current of the power tube in the first rectifier branch or the second rectifier branch is the preset threshold, the first rectifier branch or the second rectifier branch is controlled to switch from the on state to the off state, which is equivalent to delaying the shutdown of the first rectifier branch or the second rectifier branch.

[0100] The embodiment of the present application is different from the above-mentioned embodiment one and embodiment two in that, embodiment one and embodiment two delay the shutdown of the first rectifier branch or the second rectifier branch by inserting a shutdown delay device, while the embodiment of the present application delays the shutdown of the first rectifier branch or the second rectifier branch by setting the zero current detection threshold of the power tube, that is, when the current of the first rectifier branch or the second rectifier branch is a preset threshold, the first rectifier branch or the second rectifier branch is controlled to switch from the on state to the off state.

[0101] According to the control of the first rectifying branch and the second rectifying branch respectively, the embodiment of the present application may include two specific embodiments.

[0102] Embodiment three:

[0103] The timing control logic of the third embodiment is the same as that of the first embodiment in the unmodulated mode and the modulated mode, see Figure 4 . Figure 4 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0104] See also Figure 4 In the modulation mode, when the first rectifying branch (Q1, Q4) switches from the on state to the off state, when the current of the first rectifying branch (Q1, Q4) reaches a preset threshold, the first rectifying branch (Q1, Q4) is controlled to switch from the on state to the off state. That is, when the first rectifying branch (Q1, Q4) switches from the on state to the off state, when it is detected that the current of Q1, Q4 reaches a preset threshold, Q1, Q4 are turned off, such as Figure 4As shown, when switching between (a) and (b), the first rectifier branch is turned off due to delay, forming (a1), see Figure 4 In (a1), during this period, the current flows out from Cload, which is equivalent to the discharge of Cload, forming a short-term discharge current loop for VRECT in the first rectifier branch, causing the current of the receiving coil to change, and then causing the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0105] Embodiment 3 is to perform unilateral modulation on Q1 and Q4 to realize the function of ASK modulation. Specifically, by setting the zero current detection threshold, when the current of Q1 and Q4 is detected to be the preset threshold, Q1 and Q4 are turned off, and the first rectifier branch is introduced to temporarily discharge the current loop of VRECT to realize the ASK modulation function. Figure 4 , that is, (a1) is added between (a) and (b) to realize the ASK modulation function.

[0106] The control timing of the power tubes Q1~Q4 in the modulation mode and the unmodulation mode in the third embodiment is as follows: in the unmodulation mode, the timing of Q1~Q4 is: when the body diodes of Q1~Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on, and when the current flowing through the power tubes Q1~Q4 is detected to be zero-crossing, the corresponding power tubes are controlled to be turned off. In the modulation mode, the timing of Q2 and Q3 is: when the body diodes of Q2 and Q3 are detected to be turned on, Q2 and Q3 are controlled to be turned on, and when the current flowing through Q2 and Q3 is detected to be zero-crossing, Q2 and Q3 are controlled to be turned off; the timing of Q1 is: when the body diode of Q1 is detected to be turned on, Q1 is controlled to be turned on, and when the current of Q1 is detected to be a preset threshold, Q1 is controlled to be turned off; the timing of Q4 is: when the body diode of Q4 is detected to be turned on, Q4 is controlled to be turned on, and when the current of Q4 is detected to be a preset threshold, Q4 is controlled to be turned off.

[0107] For the third embodiment, the present application provides a logic control circuit 100, see Figure 8 The circuit 100 includes: a ninth comparator A9, a tenth comparator A10, an eleventh comparator A11, a twelfth comparator A12, a ninth NOR gate B9, a tenth NOR gate B10, an eleventh NOR gate B11, a twelfth NOR gate B12, a first reference voltage source VREF1 and a second reference voltage source VREF2.

[0108] A positive terminal of the ninth comparator A9 is electrically connected to AC1, a negative terminal of the ninth comparator A9 is electrically connected to VRECT+200mV, and an output terminal of the ninth comparator A9 is electrically connected to a first input terminal of a ninth NOR gate B9.

[0109] The positive end of the tenth comparator A10 is electrically connected to VRECT, the reverse end of the tenth comparator A10 is electrically connected to the first end of the first reference voltage source VREF1, the second end of the first reference voltage source VREF1 is electrically connected to AC1, and the output end of the tenth comparator A10 is electrically connected to the second input end of the tenth NOR gate B10.

[0110] The output terminal of the ninth NOR gate B9 is electrically connected to the first input terminal of the tenth NOR gate B10. The second input terminal of the ninth NOR gate B9 is electrically connected to the output terminal of the tenth NOR gate B10 and serves as the control signal terminal S-Q1 of Q1.

[0111] A positive terminal of the eleventh comparator A11 is electrically connected to -300 mV, a negative terminal of the eleventh comparator A11 is electrically connected to AC2, and an output terminal of the eleventh comparator A11 is electrically connected to a first input terminal of the eleventh NOR gate B11.

[0112] The positive end of the twelfth comparator A12 is electrically connected to AC2, the reverse end of the twelfth comparator A12 is electrically connected to the first end of the second reference voltage source VREF2, the second end of the second reference voltage source VREF2 is electrically connected to 0mV, and the output end of the twelfth comparator A12 is electrically connected to the second input end of the twelfth NOR gate B12.

[0113] The output terminal of the eleventh NOR gate B11 is electrically connected to the first input terminal of the twelfth NOR gate B12. The second input terminal of the eleventh NOR gate B11 is electrically connected to the output terminal of the twelfth NOR gate B12 and serves as the control signal terminal S-Q4 of Q4.

[0114] In the third embodiment, by setting the zero current detection threshold of the power tube, by detecting VREF1 and VREF2, when they are greater than 0mV, Q1 and Q4 are controlled to be turned off, that is, Q1 and Q4 are turned off with delay, so as to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes and chip pins without affecting the ASK modulation effect.

[0115] Embodiment 4:

[0116] The timing control logic of the fourth embodiment is the same as that of the second embodiment in the unmodulated mode and the modulated mode, see Figure 6 . Figure 6 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0117] See also Figure 6In the modulation mode, when the second rectifying branch (Q2, Q3) switches from the on state to the off state, when the current of the second rectifying branch (Q2, Q3) reaches a preset threshold, the second rectifying branch (Q2, Q3) is controlled to switch from the on state to the off state. That is, when the second rectifying branch (Q2, Q3) switches from the on state to the off state, when it is detected that the current of Q2, Q3 reaches the preset threshold, Q2, Q3 are turned off, such as Figure 6 As shown, when switching between (a) and (b), the second rectifier branch is turned off due to delay, forming (a1), see Figure 6 In (a1), during this period, the current flows out from Cload, which is equivalent to the discharge of Cload, forming a short-term discharge current loop for VRECT in the second rectifier branch, causing the current of the receiving coil to change, and then causing the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0118] Embodiment 4 is to perform unilateral modulation on Q2 and Q3 to realize the function of ASK modulation. Specifically, by setting the zero current detection threshold, when the current of Q2 and Q3 is detected to be the preset threshold, Q2 and Q3 are turned off, and the second rectifier branch is introduced to temporarily discharge the current loop of VRECT to realize the ASK modulation function. Figure 6 , that is, (a1) is added between (a) and (b) to realize the ASK modulation function.

[0119] The modulation mode and the unmodulation mode in the fourth embodiment control the timing of the power tubes Q1~Q4 as follows: In the unmodulation mode, the timing of Q1~Q4 is: when the body diodes of Q1~Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on, and when the current flowing through the power tubes Q1~Q4 is detected to be zero-crossing, the corresponding power tubes are controlled to be turned off. In the modulation mode, the timing of Q1 and Q4 is: when the body diodes of Q1 and Q4 are detected to be turned on, Q1 and Q4 are controlled to be turned on, and when the current flowing through Q1 and Q4 is detected to be zero-crossing, Q1 and Q4 are controlled to be turned off; the timing of Q2 is: when the body diode of Q2 is detected to be turned on, Q2 is controlled to be turned on, and when the current of Q2 is detected to be a preset threshold, Q2 is controlled to be turned off; the timing of Q3 is: when the body diode of Q3 is detected to be turned on, Q3 is controlled to be turned on, and when the current of Q3 is detected to be a preset threshold, Q3 is controlled to be turned off.

[0120] For the fourth embodiment, the present application provides a logic control circuit 100, see Fig. 9 The circuit 100 includes: a thirteenth comparator A13, a fourteenth comparator A14, a fifteenth comparator A15, a sixteenth comparator A16, a thirteenth NOR gate B13, a fourteenth NOR gate B14, a fifteenth NOR gate B15, a sixteenth NOR gate B16, a third reference voltage source VREF3 and a fourth reference voltage source VREF4.

[0121] A positive terminal of the thirteenth comparator A13 is electrically connected to AC2, a negative terminal of the thirteenth comparator A13 is electrically connected to VRECT+200mV, and an output terminal of the thirteenth comparator A13 is electrically connected to a first input terminal of a thirteenth NOR gate B13.

[0122] The positive end of the fourteenth comparator A14 is electrically connected to VRECT, the reverse end of the fourteenth comparator A14 is electrically connected to the first end of the third reference voltage source VREF3, the second end of the third reference voltage source VREF3 is electrically connected to AC2, and the output end of the fourteenth comparator A14 is electrically connected to the second input end of the fourteenth NOR gate B14.

[0123] The output terminal of the thirteenth NOR gate B13 is electrically connected to the first input terminal of the fourteenth NOR gate B14. The second input terminal of the thirteenth NOR gate B13 is electrically connected to the output terminal of the fourteenth NOR gate B14 and serves as the control signal terminal S-Q3 of Q3.

[0124] A positive terminal of the fifteenth comparator A15 is electrically connected to -300 mV, a negative terminal of the fifteenth comparator A15 is electrically connected to AC1, and an output terminal of the fifteenth comparator A15 is electrically connected to a first input terminal of a fifteenth NOR gate B15.

[0125] The positive end of the sixteenth comparator A16 is electrically connected to AC1, the reverse end of the sixteenth comparator A16 is electrically connected to the first end of the fourth reference voltage source VREF4, the second end of the second reference voltage source VREF4 is electrically connected to 0mV, and the output end of the sixteenth comparator A16 is electrically connected to the second input end of the sixteenth NOR gate B16.

[0126] The output terminal of the fifteenth NOR gate B15 is electrically connected to the first input terminal of the sixteenth NOR gate B16. The second input terminal of the fifteenth NOR gate B15 is electrically connected to the output terminal of the sixteenth NOR gate B16 and serves as the control signal terminal S-Q2 of Q2.

[0127] In the fourth embodiment, by setting the zero current detection threshold of the power tube, by detecting VREF3 and VREF4, when they are greater than 0mV, Q3 and Q2 are controlled to be turned off, that is, Q3 and Q2 are turned off with delay, so as to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes and chip pins without affecting the ASK modulation effect.

[0128] In a possible embodiment, the logic control circuit is in debugging mode. When the current in the first rectifier branch passes through zero when the first rectifier branch is switching from the first state to the second state, the logic control circuit controls the first rectifier branch to switch from the first state to the second state after a preset time period. When the current in the second rectifier branch passes through zero when the second rectifier branch is switching from the first state to the second state, the logic control circuit controls the second rectifier branch to switch from the first state to the second state after a preset time period.

[0129] Specifically, during the process of the first rectifying branch (Q1, Q4) switching from the on state to the off state, when the current in the first rectifying branch (Q1, Q4) passes through zero, the first rectifying branch (Q1, Q4) is controlled to switch from the on state to the off state after a preset time period; during the process of the second rectifying branch (Q3, Q2) switching from the on state to the off state, when the current in the second rectifying branch (Q3, Q2) passes through zero, the second rectifying branch (Q3, Q2) is controlled to switch from the on state to the off state after a preset time period.

[0130] The following is described by a specific embodiment:

[0131] Embodiment five:

[0132] See also Fig.10 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0133] See also Fig.10 In the modulation mode, during the process of the first rectifier branch (Q1, Q4) switching from the on state to the off state, when the current of the first rectifier branch (Q1, Q4) passes through zero, the first rectifier branch (Q1, Q4) is controlled to switch from the on state to the off state after a preset time period; during the process of the second rectifier branch (Q2, Q3) switching from the on state to the off state, when the current of the second rectifier branch (Q2, Q3) passes through zero, the second rectifier branch (Q2, Q3) is controlled to switch from the on state to the off state after a preset time period. That is, when the first rectifier branch (Q1, Q4) switches from the on state to the off state, when it is detected that the current of Q1, Q4 crosses zero, Q1, Q4 are turned off with a delay (i.e., they are turned off after a preset time); when the second rectifier branch (Q2, Q3) switches from the on state to the off state, when it is detected that the current of Q2, Q3 crosses zero, Q2, Q3 are turned off with a delay (i.e., they are turned off after a preset time). Fig.10 As shown, when switching between (a) and (b), the first rectifier branch and the second rectifier branch are turned off with a delay, forming (a1) and (b1), see Fig.10During (a1) and (b1) in the figure, the current flows out from Cload, which is equivalent to the discharge of Cload, forming a short-term discharge current loop for VRECT of the first rectifier branch and the second rectifier branch, respectively, so that the current of the receiving coil changes, which in turn causes the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0134] Embodiment 5 is to perform bilateral modulation on Q1, Q4, Q2, Q3 to realize the function of ASK modulation. Specifically, by inserting a configurable shutdown delay module at the driver of the circuit, when it is detected that the current of Q1, Q4, Q2, and Q3 is zero-crossing, the shutdown delay module is used to delay the shutdown of Q1, Q4, Q2, and Q3, respectively, to introduce a short-term discharge current loop of VRECT of the first rectifier branch and the second rectifier branch, thereby realizing the ASK modulation function. Fig.10 , that is, (a1) and (b1) are added between (a) and (b) to realize the ASK modulation function.

[0135] The control timing of the power tubes Q1~Q4 in the modulation mode and the unmodulation mode in Example 5 is specifically as follows: In the unmodulation mode, the timing of Q1~Q4 is: when the body diodes of Q1~Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on; when the current flowing through the power tubes Q1~Q4 is detected to pass through zero, the corresponding power tubes are controlled to be turned off. In the modulation mode, the timing of Q1 is: when the body diode of Q1 is detected to be turned on, Q1 is controlled to be turned on; when the current of Q1 is detected to be zero, after a preset time period, Q1 is controlled to be turned off; the timing of Q4 is: when the body diode of Q4 is detected to be turned on, Q4 is controlled to be turned on; when the current of Q4 is detected to be zero, after a preset time period, Q4 is controlled to be turned off; in the modulation mode, the timing of Q2 is: when the body diode of Q2 is detected to be turned on, Q2 is controlled to be turned on; when the current of Q2 is detected to be zero, after a preset time period, Q2 is controlled to be turned off; the timing of Q3 is: when the body diode of Q3 is detected to be turned on, Q3 is controlled to be turned on; when the current of Q3 is detected to be zero, after a preset time period, Q3 is controlled to be turned off.

[0136] For the fifth embodiment, the present application provides a logic control circuit 100, see Fig.11The circuit 100 includes: a seventeenth comparator A17, an eighteenth comparator A18, a nineteenth comparator A19, a twentieth comparator A20, a twenty-first comparator A21, a twenty-second comparator A22, a twenty-third comparator A23, a twenty-fourth comparator A24, a seventeenth NOR gate B17, an eighteenth NOR gate B18, a nineteenth NOR gate B19, a twentieth NOR gate B20, a twenty-first NOR gate B21, a twenty-second NOR gate B22, a twenty-third NOR gate B23, a twenty-fourth NOR gate B24, a thirteenth NAND gate E 13, a fourteenth NAND gate E14, a fifteenth NAND gate E15, a sixteenth NAND gate E16, a seventeenth NAND gate E17, an eighteenth NAND gate E18, a nineteenth NAND gate E19, a twentieth NAND gate E20, a twenty-first NAND gate E21, a twenty-second NAND gate E22, a twenty-third NAND gate E23, a twenty-fourth NAND gate E24, a fifth NAND gate D5, a sixth NAND gate D6, a seventh NAND gate D7, an eighth NAND gate D8, a fifth turn-off delay F5, a sixth turn-off delay F6, a seventh turn-off delay F7 and an eighth turn-off delay F8.

[0137] A positive terminal of the seventeenth comparator A17 is electrically connected to AC1, a negative terminal of the seventeenth comparator A17 is electrically connected to VRECT+200mV, and an output terminal of the seventeenth comparator A17 is electrically connected to a first input terminal of a seventeenth NOR gate B17.

[0138] A positive terminal of the eighteenth comparator A18 is electrically connected to VRECT, a negative terminal of the eighteenth comparator A18 is electrically connected to AC1, and an output terminal of the eighteenth comparator A18 is electrically connected to a second input terminal of the eighteenth NOR gate B18.

[0139] The second input terminal of the seventeenth NOR gate B17 is electrically connected to the output terminal of the eighteenth NOR gate B18, the second input terminal of the fifteenth NAND gate E15 and the input terminal of the fifth turn-off delayer F5 respectively, and the output terminal of the seventeenth NOR gate B17 is electrically connected to the first input terminal of the eighteenth NOR gate B18.

[0140] A first input terminal of the thirteenth NAND gate E13 is electrically connected to the output terminal of the fifth turn-off delayer F5 , and a second input terminal of the thirteenth NAND gate E13 is electrically connected to the fifth modulation enable signal EN_MOD_5 and the input terminal of the fifth NOT gate D5 , respectively.

[0141] The output terminal of the fifth NOT gate D5 is electrically connected to the first input terminal of the fifteenth NAND gate E15.

[0142] The output end of the thirteenth NAND gate E13 is electrically connected to the first input end of the fourteenth NAND gate E14, the output end of the fifteenth NAND gate E15 is electrically connected to the second input end of the fourteenth NAND gate E14, and the output end of the fourteenth NAND gate E14 serves as the control signal end S-Q1 of Q1.

[0143] The positive terminal of the nineteenth comparator A19 is electrically connected to -300mV, the negative terminal of the nineteenth comparator A19 is electrically connected to AC2, and the output terminal of the nineteenth comparator A19 is electrically connected to the first input terminal of the nineteenth NOR gate B19.

[0144] A positive terminal of the twentieth comparator A20 is electrically connected to AC2, a negative terminal of the twentieth comparator A20 is electrically connected to 0mV, and an output terminal of the twentieth comparator A20 is electrically connected to a second input terminal of the twentieth NOR gate B20.

[0145] The second input terminal of the nineteenth NOR gate B19 is electrically connected to the output terminal of the twentieth NOR gate B20, the second input terminal of the eighteenth NAND gate E18 and the input terminal of the sixth turn-off delayer F6 respectively, and the output terminal of the nineteenth NOR gate B19 is electrically connected to the first input terminal of the twentieth NOR gate B20.

[0146] A first input terminal of the sixteenth NAND gate E16 is electrically connected to the output terminal of the sixth turn-off delayer F6 , and a second input terminal of the sixteenth NAND gate E16 is electrically connected to the sixth modulation enable signal EN_MOD_6 and the input terminal of the sixth NOT gate D6 , respectively.

[0147] The output terminal of the sixth NOT gate D6 is electrically connected to the first input terminal of the eighteenth NAND gate E18.

[0148] The output end of the sixteenth NAND gate E16 is electrically connected to the first input end of the seventeenth NAND gate E17, the output end of the eighteenth NAND gate E18 is electrically connected to the second input end of the seventeenth NAND gate E17, and the output end of the seventeenth NAND gate E17 serves as the control signal end S-Q4 of Q4.

[0149] A positive terminal of the twenty-first comparator A21 is electrically connected to AC2, a negative terminal of the twenty-first comparator A21 is electrically connected to VRECT+200mV, and an output terminal of the twenty-first comparator A21 is electrically connected to a first input terminal of a twenty-first NOR gate B21.

[0150] A positive terminal of the twenty-second comparator A22 is electrically connected to VRECT, a negative terminal of the twenty-second comparator A22 is electrically connected to AC2, and an output terminal of the twenty-second comparator A22 is electrically connected to a second input terminal of the twenty-second NOR gate B22.

[0151] The second input terminal of the twenty-first NOR gate B21 is electrically connected to the output terminal of the twenty-second NOR gate B22, the second input terminal of the twenty-third NAND gate E23 and the input terminal of the seventh turn-off delayer F7 respectively, and the output terminal of the twenty-first NOR gate B21 is electrically connected to the first input terminal of the twenty-second NOR gate B22.

[0152] A first input terminal of the nineteenth NAND gate E19 is electrically connected to the output terminal of the seventh turn-off delayer F7 , and a second input terminal of the nineteenth NAND gate E19 is electrically connected to the seventh modulation enable signal EN_MOD_7 and the input terminal of the seventh NOT gate D7 , respectively.

[0153] An output terminal of the seventh NOT gate D7 is electrically connected to a first input terminal of the twenty-first NAND gate E21 .

[0154] The output end of the nineteenth NAND gate E19 is electrically connected to the first input end of the twentieth NAND gate E20, the output end of the twenty-first NAND gate E21 is electrically connected to the second input end of the twentieth NAND gate E20, and the output end of the twentieth NAND gate E20 serves as the control signal end S-Q3 of Q3.

[0155] The positive terminal of the twenty-third comparator A23 is electrically connected to -300mV, the negative terminal of the twenty-third comparator A23 is electrically connected to AC1, and the output terminal of the twenty-third comparator A23 is electrically connected to the first input terminal of the twenty-third NOR gate B23.

[0156] The positive terminal of the twenty-fourth comparator A24 is electrically connected to AC1, the negative terminal of the twenty-fourth comparator A24 is electrically connected to 0mV, and the output terminal of the twenty-fourth comparator A24 is electrically connected to the second input terminal of the twenty-fourth NOR gate B24.

[0157] The second input terminal of the twenty-third NOR gate B23 is electrically connected to the output terminal of the twenty-fourth NOR gate B24, the second input terminal of the twenty-fourth NAND gate E24 and the input terminal of the eighth turn-off delayer F8 respectively, and the output terminal of the twenty-third NOR gate B23 is electrically connected to the first input terminal of the twenty-fourth NOR gate B24.

[0158] A first input terminal of the twenty-second NAND gate E22 is electrically connected to the output terminal of the eighth turn-off delayer F8 , and a second input terminal of the twenty-second NAND gate E22 is electrically connected to the eighth modulation enable signal EN_MOD_8 and the input terminal of the eighth NOT gate D8 , respectively.

[0159] An output terminal of the eighth NOT gate D8 is electrically connected to a first input terminal of the twenty-fourth NAND gate E24.

[0160] The output end of the twenty-second NAND gate E22 is electrically connected to the first input end of the twenty-third NAND gate E23, the output end of the twenty-fourth NAND gate E24 is electrically connected to the second input end of the twenty-third NAND gate E23, and the output end of the twenty-third NAND gate E23 serves as the control signal end S-Q2 of Q2.

[0161] In the fifth embodiment, the fifth modulation enable signal EN_MOD_5, the sixth modulation enable signal EN_MOD_6, the seventh modulation enable signal EN_MOD_7 and the eighth modulation enable signal EN_MOD_8 in the logic control circuit are used to select the modulation mode and the unmodulated mode. The fifth turn-off delay F5, the sixth turn-off delay F6, the seventh turn-off delay F7 and the eighth turn-off delay F8 delay the turn-off of Q1 and Q4, Q3 and Q2 to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes and chip pins without affecting the ASK modulation effect.

[0162] In a possible embodiment, the logic control circuit is in debugging mode, and during the process of the first rectifier branch switching from the first state to the second state, when the current of the first rectifier branch is a preset threshold value, the first rectifier branch is controlled to switch from the first state to the second state; during the process of the second rectifier branch switching from the first state to the second state, when the current of the second rectifier branch is a preset threshold value, the second rectifier branch is controlled to switch from the first state to the second state.

[0163] Specifically, during the process of the first rectifying branch (Q1, Q4) switching from the on state to the off state, when the current of the first rectifying branch (Q1, Q4) is a preset threshold value, the first rectifying branch (Q1, Q4) is controlled to switch from the on state to the off state; during the process of the second rectifying branch (Q3, Q2) switching from the on state to the off state, when the current of the second rectifying branch (Q3, Q2) is a preset threshold value, the second rectifying branch (Q3, Q2) is controlled to switch from the on state to the off state.

[0164] The preset threshold can be set by the user according to the needs of the actual project application. The current can be selected as the preset threshold, or the voltage can be selected as the preset threshold. When the voltage is selected, the value range of the preset threshold can be (0mV) ~ (5mV). In one example, the preset threshold is 3mV; when the current is selected, the value range of the preset threshold can be (-200mA) ~ (-400mA). In one example, the preset threshold is -300mA. In the related art, when it is detected that the current of the power tube passes through zero, the corresponding power tube is turned off. In the present application, a preset threshold of a certain negative value is set. Since it takes time for the current to increase from zero to a certain negative value, when it is detected that the current of the power tube in the first rectifier branch and the second rectifier branch is the preset threshold, the first rectifier branch or the second rectifier branch is controlled to switch from the on state to the off state, which is equivalent to delaying the shutdown of the first rectifier branch or the second rectifier branch.

[0165] The embodiment of the present application is different from the above-mentioned embodiment five in that, while embodiment five delays the shutdown of the first rectifier branch and the second rectifier branch by inserting a shutdown delay device, the embodiment of the present application delays the shutdown of the first rectifier branch and the second rectifier branch by setting a zero current detection threshold of the power tube, that is, when the current of the first rectifier branch and the second rectifier branch is a preset threshold, the first rectifier branch or the second rectifier branch is controlled to switch from the on state to the off state.

[0166] The following is described by a specific embodiment:

[0167] Embodiment six:

[0168] See also Fig.10 In (a) and (b), in the unmodulated mode, the first rectifying branch (Q1, Q4) and the second rectifying branch (Q3, Q2) are controlled to switch between the on state and the off state.

[0169] See also Fig.10 , in the modulation mode, during the process of the first rectifying branch (Q1, Q4) switching from the on state to the off state, when the current of the first rectifying branch (Q1, Q4) is a preset threshold value, the first rectifying branch (Q1, Q4) is controlled to switch from the on state to the off state; during the process of the second rectifying branch (Q2, Q3) switching from the on state to the off state, when the current of the second rectifying branch (Q2, Q3) is a preset threshold value, the second rectifying branch (Q2, Q3) is controlled to switch from the on state to the off state. That is, during the process of the first rectifying branch (Q1, Q4) switching from the on state to the off state, when it is detected that the current of Q1, Q4 is the preset threshold value, Q1, Q4 are turned off; during the process of the second rectifying branch (Q2, Q3) switching from the on state to the off state, when it is detected that the current of Q2, Q3 is the preset threshold value, Q2, Q3 are turned off. As Fig.10 As shown, when switching between (a) and (b), the first rectifier branch and the second rectifier branch are turned off with a delay, forming (a1) and (b1), see Fig.10 During (a1) and (b1) in the figure, the current flows out from Cload, which is equivalent to the discharge of Cload, forming a short-term discharge current loop for VRECT of the first rectifier branch and the second rectifier branch, respectively, so that the current of the receiving coil changes, which in turn causes the current of the transmitting coil to change, thereby realizing the ASK modulation function.

[0170] Embodiment 6 is to perform bilateral modulation on Q1, Q4, Q2, Q3 to realize the function of ASK modulation. Specifically, by setting the zero current detection threshold, when the current of Q1, Q4, Q2, and Q3 is detected to be the preset threshold, Q1, Q4, Q2, and Q3 are turned off, and the first rectifier branch and the second rectifier branch are respectively introduced to temporarily discharge the current loop of VRECT to realize the ASK modulation function. Fig.10 , that is, (a1) and (b1) are added between (a) and (b) to realize the ASK modulation function.

[0171] The control timing of the power tubes Q1~Q4 in the modulation mode and the unmodulation mode in Example 6 is specifically as follows: In the unmodulation mode, the timing of Q1~Q4 is: when the body diodes of Q1~Q4 are detected to be turned on, the corresponding power tubes are controlled to be turned on; when the current flowing through the power tubes Q1~Q4 is detected to pass through zero, the corresponding power tubes are controlled to be turned off. In the modulation mode, the timing of Q1 is: when the body diode of Q1 is detected to be turned on, Q1 is controlled to be turned on; when the current of Q1 is detected to be a preset threshold, Q1 is controlled to be turned off; the timing of Q4 is: when the body diode of Q4 is detected to be turned on, Q4 is controlled to be turned on; when the current of Q4 is detected to be a preset threshold, Q4 is controlled to be turned off; in the modulation mode, the timing of Q2 is: when the body diode of Q2 is detected to be turned on, Q2 is controlled to be turned on; when the current of Q2 is detected to be a preset threshold, Q2 is controlled to be turned off; the timing of Q3 is: when the body diode of Q3 is detected to be turned on, Q3 is controlled to be turned on; when the current of Q3 is detected to be a preset threshold, Q3 is controlled to be turned off.

[0172] For the sixth embodiment, the present application provides a logic control circuit 100, see Fig.12 The circuit 100 includes: a twenty-fifth comparator A25, a twenty-sixth comparator A26, a twenty-seventh comparator A27, a twenty-eighth comparator A28, a twenty-ninth comparator A29, a thirtieth comparator A30, a thirty-first comparator A31, a thirty-second comparator A32, a twenty-fifth NOR gate B25, a twenty-sixth NOR gate B26, a twenty-seventh NOR gate B27, a twenty-eighth NOR gate B28, a twenty-ninth NOR gate B29, a thirtieth NOR gate B30, a thirty-first NOR gate B31, a thirty-second NOR gate B32, a fifth reference voltage source VREF5, a sixth reference voltage source VREF6, a seventh reference voltage source VREF7 and an eighth reference voltage source VREF8.

[0173] The positive end of the twenty-fifth comparator A25 is electrically connected to AC1, the negative end of the twenty-fifth comparator A25 is electrically connected to VRECT+200mV, and the output end of the twenty-fifth comparator A25 is electrically connected to the first input end of the twenty-fifth NOR gate B25.

[0174] The positive end of the twenty-sixth comparator A26 is electrically connected to VRECT, the reverse end of the twenty-sixth comparator A26 is electrically connected to the first end of the fifth reference voltage source VREF5, the second end of the fifth reference voltage source VREF5 is electrically connected to AC1, and the output end of the twenty-sixth comparator A26 is electrically connected to the second input end of the twenty-sixth NOR gate B26.

[0175] The output terminal of the twenty-fifth NOR gate B25 is electrically connected to the first input terminal of the twenty-sixth NOR gate B26. The second input terminal of the twenty-fifth NOR gate B25 is electrically connected to the output terminal of the twenty-sixth NOR gate B26 and serves as the control signal terminal S-Q1 of Q1.

[0176] The positive terminal of the twenty-seventh comparator A27 is electrically connected to -300mV, the negative terminal of the twenty-seventh comparator A27 is electrically connected to AC2, and the output terminal of the twenty-seventh comparator A27 is electrically connected to the first input terminal of the twenty-seventh NOR gate B27.

[0177] The positive end of the twenty-eighth comparator A28 is electrically connected to AC2, the reverse end of the twenty-eighth comparator A28 is electrically connected to the first end of the sixth reference voltage source VREF6, the second end of the sixth reference voltage source VREF6 is electrically connected to 0mV, and the output end of the twenty-eighth comparator A28 is electrically connected to the second input end of the twenty-eighth NOR gate B28.

[0178] The output terminal of the twenty-seventh NOR gate B27 is electrically connected to the first input terminal of the twenty-eighth NOR gate B28. The second input terminal of the twenty-seventh NOR gate B27 is electrically connected to the output terminal of the twenty-eighth NOR gate B28 and serves as the control signal terminal S-Q4 of Q4.

[0179] The positive end of the twenty-ninth comparator A29 is electrically connected to AC2, the negative end of the twenty-ninth comparator A29 is electrically connected to VRECT+200mV, and the output end of the twenty-ninth comparator A29 is electrically connected to the first input end of the twenty-ninth NOR gate B29.

[0180] The positive end of the 30th comparator A30 is electrically connected to VRECT, the reverse end of the 30th comparator A30 is electrically connected to the first end of the seventh reference voltage source VREF7, the second end of the seventh reference voltage source VREF7 is electrically connected to AC2, and the output end of the 30th comparator A30 is electrically connected to the second input end of the 30th NOR gate B30.

[0181] The output terminal of the twenty-ninth NOR gate B29 is electrically connected to the first input terminal of the thirtieth NOR gate B30. The second input terminal of the twenty-ninth NOR gate B29 is electrically connected to the output terminal of the thirtieth NOR gate B30 and serves as the control signal terminal S-Q3 of Q3.

[0182] The positive terminal of the thirty-first comparator A31 is electrically connected to -300mV, the negative terminal of the thirty-first comparator A31 is electrically connected to AC1, and the output terminal of the thirty-first comparator A31 is electrically connected to the first input terminal of the thirty-first NOR gate B31.

[0183] The positive end of the thirty-second comparator A32 is electrically connected to AC1, the reverse end of the thirty-second comparator A32 is electrically connected to the first end of the eighth reference voltage source VREF8, the second end of the eighth reference voltage source VREF8 is electrically connected to 0mV, and the output end of the thirty-second comparator A32 is electrically connected to the second input end of the thirty-second NOR gate B32.

[0184] The output terminal of the thirty-first NOR gate B31 is electrically connected to the first input terminal of the thirty-second NOR gate B32. The second input terminal of the thirty-first NOR gate B31 is electrically connected to the output terminal of the thirty-second NOR gate B32 and serves as the control signal terminal S-Q2 of Q3.

[0185] In the sixth embodiment, by setting the zero current detection threshold of the power tube, by detecting VREF5, VREF6, VREF7 and VREF8, when it is greater than 0mV, Q1, Q4, Q2 and Q3 are controlled to be turned off, that is, Q1, Q4, Q2 and Q3 are turned off with delay, so as to achieve the purpose of ASK modulation. It is possible to reduce or remove off-chip capacitors, on-chip switch tubes and chip pins without affecting the ASK modulation effect.

[0186] In the six embodiments of the present application, during the state switching process between the first rectifier branch and the second rectifier branch, the power tube is controlled to be delayed to be turned off by inserting a shutdown delay and setting the zero current detection threshold of the power tube, forming a short discharge current loop for VRECT, so that the current of the receiving end coil changes, thereby causing the current of the transmitting end coil to change, thereby realizing the ASK modulation function. In the specific implementation method, embodiment one and embodiment two are unilateral modulation, and the power tube is controlled to be delayed to be turned off by inserting a configurable shutdown delay at the drive of the circuit; embodiment three and embodiment four are unilateral modulation, and the power tube is controlled to be delayed to be turned off by setting the zero current detection threshold of the power tube; embodiment five and embodiment six are bilateral modulation, wherein embodiment five inserts a configurable shutdown delay at the drive of the circuit to control the power tube to be delayed to be turned off; embodiment six controls the power tube to be delayed to be turned off by setting the zero current detection threshold of the power tube. The above six embodiments can all form a short discharge current loop for VRECT to realize the ASK modulation function. It can reduce or remove off-chip capacitors, on-chip switch tubes and chip pins without affecting the ASK modulation effect.

[0187] The present application embodiment provides an ASK modulation method for a wireless charging receiving end, see Fig.13The method is applied to the above-mentioned ASK modulation circuit for the wireless charging receiving end, and the method comprises:

[0188] S1, in the modulation mode, during the process of the first rectifier branch or the second rectifier branch switching from the first state to the second state, the first rectifier branch or the second rectifier branch is controlled to switch from the first state to the second state after a preset time period, wherein the first state is the on state and the second state is the off state.

[0189] In a possible implementation, the above-mentioned S1 includes: in the modulation mode, when the first rectifier branch or the second rectifier branch is switching from the first state to the second state, when the current in the first rectifier branch or the second rectifier branch passes through zero, the first rectifier branch or the second rectifier branch is controlled to switch from the first state to the second state after a preset time period.

[0190] In a possible implementation, the above-mentioned S1 includes: in the modulation mode, when the first rectifier branch or the second rectifier branch switches from the first state to the second state, when the current of the first rectifier branch or the second rectifier branch is a preset threshold, controlling the first rectifier branch or the second rectifier branch to switch from the first state to the second state.

[0191] In a possible implementation, the above-mentioned S1 includes: in the modulation mode, when the first rectifier branch is switching from the first state to the second state, when the current in the first rectifier branch passes through zero, the first rectifier branch is controlled to switch from the first state to the second state after a preset time period; when the second rectifier branch is switching from the first state to the second state, when the current in the second rectifier branch passes through zero, the second rectifier branch is controlled to switch from the first state to the second state after a preset time period.

[0192] In a possible implementation, the above-mentioned S1 includes: in the modulation mode, during the process of switching the first rectifier branch from the first state to the second state, when the current of the first rectifier branch is a preset threshold value, controlling the first rectifier branch to switch from the first state to the second state; during the process of switching the second rectifier branch from the first state to the second state, when the current of the second rectifier branch is a preset threshold value, controlling the second rectifier branch to switch from the first state to the second state.

[0193] In a possible implementation manner, the method further includes: S2, in the unmodulated mode, controlling the first rectifying branch and the second rectifying branch to switch between the first state and the second state.

[0194] An embodiment of the present application provides a chip, including the above-mentioned ASK modulation circuit for a wireless charging receiving end.

[0195] An embodiment of the present application provides an electronic device, comprising the above-mentioned chip.

[0196] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. An ASK modulation circuit for a wireless charging receiving end, characterized in that: The circuit comprises: a logic control circuit and a rectifier circuit, the rectifier circuit comprises a first power tube, a second power tube, a third power tube and a fourth power tube, the first power tube is connected in series with the second power tube, the third power tube is connected in series with the fourth power tube, the first power tube and the second power tube are connected in parallel with the third power tube and the fourth power tube, the rectifier circuit comprises a first rectifier branch and a second rectifier branch, wherein the first rectifier branch comprises the first power tube and the fourth power tube, and the second rectifier branch comprises the second power tube and the third power tube; The logic control circuit is used to control the first rectifier branch or the second rectifier branch to switch from the first state to the second state after a preset time period in the modulation mode, when the first rectifier branch or the second rectifier branch switches from the first state to the second state, wherein the first state is the on state and the second state is the off state.

2. The ASK modulation circuit for a wireless charging receiving end according to claim 1, characterized in that: The logic control circuit is specifically used to control the first rectifier branch or the second rectifier branch to switch from the first state to the second state after a preset time period when the current in the first rectifier branch or the second rectifier branch passes through zero in the modulation mode.

3. The ASK modulation circuit for a wireless charging receiving end according to claim 1, characterized in that: The logic control circuit is specifically used to control the first rectifier branch or the second rectifier branch to switch from the first state to the second state in the modulation mode, when the current of the first rectifier branch or the second rectifier branch is a preset threshold value.

4. The ASK modulation circuit for a wireless charging receiving end according to claim 1, characterized in that: The logic control circuit is specifically used for controlling the first rectifying branch to switch from the first state to the second state after a preset time period when the current of the first rectifying branch passes through zero when the first rectifying branch switches from the first state to the second state in the modulation mode; During the process of the second rectifying branch switching from the first state to the second state, when the current in the second rectifying branch passes through zero, the second rectifying branch is controlled to switch from the first state to the second state after a preset time period.

5. The ASK modulation circuit for a wireless charging receiving end according to claim 1, characterized in that: The logic control circuit is specifically used to control the first rectifying branch to switch from the first state to the second state when the current of the first rectifying branch is a preset threshold value during the process of the first rectifying branch switching from the first state to the second state in the modulation mode; During the process of switching the second rectifying branch from the first state to the second state, when the current of the second rectifying branch reaches a preset threshold, the second rectifying branch is controlled to switch from the first state to the second state.

6. The ASK modulation circuit for a wireless charging receiving end according to any one of claims 1 to 5, characterized in that: The logic control circuit is further used to control the first rectifying branch and the second rectifying branch to switch between the first state and the second state in the unmodulated mode.

7. An ASK modulation method for a wireless charging receiving end, characterized in that: The method is applied to the ASK modulation circuit for a wireless charging receiving end according to any one of claims 1 to 5, and the method comprises: In the modulation mode, when the first rectifier branch or the second rectifier branch switches from a first state to a second state, the first rectifier branch or the second rectifier branch is controlled to switch from the first state to the second state after a preset time period, wherein the first state is an on state and the second state is an off state.

8. The ASK modulation method for a wireless charging receiving end according to claim 7, characterized in that: The method is applied to the ASK modulation circuit for a wireless charging receiving end as claimed in claim 2, and the method comprises: In the modulation mode, when the first rectifier branch or the second rectifier branch is switching from the first state to the second state, when the current in the first rectifier branch or the second rectifier branch passes through zero, the first rectifier branch or the second rectifier branch is controlled to switch from the first state to the second state after a preset time.

9. The ASK modulation method for a wireless charging receiving end according to claim 7, characterized in that: The method is applied to the ASK modulation circuit for a wireless charging receiving end as claimed in claim 3, and the method comprises: In the modulation mode, during the process of the first rectifier branch or the second rectifier branch switching from the first state to the second state, when the current of the first rectifier branch or the second rectifier branch is a preset threshold, the first rectifier branch or the second rectifier branch is controlled to switch from the first state to the second state.

10. The ASK modulation method for a wireless charging receiving end according to claim 7, characterized in that: The method is applied to the ASK modulation circuit for a wireless charging receiving end as claimed in claim 4, and the method comprises: In the modulation mode, during the process of switching the first rectifier branch from the first state to the second state, when the current in the first rectifier branch passes through zero, the first rectifier branch is controlled to switch from the first state to the second state after a preset time period; during the process of switching the second rectifier branch from the first state to the second state, when the current in the second rectifier branch passes through zero, the second rectifier branch is controlled to switch from the first state to the second state after a preset time period.

11. The ASK modulation method for a wireless charging receiving end according to claim 7, characterized in that: The method is applied to the ASK modulation circuit for a wireless charging receiving end as claimed in claim 5, and the method comprises: In the modulation mode, during the process of switching the first rectifier branch from a first state to a second state, when the current of the first rectifier branch is a preset threshold value, the first rectifier branch is controlled to switch from the first state to the second state; during the process of switching the second rectifier branch from a first state to a second state, when the current of the second rectifier branch is a preset threshold value, the second rectifier branch is controlled to switch from the first state to the second state.

12. The ASK modulation method for a wireless charging receiving end according to claim 7, characterized in that: The method further comprises: In the unmodulated mode, the first rectifying branch and the second rectifying branch are controlled to switch between the first state and the second state.

13. A chip, characterized in that: include: An ASK modulation circuit for a wireless charging receiving end as described in any one of claims 1 to 6.

14. An electronic device, characterized in that: include: The chip as claimed in claim 13.

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