Switching power supply system with self-powered control architecture

Abstract

The invention discloses a switching power supply system with a self-powered control architecture, and relates to the technical field of switching power supplies, the switching power supply system comprises a control chip and a power conversion circuit, the control chip comprises a power switching circuit, a start control circuit and a self-powered control circuit; the power switch circuit comprises a normally open high-voltage power switch and a low-voltage enhanced power switch which are connected in series; the drain end of the normally open high-voltage power switch is connected with the power conversion circuit; the gate end of the normally open high-voltage power switch is connected with the source end of the low-voltage enhanced power switch; a series node of the normally open high-voltage power switch and the low-voltage enhanced power switch is connected with the starting control circuit and the self-powered control circuit, and the starting control circuit and the self-powered control circuit are connected with a power supply VDD end of the control chip. According to the system, the self-power supply of the control chip can be realized, the VDD pin of the chip can be conveniently controlled below a lower voltage, and the device cost and the use cost can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supplies, and in particular to a switching power supply system with a self-powered control architecture. Background Art

[0002] The commonly used AC-DC (AC to DC) flyback power supply system is as follows Figure 1 As shown, it is a resistor start mode. After the AC voltage passes through the EMI filter EMI filer E2, it is rectified into a DC voltage Vbuck2 through the full-wave rectifier bridge B2 and the capacitor C10. The capacitor C13 is charged through the starting resistors Rst1 and Rst2 (usually 200V withstand voltage resistors), and the voltage of the capacitor C13 begins to rise. When the voltage of the capacitor C13 rises to a voltage exceeding the voltage set by the undervoltage lockout UVLO of the PWM control chip IC2 (for example, 15V), the undervoltage lockout is released, and the driving circuit of the PWM control chip IC2 starts to work. It can receive the pwm signal and drive the power MOS M10 to turn on and off to adjust the duty cycle, and finally achieve a stable output of the output voltage Vo. When the pwm signal starts to work, the transformer auxiliary winding AUX and the diode D11 charge the capacitor C13 to power IC2. The auxiliary winding Aux of the power transformer for IC2 is in phase with the output winding Sec, and the VDD voltage is proportional to the output voltage Vo. For some systems with variable output voltage Vo, such as Figure 2 The USB PD fast charging power supply system shown in the figure, in which IC4 is a USB PD protocol IC, and its CC1 / CC2 / DP / DN pins communicate with the load device (such as mobile phones, notebooks, etc.) through the TYPE-C interface. According to the voltage required by the load device, the voltage divider ratio of R0 / R1 is changed through the VFB pin to achieve the change of the output voltage. For USB PD3.0, the output voltage range is 3~21V, while USB PD3.1 requires an output voltage of 3~48V; the power supply voltage of IC3 is proportional to the output voltage Vo3. If the output Vo3 is 7 times the voltage of 3~21V, the power supply voltage VCC of IC3 is also required to be 7 times the voltage range. If the minimum power supply voltage of IC3 is 10V, the maximum operating voltage of IC3 is required to be at least 70V; if Vo3 is 16 times the voltage of 3~48V, the operating voltage range of IC3 needs to be 10~160V, which is a very wide requirement for the operating voltage range of IC3.

[0003] In summary, the existing switching power supply system has the following defects:

[0004] 1) Based on the resistor-based starting power supply system, after the starting process is completed, the starting resistor is still consuming current, resulting in power consumption, which does not meet the requirements of the low standby power consumption energy efficiency standard;

[0005] 2) After startup, the transformer auxiliary winding, a diode and a capacitor are required to power the controller chip, especially for fast-charging power supply systems with variable output voltage. Since the controller supply voltage and output voltage are proportional, the VDD power pin of the controller chip requires a very high voltage resistance range, which greatly increases the cost of the controller IC. Summary of the invention

[0006] The present invention provides a switching power supply system with a self-powered control architecture, which can solve the above-mentioned problem.

[0007] In order to solve the above problems, the technical solution adopted by the present invention is as follows:

[0008] The present invention provides a switching power supply system with a self-powered control architecture, comprising a control chip and a power conversion circuit, wherein the control chip comprises a power switch circuit, a startup control circuit and a self-powered control circuit; the power switch circuit comprises a normally-open high-voltage power switch and a low-voltage enhanced power switch connected in series; the drain end of the normally-open high-voltage power switch is connected to the power conversion circuit; the gate end of the normally-open high-voltage power switch is connected to the source end of the low-voltage enhanced power switch; the series node of the normally-open high-voltage power switch and the low-voltage enhanced power switch is connected to the startup control circuit and the self-powered control circuit, and the startup control circuit and the self-powered control circuit are connected to the power supply VDD end of the control chip.

[0009] Furthermore, the control chip also includes a driving circuit connected to the gate of the low-voltage enhanced power switch, the output side of which is connected to the logic AND gate of the driving circuit, an inverter and a PWM generating circuit connected to the input side of the logic AND gate, and a level conversion circuit connected to the input side of the PWM generating circuit; the self-powered control circuit is connected to the output side of the PWM generating circuit and the input side of the inverter; the undervoltage lockout signal output end of the startup control circuit is connected to the input side of the logic AND gate; and the power supply VDD end of the control chip is connected to a bypass capacitor.

[0010] Furthermore, the turn-on voltage of the normally-on high-voltage power switch is negative, and it is a high-voltage depletion-type metal oxide semiconductor field effect transistor or a high-voltage depletion-type gallium nitride high electron mobility transistor; the turn-on voltage of the low-voltage enhancement-type power switch is positive, and it is a low-voltage enhancement-type metal oxide semiconductor field effect transistor.

[0011] Furthermore, the input of the level conversion circuit is connected to the source of the low voltage enhancement mode power switch through a current detection resistor Rs.

[0012] Specifically, the startup control circuit includes resistors R4 and R5, N-type MOS switches M3 and M4, a diode D2, and an undervoltage lockout circuit; one end of the resistor R5 is connected to the connection line between the normally-open high-voltage power switch and the low-voltage enhanced power switch, and the self-powered control circuit; the other end of the resistor R5 is connected to one end of the resistor R4 and the drain of the switch M3; the source of the switch M3 is connected to the anode of the diode D2, and the gate is connected to the other end of the resistor R4 and the drain of the switch M4; the gate of the switch M4 is connected to the logic AND gate and the undervoltage lockout circuit; the input end of the undervoltage lockout circuit is connected to the diode D2, the bypass capacitor and the self-powered control circuit.

[0013] Specifically, the self-powered control circuit includes an N-type MOS switch M7, a P-type MOS switch M5, M6, resistors R7, R8, R9, R10, comparators cmp1, cmp2, ​​a diode D3, a logic NOR gate nor2, and a D flip-flop DFF1; the source of the switch M5 is connected to the source of the switch M6, one end of the resistor R7, and the resistor R5; the drain of the switch M5 is connected to the positive input end of the comparator cmp1 and the positive electrode of the diode D3; the gate of the switch M5 is connected to one end of the resistor R8, the other end of the resistor R7, and the gate of the switch M6; the resistor The other end of R8 is connected to the drain of switch M7; the gate of switch M7 is connected to the output of D flip-flop DFF1 and the input of inverter; the drain of switch M6 is connected to the negative input of comparator cmp1, and the output of comparator cmp1 is connected to logic NOR gate nor2; the cathode of diode D3 is connected to bypass capacitor and one end of resistor R9; the other end of resistor R9 is connected to resistor R10 and the positive input of comparator cmp2; the negative input of comparator cmp2 is connected to reference voltage, and the output is connected to logic NOR gate nor2; the output of logic NOR gate nor2 is connected to D flip-flop DFF1.

[0014] Furthermore, the charging of the bypass capacitor at the VDD end by the series node of the normally-open high-voltage power switch and the low-voltage enhanced power switch via the self-powered control circuit only occurs when the PWM generating circuit outputs a high-level pwm signal.

[0015] Optionally, the power conversion circuit is a flyback circuit, a forward circuit, a buck circuit, a boost circuit, a half-bridge circuit or a full-bridge circuit.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] 1) After the power supply is started, the startup circuit is completely disconnected. The startup circuit does not consume any power after normal operation, which greatly improves the no-load or light-load standby power consumption of the power supply system and can easily meet the most stringent standby power consumption and energy efficiency standards;

[0018] 2) The self-powered control circuit can control the VDD overvoltage protection voltage setting value, which is independent of the output voltage. The VDD pin can be controlled below a lower voltage, greatly saving the cost of the controller; and under the condition that the controller consumes the same operating current, the power consumed by the controller is also lower due to the low VDD voltage.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the embodiments of the present invention are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 This is a diagram of an existing AC-DC flyback power supply system;

[0022] Figure 2 This is a diagram of the existing USB PD fast charging power supply system;

[0023] Figure 3 is a diagram of a flyback switching power supply system with a self-powered control architecture according to an embodiment;

[0024] Figure 4 1 is a working principle diagram of the starting circuit in the embodiment;

[0025] Figure 5 Schematic diagram of the working principle of the self-powered control circuit in the embodiment. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments.

[0027] Please refer to Figure 3 This embodiment discloses a flyback switching power supply system with a self-powered control architecture, including a control chip IC1 and a power conversion circuit; the power conversion circuit includes an EMI filter E1, a rectifier bridge B1, capacitors C1, C2, Cout, a snubber circuit, a transformer T1, a diode D1, resistors R0, R1, R2, R3, a voltage regulator tube TL431, and an optical coupler OPTO. The control chip IC1 is connected to a bypass capacitor C3 and a resistor Rs.

[0028] The control chip IC1 integrates a startup control circuit, a self-powered control circuit, a power switch circuit (including a normally-open high-voltage power switch PM1 and a low-voltage enhanced power switch PM2 connected in series (an N-type MOS switch is selected in this embodiment), the turn-on voltage Vth of the normally-open high-voltage power switch PM1 is negative, and can be a high-voltage depletion metal oxide semiconductor field effect transistor or a high-voltage depletion gallium nitride high electron mobility transistor, and the turn-on voltage of the low-voltage enhanced power switch PM2 is positive), logic gates inv1 and AND1, a drive circuit, a level conversion circuit, and a PWM generation circuit.

[0029] The startup control circuit includes an undervoltage lockout circuit, switches M3 and M4 (both are N-type MOS switches), resistors R4 and R5, and a diode D2.

[0030] The self-powered control circuit includes P-type MOS switches M5 and M6, an N-type MOS switch M7, resistors R7, R8, R9 and R10, a diode D3, comparators cmp1 and cmp2, ​​a logic gate nor2, and a D flip-flop DFF1.

[0031] The working principle of the startup control circuit is as follows:

[0032] Figure 3 After AC is connected, the voltage of Vbuck node becomes DC high voltage after rectification by rectifier bridge B1. For example, if AC is connected with 220V voltage, the voltage of Vbuck is √2×220=311V. Figure 3 The normally-on high-voltage power switch PM1 is a high-voltage depletion-type metal oxide semiconductor field effect transistor or a high-voltage depletion-type gallium nitride high electron mobility transistor, whose turn-on voltage Vth is a negative voltage, for example, Vth=-20V, and the breakdown voltage BV=700V; while PM2 is a low-voltage enhancement MOSFET, whose turn-on voltage Vth is a positive voltage, for example, Vth=3V, and the breakdown voltage BV=40V. Figure 3When the VDD pin voltage of the control chip IC1 is in the undervoltage lockout state, the undervoltage lockout UVLO output signal pg is "0", which is input to the logic "AND" gate AND1 and then outputs a "0" signal to the drive circuit output drv is "0", turning off the low-voltage enhanced power switch PM2. Assuming that the PM1 turn-on voltage is V = -20V, the Vsd node voltage is 20V at this time; the Vsd node passes through the current limiting resistor R5, the switch M3, and the diode D2 to the VDD pin of the control chip IC1 and then to the external capacitor C3. Since the undervoltage lockout UVLO output pg is "0", the switch M4 is closed, and the resistor R4 pulls up the gate terminal Vg_m3 of the switch M3 to turn on M3; therefore, the Vbuck voltage passes through the transformer T1, the DRAIN pin of the control chip IC1, the normally open high-voltage power switch PM1, the current limiting resistor R5, the switch M3, the diode D2, and the VDD pin of the control chip IC1 to charge the external capacitor C3, and VDD The pin voltage rises until it exceeds the undervoltage lockout UVLO voltage (for example, 12V). The undervoltage lockout UVLO outputs the pg signal as a high level "1". The pg high level "1" turns on the M4 switch to pull the gate terminal Vg_m3 voltage of the M3 NMOS down to "0". The switch M3 is closed, and the charging of the VDD pin is stopped. The startup circuit completes the entire startup work, and then the pwm generation circuit starts to work normally, and the drive circuit drv starts to output a pulse level signal, such as Figure 4 shown.

[0033] The working principle of the self-powered control circuit is as follows:

[0034] When the start control circuit completes the start, Figure 3 The pwm generating circuit starts to work normally; when Figure 3 When the rising edge signal of the pwm signal output by the pwm generating circuit to the D flip-flop DFF1 arrives, the output signal pwm_ch of the D flip-flop DFF1 is set to a high level "1". This high level turns on the M7 NMOS and sets the Vg_m5 signal to a low level signal through the resistor R8. The Vg_m5 low level signal turns on the main power switch M5 PMOS and the current detection switch M6. At this time, the pwm_ch signal passes through the inverter inv1 to the input end of the logic "AND" gate AND1, and passes through the drive circuit so that the output drv of the drive circuit is still maintained at a low level "0", turning off the low-voltage enhanced power switch PM2; and the normally open high-voltage power switch PM1 is turned on, and the Vbuck voltage passes through the transformer T1, the IC1 DRAIN pin, the normally open high-voltage power switch PM1, and then through the switch M5 and the diode D3 to IC1 VDD pin, the external capacitor C3 is charged, the capacitor voltage VCC of C3 rises, and the charging current Ic of C3 also rises linearly. When the charging current Ic exceeds the ocp overcurrent setting value Iocp ( Figure 3The switch M5, switch M6, reference current Iref, and comparator cmp1 form the overcurrent ocp detection circuit of the M5 switch. Assuming that the size ratio of the switch M5 and M6 tubes is N, then Iocp = N*Iref, for example, N = 1000, Iref = 300uA, then Iocp = 1000*300uA = 300mA), then the cmp1 comparator outputs the ocp signal as a high level "1", and after passing through the logic NOR gate nor2, it outputs "0" to the reset terminal R of the D flip-flop DFF1, and sets the pwm_ch signal output by the D flip-flop DFF1 to "0". When the pwm_ch signal is "0", the switch M7 is turned off, and then the resistor R7 pulls the Vg_m5 voltage to a high level to turn off the switch M5, thereby VDD of IC1 The external C3 capacitor of pin stops charging; after the pwm_ch signal outputs "0", it passes through the inverter inv1 and outputs a logic "1" signal to the input end of the logic AND gate AND1. At this time, the logic AND gate AND1 can transmit the high-level "1" signal of the pwm generating circuit output signal pwm to the drive circuit, so that the drive circuit outputs drv as a high level "1". This high level turns on Figure 3 The low-voltage enhanced power switch PM2 in the circuit, Vbuck voltage passes through transformer T1, IC1 DRAIN pin, normally open high-voltage power switch PM1, low-voltage enhanced power switch PM2, and then to current sampling resistor Rs, and finally reaches IC ground terminal ic_gnd. The current on transformer T1 rises linearly, and the voltage Vcs (Vcs is a negative voltage relative to IC ground ic_gnd) on current sampling resistor Rs decreases linearly. The voltage of current detection resistor Rs passes through IC1 CS pin, and then through level conversion circuit (converting negative voltage into positive voltage) and then sent to pwm generation circuit until Figure 3 The output voltage Vcs_int of the level conversion circuit and the voltage of the FB pin generate a pwm shutdown signal, then the pwm generating circuit outputs pwm as a low level "0", and after the logic AND1 to the drive circuit output drv as "0", shutting down Figure 3 The medium and low voltage enhanced power switch PM2 is turned on until the next cycle of the PWM rising edge arrives, and the above process is repeated. This process realizes Figure 3 The charging process of the external capacitor C3 connected to the IC1 VDD pin and the power supply process of the capacitor C3 to IC1, such as Figure 5 As shown in cycles 1 and 2.

[0035] Since the C3 capacitor is charged in each cycle, when the C3 capacitor voltage, i.e. the VDD voltage in IC1, reaches the overvoltage protection setting value ( Figure 3The resistor R9, the resistor R10, the comparator cmp2, ​​and the reference voltage vref form a VDD overvoltage protection circuit; when the VDD voltage exceeds the reference voltage vref through the R9 / R10 resistor divider, the comparator cmp2 outputs a high level, which is output to the reset terminal R of the D flip-flop DFF1 through the logic NOR gate nor2, setting the pwm_ch signal to "0". The subsequent process is the same as the OCP protection described above, and the OCP protection is turned off. Figure 3 The middle switch M5 turns on the low-voltage enhanced power switch PM2 until the pwm generating circuit output signal pwm is "0" and then turns off the low-voltage enhanced power switch PM2; therefore, the overvoltage protection voltage For example, if R9=1200K ohms, R10=200K ohms, Vref=2V, then Vovp=14V). Figure 5 As shown in cycles 3 and 4.

[0036] The self-powered control circuit is combined with a PWM generation circuit. Figure 3 The charging of the external capacitor C3 of the VDD pin of the control chip IC1 only occurs when the output signal pwm of the pwm generating circuit is at a high level, that is, the opening of the switch M5 only occurs when the pwm signal is at a high level. Figure 5 That is, pwm_ch is in the high level stage (its high level time will not exceed the pwm high level time); further, Figure 3 The time when the pwm generating circuit outputs the pwm signal at a high level is divided into two parts, one of which is when the switch M5 is turned on. Figure 5In the high-level stage, the transformer T1 enters the energy storage state and charges the external capacitor C3 of the VDD pin of the controller IC1 at the same time. The transformer current rises linearly, which is reflected in the linear decrease of the voltage of the current sampling resistor Rs. When the pwm_ch is low, M5 is turned off to end the charging of the capacitor C3. Then the low-voltage enhanced power tube PM2 is turned on through the driving circuit, and the transformer T1 continues to maintain the energy storage state and the current of the transformer T1 continues to rise linearly, which is reflected in the voltage of the current sampling resistor Rs continues to decrease linearly until the pwm signal is low. The energy stored in the transformer is released to the output capacitor Cout through the diode D1. That is to say, the charging of the external capacitor C3 of the controller VDD only occurs in the energy storage stage of the transformer T1, and the Vbuck voltage minus the VDD voltage of IC1 falls on the transformer T1. The pri terminal (i.e., Vbuck and drain voltage) stores energy in the transformer; the benefit is that the power consumption of the controller IC1 is the VDD voltage of the controller IC1 multiplied by the operating current of IC1 (because the Vbuck voltage minus the VDD voltage, that is, the excess voltage is used to store energy in the transformer and is not wasted), and if the external capacitor of the controller IC1 VDD occurs in the non-pwm signal high level stage, the power consumption of the controller IC1 is the Vbuck voltage multiplied by the operating current of IC1. The difference in the power consumption of IC1 caused by these two is huge; for example, assuming that the operating current of the controller IC1 is 1mA, the IC1 VDD voltage is controlled at 14V (VDD overvoltage protection voltage) through the above power supply control method, then the power consumption of IC1 is 14V×1mA=14mW; if Figure 3 The AC input voltage is 220AC, then the Vbuck voltage is 311V. If the above power supply control method is not used, that is, the capacitor C3 is not charged during the energy storage stage of the voltage regulator T1, the power consumption of the controller IC1 is 311V×1mA=311mW, which is a huge difference compared to the 14mW power consumption of IC1, and the low standby power consumption requirement cannot be achieved. The above shows that this power supply control method not only realizes the self-power supply function and saves components, but also realizes the advantage of low standby power consumption.

[0037] The flyback switching power supply system with a self-powered control architecture described in this embodiment has the following advantages:

[0038] 1)Comparison Figure 1 The traditional flyback power supply system control architecture saves high-voltage startup resistors Rst1 and Rst2, transformer auxiliary winding Aux, rectifier diode D11 and other devices, greatly saving system costs; after the power supply is started, the startup circuit is completely disconnected, and the startup circuit does not consume any power after normal operation ( Figure 1The traditional flyback power supply startup resistor Rst1 / Rst2 still consumes power after startup is completed), which greatly improves the power consumption of the power system when it is idle or lightly loaded, and can easily meet the most stringent standby power consumption and energy efficiency standards.

[0039] 2) Comparison Figure 2 The traditional flyback fast charging power supply system saves high-voltage startup resistors Rst3 and Rst4, transformer auxiliary winding Aux, rectifier diode D32 and other components, greatly saving system costs; since the self-powered control circuit can control the VDD overvoltage protection voltage setting value (for example, 14V), which is independent of the output voltage Vo3, the voltage range of the VDD pin can be controlled below 15V. Figure 2 The VDD operating range of the controller IC3 is 10~70V or 10~160V, which can greatly save the cost of the controller IC3; and under the condition that the controller consumes the same working current, the power consumed by the controller is also lower due to the low VDD voltage; at the same time, the self-starting circuit also eliminates the need for Figure 2 The startup resistors Rst3 / Rst4 in the circuit are removed, so the increase in standby power consumption caused by the startup resistors Rst3 / Rst4 is also eliminated. This greatly improves the no-load or light-load standby power consumption of the power system, and can easily meet the most stringent standby power consumption and energy efficiency standards.

[0040] The above example is a method of using a high-voltage normally-on power switch (the turn-on voltage Vth is a negative voltage), such as a high-voltage depletion-type metal oxide semiconductor field effect transistor or a high-voltage depletion-type gallium nitride high electron mobility transistor in series with a low-voltage enhancement-type MOSFET, to implement a control method for a startup circuit or a self-powered circuit in a flyback power supply system. It only serves as an example and should not be limited to this architecture; it can be applied to other power topology architectures (such as forward, Buck, Boost, Buck-boost, etc. topology architectures).

[0041] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A switching power supply system with a self-powered control architecture, characterized in that: It comprises a control chip and a power conversion circuit, wherein the control chip comprises a power switch circuit, a startup control circuit and a self-powered control circuit; the power switch circuit comprises a normally-open high-voltage power switch and a low-voltage enhanced power switch connected in series; the drain end of the normally-open high-voltage power switch is connected to the power conversion circuit; the gate end of the normally-open high-voltage power switch is connected to the source end of the low-voltage enhanced power switch; the series node of the normally-open high-voltage power switch and the low-voltage enhanced power switch is connected to the startup control circuit and the self-powered control circuit, and the startup control circuit and the self-powered control circuit are connected to the power supply VDD end of the control chip.

2. The switching power supply system with a self-powered control architecture according to claim 1, characterized in that: The control chip also includes a drive circuit connected to the gate of the low-voltage enhanced power switch, an output side connected to a logic AND gate of the drive circuit, an inverter and a PWM generating circuit connected to the input side of the logic AND gate, and a level conversion circuit connected to the input side of the PWM generating circuit; the self-powered control circuit is connected to the output side of the PWM generating circuit and the input side of the inverter; the undervoltage lockout signal output end of the startup control circuit is connected to the input side of the logic AND gate; and the power supply VDD end of the control chip is connected to a bypass capacitor.

3. The switching power supply system with a self-powered control architecture according to claim 2, characterized in that: The normally-on high-voltage power switch has a negative turn-on voltage and is a high-voltage depletion-type metal oxide semiconductor field effect transistor or a high-voltage depletion-type gallium nitride high electron mobility transistor; the normally-on high-voltage enhancement-type power switch has a positive turn-on voltage and is a low-voltage enhancement-type metal oxide semiconductor field effect transistor.

4. The switching power supply system with a self-powered control architecture according to claim 3, characterized in that: The input of the level conversion circuit is connected to the source of the low voltage enhancement mode power switch through the current detection resistor Rs.

5. The switching power supply system with a self-powered control architecture according to claim 3, characterized in that: The startup control circuit includes resistors R4 and R5, N-type MOS switches M3 and M4, a diode D2, and an undervoltage lockout circuit; one end of the resistor R5 is connected to the connection line between the normally open high-voltage power switch and the low-voltage enhanced power switch, and the self-powered control circuit; the other end of the resistor R5 is connected to one end of the resistor R4 and the drain of the switch M3; the source of the switch M3 is connected to the positive electrode of the diode D2, and the gate is connected to the other end of the resistor R4 and the drain of the switch M4; the gate of the switch M4 is connected to the logic AND gate and the undervoltage lockout circuit; the input end of the undervoltage lockout circuit is connected to the diode D2, the bypass capacitor and the self-powered control circuit.

6. The switching power supply system with a self-powered control architecture according to claim 5, characterized in that: The self-powered control circuit includes an N-type MOS switch M7, P-type MOS switches M5 and M6, resistors R7, R8, R9 and R10, comparators cmp1 and cmp2, ​​a diode D3, a logic NOR gate nor2 and a D flip-flop DFF1; the source of the switch M5 is connected to the source of the switch M6, one end of the resistor R7 and the resistor R5; the drain of the switch M5 is connected to the positive input end of the comparator cmp1 and the positive electrode of the diode D3; the gate of the switch M5 is connected to one end of the resistor R8, the other end of the resistor R7 and the gate of the switch M6; the resistor R8 The other end is connected to the drain of switch M7; the gate of switch M7 is connected to the output of D flip-flop DFF1 and the input of inverter; the drain of switch M6 is connected to the negative input of comparator cmp1, and the output of comparator cmp1 is connected to logic NOR gate nor2; the cathode of diode D3 is connected to bypass capacitor and one end of resistor R9; the other end of resistor R9 is connected to resistor R10 and the positive input of comparator cmp2; the negative input of comparator cmp2 is connected to reference voltage, and the output is connected to logic NOR gate nor2; the output of logic NOR gate nor2 is connected to D flip-flop DFF1.

7. The switching power supply system with a self-powered control architecture according to claim 1, characterized in that: The power conversion circuit is a flyback circuit, a forward circuit, a buck circuit, a boost circuit, a half-bridge circuit or a full-bridge circuit.

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