Transconductance-adjustable dual-output weak signal amplifier and electronic equipment
By using a differential voltage current transmitter transconductance amplifier in a weak signal amplifier and realizing transconductance adjustment, the problems of complex device matching and poor universality in the existing technology are solved, and efficient common mode suppression and adaptability are achieved.
Patent Information
- Application Number
- CN202411334657.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2025-01-24
AI Technical Summary
Existing weak signal amplifiers require highly matching devices, with complex circuit structures and poor universality.
A differential voltage and current transmitter transconductance amplifier is used as the weak signal amplification unit. The transconductance adjustment is realized through the reference voltage generation unit and the adjustable signal input terminal, eliminating common mode noise and adapting to various downstream equipment.
It achieves a circuit structure without component matching, simplifies the implementation process, improves the common mode rejection ratio and universality, and reduces power consumption.
Smart Images
Figure CN119363051A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of digital simulation technology, and in particular to a dual-output weak signal amplifier with adjustable transconductance and an electronic device. Background Art
[0002] With the increasing application of smart sensors and smart devices in various fields, various weak underlying signals can also be collected and extracted. In order to remove unnecessary interference such as environment and noise and ensure the accuracy and reliability of weak signal acquisition, the signal to be measured must first be pre-amplified, that is, a weak signal amplifier, to output a relatively ideal analog signal, and then the signal is converted into digital form and quantized for acquisition, so as to achieve accurate acquisition of weak signals from sensors.
[0003] The basic function of a weak signal amplifier is to amplify weak differential sensor signals and suppress unwanted common-mode signals such as noise and offset, while always maintaining the function of input signal amplification. Some amplifiers with classic structures, such as the classic voltage three-op amp structure, require external resistors to change the gain, and the internal resistors need to be highly matched; for example, the current mode op amp structure requires the two input op amps to be highly matched, otherwise the CMRR (Common Mode Rejection Ratio) will be greatly reduced, and the circuit structure is more complex; for example, the capacitor-coupled op amp structure determines the gain by the ratio of the input capacitor and the feedback capacitor. A large gain requires a large area, and the internal capacitors also need to be highly matched. The above classic structures require high matching of passive devices or active devices to achieve a high CMRR, and the circuits are relatively complex and difficult to implement. In addition, the output range of the above structures is fixed and can only be connected to downstream devices with a fixed acquisition range, and the universality is poor. Summary of the invention
[0004] The purpose of the embodiments of the present disclosure is to provide a dual-output weak signal amplifier and electronic equipment with adjustable transconductance, so as to solve the problems in the prior art of requiring high device matching, complex circuit structure and poor universality.
[0005] The embodiments of the present disclosure adopt the following technical scheme: a dual-output weak signal amplifier with adjustable transconductance, comprising: a reference voltage generating unit for generating a reference voltage; a weak signal amplifying unit, comprising at least a differential voltage and current transmitter transconductance amplifier, wherein the differential voltage and current transmitter transconductance amplifier has at least a first input terminal, a second input terminal, a reference voltage input terminal, an adjustable signal input terminal, a first output terminal, and a second output terminal, wherein the first input terminal and the second input terminal are used to connect to a differential first input voltage and a second input voltage, the reference voltage input terminal is connected to the output terminal of the reference voltage generating unit, the adjustable signal input terminal is connected to a current signal with adjustable size to modulate the transimpedance of the differential voltage and current transmitter transconductance amplifier, the first output terminal is used to output an amplified current signal, and the second output terminal is used to output an amplified voltage signal.
[0006] In some embodiments, the reference voltage generating unit includes at least: a first transistor and a second transistor; wherein the first electrode of the first transistor is connected to the operating voltage, the second electrode of the first transistor is connected to the second electrode of the second transistor, the gate of the first transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is grounded, the gate of the second transistor is connected to the second electrode of the second transistor, and the output end of the reference voltage generating unit is led out between the first transistor and the second transistor.
[0007] In some embodiments, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.
[0008] In some embodiments, the differential voltage current conveyor transconductance amplifier comprises at least: a third transistor to a twenty-second transistor and a first resistor;The gate of the third transistor leads to the first input terminal, the first electrode of the third transistor is connected to the second electrode of the ninth transistor, the second electrode of the third transistor is connected to the gate of the fifteenth transistor and the second electrode of the thirteenth transistor, the gate of the fourth transistor is grounded, the first electrode of the fourth transistor is connected to the second electrode of the ninth transistor, the second electrode of the fourth transistor is connected to the second electrode of the sixth transistor and the second electrode of the fourteenth transistor, the second electrode of the fifth transistor is connected to the gate of the fifteenth transistor and the second electrode of the third transistor, the gate of the fifth transistor leads to the second input terminal, the first electrode of the fifth transistor is connected to the first electrode of the sixth transistor and the second electrode of the tenth transistor The second electrode of the sixth transistor is connected to the second electrode of the fifteenth transistor and the second electrode of the eleventh transistor, the first electrode of the ninth transistor, the first electrode of the tenth transistor and the first electrode of the eleventh transistor are all grounded, the gates of the ninth transistor, the gates of the tenth transistor and the gates of the eleventh transistor are all connected to the reference voltage, the first electrode of the thirteenth transistor, the first electrode of the fourteenth transistor and the first electrode of the fifteenth transistor are all connected to the operating voltage, the gate of the thirteenth transistor is connected to the gate of the fourteenth transistor and the second electrode of the thirteenth transistor, the first electrode of the seventh transistor is connected to the first electrode of the eighth transistor, and the first electrode of the The adjustable signal input terminal is led out between the first electrode of the seventh transistor and the first electrode of the eighth transistor, the gate of the seventh transistor is grounded, the second electrode of the seventh transistor is connected to the second electrode of the sixteenth transistor, the gate of the eighth transistor is connected to the gate of the sixth transistor, the second electrode of the eighth transistor is connected to the second electrode of the seventeenth transistor, the gate of the sixteenth transistor is connected to the second electrode of the sixteenth transistor, the gate of the nineteenth transistor and the gate of the twentieth transistor, the gate of the seventeenth transistor is connected to the second electrode of the seventeenth transistor and the gate of the eighteenth transistor, the second electrode of the eighteenth transistor is connected to the second electrode of the twelfth transistor, and the gate of the sixteenth transistor is connected to the second electrode of the seventeenth transistor. The first electrode, the first electrode of the seventeenth transistor, the first electrode of the eighteenth transistor, the first electrode of the nineteenth transistor and the first electrode of the twentieth transistor are all connected to the working voltage, the first electrode of the twelfth transistor, the first electrode of the twenty-first transistor and the first electrode of the twenty-second transistor are all grounded, the gate of the twelfth transistor is connected to the gate of the twenty-first transistor and the gate of the second second transistor, the second electrode of the nineteenth transistor is connected to the second electrode of the twenty-first transistor and leads to the first output terminal, the second electrode of the twentieth transistor is connected to the second electrode of the twenty-second transistor and the first end of the first resistor and leads to the second output terminal, and the second end of the first resistor is grounded.;
[0009] In some embodiments, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the twenty-first transistor and the twenty-second transistor are all N-type transistors; the thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor and the twentieth transistor are all P-type transistors.
[0010] In some embodiments, the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are identical transistors.
[0011] In some embodiments, the thirteenth transistor, the fourteenth transistor, and the fifteenth transistor are identical transistors.
[0012] In some embodiments, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor, and the twentieth transistor are identical transistors.
[0013] In some embodiments, the adjustable signal input terminal is connected to an output terminal of an adjustable current source.
[0014] The embodiment of the present disclosure also provides an electronic device, which at least includes the dual-output weak signal amplifier with adjustable transconductance as described above.
[0015] The beneficial effects of the embodiments of the present disclosure are as follows: common-mode noise is eliminated through differential input signals, and an improved differential voltage-current transmitter transconductance amplifier is used as a weak signal amplification unit, wherein the circuit has no component matching problems and has a simple structure and is easy to implement; at the same time, the transconductance adjustment of the weak signal amplification unit is implemented based on a current signal with adjustable size, and the linearity of the output signal is made adjustable, so that it can be adapted to various downstream devices and cooperate with two different types of output terminals to achieve the purpose of improving universality. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0017] Figure 1 It is a structural schematic diagram of a dual-output weak signal amplifier with adjustable transconductance in the first embodiment of the present disclosure;
[0018] Figure 2 A schematic diagram of a specific implementation structure of a reference voltage generating unit in the first embodiment of the present disclosure;
[0019] Figure 3 It is a schematic diagram of a specific implementation structure of the differential voltage and current conveyor transconductance amplifier in the first embodiment of the present disclosure. DETAILED DESCRIPTION
[0020] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the following will be combined with the drawings in one or more embodiments of this specification to clearly and completely describe the technical solutions in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.
[0021] With the increasing application of smart sensors and smart devices in various fields, various weak underlying signals can also be collected and extracted. In order to remove unnecessary interference such as environment and noise and ensure the accuracy and reliability of weak signal acquisition, the signal to be measured must first be pre-amplified, that is, a weak signal amplifier, to output a relatively ideal analog signal, and then the signal is converted into digital form and quantized for acquisition, so as to achieve accurate acquisition of weak signals from sensors.
[0022] The basic function of a weak signal amplifier is to amplify weak differential sensor signals and suppress unwanted common-mode signals such as noise and offset, while always maintaining the function of input signal amplification. Some amplifiers with classic structures, such as the classic voltage three-op amp structure, require external resistors to change the gain, and the internal resistors need to be highly matched; for example, the current mode op amp structure requires the two input op amps to be highly matched, otherwise the CMRR will be greatly reduced, and the circuit structure is more complex; for example, the capacitor-coupled op amp structure determines the gain by the ratio of the input capacitor and the feedback capacitor. A large gain requires a large area, and the internal capacitors also need to be highly matched. The above classic structures require high matching of passive devices or active devices to achieve a high CMRR, and the circuits are relatively complex and difficult to implement. In addition, the output range of the above structures is fixed and can only be connected to downstream devices with a fixed acquisition range, and the universality is poor.
[0023] In order to solve the above problems, the first embodiment of the present disclosure provides a dual-output weak signal amplifier with adjustable transconductance, and its structural diagram is shown in FIG. Figure 1As shown, the reference voltage generating unit 10 and the weak signal amplifying unit 20 are mainly included. Specifically, the reference voltage generating unit 10 is mainly used to generate a reference voltage v b And the reference voltage V b Provided to the weak signal amplification unit 20; the weak signal amplification unit 20 mainly includes a differential voltage and current transmitter transconductance amplifier 21, the differential voltage and current transmitter transconductance amplifier 21 at least has a first input terminal, a second input terminal, a reference voltage input terminal, an adjustable signal input terminal, a first output terminal and a second output terminal, wherein the first input terminal and the second input terminal are used to access the differential first input voltage Vin1 and the second input voltage Vin2, the differential voltage and current transmitter transconductance amplifier 21 is used to amplify the input differential voltage and convert it into an amplified current signal Iout and an amplified voltage signal Vout, which are output from the first output terminal and the second output terminal respectively, and at the same time, the reference voltage input terminal is connected to the output terminal of the reference voltage generation unit 10 to receive the reference voltage V b The adjustable signal input terminal is connected to the adjustable current signal I b , to modulate the transimpedance of the differential voltage and current transmitter transconductance amplifier 21, so as to achieve linear adjustment of the output signal.
[0024] In this embodiment, the differential input signal is transmitted simultaneously through two paths in the form of voltage, with opposite phases but equal amplitudes. It is highly immune to external interference and can eliminate common-mode noise. It is combined with a differential voltage and current transmitter transconductance amplifier to amplify the input differential voltage and convert it into current output. The circuit has no component matching problems and has a simple structure and is easy to implement. The adjustable current signal is used to adjust the transconductance of the differential voltage and current transmitter transconductance amplifier to make the output signal adjustable, so that it can be adapted to various downstream devices and cooperate with two different types of output terminals to achieve the purpose of improving universality.
[0025] Figure 2 FIG. 2 is a schematic diagram showing a specific implementation structure of the reference voltage generating unit in this embodiment. Figure 2 As shown, the reference voltage generating unit at least includes a first transistor M1 and a second transistor M2, which are connected in series, wherein a first electrode of the first transistor M1 is connected to an operating voltage VCC, a second electrode of the first transistor M1 is connected to a second electrode of the second transistor M2, a gate of the first transistor M1 is connected to a second electrode of the first transistor M1, a first electrode of the second transistor M2 is grounded, a gate of the second transistor M2 is connected to a second electrode of the second transistor M2, and an output terminal of the reference voltage generating unit is led out between the first transistor M1 and the second transistor M2 to output a reference voltage V b .
[0026] exist Figure 2In the circuit structure shown, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor. The drains of the two are connected and lead out to the output end, that is, two opposite-polarity MOS transistors are connected in series to divide the voltage and bias. Since the current flowing through M1 and M2 is the same, the reference voltage V b The formula is as follows:
[0027]
[0028] k p =μ p pC ox (W / L) p (2)
[0029] k n =μ n C ox (W / L) n (3)
[0030] Among them, V TN is the threshold voltage of M2, V TP is the threshold voltage of M1, k n and k p are the process gain factors of M2 and M1, μ p is the hole mobility of M1, μ n is the hole mobility of M2, C ox is the oxide capacitance per unit area, (W / L) p is the width-to-length ratio of M1, (W / L) n is the width-to-length ratio of M2.
[0031] The reference voltage generating unit of this embodiment provides a reference voltage for the tail current source of the differential pair circuit inside the differential voltage and current transmitter transconductance amplifier, so that the tail current source works normally, thereby suppressing the influence of the change of the input common mode level on the operation of the input pair tube and the output level. It should be noted that Figure 2 The specific circuit of the reference voltage generating unit shown is only one of the structures that can be implemented. In the actual implementation process, other structures such as a resistor voltage divider circuit, a bandgap reference voltage source, a Zener diode reference voltage source, etc. can also be used for implementation. This embodiment does not impose specific restrictions as long as the stable reference voltage V b Just output it.
[0032] Figure 3 FIG. 2 shows a schematic diagram of a specific implementation structure of a differential voltage and current transmitter transconductance amplifier in this embodiment. Figure 3As shown, the differential voltage current transmitter transconductance amplifier at least includes a third transistor M3 to a twenty-second transistor M22 and a first resistor R, and the specific connection relationship between the above devices is: the gate of the third transistor M3 leads to the first input terminal, the first electrode of the third transistor M3 is connected to the second electrode of the ninth transistor M9, the second electrode of the third transistor M3 is connected to the gate of the fifteenth transistor M15 and the second electrode of the thirteenth transistor M13, the gate of the fourth transistor M4 is grounded, the first electrode of the fourth transistor M4 is connected to the second electrode of the ninth transistor M9, the second electrode of the fourth transistor M4 is connected to the second electrode of the sixth transistor M6 and the second electrode of the fourteenth transistor M14, the second electrode of the fifth transistor M5 is connected to the gate of the fifteenth transistor M15, and the gate of the fourth transistor M4 is grounded. The gate of the fifth transistor M5 leads to the second input terminal, the first electrode of the fifth transistor M5 is connected to the first electrode of the sixth transistor M6 and the second electrode of the tenth transistor M10, the gate of the sixth transistor M6 is connected to the second electrode of the fifteenth transistor M15 and the second electrode of the eleventh transistor M11, the first electrode of the ninth transistor M9, the first electrode of the tenth transistor M10 and the first electrode of the eleventh transistor M11 are all grounded, the gate of the ninth transistor M9, the gate of the tenth transistor M10 and the gate of the eleventh transistor M11 are all connected to the reference voltage, the first electrode of the thirteenth transistor M13, the first electrode of the fourteenth transistor M14 and the first electrode of the fifteenth transistor M15 are all connected to the working voltage VCC is connected, the gate of the thirteenth transistor M13 is connected to the gate of the fourteenth transistor M14 and the second electrode of the thirteenth transistor M13, the first electrode of the seventh transistor M7 is connected to the first electrode of the eighth transistor M8, an adjustable signal input terminal is led out between the first electrode of the seventh transistor M7 and the first electrode of the eighth transistor M8, the gate of the seventh transistor M7 is grounded, the second electrode of the seventh transistor M7 is connected to the second electrode of the sixteenth transistor M16, the gate of the eighth transistor M8 is connected to the gate of the sixth transistor M6, the second electrode of the eighth transistor M8 is connected to the second electrode of the seventeenth transistor M17, the gate of the sixteenth transistor M16 is connected to the second electrode of the sixteenth transistor M16, the gate of the nineteenth transistor M19 and the twentieth transistor M2 0, the gate of the seventeenth transistor M17 is connected to the second electrode of the seventeenth transistor M17 and the gate of the eighteenth transistor M18, the second electrode of the eighteenth transistor M18 is connected to the second electrode of the twelfth transistor M12, the first electrode of the sixteenth transistor M16, the first electrode of the seventeenth transistor M17, the first electrode of the eighteenth transistor M18, the first electrode of the nineteenth transistor M19 and the first electrode of the twentieth transistor M20 are all connected to the working voltage VCC, the first electrode of the twelfth transistor M12, the first electrode of the twenty-first transistor M21 and the first electrode of the twenty-second transistor M22 are all grounded, the gate of the twelfth transistor M12 is connected to the gate of the twenty-first transistor M21 and the gate of the twenty-second transistor M22,The second electrode of the nineteenth transistor M19 is connected to the second electrode of the twenty-first transistor M21, and leads to the first output terminal to output Iout. The second electrode of the twentieth transistor M20 is connected to the second electrode of the twenty-second transistor M22 and the first end of the first resistor R, and leads to the second output terminal to output Vout. The second end of the first resistor R is grounded.
[0033] exist Figure 3 In the circuit structure shown, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8M9, the ninth transistor, the tenth transistor M10, the eleventh transistor M11, the twelfth transistor M12, the twenty-first transistor M21 and the twenty-second transistor M22 are all N-type transistors; the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15, the sixteenth transistor M16, the seventeenth transistor M17, the eighteenth transistor M18, the nineteenth transistor M19 and the twentieth transistor M20 are all P-type transistors. It should be noted that in this embodiment, the first electrodes of all transistors refer to the source electrode, and the second electrodes refer to the drain electrode. The circuit structure of the differential voltage and current transmitter transconductance amplifier 21 can also be adjusted according to the actual implementation requirements, or different types of transistors can be selected. The corresponding connection relationship is combined with the actual device type. This embodiment is not specifically limited as long as the corresponding function can be met.
[0034] In this embodiment, the circuit structure of the differential voltage current transmitter transconductance amplifier 21 mainly includes three differential pair structures, wherein the first differential pair includes M3 and M4, and the corresponding tail current source is M9, the second differential pair includes M5 and M6, and the corresponding tail current source is M10, and the third differential pair includes M7 and M8, and the corresponding tail current source input terminal is an adjustable signal input terminal, which is usually connected to an adjustable current source to achieve transconductance adjustment. The circuit has two modes in the same topology, namely voltage and transconductance modes, and has an external grounding resistor R. The structure uses an improved DVCCTA active block to provide a very wide cutoff frequency range for differential gain and CMRR. At the same time, the differential gain is electrically tuned through the adjustable signal input, there is no component matching requirement, the structure is simple and easy to implement, it has a high common mode rejection ratio, and lower power consumption.
[0035] Specifically, the first differential pair output V1 = -gm1*(V X1 -0)*ro1, in an ideal state, the transistors M13, M14 and M15 as loads are exactly the same transistors, their channel resistances are all ro1, and they all work in the saturation region; the first transconductance gm1 is V b, M1, M2 and the parameters of the tail current power supply M9. Because it is a differential pair, the circuits on both sides require high matching. Therefore, this embodiment limits M3 and M4 to be exactly the same transistors, and the first transconductance gm1 is:
[0036]
[0037] Wherein, I1 is the current generated by the tail current source M9.
[0038] Similarly, the second differential pair output V2 = -gm2*(Vin2-V Z )*ro2, the second transconductance gm2 is V b , M5, M6 and the parameters of its tail current power supply M10. Based on the assumption of differential pairs and matching degree, this embodiment limits M5, M6 and M3, M4 to be exactly the same transistors. At this time, gm2 = gm1, tail current I2 = I1, V2 = -gm1*(Vin2-V Z )*ro1. Combined Figure 3 For the circuit shown, V2 = V1, then gm1*(Vin1-0)*ro1 = gm1*(Vin2-V Z )*ro1, then the gate voltage of M6 is V Z =Vin2-Vin1.
[0039] For the third differential pair, the third transconductance gm3 is determined by the input bias current I B and the parameters of M7 and M8. In an ideal state, M16, M17, M18, M19 and M20 are exactly the same transistors, and the current I8 flowing through transistor M8 is:
[0040]
[0041] Among them, k n8 is the process gain factor of M8. As can be seen from the figure, the amplified current signal Iout outputted by the first output terminal is I8, and the amplified voltage signal Vout outputted is Iout*R, thereby realizing that the output of the differential voltage-current transmitter transconductance amplifier 21 is proportional to the input voltages Vin1 and Vin2, and the amplitude is controlled by I B By adjusting the bias current I B The transconductance of the amplifier is changed to achieve electronic controllability of the output voltage and output current.
[0042] Ideally, if the first differential pair and the second differential pair are completely consistent, the common mode rejection ratio is zero. However, in practical applications, there will be deviations between the first differential pair and the second differential pair, and the load resistance and the transconductance of the differential pair will not be completely consistent, that is, gm1*(Vin1-0)*ro1=gm1*(Vin2-V Z )*ro2, gm2≠gm1, I2≠I1, so, in this embodiment, assuming that the mismatch factor coefficient of Vin1 is β1, and the mismatch factor coefficient of Vin2 is β2, the output amplified current signal is:
[0043] Iout=I8=gm3*(β1*Vin1-β2*Vin2) (8)
[0044] The differential gain Adm is:
[0045] Adm=I8 / (Vin1-Vin2)=gm3*(β1*Vin1-β2*Vin2) / () (9)
[0046] Assuming β1=β2, then Adm=gm3;
[0047] The common mode gain Acm is:
[0048]
[0049] Wherein, Vin is the amplitude of Vin1 and Vin2. Since Vin1 and Vin2 are differential signals, they have the same amplitude and opposite phase. Combining the above formula (9) and formula (10), the common mode rejection ratio CMRR = Adm / Acm = 1 / (β1-β2) can be calculated. In actual application, combined with the existing process conditions, even if β1 and β2 cannot be completely consistent, they can still have a small difference, thereby achieving a higher common mode rejection ratio.
[0050] This embodiment eliminates common-mode noise through a differential input signal and uses an improved differential voltage-current transmitter transconductance amplifier as a weak signal amplification unit. The circuit has no component matching problem and has a simple structure and is easy to implement. At the same time, the transconductance adjustment of the weak signal amplification unit is implemented based on the current signal with adjustable size, and the linear adjustment of the output signal is achieved, so that it can be adapted to various downstream devices and cooperate with two different types of output terminals to achieve the purpose of improving universality.
[0051] Based on the same inventive concept, the second embodiment of the present disclosure provides an electronic device, which at least includes the dual-output weak signal amplifier with adjustable transconductance in the first embodiment of the present disclosure, and its upstream device can be connected to various types of weak signal sensors, and its downstream device can be an analog-to-digital converter or other micro-control device to realize the collection and processing process of weak signals in various fields, and is more conducive to application in automation systems.
[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A dual-output weak signal amplifier with adjustable transconductance, characterized in that: include: A reference voltage generating unit, used for generating a reference voltage; A weak signal amplification unit comprises at least a differential voltage and current transmitter transconductance amplifier, wherein the differential voltage and current transmitter transconductance amplifier has at least a first input terminal, a second input terminal, a reference voltage input terminal, an adjustable signal input terminal, a first output terminal and a second output terminal, wherein the first input terminal and the second input terminal are used to access a differential first input voltage and a second input voltage, the reference voltage input terminal is connected to the output terminal of the reference voltage generating unit, the adjustable signal input terminal is connected to a current signal of adjustable size to modulate the transimpedance of the differential voltage and current transmitter transconductance amplifier, the first output terminal is used to output an amplified current signal, and the second output terminal is used to output an amplified voltage signal.
2. The dual-output weak signal amplifier according to claim 1, characterized in that: The reference voltage generating unit comprises at least: a first transistor and a second transistor; wherein, The first electrode of the first transistor is connected to the working voltage, the second electrode of the first transistor is connected to the second electrode of the second transistor, the gate of the first transistor is connected to the second electrode of the first transistor, the first electrode of the second transistor is grounded, the gate of the second transistor is connected to the second electrode of the second transistor, and the output end of the reference voltage generating unit is led out between the first transistor and the second transistor.
3. The dual-output weak signal amplifier according to claim 2, characterized in that: The first transistor is a P-type transistor, and the second transistor is an N-type transistor.
4. The dual-output weak signal amplifier according to claim 1, characterized in that: The differential voltage current transmitter transconductance amplifier at least includes: a third transistor to a twenty-second transistor and a first resistor; wherein, The gate of the third transistor leads to the first input terminal, the first electrode of the third transistor is connected to the second electrode of the ninth transistor, the second electrode of the third transistor is connected to the gate of the fifteenth transistor and the second electrode of the thirteenth transistor, the gate of the fourth transistor is grounded, the first electrode of the fourth transistor is connected to the second electrode of the ninth transistor, the second electrode of the fourth transistor is connected to the second electrode of the sixth transistor and the second electrode of the fourteenth transistor, the second electrode of the fifth transistor is connected to the gate of the fifteenth transistor and the second electrode of the third transistor, the gate of the fifth transistor leads to the second input terminal, the first electrode of the fifth transistor is connected to the first electrode of the sixth transistor and the second electrode of the tenth transistor The first electrode of the seventh transistor is connected to the first electrode of the eighth transistor, the first electrode of the eighth transistor is connected to the second electrode of the thirteenth transistor, the first electrode of the thirteenth transistor is connected to the second electrode of the fifteenth transistor, the first electrode of the ninth transistor, the first electrode of the tenth transistor and the first electrode of the eleventh transistor are grounded, the gates of the ninth transistor, the tenth transistor and the eleventh transistor are connected to the reference voltage, the first electrode of the thirteenth transistor, the first electrode of the fourteenth transistor and the first electrode of the fifteenth transistor are connected to the operating voltage, the gate of the thirteenth transistor is connected to the gate of the fourteenth transistor and the second electrode of the thirteenth transistor, the first electrode of the seventh transistor is connected to the first electrode of the eighth transistor, and the seventh transistor is connected to the first electrode of the eighth transistor. The adjustable signal input terminal is led out between the first electrode of the body tube and the first electrode of the eighth transistor, the gate of the seventh transistor is grounded, the second electrode of the seventh transistor is connected to the second electrode of the sixteenth transistor, the gate of the eighth transistor is connected to the gate of the sixth transistor, the second electrode of the eighth transistor is connected to the second electrode of the seventeenth transistor, the gate of the sixteenth transistor is connected to the second electrode of the sixteenth transistor, the gate of the nineteenth transistor is connected to the gate of the twentieth transistor, the gate of the seventeenth transistor is connected to the second electrode of the seventeenth transistor and the gate of the eighteenth transistor, the second electrode of the eighteenth transistor is connected to the second electrode of the twelfth transistor, and the gate of the sixteenth transistor is connected to the second electrode of the seventeenth transistor. The first electrode of the seventeenth transistor, the first electrode of the eighteenth transistor, the first electrode of the nineteenth transistor and the first electrode of the twentieth transistor are all connected to the operating voltage, the first electrode of the twelfth transistor, the first electrode of the twenty-first transistor and the first electrode of the twenty-second transistor are all grounded, the gate of the twelfth transistor is connected to the gate of the twenty-first transistor and the gate of the twenty-second transistor, the second electrode of the nineteenth transistor is connected to the second electrode of the twenty-first transistor, and the first output end is led out, the second electrode of the twentieth transistor is connected to the second electrode of the twenty-second transistor and the first end of the first resistor, and the second output end is led out, and the second end of the first resistor is grounded.
5. The dual-output weak signal amplifier according to claim 4, characterized in that: The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, the twelfth transistor, the twenty-first transistor and the twenty-second transistor are all N-type transistors; The thirteenth transistor, the fourteenth transistor, the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor and the twentieth transistor are all P-type transistors.
6. The dual-output weak signal amplifier according to claim 5, characterized in that: The third transistor, the fourth transistor, the fifth transistor and the sixth transistor are completely identical transistors.
7. The dual-output weak signal amplifier according to claim 5, characterized in that: The thirteenth transistor, the fourteenth transistor and the fifteenth transistor are completely identical transistors.
8. The dual-output weak signal amplifier according to claim 5, characterized in that: The sixteenth transistor, the seventeenth transistor, the eighteenth transistor, the nineteenth transistor and the twentieth transistor are completely identical transistors.
9. The dual-output weak signal amplifier according to any one of claims 1 to 8, characterized in that: The adjustable signal input terminal is connected to the output terminal of the adjustable current source.
10. An electronic device, characterized in that: At least comprises a dual-output weak signal amplifier with adjustable transconductance as claimed in any one of claims 1 to 9.