A low-power and low-transmission-delay dynamic comparator

Abstract

The present invention discloses a low-power and low-transmission-delay dynamic comparator, belonging to the technical field of analog integrated circuits. It includes an external bias small-current input circuit for continuously providing a static bias current for the preamplifier; a two-stage differential-input single-ended-output preamplifier, where the positive / negative input terminals of the differential input are respectively connected to the supply voltage and the output point voltage of the external rectifier circuit; the preamplifier provides a driving voltage for the dynamic bias inverter in the dynamic bias circuit; the dynamic bias circuit is composed of a dynamic bias inverter and a diode-connected NMOS transistor connected in series, and is used to selectively provide a dynamic bias current for the preamplifier according to the difference of the differential input of the preamplifier; and a driving circuit is included. The present invention adopts a combination of static bias and dynamic bias, and can increase the bias current through dynamic bias when the difference of the comparator input signal is small, realizing a continuous-time comparator with low power consumption and low transmission delay.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits and relates to a low-power and low-transmission-delay dynamic comparator. Background Art

[0002] There is a phase difference between the output current and voltage of a piezoelectric energy harvesting sensor, so its rectifier circuit will face the situation where the current and voltage are in opposite directions. Suppose at a certain moment the voltage is positive and the current is negative. At this time, since the voltage is positive, the rectifier circuit is turned on, but since the current is negative, the piezoelectric energy harvesting sensor not only cannot provide energy for the subsequent circuit, but will instead draw energy from the subsequent interface circuit, which will lead to a decrease in the energy harvesting efficiency. To prevent this situation from occurring, when the current and voltage are in opposite directions, generally an over-zero comparison circuit is needed to disconnect the interface circuit from the piezoelectric energy harvesting sensor.

[0003] The comparison speed of an over-zero detection two-stage comparator is directly related to the magnitude of the bias current and is also directly related to the input voltage difference of the differential pair. At the same bias current, the larger the input voltage difference of the differential pair, the faster the comparison speed; the smaller the input voltage difference of the differential pair, the slower the comparison speed.

[0004] For a piezoelectric vibration energy harvesting sensor system, over-zero detection happens to be an application scenario where a comparator needs to quickly give a comparison result when the input voltage difference of the differential pair is very small. To enable the comparator to quickly give a comparison result, it is often necessary to give M N21 a relatively large bias current to enhance the transconductance of the two-stage amplifier. However, since the piezoelectric vibration energy harvesting sensor system belongs to an energy supply module (depending on the sensor, the general harvesting power is several hundred μW to several mW), it is necessary to maximize the harvested energy output to the subsequent sensing, computing, and communication modules. Therefore, the method of increasing the static bias current of the over-zero detection comparator to reduce the comparison time is obviously inappropriate. Summary of the Invention

[0005] Aiming at the problem that the traditional over-zero detection comparator has a long comparison time when the input voltage difference is small, the present invention proposes a low-power and low-transmission-delay dynamic comparator, which adopts a combination of static bias and dynamic bias, and can increase the bias current through dynamic bias when the input signal difference of the comparator is small, realizing a low-power and low-transmission-delay continuous-time comparator.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] In a first aspect, the present invention provides a low-power and low-transmission-delay dynamic comparator, comprising:

[0008] External bias small current input circuit, used to continuously provide static bias current for the preamplifier;

[0009] Two-stage differential input single-ended output preamplifier, including a first-stage amplifier and a second-stage amplifier connected in series. The positive input terminal and the negative input terminal of the differential input are respectively connected to the supply voltage and the output point voltage of the external rectifier circuit; the preamplifier provides a driving voltage for the dynamic bias inverter in the dynamic bias circuit;

[0010] Dynamic bias circuit, composed of a dynamic bias inverter and a diode-connected NMOS transistor connected in series, used to selectively provide dynamic bias current for the preamplifier according to the difference of the differential input of the preamplifier;

[0011] When the difference of the differential input of the preamplifier is greater than the threshold, the driving voltage provided by the preamplifier is far from the inversion threshold of the dynamic bias inverter, the dynamic bias inverter is in a stable output state, does not provide dynamic bias current, and the preamplifier is only biased by the static bias current; when the difference of the differential input of the preamplifier is less than or equal to the threshold, the driving voltage provided by the preamplifier is close to the inversion threshold of the dynamic bias inverter, the dynamic bias inverter is in an inversion state, and the current flowing through the dynamic bias inverter provides dynamic bias current for the preamplifier through the diode-connected NMOS transistor, and the preamplifier is biased by both the static bias current and the dynamic bias current;

[0012] Driver circuit, composed of two inverters connected in series, provides an input signal by the dynamic bias circuit and transmits it to the downstream load circuit.

[0013] Preferably, the external bias small current input circuit is a diode-connected NMOS transistor M N31 , the diode connection means that the gate terminal and the drain terminal of M N31 are short-circuited, the drain terminal of M N31 is connected to the external bias small current, the external bias small current is the static bias current, the source terminal of M N31 is grounded, and the gate terminal of M N31 is used as the output terminal of the external bias small current input circuit, and is respectively connected to the first-stage amplifier and the second-stage amplifier in the preamplifier to provide static bias current.

[0014] Preferably, the first-stage amplifier in the preamplifier includes NMOS transistor M N32 , NMOS transistor M N33 , NMOS transistor M N34 , NMOS transistor M N35 , PMOS transistor M P31 and PMOS transistor M P32 ;

[0015] The MP31 The source terminal of M is used as the negative input terminal of the first-stage amplifier and is connected to the output point voltage of the external rectifier circuit; M P32 The source terminal of M is used as the positive input terminal of the first-stage amplifier and is connected to the supply voltage; M P31 The gate terminal and the drain terminal of M are short-circuited and connected to the gate terminal of M P32 ; M N32 M, N33 M are connected to the drain terminal of M P31 ; M N34 M, N35 M are connected to the drain terminal of M P32 as the output terminal of the first-stage amplifier; M N32 M is connected to the gate terminal of M N34 and is connected to the external bias small current input circuit, M N33 M is connected to the gate terminal of M N35 and is connected to the dynamic bias circuit, M N32 M, N33 M, N34 M are connected to the source terminal of M N35 and grounded.

[0016] Preferably, the second-stage amplifier in the preamplifier is a common-source amplifier.

[0017] Preferably, the common-source amplifier is composed of NMOS transistor M N36 , NMOS transistor M N37 and PMOS transistor M P33 ;

[0018] The gate terminal of M P33 is connected to the output terminal of the first-stage amplifier, the source terminal of M P33 is connected to the supply voltage, M P33 M, N36 M are connected to the drain terminal of M N37 as the output terminal of the second-stage amplifier, the gate terminal of M N36 is connected to the external bias small current input circuit, the gate terminal of M N37 is connected to the dynamic bias circuit, M N36 M is connected to the source terminal of M N37 and grounded.

[0019] Preferably, the dynamic bias circuit includes a dynamic bias inverter composed of NMOS transistor M N39 and PMOS transistor M P34 , and a diode-connected NMOS transistor M N38 ;

[0020] The gate terminal of M N39 is connected to M P34The leakage terminals are connected together as the voltage output terminal of the dynamic bias circuit, which is used to provide an input signal for the driving circuit; M N39 is connected to the gate terminal of M P34 and is connected to the output terminal of the second-stage amplifier, and the source terminal of M P34 is connected to the supply voltage, and the source terminal of M N39 is connected to the drain terminal of M N38 The gate terminal and the drain terminal of M N38 are short-circuited to form a diode connection and used as the dynamic bias current output terminal, which is used to provide a dynamic bias current for the first-stage amplifier and the second-stage amplifier; M N38 The source terminal of M is grounded.

[0021] Preferably, the aspect ratio of the width to length of the second-stage inverter connected in series in the driving circuit is 4-5 times that of the first-stage inverter.

[0022] Preferably, the lengths of the second-stage inverter and the first-stage inverter are the same.

[0023] In a second aspect, the present invention provides an active diode, which includes a PMOS transistor M 0 and the above low-power and low-transmission-delay dynamic comparator. The output terminal of the low-power and low-transmission-delay dynamic comparator is connected to the gate terminal of M 0 and the source terminal and the drain terminal of M 0 are respectively connected to the positive input terminal and the negative input terminal of the differential input of the low-power and low-transmission-delay dynamic comparator.

[0024] In a third aspect, the present invention provides a piezoelectric vibration energy harvesting sensor system, which includes a piezoelectric vibration energy harvesting sensor, a rectifier circuit, a super capacitor and the above active diode module. The output terminal of the piezoelectric vibration energy harvesting sensor is connected to the negative input terminal of the comparator of the active diode module through the rectifier circuit, and the super capacitor is connected to the positive input terminal of the comparator of the active diode module to provide a supply voltage.

[0025] The beneficial effects of the present invention are:

[0026] The comparator provided by the present invention adopts a combination of static biasing and dynamic biasing. The dynamic biasing inverter of the dynamic biasing circuit is driven by a preamplifier. When the difference between the differential inputs of the preamplifier is greater than the threshold, the driving voltage provided by the preamplifier is far from the inversion threshold of the dynamic biasing inverter, and the dynamic biasing inverter is in a stable output state. The current flowing through the dynamic biasing inverter is the drain current of the transistor, and the dynamic biasing current is almost zero. The preamplifier is biased only by the static biasing current. When the difference between the differential inputs of the preamplifier is less than or equal to the threshold, the driving voltage provided by the preamplifier is close to the inversion threshold of the dynamic biasing inverter, and the dynamic biasing inverter is in an inversion state. The large current flowing through the dynamic biasing inverter provides a dynamic biasing current for the preamplifier through the diode-connected NMOS transistor. The preamplifier is biased by both the static biasing current and the dynamic biasing current. The dynamic biasing circuit can selectively provide a dynamic biasing current for the preamplifier according to the difference between the differential inputs of the preamplifier, and increase the overall biasing current through dynamic biasing when the difference between the input signals of the comparator is small, featuring low power consumption and low transmission delay. Description of the Drawings

[0027] Figure 1 is a schematic diagram of a piezoelectric vibration energy harvesting sensor system.

[0028] Figure 2 is a traditional zero-crossing detection comparator.

[0029] Figure 3 is a low-power and low-delay comparator circuit with dynamically adjustable power consumption proposed by the present invention.

[0030] Figure 4 is a system block diagram of a low-power and low-delay comparator circuit with dynamically adjustable power consumption proposed by the present invention.

[0031] Figure 5 is a simulation diagram of the traditional comparator and the comparator of the present invention under the same conditions. Detailed Embodiments

[0032] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0033] As Figure 2 shown in a traditional zero-crossing detection two-stage comparator, a bias current I N21 is applied to the drain terminal of M b2 , the gate terminal of M N21 is shorted to the drain terminal, and the source terminal is grounded; MN22 , M N23 and M N24 have their gate terminals connected to the gate terminal of M N21 , and their source terminals are grounded. The source terminal of M P21 is the negative terminal of the comparator. The gate terminal and the drain terminal of M P21 are short - circuited. The drain terminal of M P21 is connected to the drain terminal of M N22 ; The source terminal of M P22 is the positive terminal of the comparator. The gate terminal of M P22 is connected to the gate terminal of M P21 . The drain terminal of M P22 is connected to the drain terminal of M N23 and the gate terminal of M P23 . The source terminal of M P23 is connected to a super - capacitor. The drain terminal of M P23 is connected to the drain terminal of M N24 and the gate terminals of M P24 and M N25 . The source terminal of M P24 is connected to a super - capacitor. The drain terminal of M P24 is connected to the drain terminal of M N25 as the output of the comparator. The source terminal of M N25 is grounded. It can be seen that the comparison speed of this comparator is directly related to the magnitude of the bias current I b2 . In addition, the comparison speed of this comparator is also directly related to the input voltage difference of the differential pair. At the same bias current, the larger the input voltage difference of the differential pair, the faster the comparison speed; the smaller the input voltage difference of the differential pair, the slower the comparison speed. The bias current cannot be dynamically adjusted.

[0034] As Figure 3 shown, the low - power and low - transmission - delay dynamic comparator proposed by the present invention includes an external bias small - current input circuit, a pre - amplifier with two - stage differential input and single - end output, a dynamic bias circuit, and a driving circuit.

[0035] Among them, the external bias small - current input circuit is used to continuously provide a static bias current for the pre - amplifier;

[0036] The pre - amplifier with two - stage differential input and single - end output includes a first - stage amplifier and a second - stage amplifier connected in series. The positive input terminal and the negative input terminal of the differential input are respectively connected to the supply voltage and the output point voltage of the external rectifier circuit; The pre - amplifier provides a driving voltage for the dynamic - bias inverter in the dynamic bias circuit;

[0037] The dynamic bias circuit is composed of a dynamic - bias inverter and a diode - connected NMOS transistor connected in series, and is used to selectively provide a dynamic bias current for the pre - amplifier according to the difference of the differential input of the pre - amplifier;

[0038] When the difference between the differential inputs of the preamplifier is greater than the threshold, the driving voltage provided by the preamplifier is far from the inversion threshold of the dynamic bias inverter, and the dynamic bias inverter is in a stable output state, not providing dynamic bias current. The preamplifier is biased only by the static bias current. When the difference between the differential inputs of the preamplifier is less than or equal to the threshold, the driving voltage provided by the preamplifier approaches the inversion threshold of the dynamic bias inverter, and the dynamic bias inverter is in an inversion state. The current flowing through the dynamic bias inverter provides dynamic bias current for the preamplifier through the diode-connected NMOS transistor, and the preamplifier is biased by both the static bias current and the dynamic bias current.

[0039] The driving circuit is composed of two inverters connected in series. The input signal is provided by the dynamic bias circuit and transmitted to the downstream load circuit, which can provide sufficient current to the load circuit, thereby improving the dynamic performance of the system.

[0040] Take Figure 1 the piezoelectric vibration energy harvesting sensor system shown as an example to introduce the low-power and low-transmission-delay dynamic comparator of the present invention. Figure 1 In the figure, the system includes a piezoelectric vibration energy harvesting sensor 100, a rectifier circuit 110, an active diode module 120, and a super capacitor 130. Among them, the active diode module 120 is composed of a PMOS transistor M 0 and a low-power and low-transmission-delay dynamic comparator 122. The output terminal of the low-power and low-transmission-delay dynamic comparator is connected to the gate terminal of M 0 , and the source terminal and drain terminal of M 0 are respectively connected to the positive input terminal and negative input terminal of the differential input of the low-power and low-transmission-delay dynamic comparator. The output terminal of the piezoelectric vibration energy harvesting sensor is connected to the negative input terminal of the comparator of the active diode module through the rectifier circuit, and the super capacitor is connected to the positive input terminal of the comparator of the active diode module. The super capacitor is used to provide the supply voltage for the comparator.

[0041] Denote the voltage of the super capacitor 130 as V S , which is used as the power supply for this comparator and is connected to the positive input terminal of the first stage of the two-stage preamplifier; denote the output point voltage of the rectifier circuit as V REC , which is connected to the negative input terminal of the first-stage amplifier of this two-stage preamplifier. Denote the external bias small current as I b31 , which is used to provide the static bias current of the comparator.

[0042] As Figure 3 shown, the external bias small current input circuit is a diode-connected NMOS transistor M N31 . The so-called diode connection means that the gate terminal and drain terminal of M N31 are short-circuited, and M N31The leakage terminal is connected to an external bias small current I b31 The external bias small current is a static bias current. The source terminal of M N31 is grounded. The gate terminal of M N31 serves as the output terminal of the external bias small current input circuit. Denote the gate terminal voltage of M N31 as V b31 . This gate terminal voltage will provide a very small static bias current for the subsequent two-stage preamplifier and is connected to the first-stage amplifier and the second-stage amplifier in the preamplifier respectively.

[0043] The first-stage amplifier of the preamplifier includes the following four NMOS transistors: M N32 、M N33 、M N34 、M N35 and the following two PMOS transistors: M P31 and M P32 . Among them, the source terminal of M P31 serves as the negative input terminal of this first-stage amplifier and is connected to the output point voltage V REC of the rectifier circuit. The source terminal of M P32 serves as the positive input terminal of this first-stage amplifier and is connected to the voltage V S of the super capacitor. The gate terminals of M P31 and M P32 are connected and are connected to the drain terminal of M P31 . The drain terminals of M N32 、M N33 are connected to the drain terminal of M P31 ; The drain terminals of M N34 、M N35 are connected to the drain terminal of M P32 . The gate terminals of M N32 、M N34 are connected to the gate terminal of M N31 in the external bias small current input circuit; The source terminals of M N32 、M N33 、M N34 and M N35 are grounded. M N33 is connected to the gate terminal of M N35 and is connected to the gate terminal of M N38 in the dynamic bias circuit.

[0044] The second-stage amplifier of the two-stage preamplifier is a common-source amplifier composed of M P33 、M N36 and M N37 . Among them, the gate terminal of M P33 is connected to the drain terminal of M P32 in the first-stage amplifier. The source terminal of M P33 is connected to the voltage V S of the super capacitor. MP33 and M N36 is connected to the leakage terminal of M N37 , and the source terminal of M N36 is connected to ground, and the gate terminal of M N37 is connected to the gate terminal of M N36 in the external bias small current input circuit N31 , and the gate terminal of M N37 is connected to the gate terminal of M N38 in the dynamic bias circuit.

[0045] The dynamic bias circuit consists of two NMOS transistors: M N38 and M N39 , and a PMOS transistor M P34 . Among them, M N39 and M P34 form an inverter, and M N39 is connected to the leakage terminal of M P34 and is connected to the drive circuit, and M N39 is connected to the gate terminal of M P34 and is connected to the second-stage amplifier, and the source terminal of M P34 is connected to the voltage V of the supercapacitor S , and the source terminal of M N39 is connected to the leakage terminal of M N38 . The gate terminal of M N38 is short-circuited to the leakage terminal to form a diode connection, the source terminal of M N38 is connected to ground, and the gate terminal of M N38 is also connected to two-stage pre-amplifiers respectively.

[0046] The described drive circuit consists of NMOS transistors M N310 , M N311 and PMOS transistors M P35 , M P36 . M N310 , M P35 form the first-stage drive circuit, and M N311 , M P36 form the second-stage drive circuit. M N310 is connected to the gate terminal of M P35 and is connected to the leakage terminal of M N39 and M P34 in the dynamic bias circuit; M N310 is connected to the leakage terminal of M P35 as the output terminal of the first-stage drive circuit; the source terminal of M P35 is connected to the voltage V of the supercapacitor S , and the source terminal of M N310 is connected to ground. M N311 is connected to the gate terminal of M P36 and is connected to M N310 in the first-stage drive circuit and MP35 The drain terminal of; M N311 Connected to M P36 The drain terminal of is connected as the output terminal of the second-stage drive circuit; M P36 The source terminal of is connected to the voltage V of the supercapacitor S , M N311 The source terminal of is grounded.

[0047] Divide the Figure 3 Circuit in into Figure 4 The system block diagram form shown is used to more intuitively show the working principle of the circuit. Among them, 401 represents the comparator of the present invention, V S Is connected to the positive input terminal of the comparator, V REC Is connected to the negative input terminal of the comparator, and the output terminal of the comparator is connected to the dynamic bias inverter 402 in the dynamic bias circuit. The dynamic bias inverter 402 outputs the final voltage V OUT . The comparator has two sets of bias currents. One set is the small current I b41 Biased by the first current mirror 404, and the other set is the current I b42 Dynamically biased by the second current mirror 405. Among them, the first current mirror 404 is composed of the above-mentioned transistors M N31 , M N32 , M N34 And M N36 Constitute, and the second current mirror 405 is composed of the above-mentioned transistors M N33 , M N35 , M N37 And M N38 Constitute.

[0048] Combined with Figure 1 And Figure 3 , the working process of the comparator proposed by the present invention is described.

[0049] From a system perspective: This comparator can be applied to the active diode module 120 in a piezoelectric vibration energy harvesting sensor system, and a PMOS transistor 121 is controlled by the comparator 122 proposed by the present invention. In this scenario, regardless of whether the initial direction of the current from the piezoelectric vibration energy harvesting sensor 100 is the positive direction or the negative direction, the rectifier circuit 110 will rectify the current into the positive direction and flow into the active diode module 120.

[0050] This comparator has two working processes. One is when the voltage V REC Is less than or equal to the voltage V S On the supercapacitor, and the other is when the voltage V REC Is greater than the voltage V S On the supercapacitor. The working processes will be described separately from two aspects below.

[0051] When the current captured by the piezoelectric vibration energy harvesting sensor 100 just starts to flow into the rectifier circuit 110, at this time, since the voltage on the parasitic capacitance inside the piezoelectric vibration energy harvesting sensor 100 is low, the output voltage V of the rectifier circuit 110 REC is lower than the voltage V of the supercapacitor 130 S . The comparator 122 outputs a high-level voltage to turn off the PMOS transistor 121, isolating the piezoelectric vibration energy harvesting sensor 100 from the supercapacitor 130, preventing the current on the supercapacitor 130 from flowing back into the parasitic capacitance in the piezoelectric vibration energy harvesting sensor 100, thereby reducing the energy that can be harvested. Since the PMOS transistor 121 is turned off, the current captured by the piezoelectric vibration energy harvesting sensor 100 starts to charge the internal parasitic capacitance, and then the output voltage V of the rectifier circuit 110 REC gradually increases.

[0052] As the output voltage V of the rectifier circuit 110 REC increases and exceeds the voltage V of the supercapacitor 130 S , the comparator 122 quickly outputs a low-level voltage to turn on the PMOS transistor 121. At this time, the piezoelectric vibration energy harvesting sensor 100 and the rectifier circuit 110 can be connected to the supercapacitor 130 through the PMOS transistor 121. Since V REC is higher than V S at this time, the charge can flow from the piezoelectric vibration energy harvesting sensor 100 into the supercapacitor 130. At the same time, the voltage of V REC is clamped and approximately equal to V S .

[0053] When the current captured by the piezoelectric vibration energy harvesting sensor 100 changes from the positive direction to the negative direction, the internal parasitic capacitance of the piezoelectric vibration energy harvesting sensor 100 starts to discharge, so the output voltage V of the rectifier circuit 110 REC starts to gradually decrease. When V REC is still higher than V S , the comparator 122 still outputs a low-level voltage to turn on the PMOS transistor 121. When V REC is lower than V S , the comparator 122 quickly flips and outputs a high-level voltage to turn off the PMOS transistor 121, preventing the current from flowing back from the supercapacitor 130 into the parasitic capacitance in the piezoelectric vibration energy harvesting sensor 100. When the internal parasitic capacitance of the piezoelectric vibration energy harvesting sensor 100 finishes discharging and starts to be charged by the captured reverse current, the output voltage V of the rectifier circuit 110 REC starts to gradually rise again. The subsequent working process is as described above.

[0054] From the circuit level: The comparator has two operating modes, namely, the negative input terminal of the comparator gradually rises from a low voltage until it is higher than the positive input terminal of the comparator, and the negative input terminal of the comparator gradually drops from a high voltage until it is lower than the positive input terminal of the comparator.

[0055] First, introduce the first operating mode: The negative input terminal of the comparator gradually rises from a low voltage until it is higher than the positive input terminal of the comparator. When V REC is much lower than V S , the gate and drain voltages of M P31 in the first-stage amplifier are also lower than V S . At this time, the source-gate voltage difference of M P32 is large, so M P32 conducts, and the output voltage V P32 of the drain terminal of M O31 is a high-level voltage. This high-level voltage acts on the gate terminal of M P33 in the second-stage amplifier, causing M P33 to turn off. Therefore, the output voltage V P33 of the drain terminal of M O32 is a low-level voltage. This low-level voltage acts on the gate terminal of M N39 in the dynamic bias circuit, causing M N39 to turn off. At this time, since M N39 is turned off, there is no current flowing through M N38 . Furthermore, there is no current flowing through M N33 and M N35 in the first-stage amplifier, and M N37 in the second-stage amplifier. At this time, M N32 , M N34 and M N36 of the comparator are biased only by the small current I N31 (a dozen nA) provided by M b31 . At the same time, since M N39 is turned off and M P34 conducts, the first-stage M N310 of the drive circuit conducts, while M P35 turns off; the second-stage M P36 conducts, M N311 turns off, making the output voltage V OUT of the entire comparator a high level.

[0056] As V REC gradually approaches V S , the gate and drain voltages of M P31 in the first-stage amplifier also gradually rise, reducing the source-gate voltage difference of M P32 , so M P32The leakage terminal output voltage V O31 begins to decrease. When V REC is very close to V S , the voltage of V O31 will be close to the median value of the supply voltage. When the difference between V S and V O31 is greater than the threshold value of M P33 in the second-stage amplifier, M P33 begins to conduct, and then the leakage terminal output voltage V P33 of M O32 begins to rise. At this time, as V O32 rises, it acts on the gate terminals of M P34 and M N39 in the dynamic bias circuit. At a certain moment, both M P34 and M N39 conduct, and at this time, a relatively large transient current (from a few μA to dozens of μA) is generated from the voltage V S of the super capacitor. A relatively large transient current is generated and passes through M P34 , M N39 and M N38 in the dynamic bias circuit in sequence and then flows into the analog ground. At this time, the gate terminal voltage of M N38 is self-regulated according to this transient current. At the same time, this relatively large transient current passes through M N33 and M N35 in the first-stage amplifier and M N37 in the second-stage amplifier and is copied to the first-stage and second-stage amplifiers of the preamplifier, thereby enhancing the transconductance of the two-stage amplifier and increasing the amplification factor, and then causing V O31 to drop rapidly and V O32 to rise rapidly.

[0057] When V REC is much higher than V S , the gate terminal and leakage terminal voltages of M P31 in the first-stage amplifier are close to or higher than V S . At this time, the source-gate voltage difference of M P32 is extremely small or a negative voltage difference, so M P32 is turned off, and the leakage terminal output voltage V P32 of M O31 is a low-level voltage. This low-level voltage acts on the gate terminal of M P33 in the second-stage amplifier, causing M P33 to conduct. Therefore, the leakage terminal output voltage V P33 of M O32 is a high-level voltage. This high-level voltage acts on the gate terminal of M P34 in the dynamic bias circuit, causing M P34 to turn off. At this time, due to M P34is turned off, so there is no current flowing through M N38 and no current flows through M in the first-stage amplifier. Furthermore, M N33 and M N35 in the second-stage amplifier, and the transistor M N37 have no current flowing through them. At this time, the comparator is only biased by the small current I N31 provided by M b31 (a dozen nA). At the same time, since M P34 is turned off and M N39 is turned on, the first stage M of the drive circuit P35 is turned on and M N310 is turned off; the second stage M of the drive circuit N311 is turned on, while M P36 is turned off. In this way, the output voltage V OUT of the entire comparator is at a low level.

[0058] The following introduces the second operating mode: The negative input terminal of the comparator gradually drops from a high voltage until it is lower than the positive input terminal of the comparator. When V REC is much higher than V S , the output voltage V P32 at the drain terminal of M in the first-stage amplifier is at a low level voltage. This low level voltage acts on the gate terminal of M O31 in the second-stage amplifier, turning on M P33 . Therefore, the output voltage V P33 at the drain terminal of M P33 is at a high level voltage. This high level voltage acts on the gate terminal of M O32 in the dynamic bias circuit, turning off M P34 . At this time, since M P34 is turned off, there is no current flowing through M P34 . Furthermore, M N38 in the first-stage amplifier, M N33 and M N35 , and the transistor M N37 in the second-stage amplifier have no current flowing through them. At this time, the comparator is only biased by the small current I N31 provided by M b31 (a dozen nA). Since M P34 is turned off and M N39 is turned on, the first stage M of the drive circuit P35 is turned on and M N310 is turned off; the second stage M of the drive circuit N311 is turned on, while M P36 is turned off. This makes the output voltage V OUT of the entire comparator at a low level.

[0059] As V REC gradually approaches V S, the drain terminal output voltage V of M in the first - stage amplifier P32 starts to rise. When V O31 is very close to V REC , the voltage of V S will be close to the median value of the supply voltage. When the difference between V O31 and V S is greater than the threshold of M O31 in the second - stage amplifier, M P33 starts to turn off, and then the drain terminal output voltage V of M P33 starts to drop. At this time, as V P33 drops, it acts on the gate terminals of M O32 and M O32 in the dynamic bias circuit. At a certain moment, both M P34 and M N39 are turned on. At this time, a relatively large transient current (from a few μA to dozens of μA) is generated from the voltage V of the super - capacitor P34 and a relatively large transient current passes through M N39 in the dynamic bias circuit in sequence, then through M S and M P34 and M N39 and M N38 and then flows into the analog ground. At this time, the gate - terminal voltage of M N38 is self - regulated according to this transient current. At the same time, this relatively large transient current passes through M N33 and M N35 in the first - stage amplifier, and M N37 in the second - stage amplifier, and is copied to the first - stage and second - stage amplifiers of the pre - amplifier, thereby enhancing the transconductance of the two - stage amplifier and increasing the amplification factor, and then making V O31 rise rapidly and V O32 drop rapidly.

[0060] When V REC is much lower than V S , the drain - terminal output voltage V of M P32 in the first - stage amplifier is a high - level voltage. This high - level voltage acts on the gate terminal of M O31 in the second - stage amplifier, turning off M P33 . Therefore, the drain - terminal output voltage V of M P33 is a low - level voltage. This low - level voltage acts on the gate terminal of M P33 in the dynamic bias circuit, turning off M O32 . At this time, since M N39 is turned off, there is no current flowing through M N39 . Furthermore, there is no current flowing through M N39 , so there is no current flowing through M N38 . Then, there is no current flowing through M N33 and M N35, M in the second-stage amplifier N37 There is no current flowing through it. At this time, M of the comparator N32 , M N34 and M N36 are biased only by the small current I N31 provided by M b31 (a dozen nA). At the same time, since M N39 is turned off and M P34 is turned on at this time, the first-stage M of the drive circuit N310 is turned on, while M P35 is turned off; the second-stage M P36 is turned on and M N311 is turned off, making the output voltage V of the entire comparator OUT high level.

[0061] Figure 5 Compares Figure 2 the traditional comparator in Figure 3 and the simulation diagrams of the comparator of the present invention in S under the same conditions. The two waveforms in the first row of pictures are the positive-terminal input voltage V REC and the negative-terminal input voltage V S , where V REC is 2.5V, V P31 and M P32 is 2.49V before 1.5 μs and after 7.5 μs, and 2.51V between 1.5 μs and 7.5 μs. The two waveforms in the second row of pictures are the output waveforms of the comparator of the present invention and the traditional comparator respectively. Among them, the propagation delay of the comparator of the present invention in the first operating mode is about 177 nS, while the propagation delay of the traditional comparator is 583 nS; the propagation delay of the comparator of the present invention in the second operating mode is about 170 nS, while the propagation delay of the traditional comparator is 1450 nS. The two waveforms in the third row of pictures are the currents flowing through M P31 and M P32 , where at static, the static current flowing through M P31 and M P32 is 60 nA. The dynamic bias current of M O31 and V O32 is about 6.5 μA, while the dynamic bias current flowing through M O31 and V O32 can rise or fall quickly. Thanks to the spike current in the third row of pictures, V P21 and M P22 is about 1.5 μA. The two waveforms in the fourth row of pictures are V P21 and M P22The static current is 60 nA. And M P21 has a maximum current of approximately 110 nA, while the current flowing through M P22 has a maximum current of approximately 150 nA. The two waveforms in the sixth-line picture are the V O21 and V O22 of the traditional comparator respectively. Since the current in the fifth-line picture is small, V O21 and V O22 can only rise or fall slowly.

[0062] The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art. Although the embodiments of the present invention are described in conjunction with the accompanying drawings, those of ordinary skill in the art can make various deformations or modifications within the scope of the appended claims.

Claims

1. A low power consumption and low transmission delay dynamic comparator, characterized in that: include: An external bias low current input circuit is used to continuously provide a static bias current for the preamplifier; A two-stage differential input single-ended output preamplifier comprises a first-stage amplifier and a second-stage amplifier connected in series, wherein the positive input terminal and the negative input terminal of the differential input are respectively connected to the power supply voltage and the output point voltage of the external rectifier circuit; the preamplifier provides a driving voltage for a dynamic bias inverter in a dynamic bias circuit; Dynamic bias circuit, consisting of a dynamic bias inverter and a diode connected NMOS tube M N38 The dynamic bias inverter is composed of NMOS tube M N39 With PMOS tube M P34 Composition: N39 With M P34 The drain end of M is connected to the voltage output end of the dynamic bias circuit to provide an input signal for the driving circuit; N39 With M P34 The gate terminal is connected to the output terminal of the second stage amplifier, M P34 The source end of the power supply voltage is connected, M N39 The source and M N38 The drain end is connected to N38 The gate terminal and the drain terminal of M are short-circuited to form a diode connection and serve as a dynamic bias current output terminal, which is used to provide a dynamic bias current for the first stage amplifier and the second stage amplifier; N38 The source end is grounded; When the differential input phase difference of the preamplifier is greater than a threshold, the driving voltage provided by the preamplifier is far away from the inversion threshold of the dynamic bias inverter, the dynamic bias inverter is in a stable output state, no dynamic bias current is provided, and the preamplifier is biased only by a static bias current; When the differential input phase difference of the preamplifier is less than or equal to the threshold, the driving voltage provided by the preamplifier is close to the inversion threshold of the dynamic bias inverter, the dynamic bias inverter is in an inversion state, and the current flowing through the dynamic bias inverter provides a dynamic bias current for the preamplifier through the NMOS tube connected by the diode, and the preamplifier is biased by the static bias current and the dynamic bias current; The driving circuit is composed of two inverters connected in series, and the dynamic bias circuit provides input signals and transmits them to the downstream load circuit.

2. The low power consumption and low transmission delay dynamic comparator according to claim 1, characterized in that: The external bias low current input circuit is a diode-connected NMOS tube M N31 , the diode connection refers to M N31 The gate and drain terminals are short-circuited, M N31 The drain end of M is connected to an external bias current, and the external bias current is a static bias current. N31 The source end of the ground, M N31 The gate end of the circuit serves as the output end of the external bias small current input circuit and is respectively connected to the first-stage amplifier and the second-stage amplifier in the pre-amplifier to provide a static bias current.

3. The low power consumption and low transmission delay dynamic comparator according to claim 1, characterized in that: The first stage amplifier in the pre-amplifier includes an NMOS tube M N32 、NMOS tube M N33 、NMOS tube M N34 、NMOS tube M N35 、PMOS tube M P31 And PMOS tube M P32 ; The M P31 The source end of M is used as the negative input end of the first stage amplifier, and is connected to the output point voltage of the external rectifier circuit; P32 The source end of is used as the positive input end of the first-stage amplifier and is connected to the supply voltage; M P31 The gate and drain terminals are short-circuited and connected to M P32 The gate terminal is connected to N32 、M N33 With M P31 The drain end is connected to N34 、M N35 With M P32 The drain end is connected to the output end of the first stage amplifier; M N32 With M N34 The gate terminal is connected to the external bias small current input circuit, M N33 With M N35 The gate terminal is connected to the dynamic bias circuit, M N32 、M N33 、M N34 With M N35 The source terminal is grounded.

4. The low power consumption and low transmission delay dynamic comparator according to claim 3, characterized in that: The second stage amplifier in the pre-amplifier is a common source amplifier.

5. The low power consumption and low transmission delay dynamic comparator according to claim 4, characterized in that: The common source amplifier is composed of NMOS tube M N36 、NMOS tube M N37 And PMOS tube M P33 constitute; The M P33 The gate end is connected to the output end of the first stage amplifier, M P33 The source end of the power supply voltage is connected, M P33 、M N36 With M N37 The drain end is connected to the output end of the second stage amplifier, M N36 The gate terminal is connected to an external bias low current input circuit, M N37 The gate terminal is connected to the dynamic bias circuit, M N36 With M N37 The source terminal is grounded.

6. The low power consumption and low transmission delay dynamic comparator according to claim 1, characterized in that: The width-to-length ratio of the second-stage inverters connected in series in the driving circuit is 4-5 times that of the first-stage inverters.

7. The low power consumption and low transmission delay dynamic comparator according to claim 6, characterized in that: The second stage inverter has the same length as the first stage inverter.

8. An active diode, characterized in that: It comprises a PMOS tube M0 and the low-power, low-transmission delay dynamic comparator as described in any one of claims 1 to 7, wherein the output end of the low-power, low-transmission delay dynamic comparator is connected to the gate end of M0, and the source end and the drain end of M0 are respectively connected to the positive input end and the negative input end of the differential input of the low-power, low-transmission delay dynamic comparator.

9. A piezoelectric vibration energy capture sensor system, characterized in that: It comprises a piezoelectric vibration energy capture sensor, a rectifier circuit, a super capacitor and the active diode as claimed in claim 8, wherein the output end of the piezoelectric vibration energy capture sensor is connected to the negative input end of the comparator of the active diode through the rectifier circuit, and the super capacitor is connected to the positive input end of the comparator of the active diode to provide a power supply voltage.

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