A bootstrap switch circuit for high voltage gate

Abstract

The present invention discloses a bootstrap switch circuit of a high-voltage gate, comprising: an analog switch, a control circuit, an inverter group, and an enable pull-down circuit; the drain of the analog switch is used as the input end of the analog switch, and a Vin signal is input; the source and substrate of the analog switch are connected, and are used as the output end of the analog switch, and a Vout signal is output; the inverter group generates a control signal according to the enable signal, and inputs it into the control circuit; the control circuit controls the gate voltage of the analog switch according to the input control signal, so that the on-resistance of the analog switch remains constant; when the enable pull-down circuit judges that the bootstrap switch circuit is not working according to the enable signal, the bootstrap switch circuit is turned off. The present invention improves the accuracy and linearity of the output signal of the high-voltage domain analog switch by keeping the gate-source voltage of the analog switch constant, and does not require the capacitor and charge pump in the traditional bootstrap switch, and has a small overall area and power consumption, and can drive both low-voltage switches and high-voltage switches.

Description

Technical Field

[0001] The present invention relates to the field of analog circuit technology and semiconductor integrated circuit, and in particular to a bootstrap switch circuit of a high voltage gate. Background Art

[0002] High-voltage analog switches are widely used in automotive electronics and communications to control the on / off of high-voltage signal paths. In traditional designs, high-voltage analog switches and their control circuits face the following two problems:

[0003] (1) When the high-voltage analog switch is connected to a resistor voltage divider circuit to control the on and off of the high-voltage analog switch, its on-resistance directly affects the resistor voltage divider accuracy. The traditional control of NMOS / PMOS switches only applies a fixed voltage control signal to its gate, usually the power supply voltage. When the source voltage of the high-voltage analog switch fluctuates, its on-resistance changes with the gate-source voltage, resulting in a decrease in the linearity of the on-resistance, thereby affecting the resistor string voltage divider accuracy and the accuracy of the circuit in which the high-voltage analog switch is located;

[0004] (2) The turn-on speed of a high-voltage analog switch is directly related to the turn-on speed of the circuit in which the high-voltage analog switch is located. If it is too slow, the delay will be too large, while if it is too fast, the surge current generated when the circuit in which the high-voltage analog switch is located is too large when it is powered on quickly, which may damage the high-voltage analog switch and downstream loads. Traditional high-voltage analog switches often set the time constant of the switch opening by connecting a capacitor and a megohm-level resistor in series to the gate of the switch tube to extend the turn-on time of the switch tube to reduce the surge current. However, large capacitors and resistors occupy a large area and power consumption, which increases the design cost of the high-voltage analog switch. Summary of the invention

[0005] In view of the problems existing in the prior art, the present invention provides a bootstrap switch circuit for a high-voltage gate, which improves the accuracy and linearity of the output signal of the high-voltage domain analog switch by keeping the gate-source voltage of the analog switch constant, and does not require the capacitor and charge pump in the traditional bootstrap switch. The overall area and power consumption are small, and it can drive both low-voltage switches and high-voltage switches.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solutions: a bootstrap switch circuit for a high voltage gate, comprising: an analog switch M0, a control circuit, an inverter group, and an enable pull-down circuit;

[0007] The drain of the analog switch M0 is used as the input terminal of the analog switch M0 to input the Vin signal; the source and substrate of the analog switch M0 are connected to serve as the output terminal of the analog switch M0 to output the Vout signal;

[0008] The inverter group generates a control signal according to the enable signal EN and inputs the control signal into the control circuit;

[0009] The control circuit controls the gate voltage of the analog switch M0 according to the input control signal so that the on-resistance of the analog switch M0 remains constant;

[0010] When the enable pull-down circuit determines that the bootstrap switch circuit is not working according to the enable signal EN, the bootstrap switch circuit is turned off.

[0011] Furthermore, the inverter group is composed of a first inverter INV1 and a second inverter INV2, the input end of the first inverter INV1 is connected to the enable signal EN, the output end of the first inverter INV1 is respectively connected to the input end of the second inverter INV2 and the input end of the enable pull-down circuit, and the output end of the second inverter INV2 is connected to the input end of the control circuit.

[0012] Further, the control circuit includes: a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M3, a fourth PMOS tube M4, a fifth PMOS tube M5, a first NMOS tube M8, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, the gate of the first NMOS tube M8 serves as a control signal input end of the control circuit, the source of the first NMOS tube M8 is grounded, the drain of the first NMOS tube M8 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is respectively connected to one end of the first resistor R1, the drain of the fourth PMOS tube M4, the gate of the fourth PMOS tube M4, and the gate of the first PMOS tube M1; the other end of the first resistor R1, the source of the third PMOS tube M3, the gate of the fourth PMOS tube M4, and the gate of the first PMOS tube M1 The source of the first PMOS tube M1 is connected to the high power supply voltage VDD, the gate of the third PMOS tube M3 and the drain of the third PMOS tube M3 are connected to the source of the fourth PMOS tube M4; the drain of the first PMOS tube M1 is connected to one end of the third resistor R3, and one end of the third resistor R3 connected to the source of the fifth PMOS tube M5 is used as the control signal output end of the control circuit, the gate of the fifth PMOS tube M5 and the drain of the fifth PMOS tube M5 are connected to the source and substrate of the second PMOS tube M2, the drain of the second PMOS tube M2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded; the gate of the second PMOS tube M2 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the output end of the analog switch M0.

[0013] Further, the first PMOS tube M1 and the second PMOS tube M2 are both high-voltage PMOS tubes, the third PMOS tube M3, the fourth PMOS tube M4 and the fifth PMOS tube M5 are all low-voltage PMOS tubes, and the first NMOS tube M8 is a high-voltage NMOS tube.

[0014] Furthermore, the control signal output terminal of the control circuit is connected to the gate of the analog switch M0 and the enable pull-down circuit respectively.

[0015] Further, the enable pull-down circuit includes: a second NMOS tube M6 and a third NMOS tube M7, the drain of the third NMOS tube M7 is connected to the control signal output end of the control circuit, the source of the third NMOS tube M7 is grounded, the gate of the third NMOS tube M7 and the gate of the second NMOS tube M6 are both connected to the output end of the first inverter INV1, the drain of the second NMOS tube M6 is connected to the output end of the analog switch M0, and the source of the second NMOS tube M6 is grounded.

[0016] Furthermore, the third NMOS tube M7 is a high-voltage NMOS tube.

[0017] Furthermore, when the Vin signal input to the analog switch M0 is less than 5V, the analog switch M0 and the second NMOS tube M6 both use NMOS low-voltage tubes; when the Vin signal input to the analog switch M0 is greater than or equal to 5V, the analog switch M0 and the second NMOS tube M6 both use NMOS high-voltage tubes.

[0018] Compared with the prior art, the present invention has the following beneficial effects: the bootstrap switch circuit of the high-voltage gate of the present invention can ensure the rapid and stable conduction of the analog switch through the control circuit, and when the conduction impedance of the analog switch is turned on in normal operation, it hardly changes with the voltage change of the signal path, and achieves good linearity. In addition, the traditional bootstrap switch is realized by capacitor charging and discharging, which utilizes the characteristic that the voltage difference across the capacitor will not change suddenly. In order to keep the gate-source voltage of the bootstrap switch constant, the clock and charge pump are usually required to cooperate; while the bootstrap switch circuit of the present invention utilizes the gate voltage of the second PMOS tube and the source voltage of the fifth PMOS tube in the control circuit to control the gate-source voltage of the analog switch M0, so that the gate-source voltage of the analog switch is equal to the sum of the gate voltage of the second PMOS tube and the source voltage of the fifth PMOS tube, and remains almost unchanged, and does not require the capacitor and charge pump in the traditional bootstrap switch, which reduces the area cost, and can drive both low-voltage switches and high-voltage switches. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a circuit diagram of the bootstrap switch circuit of the high voltage gate of the present invention. DETAILED DESCRIPTION

[0020] The technical solution of the present invention is further explained below in conjunction with the accompanying drawings.

[0021] like Figure 1The present invention discloses a bootstrap switch circuit for a high-voltage gate, comprising: an analog switch M0, a control circuit, an inverter group, and an enable pull-down circuit; the drain of the analog switch M0 is used as the input terminal of the analog switch M0, and a Vin signal is input; the source and substrate of the analog switch M0 are connected, and are used as the output terminal of the analog switch M0, and a Vout signal is output; the inverter group generates a control signal according to an enable signal EN, and inputs the control circuit; the control circuit controls the gate voltage of the analog switch M0 according to the input control signal, so that the on-resistance of the analog switch M0 remains constant; when the enable pull-down circuit determines that the bootstrap switch circuit is not working according to the enable signal EN, the bootstrap switch circuit is turned off. The present invention improves the accuracy and linearity of the output signal of the high-voltage domain analog switch by keeping the gate-source voltage of the analog switch M0 constant, and does not require the capacitor and charge pump in the traditional bootstrap switch, and has a small overall area and power consumption, and can drive both low-voltage switches and high-voltage switches.

[0022] The inverter group in the present invention is composed of a first inverter INV1 and a second inverter INV2. The input end of the first inverter INV1 is connected to the enable signal EN, and the output end of the first inverter INV1 is respectively connected to the input end of the second inverter INV2 and the input end of the enable pull-down circuit. The output end of the second inverter INV2 is connected to the input end of the control circuit. The first inverter INV1 is used to generate an inverted control signal to control the enable pull-down circuit to be turned on and the bootstrap switch circuit to be turned off; the second inverter INV2 is used to generate a non-inverting control signal to control the gate voltage of the analog switch M0 through the control circuit.

[0023] The control circuit of the present invention comprises: a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M3, a fourth PMOS tube M4, a fifth PMOS tube M5, a first NMOS tube M8, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, the gate of the first NMOS tube M8 is used as a control signal input end of the control circuit, the source of the first NMOS tube M8 is grounded, the drain of the first NMOS tube M8 is connected to one end of the second resistor R2, the other end of the second resistor R2 is respectively connected to one end of the first resistor R1, the drain of the fourth PMOS tube M4, the gate of the fourth PMOS tube M4 and the gate of the first PMOS tube M1; the other end of the first resistor R1, the source of the third PMOS tube M3 and the source of the first PMOS tube M1 are connected to the control signal input end of the control circuit, the source of the first NMOS tube M8 is grounded, the drain of the first NMOS tube M8 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is respectively connected to one end of the first resistor R1, the drain of the fourth PMOS tube M4, the gate of the fourth PMOS tube M4 and the gate of the first PMOS tube M1; the other end of the first resistor R1, the source of the third PMOS tube M3 and the source of the first PMOS tube M1 are connected to the control signal input end of the control circuit, and the control signal input end of the control circuit is used as the control signal input end of the control circuit. The gates of the third PMOS tube M3 and the drain of the third PMOS tube M3 are connected to the source of the fourth PMOS tube M4; the drain of the first PMOS tube M1 is connected to one end of the third resistor R3, and one end of the third resistor R3 connected to the source of the fifth PMOS tube M5 is used as the control signal output end of the control circuit, and is respectively connected to the gate of the analog switch M0 and the enable pull-down circuit; the gate of the fifth PMOS tube M5 and the drain of the fifth PMOS tube M5 are connected to the source and substrate of the second PMOS tube M2, the drain of the second PMOS tube M2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded; the gate of the second PMOS tube M2 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the output end of the analog switch M0. The control circuit of the present invention controls the on-off of the analog switch M0 by the sum of the gate voltage of the second PMOS tube M2 and the source voltage of the fifth PMOS tube M5. The control circuit does not require capacitors and clock drives, reduces area costs, and is suitable for application scenarios of high-voltage MUX; in addition, the conduction speed of the analog switch M0 in the present invention is mainly related to the resistance value of the third resistor R3. The conduction speed of the analog switch M0 can be increased by reducing the resistance value of the third resistor R3.

[0024] Since the power supply voltage V DD Both are greater than 5V. When the enable is turned off, the drain voltage of the first NMOS tube M8 will become VDD. Therefore, the first NMOS tube M8 must be a high-voltage NMOS tube. Since the drain of the second PMOS tube M2 is connected in series with the fourth resistor R4 and then grounded, its source voltage is Vin+Vsg2, which may exceed 5V. Therefore, the second PMOS tube M2 must use a high-voltage PMOS tube. When the bootstrap switch circuit works normally, the source voltage of the first PMOS tube M1 is V DD , the drain voltage of the first PMOS tube M1 is equal to Vin+V SG2 +V SG5+R3×I3, if the input Vin is very small, the drain voltage of the first PMOS tube M1 is also very small, which may cause an overvoltage condition in the first PMOS tube M1, so the first PMOS tube M1 must be a high-voltage PMOS tube; the third PMOS tube M3, the fourth PMOS tube M4 and the fifth PMOS tube M5 are all diode-connected, and their drain voltage is one Vsg lower than the source when they work normally in the high-voltage domain, and no overvoltage condition occurs. Therefore, the third PMOS tube M3, the fourth PMOS tube M4 and the fifth PMOS tube M5 are all low-voltage PMOS tubes.

[0025] The enable pull-down circuit in the present invention comprises: a second NMOS tube M6 and a third NMOS tube M7, the drain of the third NMOS tube M7 is connected to the control signal output end of the control circuit, the source of the third NMOS tube M7 is grounded, the gate of the third NMOS tube M7 and the gate of the second NMOS tube M6 are both connected to the output end of the first inverter INV1, the drain of the second NMOS tube M6 is connected to the output end of the analog switch M0, the source of the second NMOS tube M6 is grounded, and when the enable pull-down circuit determines that the bootstrap switch circuit is not working according to the enable signal EN, the bootstrap switch circuit is turned off.

[0026] Since the gate voltage V G0 Will be raised to Vin+V SG2 +V SG5 , there will be a situation greater than 5V, therefore, the third NMOS tube M7 must be a high-voltage NMOS tube. When the Vin signal input by the analog switch M0 is less than 5V, the analog switch M0 and the second NMOS tube M6 both use NMOS low-voltage tubes; when the Vin signal input by the analog switch M0 is greater than or equal to 5V, the analog switch M0 and the second NMOS tube M6 both use NMOS high-voltage tubes, so that the bootstrap switch circuit can drive both the low-voltage switch and the high-voltage switch.

[0027] The specific working process of the bootstrap switch circuit of the high voltage gate of the present invention is as follows:

[0028] When the enable signal EN is 0, after passing through the first inverter INV1 and the second inverter INV2, the first NMOS tube M8 is in the cut-off region, and the gate potential of the first PMOS tube M1 is pulled up to the high power supply voltage VDD. Therefore, the first PMOS tube M1, the third PMOS tube M3 and the fourth PMOS tube M4 are all turned off; and the gate of the second NMOS tube M6 and the gate of the third NMOS tube M7 are connected to the output end of the first inverter INV1. At this time, the second NMOS tube M6, the third NMOS tube M7 The OS tube M7 is turned on, and the gate and source voltages of the analog switch M0 are pulled to the ground potential. The source voltage of the fifth PMOS tube M5 is pulled down to 0, and the gate voltage of the second PMOS tube M2 is also pulled down to 0. No current flows through the second PMOS tube M2 and the fifth PMOS tube M5. At this time, the drain voltage of the fifth PMOS tube M5 and the source voltage of the second PMOS tube M2 are 0, and the second PMOS tube M2, the fifth PMOS tube M5 and the analog switch M0 are all turned off, and the signal path where they are located is in an open state.

[0029] When the enable signal EN is 1, the gate of the second NMOS tube M6 and the gate of the third NMOS tube M7 are connected to the output end of the first inverter INV1, and at this time, the second NMOS tube M6 and the third NMOS tube M7 are turned off; after the enable signal EN passes through the first inverter INV1 and the second inverter INV2, the first NMOS tube M8 is turned on and is in the linear region. The on-resistance of M8 is negligible compared with the first resistor R1 and the second resistor R2. A voltage drop is generated on the first resistor R1 to turn on the first PMOS tube M1. The third PMOS tube M3 and the fourth PMOS tube M4 form a clamping circuit for the gate and source voltage of the first PMOS tube M1, and control the gate and source voltage of the first PMOS tube M1 to be the sum of the gate and source voltages of the third PMOS tube M3 and the fourth PMOS tube M4, so as to avoid the gate and source voltage of the first PMOS tube M1 being too large to break down the first PMOS tube M1, thereby making the bootstrap switch circuit invalid. After the first PMOS tube M1 is turned on, the current flows through the third resistor R3, the fifth PMOS tube M5, the second PMOS tube M2 and the fourth resistor R4. Since the output signal Vout of the analog switch M0 is initially at the ground potential, the second PMOS tube M2 and the fifth PMOS tube M5 are in a saturated state, and the source voltage of the fifth PMOS tube M5 increases, so that the analog switch M0 is turned on. Thereafter, the output voltage Vout of the analog switch M0 is equal to the input voltage Vin. When Vout=Vin>0, the gate voltage of the second PMOS tube M2 becomes higher, so that the gate control potential VG0 of the analog switch M0 generated eventually also becomes higher. After reaching the stable voltage, the gate and source voltages of the analog switch M0 are controlled by the second PMOS tube M2 and the fifth PMOS tube M5, and its gate-source voltage is the sum of the gate and source voltages of the second PMOS tube M2 and the fifth PMOS tube M5. During normal operation, since the analog switch M0 and the first PMOS tube M1 are in the deep linear region, and the second PMOS tube M2 and the fifth PMOS tube M5 are in the saturation region, the bootstrap switch circuit satisfies the following relationship:

[0030]

[0031]

[0032] Among them, V DD For high supply voltage, V SG2 、V SG5 are the voltage difference between the source and gate of the second PMOS tube M2 and the fifth PMOS tube M5, I3 is the current flowing through the third resistor R3, R on is the on-resistance of analog switch M0, V th2 is the threshold voltage of the second PMOS tube M2, V th5 is the threshold voltage of the fifth PMOS tube M5, V THN represents the threshold voltage of analog switch M0, and are the width-to-length ratios of the analog switch M0, the second PMOS transistor M2, and the fifth PMOS transistor M5, μ n and u p are the mobility of NMOS and PMOS respectively, C os is the gate oxide capacitance per unit area.

[0033] When the width-to-length ratios of the second PMOS tube M2 and the fifth PMOS tube M5 are the same, the threshold voltages of the second PMOS tube M2 and the fifth PMOS tube M5 are the same, both of which are V THP , we can calculate:

[0034]

[0035] Therefore, the gate and source voltages of the analog switch M0 are mainly affected by the resistance of the third R3 and the width-to-length ratio of the second PMOS tube M2 and the fifth PMOS tube M5, and are little affected by the input Vin. The gate and source voltages of the analog switch M0 are equal to the sum of the gate-source voltages of the second PMOS tube M2 and the fifth PMOS tube M5, and the gate and source voltages of the analog switch M0 remain constant.

[0036] In the traditional structure, the gate voltage of the high-voltage analog switch when it is turned on is the power supply voltage, and it is in the linear region, and its drain voltage is equal to the source voltage. The fluctuation from the external signal will affect the gate-source voltage of the analog switch tube, causing the switch on-resistance to change significantly with the input. In the bootstrap switch circuit of the high-voltage gate of the present invention, due to the presence of the second PMOS tube M2 and the fifth PMOS tube M5, the gate voltage of the analog switch M0 changes with the source voltage, and the difference, that is, the gate-source voltage of the analog switch M0, is approximately a constant value, achieving good linearity.

[0037] The above are only preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims

1. A bootstrap switch circuit for a high voltage gate, characterized in that: include: Analog switch M0, control circuit, inverter group, enable pull-down circuit; The drain of the analog switch M0 serves as the input terminal of the analog switch M0 and inputs the Vin signal; The source and substrate of the analog switch M0 are connected as the output end of the analog switch M0 to output a Vout signal; The inverter group generates a control signal according to the enable signal EN and inputs the control signal into the control circuit; The control circuit controls the gate voltage of the analog switch M0 according to the input control signal so that the on-resistance of the analog switch M0 remains constant; When the enable pull-down circuit determines that the bootstrap switch circuit is not working according to the enable signal EN, the bootstrap switch circuit is turned off; The control circuit includes: a first PMOS tube M1, a second PMOS tube M2, a third PMOS tube M3, a fourth PMOS tube M4, a fifth PMOS tube M5, a first NMOS tube M8, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4 and a fifth resistor R5, the gate of the first NMOS tube M8 is used as a control signal input end of the control circuit, the source of the first NMOS tube M8 is grounded, the drain of the first NMOS tube M8 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is respectively connected to one end of the first resistor R1, the drain of the fourth PMOS tube M4, the gate of the fourth PMOS tube M4 and the gate of the first PMOS tube M1; the other end of the first resistor R1, the source of the third PMOS tube M3, the first PMOS tube M4 and the fifth PMOS tube M5 are connected to the gate of the first PMOS tube M1; The source of the MOS tube M1 is connected to the high power supply voltage VDD, the gate of the third PMOS tube M3 and the drain of the third PMOS tube M3 are connected to the source of the fourth PMOS tube M4; the drain of the first PMOS tube M1 is connected to one end of the third resistor R3, and one end of the third resistor R3 connected to the source of the fifth PMOS tube M5 is used as the control signal output end of the control circuit, the gate of the fifth PMOS tube M5 and the drain of the fifth PMOS tube M5 are connected to the source and substrate of the second PMOS tube M2, the drain of the second PMOS tube M2 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded; the gate of the second PMOS tube M2 is connected to one end of the fifth resistor R5, and the other end of the fifth resistor R5 is connected to the output end of the analog switch M0.

2. A bootstrap switch circuit for a high voltage gate according to claim 1, characterized in that: The inverter group consists of a first inverter INV1 and a second inverter INV2, the input end of the first inverter INV1 is connected to the enable signal EN, the output end of the first inverter INV1 is respectively connected to the input end of the second inverter INV2 and the input end of the enable pull-down circuit, and the output end of the second inverter INV2 is connected to the input end of the control circuit.

3. The bootstrap switch circuit of a high voltage gate according to claim 1, characterized in that: The first PMOS tube M1 and the second PMOS tube M2 are both high-voltage PMOS tubes, the third PMOS tube M3, the fourth PMOS tube M4 and the fifth PMOS tube M5 are all low-voltage PMOS tubes, and the first NMOS tube M8 is a high-voltage NMOS tube.

4. The bootstrap switch circuit of a high voltage gate according to claim 1, characterized in that: The control signal output terminal of the control circuit is connected to the gate of the analog switch M0 and the enable pull-down circuit respectively.

5. The bootstrap switch circuit of a high voltage gate according to claim 4, characterized in that: The enable pull-down circuit includes: a second NMOS tube M6 and a third NMOS tube M7, the drain of the third NMOS tube M7 is connected to the control signal output end of the control circuit, the source of the third NMOS tube M7 is grounded, the gate of the third NMOS tube M7 and the gate of the second NMOS tube M6 are both connected to the output end of the first inverter INV1, the drain of the second NMOS tube M6 is connected to the output end of the analog switch M0, and the source of the second NMOS tube M6 is grounded.

6. The bootstrap switch circuit of a high voltage gate according to claim 5, characterized in that: The third NMOS transistor M7 is a high-voltage NMOS transistor.

7. The bootstrap switch circuit of a high voltage gate according to claim 5, characterized in that: When the Vin signal input by the analog switch M0 is less than 5V, the analog switch M0 and the second NMOS tube M6 both use NMOS low-voltage tubes; when the Vin signal input by the analog switch M0 is greater than or equal to 5V, the analog switch M0 and the second NMOS tube M6 both use NMOS high-voltage tubes.

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