Novel time offset calibration circuit and method

Abstract

The invention provides a novel time offset calibration circuit and method, and belongs to the technical field of analog ICs. Comprising a buffer A and a buffer B which are connected in sequence, the output node of the buffer A is grounded through a capacitor, the output node of the buffer A is grounded through a resistor and a current source set controlled by a switch, and the output end of the buffer B is connected with a time offset detection circuit. According to the clock offset calibration circuit provided by the invention, a novel topological structure is adopted, and the calibration range of time offset can be greatly expanded without a lengthy buffer chain, so that the introduction of noise is reduced. The time offset adjustment step length of the circuit structure is not limited by the minimum size of the capacitor, and has no extremely high matching requirement on the capacitor. The time offset calibration with a small step length can be realized by controlling the extracted current, and the calibration precision is ensured while the calibration range is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of analog ICs, and in particular relates to a novel time offset calibration circuit and method. Background Art

[0002] Clock skew refers to the delay difference between multiple sub-clock signals generated by the same clock. It can be expressed in various forms, including the skew between multiple outputs of the clock driver, as well as the skew between the receiving and driving clock signals caused by PCB routing errors. It can also be said to be the time offset of a clock source reaching the clock ends of two different registers. Figure 1 This is a schematic diagram of time offset, where "t" is the time offset.

[0003] In high-speed signal processing circuits, signals are generally sampled through a timing-controlled switched capacitor circuit for subsequent circuit processing. As signal processing speed increases, circuits have higher and higher requirements for clock quality. However, since the timing of clock paths transmitted by different circuits will have a certain offset, for ultra-high-speed circuits, it will bring unacceptable phase noise. Therefore, in ultra-high-speed circuits, it is usually necessary to design a special calibration circuit for the clock offset.

[0004] Existing clock offset calibration technologies mostly use variable delay buffers (inverters) to calibrate clock offset by changing the driving capability of the buffer. For example, the driving current of the buffer can be changed by adjusting the gate voltage of the tail current source, such as Figure 2 As shown, for the tail current of the MOS tube, this control method is nonlinear, and the control accuracy is limited by the step size of the tail current gate voltage change. The prior art also calibrates the clock offset by changing the buffer load through the switch capacitor, such as Figure 3 As shown, however, the calibration accuracy of this solution depends on the minimum capacitance value of the process and is limited by the mismatch of the process itself, so it is difficult to achieve high-precision regulation. In addition, when a clock offset with a larger adjustment range is required, the capacitance load required by the structure of this solution will also increase. In order to avoid excessive load on a single buffer, a lengthy buffer chain and load chain are required. However, in noise-sensitive circuits, longer buffer chains introduce greater noise, thereby limiting the maximum adjustment range of this solution. Summary of the invention

[0005] The purpose of the present invention is to provide a novel time offset calibration circuit and method to solve the technical problems of limited calibration accuracy and maximum adjustment range proposed in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions: A novel time offset calibration circuit comprises a buffer A and a buffer B connected in sequence, wherein the output node of the buffer A is grounded through a capacitor, the output node of the buffer A is grounded through a resistor and a current source group controlled by a switch, and the output end of the buffer B is connected to a time offset detection circuit.

[0007] Preferably, the capacitor is a small load capacitor, the size of which is limited by the clock offset calibration range and the driving capability of the buffer A, and the current source group is composed of a plurality of current sources.

[0008] Another object of the present invention is to provide a novel time offset calibration method. Based on the novel time offset calibration circuit, when the output clock generates an offset, the time offset detection circuit sends an N+1-bit digital code for controlling the current source switch to the current source group, and controls whether the corresponding current source is connected to the control node through the digital code, linearly controls the size of the current extracted at the falling edge of the buffer A, changes the falling edge slope of the buffer A, and realizes linear control of the falling edge of the buffer A.

[0009] The present invention has the following beneficial effects: 1. The present invention adopts a topological structure that adds capacitance at the output node of the buffer and connects the capacitor to the ground through a resistor and a current source group controlled by a digital code, thereby greatly avoiding the introduction of a lengthy inverter chain and load capacitance when a large regulation range is required, reducing circuit noise and saving circuit area.

[0010] 2. The present invention changes the extraction current through the current source group controlled by the digital code to achieve small-step time offset calibration, which reduces the dependence on circuit technology and greatly improves the accuracy of time offset calibration without requiring a very small-size process.

[0011] 3. The present invention calibrates the time offset by a current source group controlled by a digital code, which has a higher control linearity than the method of directly changing the gate voltage of the buffer tail current source. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0013] Figure 1 It is a schematic diagram of time offset; Figure 2 A circuit structure diagram of a time offset calibration based on regulating the buffer tail current gate voltage; Figure 3The structure diagram of the time offset calibration circuit based on regulating the load capacitance; Figure 4 It is a structural diagram of an improved time offset calibration circuit in an embodiment of the present invention; Figure 5 FIG. 4 is a timing diagram of an improved time offset calibration circuit in an embodiment of the present invention.

[0014] In the accompanying drawings, the components represented by the various symbols are as follows: Buffer A-1, buffer B-2, time offset detection circuit-3, current source group-4. DETAILED DESCRIPTION

[0015] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0016] See also Figure 4-Figure 5 As shown, a novel time offset calibration circuit includes a buffer A1 and a buffer B2 connected in sequence, wherein the output node of the buffer A1 is grounded through a capacitor, and the capacitor is a small load capacitor, so that the falling edge of the buffer A1 slows down to improve the control range. It also includes that the output node of the buffer A1 is grounded through a resistor and a current source group 4 controlled by a switch. The current source group 4 is composed of a plurality of current sources, and the current sources are turned on by switch control. The output end of the buffer B2 is connected to a time offset detection circuit 3. The buffer A1 buffers the input clock signal to ensure the stability and driving capability of the signal, and the buffer B2 buffers the processed clock signal to output a stable clock signal.

[0017] When the output clock is offset, the time offset detection circuit 3 sends the N+1-bit digital code for controlling the current source switch to the current source group 4, and controls whether the corresponding current source is connected to the control node through the digital code, thereby linearly regulating the current extracted at the falling edge of the buffer A1, thereby changing the falling edge slope of the buffer A1, thereby achieving linear regulation of the falling edge of the buffer A1.

[0018] For example, when the clock of Clk_out shifts backward, after the time offset detection circuit 3 detects the clock offset, the digital code of the control switch current source group is gradually increased, and more current sources are controlled to be turned on, thereby increasing the current drawn from the X node, making the falling edge of the clock here steeper. At this time, the clock edge of Clk_out will be moved forward until it moves to the required time point, thereby realizing the calibration of the clock offset.

[0019] Figure 5 The input and output waveforms of the time offset calibration circuit of the present invention are shown in the figure, and "T" is the clock offset calibration range. When the current controlled by the digital code gradually increases, the voltage drop speed on the capacitor is adjusted to be steeper, thereby achieving the regulation of the clock offset (Skew). The capacitor size is determined by Figure 5 The clock offset calibration range T and Figure 4 Buffer A1 driving capability limitation. When the calibration range T is required to be larger, the capacitance needs to be increased until the slowest falling edge of buffer A1 output covers the calibration range. That is, when the buffer driving force is constant and the falling edge of buffer A1 when the digital control current source current is the smallest ( Figure 5 Buffer A1 output falling edge (black) to the falling edge of buffer A1 when the digitally controlled current source is maximum ( Figure 5 The falling edge of the buffer A1 output (red) is required to cover the time offset calibration range.

[0020] The clock offset calibration circuit proposed in the present invention adopts a novel topological structure, which does not require a lengthy buffer chain, and can greatly improve the calibration range of the time offset, thereby reducing the introduction of noise. The time offset adjustment step of the circuit structure of the present invention is not limited by the minimum size of the capacitor, and there is no extremely high matching requirement for the capacitor. By controlling the extraction current, the time offset calibration of a smaller step can be achieved, and the calibration accuracy is guaranteed while improving the calibration range.

[0021] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.

Claims

1. A novel time offset calibration circuit, comprising a buffer A (1) and a buffer B (2) connected in sequence, characterized in that: The output node of the buffer A (1) is grounded via a capacitor, the output node of the buffer A (1) is grounded via a resistor and a current source group (4) controlled by a switch, and the output end of the buffer B (2) is connected to a time offset detection circuit (3).

2. A novel time offset calibration circuit according to claim 1, characterized in that: The size of the capacitor is limited by the clock offset calibration range and the driving capability of the buffer A (1), and the current source group (4) is composed of a plurality of current sources.

3. A novel time offset calibration method, based on the novel time offset calibration circuit according to claim 1 or 2, characterized in that: When the output clock is offset, the time offset detection circuit (3) sends an N+1-bit digital code for controlling the current source switch to the current source group (4), and controls whether the corresponding current source is connected to the control node through the digital code, thereby adjusting the magnitude of the current drawn at the falling edge of the buffer A (1), changing the falling edge slope of the buffer A (1), and realizing linear control of the falling edge of the buffer A (1).

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