Programmable IO driving chip

Abstract

According to the programmable IO driving chip provided by the invention, the driving voltage is provided for the high-voltage driving module and the high-speed driving module through the built-in programmable power supply module, so that the flexible and configurable high-voltage and high-frequency driving voltage can be provided under the driving of the digital input module, and the driving of external equipment is realized; and a comparison threshold voltage is provided for the comparator module through the built-in power supply module, so that signal detection of external equipment is realized, the driving voltage and the comparison threshold voltage required by the driving module and the comparator module are internally provided, and a user only needs to configure the required voltage by using a configuration instruction. A power supply chip does not need to be additionally arranged for an external power supply to supply power, and the power supply module is programmable in voltage, higher in compatibility and applicable to various different use occasions, so that power supply of various voltages can be realized without additionally arranging the power supply chip, a power supply circuit is simple, and the device cost is low.

Description

Technical Field

[0001] The present application relates to the field of drive test technology, and in particular to a programmable IO driver chip. Background Art

[0002] In the fields and products of semiconductor ATE (Automatic Test Equipment) testing, aging testing, and general programmers, various IO driver chips or discrete devices are often used to build hardware circuits to achieve signal drive output and input detection, thereby completing defect detection of semiconductor products, troubleshooting potential problems, or completing programming of common chips such as MCU, EEPROM, and FLASH. IO driver chips can support signal drive output and signal input detection within a certain voltage range and a certain frequency range. The architecture of common IO driver chips is generally a simple combination of a single driver and a single window comparator per channel, and the required voltage is provided externally to achieve signal drive output and signal input detection at that voltage.

[0003] The output voltage of the driver and the input threshold voltage of the comparator are both provided by an external power supply. The user needs to design a power supply and add multiple power chips to output the required voltage to the corresponding pins of the IO driver chip in order to use the chip normally. This increases the power supply wiring of the PCB board on the one hand and the device cost of the whole board on the other. Summary of the invention

[0004] The present application provides a programmable IO driver chip, which has low application cost and does not require the design of complex power supply lines.

[0005] A programmable IO driver chip, comprising: A power supply module, used for providing a first driving voltage and a comparison voltage according to a configuration instruction; A digital input module, used for outputting digital drive signals; a high-voltage driving module, connected to the digital input module and the power supply module respectively, for receiving the digital driving signal in a working state, and outputting a high-voltage driving signal according to the first driving voltage under the drive of the digital driving signal; a high-speed driving module, connected to the power module and the high-voltage driving module respectively, for receiving the digital driving signal in a working state, and outputting a high-speed driving signal according to the first driving voltage under the drive of the digital driving signal; The comparator module is connected to the power supply module and is used to convert the analog input signal into a digital logic signal using the comparison voltage as a comparison threshold voltage in a working state, wherein the voltage value of the digital logic signal is within a preset range.

[0006] In one embodiment, the high-speed driving module includes: an input overvoltage protection circuit, connected to the high-voltage drive module and to the power supply module, for receiving the first drive voltage and clamping the first drive voltage within a safety threshold range; a high-speed driving circuit, connected to the input overvoltage protection circuit and the digital input module respectively, for receiving the digital driving signal and the clamped first driving voltage in a working state, and outputting the high-speed driving signal according to the clamped first driving voltage under the drive of the digital driving signal; The output overvoltage protection circuit is connected to the high-speed drive circuit and the high-voltage drive circuit respectively, and is used to receive and output the high-speed drive signal, and disconnect the conductive path between the high-speed drive circuit and the high-voltage drive module when the voltage of the high-voltage drive signal exceeds a voltage threshold.

[0007] In one embodiment, the high-speed drive circuit includes a first driver, a transistor NM1 and a transistor PM1; the first driver is respectively connected to the digital input module, the control end of the transistor NM1 and the control end of the transistor PM1, the first connection end of the transistor PM1 is connected to the input overvoltage protection circuit, the second connection end of the transistor PM1 is commonly connected to the first connection end of the transistor NM1 and is connected to the output overvoltage protection circuit, and the second connection end of the transistor NM1 is used to receive a second drive voltage; the first driver is used to control one of the transistor PM1 and the transistor NM1 to be turned on according to the digital drive signal in a working state.

[0008] In one embodiment, the input overvoltage protection circuit includes a transistor PM2, a transistor PM3, a transistor PM4, a transistor NM2, a transistor NM3 and a current source Is1; the first connection end of the transistor PM2 and the first connection end of the transistor PM3 are respectively used to receive a voltage VCC; the control end and the second connection end of the transistor PM2, the control end of the transistor PM3 and the first connection end of the current source Is1 are commonly connected; the second connection end of the transistor PM3, the control end of the transistor NM3 and the first connection end of the transistor PM4 are commonly connected; the second connection end of the transistor PM4 is connected to the first connection end of the transistor NM2; the second connection end of the current source Is1 and the second connection end of the transistor NM2 are respectively used to receive a voltage VSS; the first connection end of the transistor NM3 is used to receive the first driving voltage, and the second connection end of the transistor NM3 is connected to the first connection end of the transistor PM1; the control end of the transistor PM4 is used to receive a control signal VA; the control end of the transistor NM2 is used to receive a control signal VB.

[0009] In one embodiment, the output overvoltage protection circuit includes a current source Is2, a comparator U logic level conversion module circuit, a transistor PM7, a transistor PM8, a transistor PM9, a transistor NM4, a transistor NM5, a transistor NM6, a transistor NM7 and a resistor R1; the first connection end of the transistor PM7, the first connection end of the transistor PM8 and the first connection end of the transistor PM9 are used to receive a voltage VCC; the control end and the second connection end of the transistor PM7, the control end of the transistor PM8 and the control end of the transistor PM9 are commonly connected and connected to the first end of the current source Is2; the second connection end of the transistor PM8 and the first connection end of the transistor NM4 are commonly connected and connected to the control end of the transistor NM6; the second connection end of the transistor PM9 and the first connection end of the transistor NM5 are commonly connected and connected to the transistor The control end of NM7 is connected; the second end of the current source Is2, the second connection end of the transistor NM4 and the second connection end of the transistor NM5 are commonly connected to receive the voltage VSS; the first connection end of the transistor NM6 and the first connection end of the transistor NM7 are commonly connected, and are respectively connected to the same direction end of the comparator U1 and the high voltage driving module; the reverse end of the comparator U1 is used to receive the reference voltage VTH_OUTOVP, and the output end of the comparator U1 is connected to the input end of the logic level conversion circuit; the output end of the logic level conversion circuit is respectively connected to the control end of the transistor NM4 and the control end of the transistor NM5; the second connection end of the transistor NM6 is commonly connected to the second connection end of the transistor NM7 through the resistor R1, and is respectively connected to the second connection end of the transistor PM1 and the first connection end of the transistor NM1.

[0010] In one embodiment, the high-speed driving module further includes: The delay circuit is connected to the digital input module and the first driver respectively, and is used to delay the digital drive signal by a preset time length before transmitting it to the first driver.

[0011] In one embodiment, the high-voltage driving module includes a second driver, a transistor NM8 and a transistor NM9, the second driver is respectively connected to the digital input module, the control end of the transistor NM8 and the control end of the transistor NM9, the first connection end of the transistor NM8 is used to receive the first driving voltage, the second connection end of the transistor NM8 is commonly connected to the first connection end of the transistor NM9 and connected to the high-speed driving module, and the second connection end of the transistor NM9 is used to receive a third driving voltage; the second driver is used to control one of the transistor NM8 and the transistor NM9 to be turned on according to the digital driving signal in a working state.

[0012] In one embodiment, the digital logic signal includes a first logic signal and a second logic signal, the comparison voltage includes a first comparison voltage and a second comparison voltage, and the comparator module includes: A gating circuit, configured to receive the analog input signal; A high-voltage comparison circuit, comprising a comparator U2 and a comparator U3, wherein the inverting terminal of the comparator U2 is used to receive the first comparison voltage, the non-inverting terminal of the comparator U2 is commonly connected with the inverting terminal of the comparator U3 and connected to the gating circuit, and the non-inverting terminal of the comparator U3 is used to receive the second comparison voltage; the high-voltage comparison circuit is used to receive the analog input signal after being gated by the gating circuit, and compare the analog input signal with the first comparison voltage and the second comparison voltage respectively to obtain a first comparison signal and a second comparison signal; A high-speed level conversion circuit, connected to the gating circuit, for receiving the analog input signal after being gated by the gating circuit, and converting the analog input signal from a single-ended signal to a two-way differential signal; The digital output circuit includes a NOR logic gate circuit and a NAND logic gate circuit. The NOR logic gate circuit is respectively connected to the output end of the comparator U2 and the high-speed level conversion circuit, and is used to perform a NOR logic operation on the first comparison signal and the first differential signal to obtain the first logic signal; the NAND logic gate circuit is respectively connected to the output end of the comparator U3 and the high-speed level conversion circuit, and is used to perform a NAND logic operation on the second comparison signal and the second differential signal to obtain the second logic signal.

[0013] In one embodiment, the gating circuit includes a high-voltage control unit, a low-voltage control unit, a low-voltage protection unit, a transistor PM10, a transistor PM10, a transistor NM10, a transistor NM11 and a transistor NM12; the control end of the transistor PM10 and the control end of the transistor NM10 are respectively connected to the high-voltage control unit; the first connection end of the transistor NM10, the first connection end of the transistor PM10 and the first connection end of the transistor NM11 are commonly connected to receive the analog input signal; the second connection end of the transistor NM10 and the second connection end of the transistor PM10 are commonly connected and connected to the inverting end of the comparator U2; the control end of the transistor NM11 is connected to the low-voltage protection unit. protection unit; the second connection end of the transistor NM11, the first connection end of the transistor PM11 and the first connection end of the transistor NM12 are commonly connected; the second connection end of the transistor PM11 and the second connection end of the transistor NM12 are commonly connected and connected to the high-speed level conversion circuit; the control end of the transistor PM11 and the control end of the transistor NM12 are respectively connected to the low-voltage control unit; the high-voltage control unit is used to control the transistor PM10 and the transistor NM10 to be turned on or off together; the low-voltage control unit is used to control the transistor PM11 and the transistor NM12 to be turned on or off together; the low-voltage protection unit is used to control the transistor NM11 to be turned on or off.

[0014] In one embodiment, the power module comprises: Transistor PM0 and transistor NM0; The feedback circuit comprises a first switch and a second switch, wherein a common output terminal of the high-voltage driving module and the high-speed driving module is connected to a first terminal of the first switch; A DAC conversion circuit for providing an output voltage; an error amplifier, wherein a non-inverting input terminal of the error amplifier is connected to the DAC conversion circuit, and an inverting input terminal of the error amplifier is connected to the second end of the first switch and the first end of the second switch respectively; A high-voltage buffer, wherein an input end of the high-voltage buffer is connected to an output end of the error amplifier, and an output end of the high-voltage buffer is respectively connected to a control end of the transistor PM0 and a control end of the transistor NM0; The first connection end of the transistor NM0 is connected to the power input port PVCC, the first connection end of the transistor PM0 is connected to the ground, the second connection end of the transistor NM0 and the second connection end of the transistor PM0 are commonly connected, and are commonly connected to the second end of the second switch, and the commonly connected end is used to output the first driving voltage.

[0015] In one embodiment, the programmable IO driver chip further includes: The pull-up and pull-down modules are connected to the high-voltage driving module and the high-speed driving module respectively, and are used to pull up or pull down the voltage of the high-voltage driving signal and the voltage of the high-speed driving signal respectively.

[0016] In one embodiment, the pull-up and pull-down modules include an operational amplifier, a transistor PM12, a transistor PM13, a transistor PM14, a transistor PM15, a transistor NM13, a transistor NM14, a transistor NM15, a transistor NM20, a resistor R2, a switch SW0, and a plurality of current mirror units; the in-phase input terminal of the operational amplifier is used to receive a reference voltage VREF, and the output terminal of the operational amplifier is connected to the control terminal of the transistor NM13; the first connection terminal of the transistor PM12 and the first connection terminal of the transistor PM13 are respectively used to receive a voltage VDD; The control terminal and the second connection terminal of the transistor PM12 and the control terminal of the transistor PM13 are connected in common, and are connected to the first connection terminal of the transistor NM13; the second connection terminal of the transistor NM13 is respectively connected to the inverting input terminal of the operational amplifier and the first end of the resistor R2; the second connection terminal of the transistor PM13, the first connection terminal and the control terminal of the transistor NM14, and the control terminal of the transistor NM20 are connected in common; the second end of the resistor R2, the second connection terminal of the transistor NM14, and the first connection terminal of the transistor NM20 are respectively used to receive the voltage VSS. The second connection terminal of the transistor NM20, the first connection terminal and the control terminal of the transistor PM14, and the control terminal of the transistor PM15 are connected in common; the second connection terminal of the transistor PM14 and the first connection terminal of the transistor PM15 are respectively used to receive the first driving voltage; the first connection terminal and the control terminal of the transistor NM15 and the second connection terminal of the transistor PM15 are connected in common; the second connection terminal of the transistor NM15 is used to receive the third driving voltage; Each group of the current mirror units includes a PMOS tube, an NMOS tube, a switch Sp and a switch Sn, wherein the control end of each of the PMOS tubes is connected to the control end of the transistor PM15, and the first connection end of each of the PMOS tubes receives the first driving voltage through the switch Sp; the control end of each of the NMOS tubes is connected to the control end of the transistor NM15, and the first connection end of each of the NMOS tubes receives the third driving voltage through the switch Sn, the second connection end of each group of the PMOS tubes and the second connection end of the NMOS tubes are connected in common, and are connected to the high-voltage driving module and the high-speed driving module through the switch SW0.

[0017] In one of the embodiments, the pull-up and pull-down modules are also used to provide pull-up voltage and source current in a pin connection detection mode; in the pin connection detection mode, the comparator module is in a working state, and the high-voltage drive module and the high-speed drive module are both in a non-working state.

[0018] In one embodiment, the programmable IO driver chip further includes: The short circuit protection module is connected to the high voltage driving module and the high speed driving module respectively, and is used to issue an alarm prompt message if it is detected that the high voltage driving module or the high speed driving module is short-circuited with an external load power supply.

[0019] In one embodiment, the short circuit protection module includes a comparator U5, a comparator U6, a first AND gate circuit, a second AND gate circuit, an inverter, a first anti-spike pulse circuit and a second anti-spike pulse circuit; the non-inverting end of the comparator U5 is connected to the power supply module for receiving the first driving voltage; the inverting end of the comparator U5 is connected to the non-inverting end of the comparator U6, and is respectively connected to the high-voltage driving module and the high-speed driving module; the output end of the comparator U5 is connected to the first input end of the first AND gate circuit; the inverting end of the comparator U6 is used to receive a third driving voltage; the output end of the comparator U6 is connected to the first input end of the second AND gate circuit; the input end of the inverter is connected to the second input end of the first AND gate circuit for receiving a digital input signal; the output end of the inverter is connected to the second input end of the second AND gate circuit; the output end of the first AND gate circuit is connected to the first anti-spike pulse circuit; the output end of the second AND gate circuit is connected to the second anti-spike pulse circuit.

[0020] The above-mentioned programmable IO driver chip provides driving voltage for the high-voltage driver module and the high-speed driver module through a built-in programmable power module, thereby providing flexible and configurable high-voltage and high-frequency driving voltage under the drive of the digital input module to realize the driving of external devices, and provides a comparison threshold voltage for the comparator module through the built-in power module, thereby realizing signal detection of external devices, and providing the required driving voltage and comparison threshold voltage for the driver module and the comparator module from the inside. The user only needs to use the configuration instruction to configure the required voltage, and there is no need to add an additional power chip to supply power for the external power supply. In addition, since the voltage of the power module is programmable, it has higher compatibility and can cope with a variety of different usage scenarios. Therefore, there is no need to add an additional power chip to realize multiple voltage power supply, the power supply line is simple and the device cost is low; in addition, since the input and output ends of the high-voltage drive signal and the high-speed drive signal are respectively connected in common, the input port and output port in the chip can be shared, thereby reducing the pin design and avoiding the increase of the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a structural block diagram of a programmable IO driver chip according to an embodiment of the present application; Figure 2 This is a structural block diagram of a programmable IO driver chip according to another embodiment of the present application; Figure 3 This is a circuit structure diagram of a programmable IO driver chip according to an embodiment of the present application; Figure 4 A circuit structure diagram of an input overvoltage protection circuit according to an embodiment of the present application; Figure 5 A circuit structure diagram of an output overvoltage protection circuit according to an embodiment of the present application; Figure 6 A circuit structure diagram of a delay circuit according to an embodiment of the present application; Figure 7 A circuit structure diagram of a comparator module according to an embodiment of the present application; Figure 8 A circuit structure diagram of a gating circuit according to an embodiment of the present application; Fig. 9 A schematic diagram of a chip application according to an embodiment of the present application; Fig.10 This is a circuit structure diagram of a pull-up and pull-down module according to an embodiment of the present application; Fig.11 A schematic diagram of a chip application according to another embodiment of the present application; Fig.12 A circuit structure diagram of a short-circuit protection circuit according to an embodiment of the present application; Fig.13 A schematic diagram of chip function implementation according to an embodiment of the present application; Fig.14 A schematic diagram of a chip application according to an embodiment of the present application; Fig.15 A schematic diagram of a chip application according to an embodiment of the present application; Fig.16 This is a circuit structure diagram of a power module according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0024] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly. The connection can be a direct connection or an indirect connection.

[0025] In addition, in this application, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0026] Figure 1 FIG. 1 is a block diagram of a programmable IO driver chip according to an embodiment of the present invention. Figure 1 As shown, the programmable IO driver chip includes a power module 110, a digital input module 120, a high-voltage driver module 130, a high-speed driver module 140 and a comparator module 150, wherein the power module 110 is used to provide a first driving voltage and a comparison voltage according to a configuration instruction; the digital input module 120 is used to output a digital driving signal; the high-voltage driver module 130 is respectively connected to the digital input module 120 and the power module 110, and is used to receive the digital driving signal in a working state, and output the high-voltage driving signal according to the first driving voltage under the drive of the digital driving signal; the high-speed driver module 140 is respectively connected to the power module 110 and the high-voltage driver module 130, and is used to receive the digital driving signal in a working state, and output the high-speed driving signal according to the first driving voltage under the drive of the digital driving signal; the comparator module 150 is connected to the power module 110, and is used to convert the analog input signal into a digital logic signal using the comparison voltage as the comparison threshold voltage in a working state, wherein the voltage value of the digital logic signal is within a preset range.

[0027] The power module 110 can output a first driving voltage and a comparison voltage to provide driving voltages to the high-voltage driving module 130 and the high-speed driving module 140, and provide a comparison threshold voltage to the comparator module 150; the configuration instruction can be provided manually or automatically by the device, and the voltage values ​​of the first driving voltage and the comparison voltage can be set through the configuration instruction, which can be applied to a variety of different occasions. In some embodiments, the programmable IO driver chip can be provided with a communication module 230 (refer to Fig.13), used to receive configuration instructions sent by external terminal equipment.

[0028] The digital input module 120 can output a digital driving signal to drive the high-voltage driving module 130 and the high-speed driving module 140. The high-voltage driving module 130 and the high-speed driving module 140 together constitute a driver module for outputting a driving signal to the outside. Among them, the high-voltage driving module 130 can be used to realize the conversion of a digital logic driving signal in a certain voltage range into a signal with high driving capability in another voltage range and output it. The high-speed driving module 140 can obtain a high-frequency high-speed driving signal based on the conversion of the digital logic driving signal to realize high-speed driving of external devices. The high-voltage drive module 130 and the high-speed drive module 140 are connected in common at their input ends for receiving the first drive voltage, and at their output ends for outputting the high-voltage drive signal and the high-speed drive signal, so that the input port and the output port in the chip can be shared, without the need to separately set the input and output pins, thereby avoiding the increase of the chip area; wherein, both the high-voltage drive module 130 and the high-speed drive module 140 receive and output signals in the working state, and their working states are both controllable. Since the high-voltage drive module 130 and the high-speed drive module 140 share pins, at most only one of the high-voltage drive module 130 and the high-speed drive module 140 enters the working state at the same time, that is, only the high-voltage drive signal or the high-speed drive signal can be output.

[0029] The comparator module 150 can be used to realize the conversion of the analog input signal of the external device, convert it into a digital logic signal within a certain voltage range and frequency range, and then send it to the terminal to realize the detection of the analog input signal.

[0030] The above-mentioned programmable IO driver chip provides driving voltage for the high-voltage driver module 130 and the high-speed driver module 140 through the built-in programmable power module 110, so that it can provide flexible and configurable high-voltage and high-frequency driving voltage under the drive of the digital input module 120 to realize the driving of external devices, and provide the comparison threshold voltage for the comparator module 150 through the built-in power module 110, so as to realize the signal detection of the external device, and provide the required driving voltage and comparison threshold voltage for the driver module and the comparator module from the inside. The user only needs to use the configuration instruction to configure the required voltage, and there is no need to add an additional power chip to supply power for the external power supply. In addition, since the voltage of the power module 110 is programmable, it has higher compatibility and can cope with a variety of different usage scenarios. Therefore, there is no need to add an additional power chip to realize multiple voltage power supply, the power supply line is simple and the device cost is low; in addition, since the input end and the output end of the high-voltage drive signal and the high-speed drive signal are respectively connected in common, the input port and the output port in the chip can be shared, thereby reducing the pin design and avoiding the increase of the chip area.

[0031] In one embodiment, the high-speed driving module 140 includes an input overvoltage protection circuit 141, a high-speed driving circuit 142 and an output overvoltage protection circuit 143; the input overvoltage protection circuit 141 is connected to the high-voltage driving module 130 and to the power supply module 110, and is used to receive a first driving voltage and clamp the first driving voltage within a safety threshold range; the high-speed driving circuit 142 is connected to the input overvoltage protection circuit 141 and the digital input module 120 respectively, and is used to receive a digital driving signal and a clamped first driving voltage in a working state, and output a high-speed driving signal according to the clamped first driving voltage under the drive of the digital driving signal; the output overvoltage protection circuit 143 is connected to the high-speed driving circuit 142, and is used to receive and output a high-speed driving signal; the output overvoltage protection circuit 143 is connected to the high-speed driving circuit 142 and the high-voltage driving circuit respectively, and is used to receive and output a high-speed driving signal, and when the voltage of the high-voltage driving signal exceeds the voltage threshold, disconnects the conductive path between the high-speed driving circuit 142 and the high-voltage driving module 130.

[0032] It can be understood that since the high-speed drive module 140 and the high-voltage drive module 130 input terminals are connected in common, the driving voltage required by the high-voltage drive module 130 is higher than that of the high-speed drive module 140, so the first driving voltage provided by the power module 110 is a voltage suitable for the high-voltage drive module 130, and the high-speed drive module 140 will first step down the voltage after receiving the first driving voltage, and then use it for internal driving. Specifically, the first driving voltage can be first stepped down by the input overvoltage protection circuit 141, and after clamping it within the safety threshold range, it is provided to the high-speed drive circuit 142 for driving. Since the high-speed drive module 140 and the high-voltage drive module 130 output terminals are connected in common, in order to prevent the high-voltage drive signal output by the high-voltage drive module 130 from damaging the driving body in the high-speed drive module 140, the output overvoltage protection circuit 143 can be used to isolate the high-voltage drive module 130, and when it is detected that the high-voltage drive signal exceeding the voltage threshold is received at the common connection terminal with the high-voltage drive module 130, the conductive path between the high-speed drive circuit 142 and the high-voltage drive module 130 is disconnected.

[0033] In the application, IO driver chips have certain requirements for voltage and frequency. From the perspective of the driver, if you want to achieve high-voltage drive, high-voltage devices, such as 24V or 30V MOS tubes, must be used in the driver circuit design. However, the minimum size of such devices is very large, which brings large parasitic capacitance and cannot achieve high-speed drive; if you want to increase the drive frequency, you need to increase the width-to-length ratio of the MOS tube. In this way, on the one hand, the area of ​​the circuit is increased, and on the other hand, when the width-to-length ratio increases to a certain extent, the drive frequency cannot be increased. To achieve high-speed drive, the most cost-effective way is to use low-voltage devices, which have a small minimum size and small parasitic capacitance, and can easily achieve high-speed drive, but they have voltage limitations. Therefore, the existing conventional IO driver chips have obvious shortcomings in the driver and cannot take into account both high voltage and high speed. Even if some products realize the integration of high-voltage drive and high-speed drive on one chip, their circuits are relatively independent in the chip, and their power supplies and pins are discrete, which increases the chip area, and there is no high-voltage resistance on the high-speed drive pins, which has high requirements for the reliability design of the application circuit.

[0034] The above-mentioned input overvoltage protection circuit 141 and output overvoltage protection circuit 143 can realize the common connection with the input and output of the high-voltage driving module 130, taking into account both high voltage and high speed, ensuring that high voltage and high speed share the same input and output pins, while avoiding the increase of chip area; the back end of the high-speed driving circuit 142 is connected to the protection module, and then connected to the same output port as the output of the high-voltage driving module 130, so as to realize compatible output of high-voltage driving and high-speed driving on the same port, and prevent high voltage from being backflowed into the high-speed driving module 140 to cause circuit damage.

[0035] In one embodiment, the high-speed driving circuit 142 includes a first driver 1421, a transistor NM1 and a transistor PM1. Figure 3 As shown; the first driver 1421 is respectively connected to the digital input module 120, the control end of the transistor NM1 and the control end of the transistor PM1, the first connection end of the transistor PM1 is connected to the input overvoltage protection circuit 141, the second connection end of the transistor PM1 is commonly connected to the first connection end of the transistor NM1, and is connected to the output overvoltage protection circuit 143, and the second connection end of the transistor NM1 is used to receive a second driving voltage (represented by VSS in the figure); the first driver 1421 is used to control one of the transistor PM1 and the transistor NM1 to be turned on according to the digital driving signal in the working state.

[0036] As shown in the figure, according to the digital driving signal, the first driver 1421 can select to turn on the transistor PM1 or the transistor NM1, thereby outputting a high level or a low level. VH represents the first driving voltage, which is transmitted to the first connection terminal of the transistor PM1 after voltage limiting by the input overvoltage protection circuit 141, and VDDH represents the first driving voltage VH after voltage limiting; when the transistor PM1 is turned on, the voltage PRE_DOUT at the output terminal is pulled up to a high level, and is output after passing through the output overvoltage protection circuit 143; when the transistor NM1 is turned on, the voltage PRE_DOUT at the output terminal is pulled down to a low level, and is output after passing through the output overvoltage protection circuit 143.

[0037] The transistor PM1 can be a PMOS transistor, and the transistor NM1 can be an NMOS transistor, both of which are low-voltage MOS transistors, thereby reducing delay and achieving high-speed driving. The first driver 1421 uses the internal power supply voltage 5V as the power rail to drive the final output MOS transistor of the VDDH-VSS power rail.

[0038] In one embodiment, Figure 4 As shown, the input overvoltage protection circuit 141 includes a transistor PM2, a transistor PM3, a transistor PM4, a transistor NM2, a transistor NM3 and a current source Is1; the first connection end of the transistor PM2 and the first connection end of the transistor PM3 are respectively used to receive the voltage VCC; the control end and the second connection end of the transistor PM2, the control end of the transistor PM3 and the first connection end of the current source Is1 are commonly connected; the second connection end of the transistor PM3, the control end of the transistor NM3 and the first connection end of the transistor PM4 are commonly connected; the second connection end of the transistor PM4 is connected to the first connection end of the transistor NM2; the second connection end of the current source Is1 and the second connection end of the transistor NM2 are respectively used to receive the voltage VSS; the first connection end of the transistor NM3 is used to receive the first driving voltage VH, and the second connection end of the transistor NM3 is connected to the first connection end of the transistor PM1; the control end of the transistor PM4 is used to receive the control signal VA; the control end of the transistor NM2 is used to receive the control signal VB.

[0039] It can be understood that the control signal VA and the control signal VB are used to control the conduction and disconnection of the transistor PM4 and the transistor NM2, respectively. The transistor PM2 and the transistor PM3 form a current mirror. When the transistor PM4 and the transistor NM2 are both turned on, the voltage V_OVP+vth will be generated at the a terminal, thereby turning on the transistor NM3. If the threshold voltage of the transistor NM3 is vth, then the voltage VDDH is equal to V_OVP+vth-vth, that is, equal to V_OVP. Therefore, by controlling the transistor PM4 and the transistor NM2, the voltage VDDH can be limited. Assuming the limiting voltage is 5V, using the above circuit, the VDDH voltage can be equal to the VH voltage within the range below 5V. If the VH voltage is higher than 5V, the VDDH voltage is limited to 5V, thereby protecting the high-speed drive circuit 142.

[0040] Wherein, VCC is a fixed power supply voltage, and VSS is a power ground voltage. In some embodiments, the input overvoltage protection circuit 141 is further provided with a diode D1, whose cathode is connected to the gate of the transistor NM3, and whose anode is used to receive the second driving voltage VSS, which can be used to clamp the gate voltage of the transistor NM3 to prevent the gate voltage of the transistor NM3 from being too high.

[0041] In one embodiment, Figure 5As shown, the output overvoltage protection circuit 143 includes a current source Is2, a comparator U1, a logic level conversion module circuit, a transistor PM7, a transistor PM8, a transistor PM9, a transistor NM4, a transistor NM5, a transistor NM6, a transistor NM7 and a resistor R1; the first connection end of the transistor PM7, the first connection end of the transistor PM8 and the first connection end of the transistor PM9 are used to receive the voltage VCC; the control end and the second connection end of the transistor PM7, the control end of the transistor PM8 and the control end of the transistor PM9 are commonly connected and connected to the first end of the current source Is2; the second connection end of the transistor PM8 and the first connection end of the transistor NM4 are commonly connected and connected to the control end of the transistor NM6; the second connection end of the transistor PM9 and the first connection end of the transistor NM5 are commonly connected and connected to the transistor NM 7; the second end of the current source Is2, the second connection end of the transistor NM4 and the second connection end of the transistor NM5 are commonly connected to receive the voltage VSS; the first connection end of the transistor NM6 and the first connection end of the transistor NM7 are commonly connected, and are respectively connected to the same direction end of the comparator U1 and the high voltage driving module 130; the reverse end of the comparator U1 is used to receive the reference voltage VTH_OUTOVP, and the output end of the comparator U1 is connected to the input end of the logic level conversion circuit 1431; the output end of the logic level conversion circuit 1431 is respectively connected to the control end of the transistor NM4 and the control end of the transistor NM5; the second connection end of the transistor NM6 is commonly connected to the second connection end of the transistor NM7 through the resistor R1, and is respectively connected to the second connection end of the transistor PM1 and the first connection end of the transistor NM1.

[0042] It can be understood that the comparator U1 can be used to compare the common terminal voltage (represented by DOUT in the figure) of the high-voltage driving module 130 and the high-speed driving module 140 with the reference voltage VTH_OUTOVP. If the common terminal voltage exceeds the reference voltage VTH_OUTOVP, it may indicate that the high-voltage driving signal output by the high-voltage driving module 130 exceeds the safety threshold of the high-speed driving circuit 142. At this time, in order to avoid damage to the high-speed driving circuit 142, the SD-A signal and the SD-B signal can be pulled high, thereby directly turning off the transistor NM6 and the transistor NM7 on the output series path, completing the isolation of the high-speed driving circuit 142 and the high voltage of the output port, thereby protecting the high-speed driving circuit 142; wherein the transistor NM6 and the transistor NM7 can be high-voltage thick-gate NMOS tubes.

[0043] In addition, the circuit also has an output impedance selection function. The impedances of the paths where transistors NM6 and NM7 are located are different. By selecting different high-voltage thick-gate NMOS tubes, namely transistors NM6 and NM7, impedance selection can be completed to achieve impedance matching on the high-speed drive signal path.

[0044] In one embodiment, continue to refer to Figure 3 The high-voltage driving module 130 includes a second driver 131, a transistor NM8 and a transistor NM9. The second driver 131 is respectively connected to the digital input module 120, the control end of the transistor NM8 and the control end of the transistor NM9. The first connection end of the transistor NM8 is used to receive a first driving voltage (represented by VH). The second connection end of the transistor NM8 is commonly connected to the first connection end of the transistor NM9 and is connected to the high-speed driving module 140. The second connection end of the transistor NM9 is used to receive a third driving voltage (represented by VL). The second driver 131 is used to control one of the transistor NM8 and the transistor NM9 to be turned on according to the digital driving signal in the working state.

[0045] As shown in the figure, according to the digital drive signal, the second driver 131 can select to turn on the transistor NM8 or the transistor NM9, thereby outputting a high level or a low level. VH represents the first drive voltage, and the upper limit can be set to VCC-5V; VL represents the third drive voltage, which can be provided by an external power supply and can generally be connected to VSS; when the transistor NM8 is turned on, the voltage DOUT at the output end is pulled up to a high level for output; when the transistor NM9 is turned on, the voltage DOUT at the output end is pulled down to a low level for output.

[0046] The transistor NM8 and the transistor NM9 can be NMOS tubes, which are both high-voltage thick-gate MOS tubes. The second driver 131 uses a driving circuit with VCC-VSS as the power rail to drive the final output MOS tube of the VH-VL power rail. The upper tube and the lower tube of the final output MOS tube are both high-voltage thick-gate NMOS tubes, so that high-voltage driving can be achieved while ensuring the output signal quality.

[0047] In one embodiment, the high-speed driving module 140 further includes a delay circuit 144, referring to Figure 3 As shown, the delay circuit 144 is connected to the digital input module 120 and the first driver 1421 respectively, and is used to delay the digital driving signal by a preset time length before transmitting it to the first driver 1421.

[0048] It can be understood that by setting the delay circuit 144 in the high-speed driving module 140, the delay can be adjusted as needed to achieve timing matching, which can be adapted to some occasions that require signal timing matching. In some embodiments, the circuit structure of the delay circuit 144 can refer to Figure 6 As shown, it may include multiple buffers and selection circuits connected in cascade, the first-stage buffer is connected to the digital input module 120, and the output end of each buffer is also connected to each channel of the selection circuit respectively. Each buffer can delay the digital drive signal for a certain time, and control a certain channel of the conduction selection circuit by delaying the selection signal, and a corresponding number of buffer delays can be selected, thereby delaying the corresponding time.

[0049] In one embodiment, Figure 7 As shown, the digital logic signal includes a first logic signal and a second logic signal (indicated by QH and QL in the figure), the comparison voltage includes a first comparison voltage and a second comparison voltage, the comparator module 150 includes a gating circuit 151, a high-voltage comparison circuit 154, a high-speed level conversion circuit 152 and a digital output circuit 153, the gating circuit 151 is used to receive the analog input signal VINP; the high-voltage comparison circuit 154 includes a comparator U2 and a comparator U3, the inverting end of the comparator U2 is used to receive the first comparison voltage CVH, the non-inverting end of the comparator U2 is connected to the inverting end of the comparator U3, and is connected to the gating circuit 151, and the non-inverting end of the comparator U3 is used to receive the second comparison voltage CVL; the high-voltage comparison circuit 154 is used to receive the analog input signal after being selected by the gating circuit 151, and compare the analog input signal with The first comparison voltage is compared with the second comparison voltage to obtain a first comparison signal and a second comparison signal; the high-speed level conversion circuit 152 is connected to the selection circuit 151, and is used to receive the analog input signal after being selected by the selection circuit 151, and convert the analog input signal from a single-ended signal into a two-way differential signal; the digital output circuit 153 includes a NOR logic gate circuit N1 and a NAND logic gate circuit N2, and the NOR logic gate circuit N1 is respectively connected to the output end of the comparator U2 and the high-speed level conversion circuit 152, and is used to perform a NOR logic operation on the first comparison signal and the first differential signal to obtain a first logic signal QH; the NAND logic gate circuit N2 is respectively connected to the output end of the comparator U3 and the high-speed level conversion circuit 152, and is used to perform a NAND logic operation on the second comparison signal and the second differential signal to obtain a second logic signal QL.

[0050] It can be understood that the first comparison voltage (represented by CVH in the figure) and the second comparison voltage (represented by CVL in the figure) are both programmable and configurable, so as to be applicable to various analog input signal detection occasions. In some embodiments, the first comparison voltage CVH and the second comparison voltage CVL can be obtained by dividing the first driving voltage VH. The selection circuit 151 is used to select the analog input signal VINP to be output to the high-voltage comparison circuit 154 or the high-speed level conversion circuit 152.

[0051] Among them, the high-voltage comparison circuit 154 is composed of a window comparator, which compares the high-voltage signal with the threshold voltage signal and processes it into a logic level signal inside the chip. The threshold voltage can be provided by the internal programmable threshold voltage. The user can directly configure the register to select the required threshold, and it also supports external supply. The high-speed signal converts the single-ended signal into a differential signal through a high-speed level conversion circuit, and the converted differential signal level is consistent with the signal level processed by the high-voltage comparison circuit.

[0052] When outputting to the high-voltage comparison circuit 154, the high-speed level conversion circuit 152 ignores the analog input signal, the output terminal b is fixed to output a low level, and the output terminal c is fixed to output a high level; if the analog input signal VINP is a high level, the comparator U2 outputs a high level, the comparator U3 outputs a low level, QH is a low level, and QL is a high level; if the analog input signal VINP is a low level, the comparator U2 outputs a low level, the comparator U3 outputs a high level, the first logic signal QH is a high level, and the second logic signal QL is a low level.

[0053] When outputting to the high-speed level conversion circuit 152, the comparator U2 ignores the analog input signal and outputs a fixed low level, and the comparator U3 ignores the analog input signal and outputs a fixed high level. If the analog input signal VINP is a high level, the output terminal b of the high-speed level conversion circuit 152 outputs a high level, and the output terminal c outputs a low level, QH is a low level, and QL is a high level; if the analog input signal VINP is a low level, the output terminal b of the high-speed level conversion circuit 152 outputs a low level, and the output terminal c outputs a high level, the first logic signal QH is a high level, and the second logic signal QL is a low level.

[0054] In this way, the front end of the high-speed level conversion circuit 152 is connected to the same input port as the input of the high-voltage comparison circuit through the selection circuit 151, so that the same port is compatible with high-voltage input and high-speed input, and high voltage is prevented from entering the high-speed level conversion circuit 152 to damage the circuit; and, the output signal of the high-voltage comparison circuit 154 and the output signal of the high-speed level conversion circuit 152 are finally output QH and QL after logical operation by the digital output circuit 153, that is, after the conversion of the high-voltage input signal and the high-speed input signal, the digital logic signal that can be recognized by the external circuit is output at the same port, and the user only needs to switch and select the high-voltage comparison circuit 154 or the high-speed level conversion circuit 152 as needed to input high voltage or high-speed signals at the same port, and finally obtain the required digital logic signal at the same output port, without the need to design an additional high-voltage / high-speed switching circuit outside the chip, it is easy to use, and the circuit structure is simple.

[0055] In one embodiment, Figure 8As shown, the gating circuit 151 includes a high-voltage control unit 1511, a low-voltage control unit 1512, a low-voltage protection unit 1513, a transistor PM10, a transistor PM11, a transistor NM10, a transistor NM11 and a transistor NM12; the control end of the transistor PM10 and the control end of the transistor NM10 are respectively connected to the high-voltage control unit 1511; the first connection end of the transistor NM10, the first connection end of the transistor PM10 and the first connection end of the transistor NM11 are commonly connected to receive the analog input signal VINP; the second connection end of the transistor NM10 and the second connection end of the transistor PM10 are commonly connected and connected to the inverting end of the comparator U2; the control end of the transistor NM11 is connected to the low-voltage The protection unit 1513 is connected; the second connection end of the transistor NM11, the first connection end of the transistor PM11 and the first connection end of the transistor NM12 are connected in common; the second connection end of the transistor PM11 and the second connection end of the transistor NM12 are connected in common and connected to the high-speed level conversion circuit 152; the control end of the transistor PM11 and the control end of the transistor NM12 are respectively connected to the low-voltage control unit 1512; the high-voltage control unit 1511 is used to control the transistor PM10 and the transistor NM10 to be turned on or off together; the low-voltage control unit 1512 is used to control the transistor PM11 and the transistor NM12 to be turned on or off together; the low-voltage protection unit 1513 is used to control the transistor NM11 to be turned on or off.

[0056] It can be understood that the high-voltage control unit 1511 is used to control the selection of the high-voltage comparison circuit 154, and the low-voltage protection unit 1513 and the low-voltage control unit 1512 are used to select the high-speed level conversion circuit 152; when it is necessary to convert the analog input signal VINP through the high-voltage comparison circuit 154, the high-voltage control unit 1511 controls the transistor PM10 and the transistor NM10 to be turned on at the same time, the low-voltage protection unit 1513 controls the transistor NM11 to be turned off, and the low-voltage control unit 1512 also controls the transistor PM11 and the transistor NM12 to be turned off; when it is necessary to convert the analog input signal VINP through the high-speed level conversion circuit 152, the high-voltage control unit 1511 controls the transistor PM10 and the transistor NM10 to be turned off at the same time, the low-voltage protection unit 1513 controls the transistor NM11 to be turned on, and the low-voltage control unit 1512 also controls the transistor PM11 and the transistor NM12 to be turned on. The transistor PM10 and the transistor NM10, as well as the transistor PM11 and the transistor NM12 are turned on at the same time to reduce the on-resistance and not affect the quality of the signal passing through; the transistor NM11 can be used to provide a clamping voltage to protect the components at the back end of the circuit.

[0057] In one embodiment, the power module 110 includes a transistor PM0, a transistor NM0, a feedback circuit, a DAC conversion circuit 101, an error amplifier 102 and a high-voltage buffer 103. Fig. 9 and Fig.16 As shown; the feedback circuit includes a first switch S1 and a second switch S2, and the common output terminal of the high-voltage driving module 130 and the high-speed driving module 140 is connected to the first end of the first switch S1; the DAC conversion circuit 101 is used to provide an output voltage; the non-inverting input terminal of the error amplifier 102 is connected to the DAC conversion circuit 101, and the inverting input terminal of the error amplifier 102 is respectively connected to the second end of the first switch S1 and the first end of the second switch S2; the input terminal of the high-voltage buffer 103 is connected to the output terminal of the error amplifier 102, and the output terminal of the high-voltage buffer 103 is respectively connected to the control terminal of the transistor PM0 and the control terminal of the transistor NM0; the first connection terminal of the transistor NM0 is connected to the power input port PVCC, the first connection terminal of the transistor PM0 is connected to the ground terminal, the second connection terminal of the transistor NM0 is commonly connected to the second connection terminal of the transistor PM0, and is commonly connected to the second end of the second switch S2, and the commonly connected terminal is used to output the first driving voltage VH.

[0058] Wherein, SH represents the transistor NM8 in the high-voltage drive module 130, and SL represents the transistor NM9 in the high-voltage drive module 130; the DAC conversion circuit 101 can be a 10-bit high-precision DAC circuit, and its output voltage can be configured to provide a reference for the error amplifier 102. The power supply module 110 can be used to power an external device (wherein the external device may include a resistor RLine, a resistor RL, and a capacitor CL connected in parallel with the resistor RL). At this time, remote feedback is achieved by closing the first switch S1 of the feedback circuit. The power supply module 110 can also be used only to achieve internal drive, that is, to provide a first drive signal and a comparison signal. At this time, near-end feedback is achieved by closing the second switch S2 of the feedback circuit. After the error amplifier 102 amplifies the difference between the input variable output voltage and the feedback signal of the final output voltage (first drive voltage VH), it drives the power MOS tube to generate the first drive voltage VH through the high-voltage buffer 103, and the voltage can be converted into the threshold voltages CVH and CVL of the comparator after processing.

[0059] The power module 110 has an independent power input port PVCC. In situations where there are high requirements for power consumption, the user can supply power to PVCC separately, and reduce power consumption by reducing the voltage difference between the PVCC voltage and the first drive voltage VH; in general, PVCC can be directly connected to the chip power supply VCC to share the same external power supply. In some embodiments, the power module 110 may also include a resistance compensation circuit, which includes a third switch S3 and a variable resistor Rz. The third switch S3 and the variable resistor Rz are connected in parallel and connected between the error amplifier 102 and the external compensation port COMP of the power module 110. In this way, the compensation resistor can be connected to the external port through software configuration to ensure that the power module 110 can cope with various input power supplies and output voltage configurations, and can output stably without oscillation under different configurations; in addition, a compensation capacitor C can be connected to the outside of the port. VH and C C To ensure stable power output.

[0060] In one embodiment, the programmable IO driver chip may further include a pull-up and pull-down module 160, such as Figure 3 As shown, the pull-up and pull-down modules 160 are respectively connected to the high-voltage driving module 130 and the high-speed driving module 140 , and are used to pull up or pull down the voltage of the high-voltage driving signal and the voltage of the high-speed driving signal respectively.

[0061] The pull-up and pull-down voltages provided by the pull-up and pull-down modules 160 are configurable. The pull-up and pull-down modules 160 with configurable driving capabilities are connected in parallel to the signal driving output line, so that users can configure pull-ups and pull-downs with different driving capabilities for the output ports as needed to meet various requirements.

[0062] In one embodiment, Fig.10As shown, the pull-up and pull-down module 160 may include an operational amplifier U4, a transistor PM12, a transistor PM13, a transistor PM14, a transistor PM15, a transistor NM13, a transistor NM14, a transistor NM15, a transistor NM20, a resistor R2, and a plurality of current mirror units. Among them, the in-phase input terminal of the operational amplifier U4 is used to receive the reference voltage VREF, and the output terminal of the operational amplifier U4 is connected to the control terminal of the transistor NM13; the first connection terminal of the transistor PM12 and the first connection terminal of the transistor PM13 are respectively used to receive the voltage VDD, the control terminal and the second connection terminal of the transistor PM12 and the control terminal of the transistor PM13 are commonly connected, and are connected to the first connection terminal of the transistor NM13; the second connection terminal of the transistor NM13 is respectively connected to the inverting input terminal of the operational amplifier U4 and the first end of the resistor R2. The second connection terminal of the transistor PM13, the first connection terminal and the control terminal of the transistor NM14, and the control terminal of the transistor NM20 are commonly connected; the second end of the resistor R2, the second connection terminal of the transistor NM14, and the first connection terminal of the transistor NM20 are respectively used to receive the voltage VSS. The second connection terminal of transistor NM20, the first connection terminal and the control terminal of transistor PM14, and the control terminal of transistor PM15 are connected in common; the second connection terminal of transistor PM14 and the first connection terminal of transistor PM15 are respectively used to receive the first driving voltage VH; the second connection terminal of transistor PM15, the first connection terminal and the control terminal of transistor NM15 are connected in common; the second connection terminal of transistor NM15 is used to receive the third driving voltage VL.

[0063] Each group of current mirror units includes a PMOS tube, an NMOS tube, a switch Sp and a switch Sn (taking 4 groups of current mirror units as an example, the PMOS tube and the NMOS tube are respectively shown as PM16 and NM16, PM17 and NM17...PM19 and NM19 in the figure, the switch Sp is shown as Sp1~Sp4, and the switch Sn is shown as Sn1~Sn4), wherein the control end of each PMOS tube is respectively connected to the control end of the transistor PM15, and the first connection end of each PMOS tube receives the first driving voltage VH through the switch Sp; the control end of each NMOS tube is respectively connected to the control end of the transistor NM15, and the first connection end of each NMOS tube receives the third driving voltage VL through the switch Sn, the second connection end of the PMOS tube of each group and the second connection end of the NMOS tube are connected in common, and are connected to the high-voltage driving module 130 and the high-speed driving module 140 through the switch SW0.

[0064] Among them, only one set of switches Sn and Sp is turned on at the same time to realize pull-up or pull-down. The above method generates a fixed reference current by the internal reference voltage VREF in the internal low-voltage power rail, and then realizes the conversion of the current source power rail from the internal low-voltage power rail to the drive power rail VH-VL through the current mirror composed of transistors NM14 and NM20, and the current mirror composed of transistors PM14 and PM15, and finally realizes the pull-up and pull-down functions with different driving capabilities by selecting different combinations of high-voltage thin-gate NMOS or high-voltage thin-gate PMOS.

[0065] In one embodiment, the pull-up and pull-down modules are also used to provide a pull-up voltage Vpu and a source current Is3 in a pin connection detection mode; in the pin connection detection mode, the comparator module 150 is in a working state, and the high-voltage drive module and the high-speed drive module are both in a non-working state.

[0066] It can be understood that the pull-up / pull-down module 160 can realize the FIMV (add current and measure voltage) function, thereby realizing the pin connection detection of the external load, wherein the external load can be a load module in an external device. Figure 1 , Figure 3 and Fig.11 As shown, in the pin detection mode, the pull-up and pull-down modules 160 provide the pull-up voltage Vpu and the source current Is3 to the pin PIN of the external load DUT. At this time, the high-voltage drive module 130 and the high-speed drive module 140 are not working, and only the comparator module 150 is working. The comparator module 150 is used to receive the analog input signal VINP output by the external load DUT after the external load DUT is powered, and then the pin detection status of the external load can be obtained according to the digital logic signal output by the comparator module 150, that is, whether the tested pin is open-circuited or short-circuited, thereby screening defective products. The diode Dm is a diode in the external load DUT.

[0067] Specifically, when the comparator module 150 includes a gating circuit 151, a high-voltage comparison circuit 154, a high-speed level conversion circuit 152, and a digital output circuit 153, in the pin connection detection mode, the gating circuit 151 selects the high-voltage comparison circuit 154 to be turned on to convert the analog input signal. In this mode, the first driving voltage VH can be configured as a low voltage, so that the comparison voltage obtained by dividing the first driving voltage VH is also a low voltage. In some embodiments, the first driving voltage VH can be 3V or 5V.

[0068] In one embodiment, the programmable IO driver chip further includes a short circuit protection module 170, referring to Figure 3As shown, the short circuit protection module 170 is connected to the high voltage driving module 130 and the high speed driving module 140 respectively, and is used to issue an alarm prompt message if it is detected that the high voltage driving module 130 or the high speed driving module 140 is short-circuited with the external load power supply.

[0069] It can be understood that the short-circuit protection module 170 detects whether the high-voltage drive module 130 or the high-speed drive module 140 is short-circuited with the external load power supply, and can detect whether the common connection end of the high-voltage drive module 130 and the high-speed drive module 140 is short-circuited with the external load power supply. If an abnormality is detected, an alarm prompt message can be output to inform the user of the abnormal state so that the user can handle the abnormality in time.

[0070] In one embodiment, Fig.12 As shown, the short circuit protection module 170 may include a comparator U5, a comparator U6, a first AND gate circuit N3, a second AND gate circuit N4, an inverter, a first anti-spike pulse circuit 171 and a second anti-spike pulse circuit 172; the in-phase end of the comparator U5 is connected to the power supply module 110 for receiving the first driving voltage VH; the inverting end of the comparator U5 is connected to the in-phase end of the comparator U6, and is respectively connected to the high-voltage driving module 130 and the high-speed driving module 140; the output end of the comparator U5 is connected to the first AND gate circuit N3 The first input terminal of the comparator U6 is connected; the inverting terminal of the comparator U6 is used to receive the third driving voltage VL; the output terminal of the comparator U6 is connected to the first input terminal of the second AND gate circuit N4; the input terminal of the inverter is connected to the second input terminal of the first AND gate circuit N3, for receiving the digital input signal; the output terminal of the inverter is connected to the second input terminal of the second AND gate circuit N4; the output terminal of the first AND gate circuit N3 is connected to the first anti-spike pulse circuit 171; the output terminal of the second AND gate circuit N4 is connected to the second anti-spike pulse circuit 172.

[0071] Among them, the digital input signal (represented by DATA in the figure) can be used as data input to control the digital input module 120 to output a digital drive signal. The level value of the digital input signal determines the level values ​​of the high-voltage drive signal and the high-speed drive signal generated under the digital drive signal, that is, when the digital input signal is at a high level, the high-voltage drive signal and the high-speed drive signal are also at a high level; when the digital input signal is at a low level, the high-voltage drive signal and the high-speed drive signal are also at a low level.

[0072] The above circuit can be used to detect whether the output port is abnormally short-circuited with the external load power supply (voltage is VH, or VL / VSS). Specifically, when the digital input signal DATA is at a high level, under normal circumstances, the commonly connected output DOUT of the high-voltage drive module 130 and the high-speed drive module 140 is also at a high level, the comparator U5 outputs a low level, the first AND gate circuit N3 outputs a low level, and the abnormal diagnosis signal ERR_SHORT_TO_VL is a low level. If the output is short-circuited with the external load power supply (where the voltage of the external load power supply is VL / VSS), the comparator U5 outputs a high level, and the abnormal diagnosis signal ERR_SHORT_TO_VL is a high level; therefore, if it is detected that the abnormal diagnosis signal ERR_SHORT_TO_VL changes from low to high, it indicates that the output is short-circuited with the external load power supply with a voltage of VL / VSS.

[0073] Similarly, when the digital input signal DATA is at a low level, under normal circumstances, the commonly connected output DOUT of the high-voltage driving module 130 and the high-speed driving module 140 is also at a low level, the comparator U6 outputs a low level, the second AND gate circuit N4 outputs a low level, and the abnormal diagnostic signal ERR_SHORT_TO_VH is a low level. If the output is short-circuited with the external load power supply (wherein the voltage of the external load power supply may be the same as the first driving voltage VH), the comparator U6 outputs a high level, and the abnormal diagnostic signal ERR_SHORT_TO_VH is a high level; therefore, if it is detected that the abnormal diagnostic signal ERR_SHORT_TO_VH changes from low to high, it indicates that the output is short-circuited with the voltage VH external load power supply.

[0074] The first anti-spike pulse circuit 171 and the second anti-spike pulse circuit 172 are used to improve the accuracy of short-circuit protection, avoid misjudgment of the result due to the occurrence of signal spikes, and then falsely trigger the alarm prompt function. In this way, the short-circuit protection circuit can obtain the output short-circuit condition by monitoring the abnormal diagnosis signal ERR_SHORT_TO_VH and the abnormal diagnosis signal ERR_SHORT_TO_VL, and then decide whether to issue an alarm prompt information.

[0075] Another embodiment of the present invention further provides a programmable IO driver chip, including a power module 110, a digital input module 120, a high-voltage driver module 130, a high-speed driver module 140, a comparator module 150, a pull-up and pull-down module 160, a short-circuit protection module 170, a power management module 210, a clock module 220, a communication module 230 and a test module 240; wherein the high-speed driver module 140 includes an input overvoltage protection circuit 141, a high-speed driver circuit 142, an output overvoltage protection circuit 143 and a delay circuit 144, the comparator module 150 includes a gating circuit 151, a high-voltage comparison circuit 154, a high-speed level conversion circuit 152 and a digital output circuit 153, the power module 110 includes a feedback circuit, a DAC conversion circuit 101, an error amplifier 102 and a high-voltage buffer 103; the power management module 210 is used to manage the power module 110, the clock module 220 is used to provide clock signals for other circuits, the communication module 230 is used to realize data communication with external circuits, and the test module 240 is used to realize chip testing. The specific circuit structure and connection relationship of each circuit module can be referred to the above specific embodiment, which will not be described in detail here.

[0076] The following is a comprehensive description of the various functions of the programmable IO driver chip in combination with its functional diagram. Fig.13 As shown, the driver chip may include multiple channels, each of which includes the modules for realizing drive output and input detection in the above-mentioned embodiments. In addition, each channel is also provided with a general module, which includes a power management module 210, a clock module 220, a communication module 230 and a test module 240. In each channel, the power module 110 provides corresponding voltages for the driver module and the comparator module 150. In the driving mode, the digital logic input signal is input to the driver module to drive one of the high-voltage drive module 130 and the high-speed drive module 140 to work, so as to output a high-voltage drive signal or a high-speed drive signal to realize analog output; wherein the high-speed drive module 140 is provided with input protection and output protection, so as to share the power input pin and the signal output pin with the high-voltage drive module 130. In the detection mode, the analog input signal is selected by the selection circuit 151 to be processed by one of the high-voltage comparison circuit 154 and the high-speed level conversion circuit 152, and finally converted into a digital logic signal for output.

[0077] The programmable IO driver chip may include the following specific applications: 1. Use FPGA chips to communicate with high-voltage equipment.

[0078] Specifically, the FPGA chip can communicate with this chip, configure and enable the high-voltage drive module 130 and the high-voltage comparison circuit 154, and disable the high-speed drive module 140 and the high-speed level conversion circuit 152 to avoid interference and reduce power consumption; at the same time, the power module 110 is configured to keep the IO level voltage of the high-voltage device consistent, so that the communication between the low-voltage IO port of the FPGA and the high-voltage IO port of the high-voltage device can be realized. Fig.14 As shown. The switch closure is only used to indicate that each circuit on the branch is in working state.

[0079] 2. Use FPGA chips to communicate with low-voltage devices at high speed.

[0080] Specifically, the FPGA chip can communicate with this chip, configure and enable the high-speed driving module 140 and the high-speed level conversion circuit 152, and disable the high-voltage driving module 130 and the high-voltage comparison circuit 154 to avoid interference and reduce power consumption; at the same time, the power supply module 110 voltage is configured to be consistent with the IO level voltage of the low-voltage device, so that the communication between the low-voltage IO port of the FPGA chip and the high-speed IO port of the low-voltage device can be realized. Fig.15 shown.

[0081] 3. Pin connection detection for external load Specifically, the FPGA chip configures and enables the FIMV function and the high-voltage comparison circuit 154 in the pull-up and pull-down modules 160 by communicating with this chip, and disables the high-voltage drive module 130, the high-speed drive module 140 and the high-speed level conversion circuit 152; at the same time, the power module 110 is configured to be low voltage (such as 3V or 5V), and then the FPGA can determine the open and short circuit status of the tested pin by reading the QH and QL logic levels, and then filter out defective products. Fig.11 shown.

[0082] 4. Used for external power supply Specifically, the FPGA chip configures and enables the high-voltage drive module 130 by communicating with this chip, configures the VH voltage and configures it as a remote feedback mode (i.e., only S1 is closed); at the same time, the high-speed drive module 140, the high-voltage comparison circuit 154 and the high-speed level conversion circuit 152 are disabled to reduce power consumption. Fig. 9 shown.

[0083] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A programmable IO driver chip, characterized in that: include: A power supply module, used for providing a first driving voltage and a comparison voltage according to a configuration instruction; A digital input module, used for outputting digital drive signals; a high-voltage driving module, connected to the digital input module and the power supply module respectively, for receiving the digital driving signal in a working state, and outputting a high-voltage driving signal according to the first driving voltage under the drive of the digital driving signal; a high-speed driving module, connected to the power module and the high-voltage driving module respectively, for receiving the digital driving signal in a working state, and outputting a high-speed driving signal according to the first driving voltage under the drive of the digital driving signal; The comparator module is connected to the power supply module and is used to convert the analog input signal into a digital logic signal using the comparison voltage as a comparison threshold voltage in a working state, wherein the voltage value of the digital logic signal is within a preset range.

2. The programmable IO driver chip according to claim 1, characterized in that: The high-speed driving module comprises: an input overvoltage protection circuit, connected to the high-voltage drive module and to the power supply module, for receiving the first drive voltage and clamping the first drive voltage within a safety threshold range; a high-speed driving circuit, connected to the input overvoltage protection circuit and the digital input module respectively, for receiving the digital driving signal and the clamped first driving voltage in a working state, and outputting the high-speed driving signal according to the clamped first driving voltage under the drive of the digital driving signal; The output overvoltage protection circuit is connected to the high-speed drive circuit and the high-voltage drive circuit respectively, and is used to receive and output the high-speed drive signal, and disconnect the conductive path between the high-speed drive circuit and the high-voltage drive module when the voltage of the high-voltage drive signal exceeds a voltage threshold.

3. The programmable IO driver chip according to claim 2, characterized in that: The high-speed driving circuit includes a first driver, a transistor NM1 and a transistor PM1; the first driver is respectively connected to the digital input module, the control end of the transistor NM1 and the control end of the transistor PM1, the first connection end of the transistor PM1 is connected to the input overvoltage protection circuit, the second connection end of the transistor PM1 is commonly connected to the first connection end of the transistor NM1 and is connected to the output overvoltage protection circuit, and the second connection end of the transistor NM1 is used to receive a second driving voltage; the first driver is used to control one of the transistor PM1 and the transistor NM1 to be turned on according to the digital driving signal in a working state.

4. The programmable IO driver chip according to claim 3, characterized in that: The input overvoltage protection circuit includes a transistor PM2, a transistor PM3, a transistor PM4, a transistor NM2, a transistor NM3 and a current source Is1; the first connection end of the transistor PM2 and the first connection end of the transistor PM3 are respectively used to receive a voltage VCC; the control end and the second connection end of the transistor PM2, the control end of the transistor PM3 and the first connection end of the current source Is1 are commonly connected; the second connection end of the transistor PM3, the control end of the transistor NM3 and the first connection end of the transistor PM4 are commonly connected; the second connection end of the transistor PM4 is connected to the first connection end of the transistor NM2; the second connection end of the current source Is1 and the second connection end of the transistor NM2 are respectively used to receive a voltage VSS; the first connection end of the transistor NM3 is used to receive the first driving voltage, and the second connection end of the transistor NM3 is connected to the first connection end of the transistor PM1; the control end of the transistor PM4 is used to receive a control signal VA; the control end of the transistor NM2 is used to receive a control signal VB.

5. The programmable IO driver chip according to claim 3, characterized in that: The output overvoltage protection circuit includes a current source Is2, a comparator U1, a logic level conversion module circuit, a transistor PM7, a transistor PM8, a transistor PM9, a transistor NM4, a transistor NM5, a transistor NM6, a transistor NM7 and a resistor R1; the first connection end of the transistor PM7, the first connection end of the transistor PM8 and the first connection end of the transistor PM9 are used to receive a voltage VCC; the control end and the second connection end of the transistor PM7, the control end of the transistor PM8 and the control end of the transistor PM9 are commonly connected and connected to the first end of the current source Is2; the second connection end of the transistor PM8 and the first connection end of the transistor NM4 are commonly connected and connected to the control end of the transistor NM6; the second connection end of the transistor PM9 and the first connection end of the transistor NM5 are commonly connected and connected to the The control end is connected; the second end of the current source Is2, the second connection end of the transistor NM4 and the second connection end of the transistor NM5 are commonly connected to receive the voltage VSS; the first connection end of the transistor NM6 and the first connection end of the transistor NM7 are commonly connected, and are respectively connected to the same direction end of the comparator U1 and the high voltage driving module; the reverse end of the comparator U1 is used to receive the reference voltage VTH_OUTOVP, and the output end of the comparator U1 is connected to the input end of the logic level conversion circuit; the output end of the logic level conversion circuit is respectively connected to the control end of the transistor NM4 and the control end of the transistor NM5; the second connection end of the transistor NM6 is commonly connected to the second connection end of the transistor NM7 through the resistor R1, and is respectively connected to the second connection end of the transistor PM1 and the first connection end of the transistor NM1.

6. The programmable IO driver chip according to claim 3, characterized in that: The high-speed driving module also includes: The delay circuit is connected to the digital input module and the first driver respectively, and is used to delay the digital drive signal by a preset time length before transmitting it to the first driver.

7. The programmable IO driver chip according to claim 1, characterized in that: The high-voltage driving module includes a second driver, a transistor NM8 and a transistor NM9, the second driver is respectively connected to the digital input module, the control end of the transistor NM8 and the control end of the transistor NM9, the first connection end of the transistor NM8 is used to receive the first driving voltage, the second connection end of the transistor NM8 is commonly connected to the first connection end of the transistor NM9 and connected to the high-speed driving module, and the second connection end of the transistor NM9 is used to receive a third driving voltage; the second driver is used to control one of the transistor NM8 and the transistor NM9 to be turned on according to the digital driving signal in a working state.

8. The programmable IO driver chip according to claim 1, characterized in that: The digital logic signal includes a first logic signal and a second logic signal, the comparison voltage includes a first comparison voltage and a second comparison voltage, and the comparator module includes: A gating circuit, configured to receive the analog input signal; A high-voltage comparison circuit, comprising a comparator U2 and a comparator U3, wherein the inverting terminal of the comparator U2 is used to receive the first comparison voltage, the non-inverting terminal of the comparator U2 is commonly connected with the inverting terminal of the comparator U3 and connected to the gating circuit, and the non-inverting terminal of the comparator U3 is used to receive the second comparison voltage; the high-voltage comparison circuit is used to receive the analog input signal after being gated by the gating circuit, and compare the analog input signal with the first comparison voltage and the second comparison voltage respectively to obtain a first comparison signal and a second comparison signal; A high-speed level conversion circuit, connected to the gating circuit, for receiving the analog input signal after being gated by the gating circuit, and converting the analog input signal from a single-ended signal to a two-way differential signal; The digital output circuit includes a NOR logic gate circuit and a NAND logic gate circuit. The NOR logic gate circuit is respectively connected to the output end of the comparator U2 and the high-speed level conversion circuit, and is used to perform a NOR logic operation on the first comparison signal and the first differential signal to obtain the first logic signal; the NAND logic gate circuit is respectively connected to the output end of the comparator U3 and the high-speed level conversion circuit, and is used to perform a NAND logic operation on the second comparison signal and the second differential signal to obtain the second logic signal.

9. The programmable IO driver chip according to claim 8, characterized in that: The gating circuit includes a high-voltage control unit, a low-voltage control unit, a low-voltage protection unit, a transistor PM10, a transistor PM11, a transistor NM10, a transistor NM11 and a transistor NM12; the control end of the transistor PM10 and the control end of the transistor NM10 are respectively connected to the high-voltage control unit; the first connection end of the transistor NM10, the first connection end of the transistor PM10 and the first connection end of the transistor NM11 are commonly connected to receive the analog input signal; the second connection end of the transistor NM10 and the second connection end of the transistor PM10 are commonly connected and connected to the inverting end of the comparator U2; the control end of the transistor NM11 is connected to the low-voltage protection unit The second connection terminal of the transistor NM11, the first connection terminal of the transistor PM11 and the first connection terminal of the transistor NM12 are commonly connected; the second connection terminal of the transistor PM11 and the second connection terminal of the transistor NM12 are commonly connected and connected to the high-speed level conversion circuit; the control terminal of the transistor PM11 and the control terminal of the transistor NM12 are respectively connected to the low-voltage control unit; the high-voltage control unit is used to control the transistor PM10 and the transistor NM10 to be turned on or off together; the low-voltage control unit is used to control the transistor PM11 and the transistor NM12 to be turned on or off together; the low-voltage protection unit is used to control the transistor NM11 to be turned on or off.

10. The programmable IO driver chip according to claim 1, characterized in that: The power module comprises: Transistor PM0 and transistor NM0; The feedback circuit comprises a first switch and a second switch, wherein a common output terminal of the high-voltage driving module and the high-speed driving module is connected to a first terminal of the first switch; A DAC conversion circuit for providing an output voltage; an error amplifier, wherein a non-inverting input terminal of the error amplifier is connected to the DAC conversion circuit, and an inverting input terminal of the error amplifier is connected to the second end of the first switch and the first end of the second switch respectively; A high-voltage buffer, wherein an input end of the high-voltage buffer is connected to an output end of the error amplifier, and an output end of the high-voltage buffer is respectively connected to a control end of the transistor PM0 and a control end of the transistor NM0; The first connection end of the transistor NM0 is connected to the power input port PVCC, the first connection end of the transistor PM0 is connected to the ground, the second connection end of the transistor NM0 and the second connection end of the transistor PM0 are commonly connected, and are commonly connected to the second end of the second switch, and the commonly connected end is used to output the first driving voltage.

11. The programmable IO driver chip according to claim 1, characterized in that: The programmable IO driver chip also includes: The pull-up and pull-down modules are connected to the high-voltage driving module and the high-speed driving module respectively, and are used to pull up or pull down the voltage of the high-voltage driving signal and the voltage of the high-speed driving signal respectively.

12. The programmable IO driver chip according to claim 11, characterized in that: The pull-up and pull-down modules include an operational amplifier, a transistor PM12, a transistor PM13, a transistor PM14, a transistor PM15, a transistor NM13, a transistor NM14, a transistor NM15, a transistor NM20, a resistor R2, a switch SW0, and a plurality of current mirror units; the in-phase input terminal of the operational amplifier is used to receive a reference voltage VREF, and the output terminal of the operational amplifier is connected to the control terminal of the transistor NM13; the first connection terminal of the transistor PM12 and the first connection terminal of the transistor PM13 are respectively used to receive a voltage VDD; the transistor P The control terminal and the second connection terminal of M12 and the control terminal of the transistor PM13 are connected in common, and are connected to the first connection terminal of the transistor NM13; the second connection terminal of the transistor NM13 is respectively connected to the inverting input terminal of the operational amplifier and the first end of the resistor R2; the second connection terminal of the transistor PM13, the first connection terminal and the control terminal of the transistor NM14, and the control terminal of the transistor NM20 are connected in common; the second end of the resistor R2, the second connection terminal of the transistor NM14, and the first connection terminal of the transistor NM20 are respectively used to receive the voltage VSS. The second connection terminal of the transistor NM20, the first connection terminal and the control terminal of the transistor PM14, and the control terminal of the transistor PM15 are connected in common; the second connection terminal of the transistor PM14 and the first connection terminal of the transistor PM15 are respectively used to receive the first driving voltage; the first connection terminal and the control terminal of the transistor NM15, and the second connection terminal of the transistor PM15 are connected in common; the second connection terminal of the transistor NM15 is used to receive the third driving voltage; Each group of the current mirror units includes a PMOS tube, an NMOS tube, a switch Sp and a switch Sn, wherein the control end of each of the PMOS tubes is connected to the control end of the transistor PM15, and the first connection end of each of the PMOS tubes receives the first driving voltage through the switch Sp; the control end of each of the NMOS tubes is connected to the control end of the transistor NM15, and the first connection end of each of the NMOS tubes receives the third driving voltage through the switch Sn, the second connection end of each group of the PMOS tubes and the second connection end of the NMOS tubes are connected in common, and are connected to the high-voltage driving module and the high-speed driving module through the switch SW0.

13. The programmable IO driver chip according to claim 11, characterized in that: The pull-up and pull-down modules are also used to provide pull-up voltage and source current in a pin connection detection mode; in the pin connection detection mode, the comparator module is in a working state, and the high-voltage drive module and the high-speed drive module are both in a non-working state.

14. The programmable IO driver chip according to claim 1, characterized in that: The programmable IO driver chip also includes: The short circuit protection module is connected to the high voltage driving module and the high speed driving module respectively, and is used to issue an alarm prompt message if it is detected that the high voltage driving module or the high speed driving module is short-circuited with an external load power supply.

15. The programmable IO driver chip according to claim 14, characterized in that: The short-circuit protection module includes a comparator U5, a comparator U6, a first AND gate circuit, a second AND gate circuit, an inverter, a first anti-spike pulse circuit and a second anti-spike pulse circuit; the non-inverting end of the comparator U5 is connected to the power supply module for receiving the first driving voltage; the inverting end of the comparator U5 is connected to the non-inverting end of the comparator U6, and is respectively connected to the high-voltage driving module and the high-speed driving module; the output end of the comparator U5 is connected to the first input end of the first AND gate circuit; the inverting end of the comparator U6 is used to receive the third driving voltage; the output end of the comparator U6 is connected to the first input end of the second AND gate circuit; The input end of the inverter is connected to the second input end of the first AND gate circuit for receiving a digital input signal; The output end of the inverter is connected to the second input end of the second AND gate circuit; the output end of the first AND gate circuit is connected to the first anti-spike pulse circuit; the output end of the second AND gate circuit is connected to the second anti-spike pulse circuit.

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