Single-ended to differential signal conversion circuit and method

Abstract

The invention provides a single-ended to differential signal conversion circuit and method. The circuit comprises four field effect transistors which are arranged in parallel, a first negative feedback circuit is arranged between the second field effect transistor M2 and the third field effect transistor M3, and a second negative feedback circuit is arranged between the first field effect transistor M1 and the fourth field effect transistor M4; a first adjusting circuit is arranged between the first field effect transistor M1 and the third field effect transistor M3, and a second adjusting circuit is arranged between the second field effect transistor M2 and the fourth field effect transistor M4. A to-be-converted single-ended signal is input into the grid electrodes of the first field effect transistor M1 and the second field effect transistor M2, and a reference signal is input into the grid electrodes of the third field effect transistor M3 and the fourth field effect transistor M4. And a converted differential signal is output through the fourth field effect transistor M4 and the first field effect transistor M1. According to the invention, under the condition that a linear equalizer is not arranged, the problem of phase mismatching of differential signals is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and more particularly, to a single-ended to differential signal conversion circuit and method. Background Art

[0002] Currently, high-speed storage interfaces (such as DDR, LPDDR, and GDDR) and chiplet interconnect protocols (such as UCIe) typically use single-ended signals for high-speed transmission at chip interfaces to save area and power. Internally, differential signals are often used for transmission to mitigate interference and noise. Therefore, a high-speed single-ended-to-differential amplifier is often required between the single-ended and differential signals. Specifically, the receiver needs a high-speed single-ended-to-differential amplifier to convert the high-speed single-ended signal input from the transmitter into an internal differential signal. However, as interface speeds increase, the receiver signal will experience channel attenuation. Therefore, a CTLE (Complementary Linear Equalizer) is often required after the single-ended-to-differential amplifier to compensate for channel attenuation.

[0003] However, in existing current-mode single-ended-to-differential amplifiers, since the Vin signal has no direct path to the Von node, there will be a huge mismatch in gain and phase at both ends of the amplifier output. Due to the influence of the output node resistance, load capacitance, and parasitic capacitance, it is also difficult to achieve high speed and high bandwidth. The output node Von of the inverter-based single-ended-to-differential amplifier does not pass through any inverter, while the output node Vop passes through a first-stage inverter. As a result, there will be a very large phase mismatch between Vop and Von. In addition, the power supply rejection of the inverter-based single-ended-to-differential amplifier is also relatively poor, and it is greatly affected by the power supply voltage disturbance. It is also necessary to design an additional linear equalizer to provide high-frequency signal attenuation compensation, which will also increase additional power consumption and area. Summary of the Invention

[0004] In view of the above problems, the present invention provides a single-ended to differential signal conversion circuit and method to solve the problems of phase mismatch in existing single-ended signal to differential signal conversion methods, the need for a linear equalizer to compensate for signal attenuation, increased power consumption, and larger circuit size.

[0005] The single-ended to differential signal conversion circuit provided by the present invention includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3 and a fourth field effect transistor M4 which are arranged in parallel; A first negative feedback circuit is provided between the second field effect transistor M2 and the third field effect transistor M3, and a second negative feedback circuit is provided between the first field effect transistor M1 and the fourth field effect transistor M4; A first regulating circuit is provided between the first field effect transistor M1 and the third field effect transistor M3, and a second regulating circuit is provided between the second field effect transistor M2 and the fourth field effect transistor M4; The single-ended signal to be converted is input into the gates of the first field effect transistor M1 and the second field effect transistor M2, and the reference signal is input into the gates of the third field effect transistor M3 and the fourth field effect transistor M4; The converted differential signal is outputted through the drain of the fourth field effect transistor M4 and the drain of the first field effect transistor M1.

[0006] In addition, an optional technical solution is that the first negative feedback circuit includes a first adjustable resistor and a first capacitor arranged in parallel; One end of the first negative feedback circuit is connected to the source of the second field effect transistor M2 , and the other end is connected to the source of the third field effect transistor M3 .

[0007] In addition, an optional technical solution is that the second negative feedback circuit includes a second adjustable resistor and a second capacitor arranged in parallel; One end of the second negative feedback circuit is connected to the source of the first field effect transistor M1 , and the other end is connected to the source of the fourth field effect transistor M4 .

[0008] In addition, an optional technical solution is that the first regulating circuit includes a fifth field effect transistor M5 and a sixth field effect transistor M6; The gate of the fifth field effect transistor M5 is connected to the gate of the sixth field effect transistor M6, and the source of the fifth field effect transistor M5 is connected to the source of the sixth field effect transistor M6; The drain of the fifth field effect transistor M5 is connected to the drain of the first field effect transistor M1 , and the drain of the sixth field effect transistor M6 is connected to the drain of the third field effect transistor M3 .

[0009] In addition, an optional technical solution is that the second regulating circuit includes a seventh field effect transistor M7 and an eighth field effect transistor M8; The gate of the seventh field effect transistor M7 is connected to the gate of the eighth field effect transistor M8, and the source of the seventh field effect transistor M7 is connected to the source of the eighth field effect transistor M8; The drain of the seventh field effect transistor M7 is connected to the drain of the second field effect transistor M2 , and the drain of the eighth field effect transistor M8 is connected to the drain of the fourth field effect transistor M4 .

[0010] In addition, an optional technical solution is that the source of the sixth field effect transistor M6 is connected to the source of the seventh field effect transistor M7.

[0011] In addition, an optional technical solution is that a first resistor R1 is provided between the drain and source of the sixth field effect transistor M6 , and a second resistor R2 is provided between the drain and source of the seventh field effect transistor M7 .

[0012] In addition, an optional technical solution is that the first field effect transistor M1, the second field effect transistor M2, the third field effect transistor M3 and the fourth field effect transistor M4 are PMOS field effect transistors; The fifth field effect transistor M5 , the sixth field effect transistor M6 , the seventh field effect transistor M7 , and the eighth field effect transistor M8 are NMOS field effect transistors.

[0013] In addition, an optional technical solution is that the drain of the fourth field effect transistor M4 outputs the positive voltage of the differential signal, and the drain of the first field effect transistor M1 outputs the negative voltage of the differential signal.

[0014] On the other hand, the present invention further provides a single-ended to differential signal conversion method, which uses the above-mentioned single-ended to differential signal conversion circuit to perform differential conversion on a single-ended signal.

[0015] Using the above-mentioned single-ended to differential signal conversion circuit and method, a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, and a fourth field-effect transistor M4 are arranged in parallel, and a first regulation circuit is provided between the first field-effect transistor M1 and the third field-effect transistor M3, and a second regulation circuit is provided between the second field-effect transistor M2 and the fourth field-effect transistor M4. After the single-ended signal to be converted is input into the gates of the first field-effect transistor M1 and the second field-effect transistor M2, the converted differential signal is output through the drain of the fourth field-effect transistor M4 and the drain of the first field-effect transistor M1. This can improve the high-frequency gain of the single-ended to differential amplifier and achieve linear equalization, making it suitable for application scenarios of ultra-high-speed interfaces. In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all of these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By referring to the following description in conjunction with the accompanying drawings, and with a more complete understanding of the present invention, other objects and results of the present invention will become more clear and easy to understand. In the accompanying drawings: Figure 1 is a structural block diagram of a single-ended to differential signal conversion circuit according to an embodiment of the present invention; Figure 2 is a differential amplitude-frequency simulation curve of a single-ended to differential signal conversion circuit according to an embodiment of the present invention; FIG3 is a single-ended gain curve of a single-ended to differential signal conversion circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] In the following description, for illustrative purposes, numerous specific details are set forth to provide a comprehensive understanding of one or more embodiments. However, it will be apparent that the embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description of one or more embodiments.

[0018] In the description of the present invention, it should be understood that the connection method of the various circuit devices / elements in the accompanying drawings is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0019] It will be understood by those skilled in the art that, unless otherwise stated, the singular forms "a," "an," "said," and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that the term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0020] Those skilled in the art will understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art in the art to which this invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with their meanings in the context of the prior art and, unless defined as such, will not be interpreted in an idealized or overly formal sense.

[0021] In the following description, all logic circuits involved can be composed of various types of gate circuits and triggers, and are not limited to the specific structures shown in the drawings.

[0022] To describe the single-ended to differential signal conversion circuit and method of the present invention in detail, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 1 The schematic structure of a single-ended to differential signal conversion circuit according to an embodiment of the present invention is shown.

[0024] like Figure 1As shown, the single-ended to differential signal conversion circuit of an embodiment of the present invention includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3 and a fourth field effect transistor M4 arranged in parallel, a first regulation circuit is provided between the first field effect transistor M1 and the third field effect transistor M3, and a second regulation circuit is provided between the second field effect transistor M2 and the fourth field effect transistor M4. The single-ended signal to be converted is input into the gates of the first field effect transistor M1 and the second field effect transistor M2, and the reference signal is input into the gates of the third field effect transistor M3 and the fourth field effect transistor M4. The converted differential signal is output through the drain of the fourth field effect transistor M4 and the drain of the first field effect transistor M1, thereby realizing high-speed single-ended signal to differential signal conversion.

[0025] A first negative feedback circuit is provided between the second field-effect transistor M2 and the third field-effect transistor M3, and a second negative feedback circuit is provided between the first field-effect transistor M1 and the fourth field-effect transistor M4. The first negative feedback circuit and the second filter circuit may employ the same structure. For example, the first negative feedback circuit includes a first adjustable resistor and a first capacitor connected in parallel, with one end of the first negative feedback circuit connected to the source of the second field-effect transistor M2 and the other end connected to the source of the third field-effect transistor M3. Similarly, the second negative feedback circuit includes a second adjustable resistor and a second capacitor connected in parallel, with one end of the second negative feedback circuit connected to the source of the first field-effect transistor M1 and the other end connected to the source of the fourth field-effect transistor M4. Current sources are connected to both ends of the first negative feedback circuit and the second negative feedback circuit, respectively. The first and second negative feedback circuits form source negative feedback for the entire GM amplification unit, thereby increasing the high-frequency gain of signal conversion.

[0026] Specifically, the above-mentioned first regulation circuit includes a fifth field effect transistor M5 and a sixth field effect transistor M6; the gate of the fifth field effect transistor M5 is connected to the gate of the sixth field effect transistor M6, and the source of the fifth field effect transistor M5 is connected to the source of the sixth field effect transistor M6; the drain of the fifth field effect transistor M5 is connected to the drain of the first field effect transistor M1, and the drain of the sixth field effect transistor M6 is connected to the drain of the third field effect transistor M3; correspondingly, the second regulation circuit includes a seventh field effect transistor M7 and an eighth field effect transistor M8; the gate of the seventh field effect transistor M7 is connected to the gate of the eighth field effect transistor M8, and the source of the seventh field effect transistor M7 is connected to the source of the eighth field effect transistor M8; the drain of the seventh field effect transistor M7 is connected to the drain of the second field effect transistor M2, and the drain of the eighth field effect transistor M8 is connected to the drain of the fourth field effect transistor M4; in addition, the source of the sixth field effect transistor M6 is connected to the source of the seventh field effect transistor M7, thereby forming a mirror-symmetrical circuit structure.

[0027] It can be seen that due to the current mirroring effect formed by the fifth FET M5, the sixth FET M6, the seventh FET M7, and the eighth FET M8, the input signal Vin reaches V0- through the path formed by the first FET M1, and simultaneously reaches Vo+ through the path formed by the second FET M2, the seventh FET M7, and the eighth FET M8. If the sizes and currents of the fifth FET M5, the sixth FET M6, the seventh FET M7, and the eighth FET M8 are exactly the same, calculation shows that: VO- = Vref*gm3 - Vin*gm1, and VO+ = Vin*gm2 - Vref*gm4, where gm represents transconductance and Vref represents the reference signal. Furthermore, if the sizes and currents of the first FET M1, the second FET M2, the third FET M3, and the fourth FET M4 are exactly the same, then VO- = VO+, resulting in a perfect differential signal output.

[0028] In a specific embodiment of the present invention, the source negative feedback circuit (including the first negative feedback circuit and the second negative feedback circuit) composed of Rs and Cs can add two zero points, thereby improving the high-frequency gain of the single-ended to differential circuit and achieving the purpose of linear equalization.

[0029] It can be seen that the drain of the fourth field-effect transistor M4 outputs the positive voltage VO+ of the differential signal, and the drain of the first field-effect transistor M1 outputs the negative voltage VO- of the differential signal. To further improve and match the high-frequency gain of VO- and VO+, in the single-ended to differential signal conversion circuit of the present invention, a first resistor R1 may be provided between the drain and source of the sixth field-effect transistor M6, and a second resistor R2 may be provided between the drain and source of the seventh field-effect transistor M7. The additional addition of R1 and R2 can improve the high-frequency gain of the output signal.

[0030] It should be noted that the above-mentioned first field effect transistor M1, second field effect transistor M2, third field effect transistor M3 and fourth field effect transistor M4 can be PMOS field effect transistors; the fifth field effect transistor M5, sixth field effect transistor M6, seventh field effect transistor M7 and eighth field effect transistor M8 can be NMOS field effect transistors. The specific circuit structure can select other types of devices according to the conversion requirements and application scenarios.

[0031] In the specific application process, according to Figure 2 The differential amplitude-frequency simulation curve (x-axis represents frequency, unit Hz, y-axis represents gain, unit dB) shows that the single-ended to differential signal conversion circuit of the embodiment of the present invention can fully realize the function of a linear equalizer, achieving an adjustable maximum high-frequency and low-frequency gain difference of 6dB, and the frequency of the highest gain point can be as high as 19GHz, which is very suitable for ultra-high-speed interface application scenarios. Figure 3The single-ended gain curve shown (the x-axis represents frequency in Hz, and the y-axis represents gain in dB) shows that the blue line represents the negative-end signal gain, and the red line represents the positive-end signal gain. The gains of the two differential outputs, VO+ and VO-, of the single-ended-to-differential signal conversion circuit are well matched at both high frequencies (<10 GHz) and low frequencies, perfectly achieving the single-ended-to-differential conversion function.

[0032] Corresponding to the above-mentioned single-ended to differential signal conversion circuit, the present invention also provides a single-ended to differential signal conversion method, which utilizes the above-mentioned single-ended to differential signal conversion circuit to perform differential conversion on a target high-speed single-ended signal.

[0033] It should be noted that the embodiments of the above-mentioned single-ended to differential signal conversion method can refer to the description in the embodiment of the single-ended to differential signal conversion circuit, and will not be repeated here.

[0034] According to the single-ended to differential signal conversion circuit and method of the present invention described above, the high-frequency gain of the single-ended to differential amplifier can be improved without relying on an external linear equalizer, thereby achieving the effect of linear equalization; and the structure combining field-effect transistors and current mode can also improve the ability to suppress power supply noise, which is suitable for application scenarios of ultra-high-speed interfaces. The single-ended to differential signal conversion circuit and method according to the present invention have been described above by way of example with reference to the accompanying drawings. However, those skilled in the art will appreciate that various modifications may be made to the single-ended to differential signal conversion circuit and method described above without departing from the scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A single-ended to differential signal conversion circuit, characterized in that: It includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3 and a fourth field effect transistor M4 which are arranged in parallel; A first negative feedback circuit is provided between the second field effect transistor M2 and the third field effect transistor M3, and a second negative feedback circuit is provided between the first field effect transistor M1 and the fourth field effect transistor M4; A first regulating circuit is provided between the first field effect tube M1 and the third field effect tube M3, and a second regulating circuit is provided between the second field effect tube M2 and the fourth field effect tube M4; The single-ended signal to be converted is input into the gates of the first field effect transistor M1 and the second field effect transistor M2, and the reference signal is input into the gates of the third field effect transistor M3 and the fourth field effect transistor M4; The converted differential signal is outputted through the drain of the fourth field effect transistor M4 and the drain of the first field effect transistor M1.

2. The single-ended to differential signal conversion circuit according to claim 1, characterized in that: The first negative feedback circuit includes a first adjustable resistor and a first capacitor arranged in parallel; One end of the first negative feedback circuit is connected to the source of the second field effect transistor M2 , and the other end is connected to the source of the third field effect transistor M3 .

3. The single-ended to differential signal conversion circuit according to claim 1, characterized in that: The second negative feedback circuit includes a second adjustable resistor and a second capacitor arranged in parallel; One end of the second negative feedback circuit is connected to the source of the first field effect transistor M1 , and the other end is connected to the source of the fourth field effect transistor M4 .

4. The single-ended to differential signal conversion circuit according to claim 1, characterized in that: The first regulating circuit includes a fifth field effect transistor M5 and a sixth field effect transistor M6; The gate of the fifth field effect transistor M5 is connected to the gate of the sixth field effect transistor M6, and the source of the fifth field effect transistor M5 is connected to the source of the sixth field effect transistor M6; The drain of the fifth field effect transistor M5 is connected to the drain of the first field effect transistor M1 , and the drain of the sixth field effect transistor M6 is connected to the drain of the third field effect transistor M3 .

5. The single-ended to differential signal conversion circuit according to claim 4, characterized in that: The second regulating circuit includes a seventh field effect transistor M7 and an eighth field effect transistor M8; The gate of the seventh field effect transistor M7 is connected to the gate of the eighth field effect transistor M8, and the source of the seventh field effect transistor M7 is connected to the source of the eighth field effect transistor M8; The drain of the seventh field effect transistor M7 is connected to the drain of the second field effect transistor M2 , and the drain of the eighth field effect transistor M8 is connected to the drain of the fourth field effect transistor M4 .

6. The single-ended to differential signal conversion circuit according to claim 5, characterized in that: The source of the sixth field effect transistor M6 is connected to the source of the seventh field effect transistor M7.

7. The single-ended to differential signal conversion circuit according to claim 5, characterized in that: A first resistor R1 is disposed between the drain and source of the sixth field effect transistor M6 , and a second resistor R2 is disposed between the drain and source of the seventh field effect transistor M7 .

8. The single-ended to differential signal conversion circuit according to claim 5, characterized in that: The first field effect transistor M1, the second field effect transistor M2, the third field effect transistor M3 and the fourth field effect transistor M4 are PMOS field effect transistors; The fifth field effect transistor M5 , the sixth field effect transistor M6 , the seventh field effect transistor M7 and the eighth field effect transistor M8 are NMOS field effect transistors.

9. The single-ended to differential signal conversion circuit according to claim 1, characterized in that: The drain of the fourth field effect transistor M4 outputs the positive voltage of the differential signal, and the drain of the first field effect transistor M1 outputs the negative voltage of the differential signal.

10. A method for converting a single-ended signal to a differential signal, characterized in that: A single-ended signal is converted into a differential signal using the single-ended to differential signal conversion circuit as claimed in any one of claims 1 to 9.

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