Broadband high-speed frequency hopping method based on PLL frequency synthesizer
By improving the order of SRAM memory, optimizing the timing control of the PLL frequency synthesizer, solving the problem of complex control of the PLL frequency synthetic frequency jumper in existing technology, and realizing high -efficiency broadband high -speed frequency jump.
Patent Information
- Application Number
- CN202411498251.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-25
- Publication Date
- 2025-01-24
AI Technical Summary
When the existing PLL frequency synthesizer is operating at frequency hopping, the timing control is complex and difficult to optimize, resulting in the frequency switching response speed not being fast enough.
By improving the order of SRAM memory, optimize the timing control of the PLL frequency synthesizer, and increase the frequency jump rate. Specific methods include setting frequency jump points and rates at the upper machine, transfer the PLL register configuration information to SRAM memory, and read the configuration information through the FPGA controller to realize the rapid switching of the PLL frequency synthesizer.
Without changing the hardware device, the timing control optimization of the PLL frequency synthesizer is achieved, and the frequency jump rate has been improved. The experiment proves that the frequency jump rate can reach 30000hop/s above.
Smart Images
Figure CN119363102A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technology, and in particular to a broadband high-speed frequency hopping method based on a PLL frequency synthesizer. Background Art
[0002] The PLL frequency synthesizer can perform precise frequency and phase control on the input signal and is mainly used for synchronization and frequency adjustment of the clock signal. Its carrier frequency switches rapidly between multiple predetermined frequencies. The timing control of the existing PLL frequency synthesizer is relatively complex, involving PLL frequency configuration, frequency calibration, feedback division ratio, and rapid switching, etc., to ensure that the PLL can obtain stable and reliable frequency output and rapid frequency switching response speed during frequency hopping operation, which usually involves many hardware equipment improvements.
[0003] How to optimize the timing control of PLL without improving the hardware equipment is an important research and development direction in this field. Summary of the invention
[0004] Therefore, in view of the above problems, the present invention proposes a broadband high-speed frequency hopping method based on a PLL frequency synthesizer, which optimizes the timing control of the PLL frequency synthesizer by improving the sequential reading of the SRAM memory and improving the frequency hopping rate.
[0005] To achieve the above object, the present invention adopts the following technical solutions:
[0006] A broadband high-speed frequency hopping method based on a PLL frequency synthesizer is applied to a frequency hopping system, wherein the frequency hopping system comprises a host computer and an FPGA controller, and an SRAM memory electrically connected to the FPGA controller, a communication interface, a first PLL frequency synthesizer, a second PLL frequency synthesizer, a differential oscillator and a radio frequency device, wherein the host computer is electrically connected to the communication interface;
[0007] The broadband high-speed frequency hopping method based on PLL frequency synthesizer includes the following steps:
[0008] Step 1, resetting and initializing the registers of the first PLL frequency synthesizer and the second PLL frequency synthesizer;
[0009] Step 2: Edit the frequency hopping strategy;
[0010] Set the frequency hopping points, frequency set size and frequency hopping rate on the host computer, convert all frequency hopping points into corresponding PLL register configuration information, convert the frequency set size into the address space of the SRAM memory, and convert the frequency hopping rate into the corresponding frequency hopping point interval count;
[0011] Step 3: Data writing;
[0012] The frequency hopping frequency, frequency set size and frequency hopping rate described in step 2 are sent to the FPGA controller through the communication interface, and the FPGA controller extracts the PLL register configuration information of each frequency hopping frequency and sequentially transfers it to the SRAM memory;
[0013] Step 4: SRAM memory reading and RF gating switching, including the following steps performed in sequence:
[0014] Step (1), for the first frequency hopping frequency point, the FPGA controller reads the PLL register configuration information of the first frequency hopping frequency point in the SRAM memory, transmits the PLL register configuration information to the first PLL frequency synthesizer, and sets the working state of the first PLL frequency synthesizer;
[0015] Step (2), configuring the second PLL frequency synthesizer, the FPGA controller sequentially reads the PLL register configuration information of the next frequency hopping point in the SRAM memory and transmits it to the second PLL frequency synthesizer, and sets the working state of the second PLL frequency synthesizer;
[0016] Step (3), the first PLL frequency synthesizer starts outputting, and controls the RF device to select the first PLL frequency synthesizer to generate a corresponding first frequency hopping frequency point RF frequency output;
[0017] Step (4), configuring the first PLL frequency synthesizer, sequentially reading the PLL register configuration information of the next frequency hopping point in the SRAM memory, and transmitting it to the first PLL frequency synthesizer, and setting the working state of the first PLL frequency synthesizer;
[0018] Step (5), the second PLL frequency synthesizer starts outputting, and controls the RF device to select the second PLL frequency synthesizer to generate a corresponding second frequency hopping frequency point RF frequency output;
[0019] Step (6), and so on, repeat the above steps (2), (3), (4) and (5) to generate the corresponding third frequency hopping frequency point RF frequency output, the fourth frequency hopping frequency point RF frequency output ... until the last frequency hopping frequency point RF frequency output is executed, and return to step (1) to continue execution;
[0020] Until the host computer issues a stop command.
[0021] Further, the PLL register configuration information of each frequency hopping frequency point includes a frequency configuration control word, a frequency calibration control word and a frequency output enable control word;
[0022] In the step (1), the method in which the FPGA controller sequentially reads the PLL register configuration information of the first frequency hopping frequency point in the SRAM memory is: sequentially reading the frequency configuration control word and the frequency calibration control word of the PLL register configuration information of the first frequency hopping frequency point;
[0023] In the step (2), after reading the frequency calibration control word of the first frequency hopping frequency point and after time t1, the frequency output enable control word is read, and the frequency output enable control word is transmitted to the second PLL frequency synthesizer, and the radio frequency device is controlled not to select the second PLL frequency synthesizer during the first round of frequency hopping; after time t2, the frequency configuration control word and the frequency calibration control word of the PLL register configuration information of the next frequency hopping frequency point are sequentially read to configure the second PLL frequency synthesizer;
[0024] In the step (3), the frequency output start control word of the first frequency hopping frequency point is read, the frequency output start control word is transmitted to the first PLL frequency synthesizer, the output is turned on, and the RF device is controlled to select the first PLL frequency synthesizer to generate the RF frequency output of the first frequency hopping frequency point;
[0025] In the step (4), the first PLL frequency synthesizer output is turned on and after time t2 has passed, the frequency configuration control word and the frequency calibration control word of the next frequency hopping frequency point PLL register configuration information are sequentially read to configure the first PLL frequency synthesizer;
[0026] In the step (5), after reading the frequency calibration control word of the next frequency hopping frequency point and after time t1, the frequency output start control word is read, and the frequency output start control word is passed to the second PLL frequency synthesizer to start the output, and the RF device is controlled to select the second PLL frequency synthesizer to generate the second frequency hopping frequency point RF frequency output.
[0027] Further, the PLL register configuration information of each frequency hopping frequency point in the SRAM memory includes 11 address bits, each address bit is 24 bits;
[0028] The first nine address bits are the frequency configuration control word, the tenth address bit is the frequency calibration control word, and the eleventh address bit is the frequency output enable control word.
[0029] Furthermore, the FPGA controller adopts any FPGA of the Spartan-6 series;
[0030] The communication interface adopts FT232RL interface conversion chip;
[0031] The radio frequency device adopts a HMC345ALP3E radio frequency device, and the first PLL frequency synthesizer and the second PLL frequency synthesizer are electrically connected to the radio frequency device respectively;
[0032] The SRAM memory adopts CY7C1360C-200AXC memory;
[0033] The first PLL frequency synthesizer and the second PLL frequency synthesizer both adopt LMX2594RHAR synthesizer.
[0034] Furthermore, the frequency hopping system further comprises a differential oscillator, and the first PLL frequency synthesizer, the second PLL frequency synthesizer and the FPGA controller are electrically connected to the differential oscillator respectively;
[0035] The differential oscillator generates a 100 MHz differential oscillation signal as an external clock reference signal for the phase detector of the first PLL frequency synthesizer and the second PLL frequency synthesizer;
[0036] The 100MHz differential oscillation signal generated by the differential oscillator is multiplied to obtain a 200MHz clock signal as the phase detection frequency of the phase detector.
[0037] Furthermore, the differential oscillator adopts LMK61 PD0A2 differential oscillator.
[0038] Furthermore, the first PLL frequency synthesizer and the second PLL frequency synthesizer share a SCK clock line and an SD I data line.
[0039] By adopting the above technical solution, the beneficial effects of the present invention are:
[0040] The frequency hopping system in this scheme is an existing common equipment structure. This broadband high-speed frequency hopping method based on PLL frequency synthesizer can optimize the timing control of the first PLL frequency synthesizer and the second PLL frequency synthesizer by optimizing the sequential reading of the memory without changing the hardware structure of the existing frequency hopping system, thereby further improving the frequency hopping rate. Experiments have shown that the frequency hopping rate can reach more than 30,000 Hop / s without affecting the frequency hopping effect. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figure 1 It is a circuit structure block diagram of the frequency hopping system of the present invention.
[0042] Figure 2 It is a flow chart of the present invention.
[0043] Figure 3 This is a schematic diagram of the storage address division of four frequency hopping points in the SRAM memory.
[0044] Figure 4 It is a timing control diagram of the first PLL frequency synthesizer and the second PLL frequency synthesizer.
[0045] Figure 5 This is the waveform simulation diagram when the frequency hopping rate is 30000Hop / s. DETAILED DESCRIPTION
[0046] The present invention will now be further described with reference to the accompanying drawings and specific implementation methods.
[0047] refer to Figure 1-Figure 5 This embodiment provides a broadband high-speed frequency hopping method based on a PLL frequency synthesizer, which is applied to a frequency hopping system. The frequency hopping system includes a host computer 1 and an FPGA controller 2, as well as an SRAM memory 3, a communication interface 4, a first PLL frequency synthesizer 5, a second PLL frequency synthesizer 6, a differential oscillator 7 and a radio frequency device 8 electrically connected to the FPGA controller 2. The first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6 share an SCK clock line and an SD I data line. The host computer 1 is electrically connected to the FPGA controller 2 through the communication interface 4. The host computer 1 is a computer terminal. All of the above electronic components are existing equipment, and the selection of the above electronic components is also a conventional technology in the field.
[0048] In this specific embodiment, preferably:
[0049] The FPGA controller 2 uses any FPGA of the Spartan-6 series;
[0050] The SRAM memory 3 adopts CY7C1360C-200AXC memory;
[0051] The communication interface 4 adopts FT232RL interface conversion chip;
[0052] The radio frequency device 8 is a HMC345ALP3E radio frequency device, and the radio frequency device 8 is electrically connected to the first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6 respectively;
[0053] The first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6 both adopt LMX2594RHAR synthesizer; the first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6 use SPI communication with the FPGA controller 2 for data transmission.
[0054] The differential oscillator 7 is a LMK61 PD0A2 differential oscillator. The first PLL frequency synthesizer 5, the second PLL frequency synthesizer 6 and the FPGA controller 2 are electrically connected to the differential oscillator 7 respectively.
[0055] The FPGA controller 2 is used to generate various clock signals and control signals, the clock signals include the SRAM memory 3 working clock and the SPI communication clock, the control signals include the communication interface 4 data reception control, the SRAM memory 3 write and read control, and the first PLL frequency synthesizer 5, the second PLL frequency synthesizer 6 and the RF device 8 output selection control.
[0056] The FPGA controller 2 generates a 150MHz SRAM memory 3 working clock;
[0057] Divide the 150MHz clock signal by two to obtain a 75MHz SPI communication clock as the SPI communication clock SCK required for configuring the first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6;
[0058] The differential oscillator 7 generates a 100 MHz differential oscillation signal as an external clock reference signal for the phase detectors of the first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6 (the phase detectors of the first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6);
[0059] The 100 MHz differential oscillation signal generated by the differential oscillator 7 is multiplied to obtain a 200 MHz clock signal as the phase detection frequency of the phase detector.
[0060] The broadband high-speed frequency hopping method based on PLL frequency synthesizer comprises the following steps:
[0061] Step 1, resetting and initializing the registers of the first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6;
[0062] Step 2: Edit the frequency hopping strategy;
[0063] Edit the frequency hopping points (equal interval or variable interval), frequency set size and frequency hopping rate in the host computer 1, convert all the frequency hopping points into the corresponding PLL register configuration information, convert the frequency set size into the address space of the SRAM memory, and convert the frequency hopping rate into the corresponding frequency hopping frequency point interval count;
[0064] Step 3: Data writing;
[0065] All the frequency hopping frequencies, frequency set sizes and frequency hopping rates in step 2 are sent to the FPGA controller 2 through the communication interface 4, and the FPGA controller 2 extracts the PLL register configuration information of each frequency hopping frequency and sequentially transfers it to the SRAM memory 3;
[0066] Step 4, SRAM memory 3 reading and RF gating switching, including the following steps performed in sequence:
[0067] Step (1), for the first frequency hopping frequency point, the FPGA controller 2 reads the PLL register configuration information of the first frequency hopping frequency point in the SRAM memory 3, transmits the PLL register configuration information to the first PLL frequency synthesizer 5, and sets the working state of the first PLL frequency synthesizer 5;
[0068] Step (2), configuring the second PLL frequency synthesizer 6, the FPGA controller 2 sequentially reads the PLL register configuration information of the next frequency hopping point in the SRAM memory 3 and transmits it to the second PLL frequency synthesizer 6, and sets the working state of the second PLL frequency synthesizer 6;
[0069] Step (3), the first PLL frequency synthesizer 5 starts outputting, and the RF device 8 is controlled to select the first PLL frequency synthesizer 5 to generate a corresponding first frequency hopping frequency point RF frequency output;
[0070] Step (4), configuring the first PLL frequency synthesizer 5, sequentially reading the PLL register configuration information of the third frequency hopping frequency point in the SRAM memory 3, and transmitting it to the first PLL frequency synthesizer 5, and setting the working state of the first PLL frequency synthesizer 5;
[0071] Step (5), the second PLL frequency synthesizer 6 starts outputting, and controls the RF device 8 to select the second PLL frequency synthesizer 6, so as to generate a corresponding second frequency hopping frequency point RF frequency output;
[0072] Step (6), and so on, repeat the above steps (2), (3), (4) and (5) to generate the corresponding third frequency hopping frequency point RF frequency output, the fourth frequency hopping frequency point RF frequency output ... until the last frequency hopping frequency point RF frequency output is executed, and return to step (1) to continue execution;
[0073] Until the host computer 1 issues a stop command.
[0074] In step 2 above:
[0075] The PLL register configuration information of each frequency hopping frequency point includes a frequency configuration control word, a frequency calibration control word, and a frequency output enable control word.
[0076] More specifically, the PLL register configuration information of each frequency hopping frequency in the SRAM memory 3 includes 11 address bits, each address bit is 24 bits; in the PLL register configuration information defined in a frequency hopping frequency, the first nine address bits are the frequency configuration control word, the tenth address bit is the frequency calibration control word, and the eleventh address bit is the frequency output enable control word.
[0077] like Figure 3 In this embodiment, taking four frequency hopping points as an example, the frequency configuration control word and frequency calibration control word of the first frequency hopping point are address bits 0-9, the frequency configuration control word and frequency calibration control word of the second frequency hopping point are address bits 11-20, the frequency configuration control word and frequency calibration control word of the third frequency hopping point are address bits 22-31, and the frequency configuration control word and frequency calibration control word of the fourth frequency hopping point are address bits 33-42. Address bits 10, 21, 32, and 43 are frequency output enable control words.
[0078] like Figure 4 In the step (1), the method by which the FPGA controller 2 sequentially reads the PLL register configuration information of the first frequency hopping frequency point in the SRAM memory 3 is: sequentially read the frequency configuration control word and the frequency calibration control word 0-9 of the PLL register configuration information of the first frequency hopping frequency point.
[0079] In the step (2), after reading the frequency calibration control word 9 of the first frequency hopping frequency point and after time t1, the address 10 is read, and the frequency output start control word is passed to the second PLL frequency synthesizer 6, and the RF device 8 is controlled not to select the second PLL frequency synthesizer 6 during the first round of frequency hopping. After time t2, the frequency configuration control word and frequency calibration control words 11-20 of the PLL register configuration information of the second frequency hopping frequency point are sequentially read to configure the second PLL frequency synthesizer 6.
[0080] In the step (3), after reading the frequency calibration control word 20 of the second frequency hopping frequency point and after a time t1, the address 21 is read, and the frequency output start control word is passed to the first PLL frequency synthesizer 5 to start the output, and the RF device 8 is controlled to select the first PLL frequency synthesizer 5 to generate the first frequency hopping frequency point RF frequency output.
[0081] In the step (4), the output of the first PLL frequency synthesizer 5 is turned on and after time t2, the frequency configuration control word and frequency calibration control word 22-31 of the third frequency hopping frequency point PLL register configuration information are sequentially read to configure the first PLL frequency synthesizer 5.
[0082] In the step (5), after reading the frequency calibration control word of the third frequency hopping frequency point and after time t1, read address 32, pass the frequency output start control word to the second PLL frequency synthesizer 6, turn on the output, and control the RF device 8 to select the second PLL frequency synthesizer 6 to generate the second frequency hopping frequency point RF frequency output.
[0083] The time required for frequency calibration of the first PLL frequency synthesizer 5 and the second PLL frequency synthesizer 6 is denoted as T 校准 ;
[0084] The time required to configure a PLL register configuration information is recorded as T0;
[0085] The frequency hopping period is denoted as T 跳频周期 .
[0086] t1=T 校准 -T 跳频周期 ;
[0087] t2=2×T 跳频周期 -T 校准 -11×T0.
[0088] like Figure 5 After circuit simulation, the frequency hopping rate can reach more than 30000 Hop / s in the bandwidth of 30MHz-8GHz without affecting the frequency hopping effect.
[0089] And the larger the capacity of the SRAM memory 3 is, the larger the frequency set supported is. In addition, more excellent frequency hopping performance can be obtained by replacing components or appropriately expanding.
[0090] Although the present invention has been specifically shown and described in conjunction with the preferred embodiments, it should be understood by those skilled in the art that various changes may be made to the present invention in form and details without departing from the spirit and scope of the present invention as defined by the appended claims, all of which are within the scope of protection of the present invention.
Claims
1. A broadband high-speed frequency hopping method based on a PLL frequency synthesizer, applied to a frequency hopping system, wherein the frequency hopping system comprises a host computer and an FPGA controller, and an SRAM memory electrically connected to the FPGA controller, a communication interface, a first PLL frequency synthesizer, a second PLL frequency synthesizer, a differential oscillator and a radio frequency device, wherein the host computer is electrically connected to the communication interface; It is characterized in that The broadband high-speed frequency hopping method based on PLL frequency synthesizer includes the following steps: Step 1, resetting and initializing the registers of the first PLL frequency synthesizer and the second PLL frequency synthesizer; Step 2: Edit the frequency hopping strategy; Set the frequency hopping points, frequency set size and frequency hopping rate on the host computer, convert all frequency hopping points into corresponding PLL register configuration information, convert the frequency set size into the address space of the SRAM memory, and convert the frequency hopping rate into the corresponding frequency hopping point interval count; Step 3: Data writing; The frequency hopping frequency, frequency set size and frequency hopping rate described in step 2 are sent to the FPGA controller through the communication interface, and the FPGA controller extracts the PLL register configuration information of each frequency hopping frequency and sequentially transfers it to the SRAM memory; Step 4: SRAM memory reading and RF gating switching, including the following steps performed in sequence: Step (1), for the first frequency hopping frequency point, the FPGA controller reads the PLL register configuration information of the first frequency hopping frequency point in the SRAM memory, transmits the PLL register configuration information to the first PLL frequency synthesizer, and sets the working state of the first PLL frequency synthesizer; Step (2), configuring the second PLL frequency synthesizer, the FPGA controller sequentially reads the PLL register configuration information of the next frequency hopping point in the SRAM memory and transmits it to the second PLL frequency synthesizer, and sets the working state of the second PLL frequency synthesizer; Step (3), the first PLL frequency synthesizer starts outputting, and controls the RF device to select the first PLL frequency synthesizer to generate a corresponding first frequency hopping frequency point RF frequency output; Step (4), configuring the first PLL frequency synthesizer, sequentially reading the PLL register configuration information of the next frequency hopping point in the SRAM memory, and transmitting it to the first PLL frequency synthesizer, and setting the working state of the first PLL frequency synthesizer; Step (5), the second PLL frequency synthesizer starts outputting, and controls the RF device to select the second PLL frequency synthesizer to generate a corresponding second frequency hopping frequency point RF frequency output; Step (6), and so on, repeat the above steps (2), (3), (4) and (5) to generate the corresponding third frequency hopping frequency point RF frequency output, the fourth frequency hopping frequency point RF frequency output ... until the last frequency hopping frequency point RF frequency output is executed, and return to step (1) to continue execution; Until the host computer issues a stop command.
2. A broadband high-speed frequency hopping method based on a PLL frequency synthesizer according to claim 1, characterized in that : The PLL register configuration information of each frequency hopping frequency point includes a frequency configuration control word, a frequency calibration control word, and a frequency output enable control word; In the step (1), the method in which the FPGA controller sequentially reads the PLL register configuration information of the first frequency hopping frequency point in the SRAM memory is: sequentially reading the frequency configuration control word and the frequency calibration control word of the PLL register configuration information of the first frequency hopping frequency point; In the step (2), after reading the frequency calibration control word of the first frequency hopping frequency point and after time t1, the frequency output enable control word is read, and the frequency output enable control word is transmitted to the second PLL frequency synthesizer, and the radio frequency device is controlled not to select the second PLL frequency synthesizer during the first round of frequency hopping; and after time t2, the frequency configuration control word and the frequency calibration control word of the PLL register configuration information of the next frequency hopping frequency point are sequentially read to configure the second PLL frequency synthesizer; In the step (3), the frequency output start control word of the first frequency hopping frequency point is read, the frequency output start control word is transmitted to the first PLL frequency synthesizer, the output is turned on, and the RF device is controlled to select the first PLL frequency synthesizer to generate the RF frequency output of the first frequency hopping frequency point; In the step (4), the first PLL frequency synthesizer output is turned on and after time t2 has passed, the frequency configuration control word and the frequency calibration control word of the next frequency hopping frequency point PLL register configuration information are sequentially read to configure the first PLL frequency synthesizer; In the step (5), after reading the frequency calibration control word of the next frequency hopping frequency point and after time t1, the frequency output start control word is read, and the frequency output start control word is passed to the second PLL frequency synthesizer to start the output, and the RF device is controlled to select the second PLL frequency synthesizer to generate the second frequency hopping frequency point RF frequency output.
3. The broadband high-speed frequency hopping method based on a PLL frequency synthesizer according to claim 2, characterized in that: The PLL register configuration information of each frequency hopping frequency point in the SRAM memory includes 11 address bits, each address bit is 24 bits; The first nine address bits are the frequency configuration control word, the tenth address bit is the frequency calibration control word, and the eleventh address bit is the frequency output enable control word.
4. The broadband high-speed frequency hopping method based on a PLL frequency synthesizer according to claim 1, characterized in that: The FPGA controller adopts any FPGA of the Spartan-6 series; The communication interface adopts FT232RL interface conversion chip; The radio frequency device adopts a HMC345ALP3E radio frequency device, and the first PLL frequency synthesizer and the second PLL frequency synthesizer are electrically connected to the radio frequency device respectively; The SRAM memory adopts CY7C1360C-200AXC memory; The first PLL frequency synthesizer and the second PLL frequency synthesizer both adopt LMX2594RHAR synthesizer.
5. A broadband high-speed frequency hopping method based on a PLL frequency synthesizer according to any one of claims 1 to 4, characterized in that: The frequency hopping system further comprises a differential oscillator, and the first PLL frequency synthesizer, the second PLL frequency synthesizer and the FPGA controller are electrically connected to the differential oscillator respectively; The differential oscillator generates a 100 MHz differential oscillation signal as an external clock reference signal for the phase detector of the first PLL frequency synthesizer and the second PLL frequency synthesizer; The 100MHz differential oscillation signal generated by the differential oscillator is multiplied to obtain a 200MHz clock signal as the phase detection frequency of the phase detector.
6. The broadband high-speed frequency hopping method based on a PLL frequency synthesizer according to claim 5, characterized in that: The differential oscillator adopts LMK61 PD0A2 differential oscillator.
7. The broadband high-speed frequency hopping method based on PLL frequency synthesizer according to claim 6, characterized in that: The first PLL frequency synthesizer and the second PLL frequency synthesizer share a SCK clock line and a SDI data line.