Successive approximation analog-to-digital converter with noise elimination function and control method of successive approximation analog-to-digital converter
By adopting noise eliminates in the SAR ADC to approach the structure of the modulus -type digital converter one by one, the combination of the first capacitor array and the second capacitance array is used to freeze and eliminate the KT/C noise. The problem of large area, high power consumption and conversion speed, and low accuracy have achieved more efficient modulus conversion.
Patent Information
- Application Number
- CN202411494655.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-24
- Publication Date
- 2025-01-24
AI Technical Summary
In existing high-precision SAR ADCs, KT/C noise limitations lead to large ADC area, high power consumption, and low conversion speed and accuracy.
Using noise eliminates a one -time approaching model digital converter structure, including sampling unit, front placement large unit, and logical conversion unit. Through the cooperation of the first capacitor array and the second capacitor array, the noise voltage is changed during the sampling process. It is eliminated as a fixed disorder voltage at the quantification stage.
It effectively reduces the KT/C noise of the overall analog-to-digital converter, reduces the value of the capacitor array, reduces the effective area of the capacitor array and DAC setup time, and improves the conversion speed and accuracy of the analog-to-digital converter.
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Figure CN119363108A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of analog-to-digital converters, and in particular to a successive approximation analog-to-digital converter with noise elimination and a control method thereof. Background Art
[0002] Common Nyquist analog-to-digital converters (ADCs) include flash ADCs, two-step ADCs, pipeline ADCs, successive approximation ADCs, etc. Among them, the successive approximation register (SAR) has the advantages of simple structure, low power consumption, and small area, and is usually used in medium-to-high-precision and low-speed applications. The difficulty in implementing high-precision SAR ADCs is mainly limited by the DAC network and high-precision comparators. The DAC network has the following bottlenecks: As the accuracy increases, the number of capacitors increases exponentially, and affected by KT / C noise, the value of the unit capacitance also increases, resulting in an increase in area, increased power consumption, and the speed of analog-to-digital conversion is also affected.
[0003] In the current high-precision SAR ADC, the capacitor array is segmented, which can alleviate the problem of exponential growth of capacitance and reduce the area of the capacitor array. There are many segmentation methods. The capacitor array is divided into the MSB (Most Significant Bit) capacitor array and the LSB (Least Significant Bit) capacitor array, which are bridged by coupling capacitors. The value of the coupling capacitor needs to meet the following requirements: the value of the LSB capacitor array and the coupling capacitor in series is equal to the lowest bit capacitance value of the MSB capacitor array. The segmentation method ranges from two to four segments, and the bridge capacitor uses a unit capacitor or a multiple of a unit capacitor. For example, for a 10-bit SAR ADC, you can choose "5+5", "6+4", "7+3", etc. Different segmentation methods have different areas, power consumption, and nonlinearity. They are obtained by weighing the pros and cons according to your own design requirements. However, the size of the unit capacitance value is still limited by KT / C noise, resulting in ADC area and power consumption limitations, and the conversion speed and accuracy will also be affected by noise. Summary of the invention
[0004] The purpose of the embodiments of the present disclosure is to provide a successive approximation analog-to-digital converter with noise elimination and a control method thereof, so as to solve the problems of large ADC area, high power consumption, low conversion speed and accuracy caused by KT / C noise limitation in the prior art.
[0005] The embodiment of the present disclosure adopts the following technical scheme: a successive approximation analog-to-digital converter with noise elimination, comprising at least: a sampling unit, a preamplifier unit and a logic conversion unit; wherein the sampling unit comprises at least a first capacitor array, a first operational amplifier, and a second capacitor array, one side of the first capacitor array is connected to a differential input signal or a common signal through a first switch, the other side of the first capacitor array is connected to the differential input end of the first operational amplifier, the differential output end of the first operational amplifier is connected to one side of the second capacitor array, the other side of the second capacitor array is connected to the input end of the preamplifier unit, and the other side of the first capacitor array is also connected to the common mode signal through a second switch, and the other side of the second capacitor array is also connected to the common mode signal through a third switch; the preamplifier unit is used to enhance the signal amplitude output by the sampling unit; the logic conversion unit is used to perform successive logic conversion on the signal processed by the preamplifier unit, and adjust the common signal connected to the first capacitor array based on the comparison result until the converted digital signal is output.
[0006] In some embodiments, the first operational amplifier is a dynamic operational amplifier.
[0007] In some embodiments, the sampling unit further includes: a third capacitor array and a fourth switch, one side of the third capacitor array is connected to the differential output terminal of the first operational amplifier, the other side of the third capacitor array is connected to the common mode signal, and the fourth switch is a complementary switch of the third switch.
[0008] In some embodiments, the preamplifier unit includes at least: a second operational amplifier and a third operational amplifier connected in series, and a complementary fifth switch and a sixth switch, the differential input terminal of the second operational amplifier is connected to the other side of the second capacitor array, and the differential output terminal of the third operational amplifier is connected to the logic conversion unit as the output terminal of the preamplifier unit; one end of the fifth switch is connected to the differential output terminal of the third operational amplifier, and the other end of the fifth switch is connected to the logic conversion unit, one end of the sixth switch is connected to the differential input terminal of the second operational amplifier, and the other end of the sixth switch is connected to the other end of the fifth switch.
[0009] In some embodiments, the second operational amplifier and the third operational amplifier are static operational amplifiers.
[0010] The embodiment of the present disclosure also provides a control method of the successive approximation analog-to-digital converter with noise elimination as described above, which at least includes: a sampling stage and a quantization stage; the sampling stage at least includes a first capacitor array sampling period and a second capacitor array sampling period, wherein, in the first capacitor array sampling period, the logic conversion unit controls the first switch, the second switch and the third switch to be closed, so that the first capacitor array samples the differential input signal; in the second capacitor array sampling period, the logic conversion unit controls the first switch and the third switch to be closed, and the second switch to be opened, so that the voltage across the first capacitor array is frozen to Vin(t1)+V1, and the second capacitor array samples the amplified signal output by the first operational amplifier; wherein Vin(t1) is the second The input signal collected by the first capacitor array when the switch is disconnected, V1 is the sampled thermal noise of the first capacitor array; in the quantization stage, the logic conversion unit controls the first switch, the second switch and the third switch to be disconnected, so that the voltage across the second capacitor array is frozen to A[Vin(t2)-Vin(t1)-V1-Vos1]+V2, and starts to perform successive logic conversion until the voltage on the other side of the second capacitor array is 0, and outputs the converted digital signal Dout=Vin(t2)+V2 / A, wherein Vin(t2) is the input signal collected by the first capacitor array when the third switch is disconnected, A is the amplification factor of the first operational amplifier, Vos1 is the offset voltage of the first operational amplifier, and V2 is the sampled thermal noise of the second capacitor array.
[0011] In some embodiments, the quantization stage further includes: the logic conversion unit drives the first operational amplifier to reset and close the fourth switch.
[0012] In some embodiments, the quantization stage also includes: during the first logic conversion, the Nth logic conversion to the last logic conversion, the logic conversion unit controls the fifth switch to be opened and the sixth switch to be closed; during the second logic conversion to the N-1th logic conversion, the logic conversion unit controls the fifth switch to be closed and the sixth switch to be opened.
[0013] In some embodiments, the value of N is calculated based on the values of the power supply voltage, the reference voltage, and the common mode voltage of the successive approximation analog-to-digital converter.
[0014] In some embodiments, after the sampling stage, a disturbance voltage injection stage is also included; wherein, when a positive disturbance voltage is injected, the logic conversion unit controls one side of the first multiplexed capacitor in the first capacitor array to switch from the common mode voltage to the reference voltage, and controls one side of the second multiplexed capacitor in the first capacitor array to switch from the common mode voltage to the ground; when a negative disturbance voltage is injected, the logic conversion unit controls one side of the first multiplexed capacitor to switch from the common mode voltage to the ground, and controls one side of the second multiplexed capacitor to switch from the common mode voltage to the reference voltage; wherein the first multiplexed capacitor and the second multiplexed capacitor are capacitors with different unit capacitances, the other side of the first multiplexed capacitor is connected to the non-inverting input terminal of the first operational amplifier, and the other side of the second multiplexed capacitor is connected to the inverting input terminal of the first operational amplifier, and during the disturbance voltage injection stage, the states of other capacitors in the first capacitor array except the first multiplexed capacitor and the second multiplexed capacitor remain unchanged and remain connected to the common mode voltage.
[0015] The beneficial effects of the disclosed embodiments are as follows: by improving the specific structure of the sampling unit in the SAR ADC, the first capacitor array and the second capacitor array are used to freeze the time-varying noise voltage during the sampling process, and it is regarded as a fixed offset voltage of the front input in the quantization stage, and is eliminated based on the offset elimination technology, so that the sampling thermal noise of the first capacitor array and the offset of the first operational amplifier are eliminated, the sampling thermal noise of the second capacitor array is reduced, and the KT / C noise of the overall analog-to-digital converter is effectively reduced, so that the value of the capacitor array is no longer affected by the KT / C noise, the effective area of the capacitor array and the DAC settling time are reduced, and the conversion speed and accuracy of the analog-to-digital converter are improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate one or more embodiments of this specification or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0017] Figure 1 It is a structural schematic diagram of a successive approximation analog-to-digital converter with noise elimination in the first embodiment of the present disclosure;
[0018] Figure 2 It is a system overall framework diagram of a successive approximation analog-to-digital converter with noise cancellation in the first embodiment of the present disclosure;
[0019] Figure 3 A schematic diagram of eliminating KT / C noise in the first embodiment of the present disclosure;
[0020] Figure 4 1 is a flow chart of a control method of a successive approximation analog-to-digital converter with noise elimination in a second embodiment of the present disclosure;
[0021] Figure 5 It is a schematic diagram of a perturbation-based digital calibration technology in the prior art;
[0022] Figure 6 Schematic diagram of disturbance voltage injection in the second embodiment of the present disclosure. DETAILED DESCRIPTION
[0023] In order to enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below in conjunction with the drawings in one or more embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. Based on one or more embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this document.
[0024] Common Nyquist analog-to-digital converters include flash ADC, two-step ADC, pipeline ADC, successive approximation ADC, etc. Among them, the successive approximation type has the advantages of simple structure, low power consumption, and small area, and is usually used in medium-to-high precision and low-speed applications. The difficulty in implementing high-precision SAR ADC is mainly limited by the DAC network and high-precision comparator. The DAC network has the following bottlenecks: As the accuracy increases, the number of capacitors increases exponentially, and affected by KT / C noise, the value of unit capacitance also increases, resulting in an increase in area, increased power consumption, and the speed of analog-to-digital conversion is also affected.
[0025] In the current high-precision SAR ADC, capacitor arrays are all segmented, which can alleviate the problem of exponential growth of capacitance and reduce the area of the capacitor array. There are many segmentation methods. The capacitor array is divided into an MSB capacitor array and an LSB capacitor array, which are bridged by coupling capacitors. The value of the coupling capacitor needs to meet the following requirements: the value of the LSB capacitor array and the coupling capacitor in series is equal to the lowest capacitance value of the MSB capacitor array. The segmentation method ranges from two to four segments, and the bridge capacitor uses a unit capacitor or a multiple of a unit capacitor. For example, for a 10-bit SAR ADC, you can choose "5+5", "6+4", "7+3", etc. Different segmentation methods have different areas, power consumption, and nonlinearity. You can weigh the pros and cons according to your own design requirements. However, the size of the unit capacitance value is still limited by KT / C noise, resulting in ADC area and power consumption limitations, and the conversion speed and accuracy will also be affected by noise.
[0026] In addition, the comparator is another very critical analog module in the SAR ADC besides the capacitor array. With the continuous improvement of the accuracy of SAR ADC, higher requirements are also placed on the accuracy of the comparator. If the accuracy of the comparator is not enough, the last few comparisons in the successive approximation process may produce wrong comparison results, which directly leads to errors in the last few digital output codes and reduces the accuracy of the entire ADC. Traditional high-precision (above 16 bits) SAR ADC comparators usually adopt a static pre-amplifier plus a dynamic comparator cascade structure. In this case, the static amplifier contributes to a large power consumption, which violates the advantage of low power consumption of SAR ADC.
[0027] In order to solve the above problems, the first embodiment of the present disclosure provides a successive approximation analog-to-digital converter with noise elimination, and its structural diagram is shown in FIG. Figure 1 As shown, it mainly includes a sampling unit 10, a preamplifier unit 20 and a logic conversion unit 30 which are coupled to each other, wherein the sampling unit 10 is mainly used to store the input signal to be converted, and compare it with the reference voltage during the conversion process, so as to gradually determine the digital representation of the input signal; the preamplifier unit 20 is mainly used to enhance the amplitude of the input signal to ensure that the signal level is suitable for accurate analog-to-digital conversion; the logic conversion unit 30 is mainly used to realize successive logic conversion, and output a digital signal of corresponding bits based on the comparison result between the sampling signal and the reference voltage, and adjust the size of the common signal connected to the capacitor array in the sampling unit according to the comparison result until the analog-to-digital conversion of all bits is completed.
[0028] Figure 2 FIG. 4 shows the overall system framework of the analog-to-digital converter of this embodiment. Figure 2 As shown, the sampling unit 10 in this embodiment at least includes a first capacitor array C1, a first operational amplifier A1 and a second capacitor array, wherein the first capacitor array C1 can be a conventional binary segmented sampling capacitor array, and its specific segmented form and the connection relationship between each capacitor can be directly implemented by a conventional sampling array, and this embodiment does not limit its specific structure. Figure 2The specific structure of C1 shown in the figure is only an achievable example and does not limit the implementation of other capacitor arrays in this embodiment; the second capacitor array includes two completely identical second capacitors C2, and the above two second capacitors C2 are respectively connected in series to the two outputs of the differential output end of the first operational amplifier A1. Specifically, one side of the first capacitor array C1 (also referred to as the lower plate of C1) is connected to the differential input signal (Vin, Vip) or the common signal through the first switch S1, the other side of the first capacitor array C1 (also referred to as the upper plate of C1) is connected to the differential input terminal of the first operational amplifier A1, the differential output terminal of A1 is connected to one side of the second capacitor array (also referred to as the lower plate of the second capacitor array) (that is, one path of the differential output terminal of A1 is connected to one side of one of the second capacitors C2, and the other path of the differential output terminal is connected to one side of the other second capacitor C2), the other side of C2 (also referred to as the upper plate of the second capacitor array, that is, the other side of the above two second capacitors C2) is connected to the input terminal of the preamplifier unit as the output terminal of the sampling unit 10; and, the lower plate of C1 is also connected to the common mode signal Vcm through the second switch S2, and the upper plate of C2 is connected to the common mode signal Vcm through the third switch S3.
[0029] It should be understood that the input and output of all devices in this embodiment are differential, and corresponding to the differential input and output, the first capacitor array C1 and the second capacitor array are corresponding to each path of the differential input and output. The settings corresponding to the second switch S2 and the third switch S3 are also independently designed for each path of the differential input and output, but the actual control of the switch on and off and the sampling of the capacitor array should be carried out synchronously according to the conventional control logic, and this embodiment will not be described in detail here. In addition, the common signal in this embodiment at least includes a common mode signal Vcm, a reference signal Vref and a ground signal GND. The logic conversion unit 30 adjusts the signal connected to one side of the first capacitor array C1 in combination with the specific conversion stage and the comparison result under the current bit number. The specific adjustment logic can be based on the conventional adjustment method, and this embodiment will not be described in detail. It should be noted that the first switch S1 can be a switch array set in combination with the capacitor array situation of the first capacitor array C1. The specific control situation of each switch in the switch array can be synchronized or independently switched by the logic conversion unit 30 in combination with the actual conversion stage. In this embodiment, if not specifically stated, it can be switched by conventional control logic. In addition, the latch LATCH and the conversion logic Logic specifically included in the logic conversion unit 30 can be implemented based on a conventional method, which will not be described in this embodiment.
[0030] The traditional DAC is affected by KT / C noise. The constraints are shown in formula (1). Under the power supply voltage of 1.8V, the minimum capacitance is 64.4fF. The MIM (Metal-Insulator-Metal) capacitor needs to be a block capacitor, so the final value is 9u*9u=78.49fF.
[0031]
[0032] Where K is the Boltzmann constant, T is the temperature, C is the DAC array capacitance, LSB is the least significant bit, N is the resolution of the ADC, and V is the supply voltage.
[0033] In this embodiment, the schematic diagram of eliminating KT / C noise is as follows: Figure 3As shown, the relevant structures and connection relationships in the sampling unit 10 are simplified to the structure shown in Figure 3. Specifically, in the conversion process of the analog-to-digital converter, when the second switch S2 is disconnected, the time-varying noise voltage is frozen at a constant input voltage. In the subsequent entire SAR conversion stage, its role can be regarded as a fixed offset voltage at the input of the preamplifier, and it is eliminated based on the offset elimination technology. Specifically, the SAR ADC in this embodiment is mainly divided into a sampling stage and a quantization stage, wherein the sampling stage includes at least a first capacitor array sampling period and a second capacitor array sampling period. In the first capacitor array sampling period, S1, S2 and S3 are closed, and C1 samples Vin. In the second capacitor array sampling period, S2 is disconnected. When S2 is disconnected (i.e., at t1), the input signal Vin(t1) collected by the first capacitor array and the sampled thermal noise V1 of C1 are stored on C1. In subsequent operations, the voltage across C1 can be regarded as frozen, i.e., Vin(t1)+V1. At this time, S1 and S3 are still closed, so C2 continues to sample until S3 enters the quantization stage. In the quantization stage, S1, S2 and S3 are all disconnected, and the sampling thermal noise V2 of S2 is stored on C2. At this time, the voltage frozen on C2 is the voltage of C1 and the voltage after the offset is amplified by the operational amplifier plus the sampling thermal noise of S2, that is, A[Vin(t2)-Vin(t1)-V1-Vos1]+V2, wherein Vin(t2) is the input signal collected by the first capacitor array when the third switch is disconnected, A is the gain of the first operational amplifier, Vos1 is the offset voltage of the first operational amplifier, and V2 is the sampling thermal noise of C2; then the preamplifier unit 20 and the logic conversion unit 30 start quantization. After the quantization is completed, due to the working principle of the SAR ADC, the voltage of the right plate of C2 is 0 after the quantization is completed. According to the law of charge conservation, the output digital signal Dout=Vin(t2)+V2 / A can be obtained. At this time, the sampling thermal noise of C1 and the offset of A1 are eliminated, and the sampling thermal noise of C2 is reduced by A times, which effectively completes the elimination of KT / C noise.
[0034] Based on the sampling unit structure design of this embodiment, the sampling thermal noise of C1 is eliminated, and the sampling thermal noise of C2 is reduced. Further combined with the restriction of formula (1), under the same power supply voltage, the theoretical capacitance array value of this embodiment is no longer affected by KT / C noise, so it can be set to the minimum MIM capacitance value under the preparation process of the corresponding size. For example, under the 0.18um CMOS process, the minimum MIM capacitance value is 4u*4u=15.5fF, and the total capacitance is reduced from 40.1pF to 7.9pF, which not only meets the reduction of the capacitance array area, but also reduces the power consumption of the capacitance array based on the smaller capacitance value, and improves the conversion speed and accuracy.
[0035] Furthermore, compared with the traditional static operational amplifier, the first operational amplifier in this embodiment adopts a dynamic operational amplifier, combined with the control of S2 and S3 by the logic conversion unit 30, so that A1 remains closed during the sampling period of C1. After the sampling of C1 is completed, the input signal and the sampling thermal noise are frozen on C1, and then amplified by A1 to C2, so as to eliminate the sampling noise and reduce the static power consumption. However, during the sampling and conversion period, with the switching control of different switches, the load capacitance of A1 changes. In order to keep the gain of the dynamic operational amplifier consistent, in some embodiments, a third capacitor array and a fourth switch S4 can be added to the sampling unit 10, such as Figure 2 As shown, one side of the third capacitor array C3 is connected to the differential output terminal of the first operational amplifier A1, the other side of the third capacitor array C3 is connected to the common mode signal Vcm, and the fourth switch S4 is a complementary switch of the third switch S3; it should be noted that the third capacitor array is similar to the second capacitor array, specifically including two completely identical third capacitors C3, which are respectively connected between the two outputs of the differential output terminal of A1 and the second capacitor array, and are used as the load of the first operational amplifier after the second capacitor is frozen during sampling and conversion. At this time, after entering the quantization stage, the logic conversion unit controls S3 to be disconnected, and the voltage on C2 is frozen during the entire conversion cycle. At the same time, the logic conversion unit controls A1 to reset to prepare for the next amplification. At this time, C2 floats and no longer acts as a load capacitor of A1. Therefore, by closing S4, C3 with the same voltage as C2 is used as a load capacitor of A1 to ensure that the dynamic operational amplifier A1 has the same gain during the subsequent conversion process.
[0036] like Figure 2 As shown, the preamplifier unit 20 in this embodiment at least includes: a second operational amplifier A2 and a third operational amplifier A3 connected in series, and a complementary fifth switch S5 and a sixth switch S6, wherein the differential input terminal of the second operational amplifier A2 is connected to the other side of the second capacitor array, and the differential output terminal of the third operational amplifier A3 is connected to the logic conversion unit 30 as the output terminal of the preamplifier unit 20; one end of the fifth switch S5 is connected to the differential output terminal of the third operational amplifier A3, and the other end of the fifth switch S5 is connected to the logic conversion unit 30, one end of the sixth switch S6 is connected to the differential input terminal of the second operational amplifier A2, and the other end of the sixth switch S6 is connected to the other end of the fifth switch S5. In some embodiments, the second operational amplifier A2 and the third operational amplifier A3 are both static amplifiers.
[0037] In the conventional SAR ADC conversion process, the LATCH (latch) offset and noise are much larger than the LSB voltage, which causes errors in the comparison process, affecting the normal quantization process of the ADC and causing large nonlinearity. In order to reduce the impact of LATCH offset and noise, the traditional design adopts the method of pre-amplification plus LATCH cascade. The offset and noise of LATCH reach a smaller value after being amplified by the pre-amplifier. However, the principle of SAR ADC is to use binary division to approximate successively. In the first few comparison processes, the signal amplitude is large, and the correct result can be obtained by LATCH comparison without pre-amplification. The role of the pre-amplifier is not fully utilized, but it will cause large static power consumption and delay waste. In this embodiment, through the design and connection of the fifth switch S5 and the sixth switch S6, the signal path is directly connected to the LATCH for comparison in the first few times of the quantization process, and the pre-amplifier is turned off to reduce power consumption and shorten delay.
[0038] Specifically, this embodiment adopts a switch switching strategy based on Vcm-base, connecting the preamplifier during the first logic conversion, the Nth logic conversion to the last logic conversion, and disconnecting the preamplifier corresponding to the second logic conversion to the N-1th logic conversion to reduce power consumption. The above-mentioned value of N can be calculated in combination with the power supply voltage, reference voltage and common-mode voltage of the successive approximation analog-to-digital converter. At the same time, the LATCH offset also needs to be considered. For example, the power supply voltage is 1.8V. When the input signal is switched for the first time, the capacitor arrays at both ends are switched from Vcm to Vref and GND respectively. Therefore, the levels change to Vip+0.9 / 2 and Vip-0.9 / 2 respectively. At this time, the minimum differential level is 0.9V, and the LATCH offset is about 4mv. Therefore, LATCH can be used directly to compare and generate results before the 7th comparison (the differential level is less than 4mv after the 7th comparison, that is, N=7). From the 7th comparison to the last comparison, S5 is closed and S6 is opened to access the preamplifier. The signal is pre-amplified and then the comparison result is generated by LATCH.
[0039] In some embodiments, Figure 2As shown, in the SAR ADC, a digital calibration unit 40 (Digital Calibration) can be further connected after the logic conversion unit 30 to calibrate and optimize the capacitor mismatch through digital calibration technology, that is, by injecting a disturbance voltage of known size, an error is generated after subtraction in the digital domain, and the error is calibrated by LMS. The specific injection method of the above-mentioned disturbance voltage can be implemented by adding an additional capacitor Cp to the first capacitor array, or it can be completed by multiplexing the first capacitor array. The specific disturbance voltage injection process will be described in detail in the second embodiment of the present disclosure. The digital calibration unit 40 in this embodiment is mainly used to complete the calibration process after the disturbance voltage is injected. It can specifically adopt a conventional digital calibration method. This embodiment does not provide a specific calibration description.
[0040] This embodiment improves the specific structure of the sampling unit in the SAR ADC, and uses the cooperation of the first capacitor array and the second capacitor array to achieve freezing of the time-varying noise voltage during the sampling process, and regards it as a fixed offset voltage of the front input in the quantization stage, and eliminates it based on the offset elimination technology, so that the sampling thermal noise of the first capacitor array and the offset of the first operational amplifier are eliminated, and the sampling thermal noise of the second capacitor array is reduced, which effectively reduces the KT / C noise size of the overall analog-to-digital converter, so that the value of the capacitor array is no longer affected by the KT / C noise, the effective area of the capacitor array and the DAC settling time are reduced, and the conversion speed and accuracy of the analog-to-digital converter are improved.
[0041] Based on the same inventive concept, the second embodiment of the present disclosure provides a control method of the successive approximation analog-to-digital converter of the first embodiment of the present disclosure, and its flow chart is as follows: Figure 4 shown.
[0042] Specifically, the conversion process of the SAR ADC of the present embodiment mainly includes a sampling stage S10 and a quantization stage S20, and the sampling stage includes at least a first capacitor array sampling period S11 and a second capacitor array sampling period S12, wherein, in the first capacitor array sampling period S11, the logic conversion unit controls the first switch, the second switch and the third switch to be closed, so that the first capacitor array samples the differential input signal; in the second capacitor array sampling period S12, the logic conversion unit controls the first switch and the third switch to be closed, and the second switch to be disconnected, so that the voltage across the first capacitor array is frozen as Vin(t1)+V1, and the second capacitor array samples the amplified signal output by the first operational amplifier; wherein Vin(t1) is the voltage of the first capacitor when the second switch is disconnected. The input signal collected by the array, V1 is the sampled thermal noise of the first capacitor array; in the quantization stage S20, the logic conversion unit controls the first switch, the second switch and the third switch to be disconnected, so that the voltage across the second capacitor array is frozen to A[Vin(t2)-Vin(t1)-V1-Vos1]+V2, and starts to perform successive logic conversion until the voltage on the other side of the second capacitor array is 0, and outputs the converted digital signal Dout=Vin(t2)+V2 / A, wherein Vin(t2) is the input signal collected by the first capacitor array when the third switch is disconnected, A is the amplification factor of the first operational amplifier, Vos1 is the offset voltage of the first operational amplifier, and V2 is the sampled thermal noise of the second capacitor array.
[0043] In some embodiments, the quantization stage further includes a logic conversion unit driving the first operational amplifier to reset and closing the fourth switch to achieve load switching of the first operational amplifier to ensure that its gain remains unchanged.
[0044] In some embodiments, the quantization stage also includes: in the process of the first logic conversion, the Nth logic conversion to the last logic conversion, the logic conversion unit controls the fifth switch to be opened and the sixth switch to be closed; in the process of the second logic conversion to the N-1th logic conversion, the logic conversion unit controls the fifth switch to be closed and the sixth switch to be opened, so as to realize the logic control of the preamplifier unit and achieve the purpose of reducing its power consumption. It should be noted that the SAR ADC should include a clock unit to generate a unified clock signal. In asynchronous logic, each time a comparison is completed, a clock rising edge will be generated to control the level switching and logic value storage. Therefore, the logic conversion unit can adjust the on-off status of the fifth switch and the sixth switch in combination with the clock signal to realize the switching of the preamplifier access status.
[0045] It should be noted that the control steps of the sampling unit and the preamplifier unit and the specific implementation principles of noise elimination and reduction of preamplifier power consumption have been described in detail in the first embodiment, and will not be repeated in this embodiment.
[0046] Furthermore, due to the limitation of integrated circuit process level, the influence of capacitor size deviation and process deviation is inevitable in the production process, resulting in mismatch between the capacitors in the capacitor array, that is, capacitor mismatch. The existence of capacitor mismatch will make the weight no longer a binary relationship, resulting in deviation in the quantized digital code, bringing nonlinearity to the SAR ADC and degrading the accuracy of the SAR ADC. Figure 5 As shown, the prior art often uses digital calibration technology based on disturbance injection to calibrate the mismatch of DAC array capacitance. The principle of digital calibration technology based on disturbance injection is to inject two opposite analog quantities into the same input signal, generate errors after subtracting them in the digital domain, and converge the errors. Conventional calibration methods can work in both the foreground and background, but the rate is reduced to half of the original. After calibration, the capacitance weight value changes from the original integer value to a decimal. When implementing in RTL, it is necessary to make a trade-off in the number of decimal places based on the accuracy. The traditional injection method is to add an additional capacitor C to the sampling capacitor array. p According to the charge conservation law, the injected voltage value is V ref ·C p / (C p +C total ), but this additional capacitance causes the total number of capacitors in the array to become C p +C total , the weights do not meet the binary requirements, which in turn affects the conversion accuracy.
[0047] This embodiment performs disturbance injection by multiplexing capacitors in the first capacitor array through a logic conversion unit. Specifically, when a positive disturbance voltage is injected, the logic conversion unit controls one side of the first multiplexed capacitor in the first capacitor array to switch from the common mode voltage to the reference voltage, and controls one side of the second multiplexed capacitor in the first capacitor array to switch from the common mode voltage to the ground; when a negative disturbance voltage is injected, the logic conversion unit controls one side of the first multiplexed capacitor to switch from the common mode voltage to the ground, and controls one side of the second multiplexed capacitor to switch from the common mode voltage to the reference voltage; wherein the first multiplexed capacitor and the second multiplexed capacitor are capacitors with different unit capacitances, the other side of the first multiplexed capacitor is connected to the positive input terminal of the first operational amplifier, and the other side of the second multiplexed capacitor is connected to the inverting input terminal of the first operational amplifier. During the disturbance voltage injection stage, the states of other capacitors in the first capacitor array except the first multiplexed capacitor and the second multiplexed capacitor remain unchanged and remain connected to the common mode voltage. After the disturbance voltage is injected, the digital calibration unit can be used to calibrate the capacitance based on Figure 5 The calibration principle shown completes the error convergence of the output result of the analog-to-digital converter and realizes the output of digital results with higher accuracy.
[0048] When actually selecting the first multiplexed capacitor and the second multiplexed capacitor from the first capacitor array, the selection can be made in combination with the magnitude of the disturbance voltage to be injected and the unit capacitance value of the capacitor. Figure 6 The capacitor array shown in the figure has a power supply voltage of 1.8V. Through the algorithm-level simulation, the disturbance voltage to be injected is 0.01V. Therefore, the 4Cu of the high-order segment can be selected as one end for injection, and the 2Cu of the high-order segment can be injected at the other end (i.e. Figure 6 The two capacitors marked by dotted lines in the figure make the equivalent injected voltage value (4+2) / 512*0.9=0.01V, which is closer to 0.01V than the symmetrical capacitor injection at both ends. It should be noted that Figure 6 The capacitor array shown is only one implementation of the first capacitor array. When its segmentation mode, number of capacitors, and unit capacitance change, the first multiplexed capacitor and the second multiplexed capacitor selected in the first capacitor array should also change accordingly. The specific selection of two (or even more) capacitors for multiplexing needs to be determined in combination with the specific simulation injection results and capacitance conditions. This embodiment does not impose specific restrictions, as long as the injected voltage result meets the injection requirements.
[0049] This embodiment improves the specific structure and control method of the sampling unit in the SAR ADC, and uses the cooperation of the first capacitor array and the second capacitor array to achieve freezing of the time-varying noise voltage during the sampling process, and regards it as a fixed offset voltage of the pre-input in the quantization stage, and eliminates it based on the offset elimination technology, thereby eliminating the sampling thermal noise of the first capacitor array and the offset of the first operational amplifier, and reducing the sampling thermal noise of the second capacitor array, effectively reducing the KT / C noise size of the overall analog-to-digital converter, so that the value of the capacitor array is no longer affected by the KT / C noise, the effective area of the capacitor array and the DAC settling time are reduced, and the conversion speed and accuracy of the analog-to-digital converter are improved. At the same time, based on the reuse of capacitors in the first capacitor array, the injection of the disturbance voltage is completed to help digital calibration, solve the capacitor mismatch problem, and improve the conversion precision and accuracy of the ADC.
[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. A successive approximation analog-to-digital converter with noise cancellation, characterized in that At least: Sampling unit, preamplification unit and logic conversion unit; wherein, The sampling unit at least includes a first capacitor array, a first operational amplifier, and a second capacitor array, one side of the first capacitor array is connected to a differential input signal or a common signal through a first switch, the other side of the first capacitor array is connected to a differential input terminal of the first operational amplifier, the differential output terminal of the first operational amplifier is connected to one side of the second capacitor array, the other side of the second capacitor array is connected to an input terminal of the preamplifier unit, and the other side of the first capacitor array is also connected to a common mode signal through a second switch, and the other side of the second capacitor array is also connected to the common mode signal through a third switch; The preamplifier unit is used to enhance the amplitude of the signal output by the sampling unit; The logic conversion unit is used to perform successive logic conversion on the signal processed by the preamplifier unit, and adjust the common signal connected to the first capacitor array based on the comparison result until the converted digital signal is output.
2. The successive approximation analog-to-digital converter according to claim 1, characterized in that: The first operational amplifier is a dynamic operational amplifier.
3. The successive approximation analog-to-digital converter according to claim 2, characterized in that: The sampling unit further includes: a third capacitor array and a fourth switch, one side of the third capacitor array is connected to the differential output terminal of the first operational amplifier, the other side of the third capacitor array is connected to the common mode signal, and the fourth switch is a complementary switch of the third switch.
4. The successive approximation analog-to-digital converter according to any one of claims 1 to 3, characterized in that: The preamplifier unit at least includes: a second operational amplifier and a third operational amplifier connected in series, and a complementary fifth switch and a sixth switch, wherein the differential input terminal of the second operational amplifier is connected to the other side of the second capacitor array, and the differential output terminal of the third operational amplifier is connected to the logic conversion unit as the output terminal of the preamplifier unit; one end of the fifth switch is connected to the differential output terminal of the third operational amplifier, and the other end of the fifth switch is connected to the logic conversion unit; one end of the sixth switch is connected to the differential input terminal of the second operational amplifier, and the other end of the sixth switch is connected to the other end of the fifth switch.
5. The successive approximation analog-to-digital converter according to claim 4, characterized in that: The second operational amplifier and the third operational amplifier are static operational amplifiers.
6. A control method for a successive approximation analog-to-digital converter with noise cancellation according to any one of claims 1 to 5, characterized in that: At least includes: sampling stage and quantization stage; The sampling phase at least includes a first capacitor array sampling period and a second capacitor array sampling period, wherein in the first capacitor array sampling period, the logic conversion unit controls the first switch, the second switch and the third switch to be closed, so that the first capacitor array samples the differential input signal; in the second capacitor array sampling period, the logic conversion unit controls the first switch and the third switch to be closed, and the second switch to be disconnected, so that the voltage across the first capacitor array is frozen to Vin(t1)+V1, and the second capacitor array samples the amplified signal output by the first operational amplifier; wherein Vin(t1) is the input signal collected by the first capacitor array when the second switch is disconnected, and V1 is the sampling thermal noise of the first capacitor array; In the quantization stage, the logic conversion unit controls the first switch, the second switch and the third switch to be disconnected so that the voltage across the second capacitor array is frozen to A[Vin(t2)-Vin(t1)-V1-Vos1]+V2, and starts to perform successive logic conversion until the voltage on the other side of the second capacitor array is 0, and outputs the converted digital signal Dout=Vin(t2)+V2 / A, wherein Vin(t2) is the input signal collected by the first capacitor array when the third switch is disconnected, A is the amplification factor of the first operational amplifier, Vos1 is the offset voltage of the first operational amplifier, and V2 is the sampling thermal noise of the second capacitor array.
7. The control method according to claim 6, characterized in that: The quantization stage further includes: the logic conversion unit drives the first operational amplifier to reset and close the fourth switch.
8. The control method according to claim 6, characterized in that: The quantization stage also includes: During the first logic conversion, the Nth logic conversion, and the last logic conversion, the logic conversion unit controls the fifth switch to be opened and the sixth switch to be closed; During the process from the second logic conversion to the N-1th logic conversion, the logic conversion unit controls the fifth switch to be closed and the sixth switch to be open.
9. The control method according to claim 8, characterized in that: The value of N is calculated based on the values of the power supply voltage, reference voltage, and common-mode voltage of the successive approximation analog-to-digital converter.
10. The control method according to any one of claims 6 to 9, characterized in that: After the sampling stage, a disturbance voltage injection stage is also included; wherein, When a positive disturbance voltage is injected, the logic conversion unit controls one side of the first multiplexed capacitor in the first capacitor array to switch from the common mode voltage to the reference voltage, and controls one side of the second multiplexed capacitor in the first capacitor array to switch from the common mode voltage to the ground; when a negative disturbance voltage is injected, the logic conversion unit controls one side of the first multiplexed capacitor to switch from the common mode voltage to the ground, and controls one side of the second multiplexed capacitor to switch from the common mode voltage to the reference voltage; wherein the first multiplexed capacitor and the second multiplexed capacitor are capacitors with different unit capacitances, the other side of the first multiplexed capacitor is connected to the non-inverting input terminal of the first operational amplifier, and the other side of the second multiplexed capacitor is connected to the inverting input terminal of the first operational amplifier, and during the disturbance voltage injection stage, the states of other capacitors in the first capacitor array except the first multiplexed capacitor and the second multiplexed capacitor remain unchanged and remain connected to the common mode voltage.