Analog-digital conversion implementation method based on phase-locked loop

Abstract

The application discloses a kind of based on the realization method of analog-digital conversion of phase-locked loop, belong to CMOS integrated circuit technical field.The application utilizes the phase-locked loop increased in circuit, by reasonably adjusting input-output relationship, and correcting signal between voltage-controlled oscillator and phase-locked loop circuit, can guarantee the linearity of overall circuit in larger input range, with higher stability;At the same time, with the frequency divider in phase-locked loop, the pressure of subsequent counter is relieved, and a more digital circuit is obtained.The application can accurately determine the time when the output signal frequency reaches stability by checking the input signal voltage change of voltage-controlled oscillator in phase-locked loop.

Description

Technical Field

[0001] The invention belongs to the technical field of CMOS integrated circuits, and in particular relates to a method for realizing analog-to-digital conversion based on a phase-locked loop. Background Art

[0002] As CMOS process sizes continue to shrink, the voltage margin and voltage gain of analog circuits continue to decrease. Increasing the aspect ratio of MOS transistors or increasing the number of analog circuit stages to compensate for these losses will lead to a significant increase in circuit area and power consumption, making it difficult to optimize overall circuit performance. Digital circuits, however, offer significant advantages in the face of shrinking CMOS process sizes, thanks to their faster switching speeds, smaller area, and lower power consumption.

[0003] In the field of analog-to-digital converter (ADC) technology, many architectures require analog circuit modules, such as comparator circuits and digital-to-analog conversion circuits. Especially in the field of high-precision ADC, these analog circuits have high requirements. As the size of CMOS continues to decrease, these analog circuits need to be continuously iterated and the design difficulty is increasing. One solution is to reduce the number of analog circuit modules in the ADC. An ADC based on a voltage-controlled oscillator (VCO) is Figure 1 As shown, it uses a voltage-controlled oscillator (VCO) to convert the input signal's amplitude into frequency, and then uses a counter to convert the frequency into time. The time information is represented as digital binary code, thus achieving analog-to-digital conversion. Both the VCO and the counter can be constructed using simple digital modules. However, this structure presents several issues: the VCO output is connected to a large counter, which creates a heavy load and fluctuates over time. As a result, the VCO's output frequency is no longer a constant linearly related to the input signal amplitude, resulting in significant nonlinearity. Furthermore, the VCO's input and output typically have a narrow range of linear variations. When designing an analog-to-digital converter, only this linear range can be utilized, resulting in a limited input amplitude range. Furthermore, because the VCO's input is directly connected to the analog signal, it's difficult to determine when the VCO's output frequency reaches stability, complicating the subsequent design of the counter's control clock. Summary of the Invention

[0004] In view of the above problems, the present invention proposes a method for realizing analog-to-digital conversion based on a phase-locked loop.

[0005] The technical solutions of the present invention are as follows:

[0006] A method for implementing analog-digital conversion based on phase-locked loop, comprising the steps of:

[0007] 1) inputting an analog signal Analog Input into a sample-hold circuit module S / H, the amplitude of the analog signal Analog Input being αV, the output of the sample-hold circuit module S / H being connected to the input of a voltage-controlled oscillator VCO1, the output signal frequency of the voltage-controlled oscillator VCO1 being positively linearly related to the input signal amplitude, and outputting a fixed frequency signal;

[0008] 2) the output of the voltage-controlled oscillator VCO1 being connected to the output of a calibration cell Calibration Cell, and fixing the output signal frequency of the voltage-controlled oscillator VCO1 as βHz, β = K vco α, wherein K vco = 25MHz / V;

[0009] 3) the output of the calibration cell Calibration Cell being connected to the input of a phase-locked loop circuit module PLL, and using the phase-locked loop circuit module PLL to lock the output signal frequency βHz as β·γHz, γ being a constant value;

[0010] 4) the output of the phase-locked loop circuit module PLL being connected to the input of a counter module Counter, and the counter module Counter outputting a binary count δ in a unit time t as a digital output Digital Output.

[0011] Further, the range of αV is 0.5V to 2.5V.

[0012] Further, the input analog signal Analog Input is a sine waveform signal or a ramp analog signal.

[0013] Further, the phase-locked loop circuit module PLL comprises a frequency discriminator phase discriminator module PFD, a charge pump module CP, a low-pass filter module LPF, a voltage-controlled oscillator module VCO2 and a frequency divider module Divider, wherein the first input end of the frequency discriminator phase discriminator module PFD serves as the input end of the phase-locked loop circuit module PLL, the output end of the frequency discriminator phase discriminator module PFD is connected with the input end of the charge pump module CP, the output end of the charge pump module CP is connected with the input end of the low-pass filter module LPF, the output end of the low-pass filter module LPF is connected with the input end of the voltage-controlled oscillator module VCO2, the input end of the frequency divider module Divider is connected with the output end of the voltage-controlled oscillator module VCO2, the second input end of the frequency discriminator phase discriminator module PFD is connected with the output end of the frequency divider module Divider, and the output end of the frequency divider module Divider serves as the output end of the phase-locked loop circuit module PLL.

[0014] Further, the gamma value is the same as the frequency division number of the frequency divider Divider.

[0015] Further, the phase-locked loop module is a charge pump phase-locked loop or other type of phase-locked loop.

[0016] Further, the VCO2 uses the structure of a LOOP-VCO to generate a plurality of Phases with consistent frequency and different phases, then outputs one or more Phases to an equal number of counter modules Counter through the frequency divider module Divider, and finally accumulates the counting values of the one or more counter modules Counter in a unit time t to obtain the final counting output.

[0017] The technical effect of the present application is that:

[0018] Firstly, compared with the conventional analog-to-digital conversion method, the present application increases a phase-locked loop in the circuit, adjusts the input-output relationship reasonably, and corrects the signal between the voltage-controlled oscillator and the phase-locked loop circuit, so that the linearity of the overall circuit can be ensured in a larger input range, and higher stability is achieved.

[0019] Secondly, the existing analog-to-digital converter based on a voltage-controlled oscillator usually needs a large counter, and the present application relieves the pressure of the subsequent counter by means of the frequency divider in the phase-locked loop, so that a more digitalized circuit is obtained.

[0020] Thirdly, after the phase-locked loop is added in the circuit, the time when the output signal frequency reaches stability can be accurately judged by observing the input signal voltage change of the voltage-controlled oscillator in the phase-locked loop, and then the counter is controlled to start working; the resolution of the analog-to-digital conversion is theoretically only dependent on the clock frequency of the counter, and the higher the clock frequency, the higher the resolution, which is relatively easy to control and estimate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic diagram of an analog-to-digital converter based on a voltage-controlled oscillator in the prior art;

[0023] Figure 2 Schematic diagram of the analog-to-digital conversion structure based on a phase-locked loop of the present invention;

[0024] Figure 3 This is a waveform diagram of the digital signal Digital Output when a sinusoidal signal Analog Input with a 1.5V bias and 1V amplitude is input according to a specific embodiment of the present invention;

[0025] Figure 4 This is a waveform diagram of the digital signal Digital Output output when a sinusoidal signal AnalogInput with a 1.5V bias and 0.00005V amplitude is input according to a specific embodiment of the present invention;

[0026] Figure 5 This is a waveform diagram of the digital signal Digital Output when a ramp signal Analog Input with an amplitude range of 0.5V to 2.5V is input according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0027] The present invention will be further clearly and completely described below through specific embodiments in conjunction with the accompanying drawings.

[0028] The present invention is based on the phase-locked loop analog-to-digital conversion implementation method, such as Figure 2 As shown, the steps include:

[0029] 1) Inputting an analog signal Analog Input into a sample-and-hold circuit module S / H, where the amplitude of the analog signal Analog Input is αV, and αV is 0.5V to 2.5V. The output end of the sample-and-hold circuit module S / H is connected to the input end of a voltage-controlled oscillator VCO1. The output signal frequency of the voltage-controlled oscillator VCO1 has a positive linear relationship with the input signal amplitude, and outputs a fixed-frequency signal;

[0030] 2) The output of the voltage controlled oscillator VCO1 is connected to the output of the calibration cell, and the frequency of the output signal of the voltage controlled oscillator VCO1 is fixed to β Hz, β = K vco α, where K vco = 25 MHz / V;

[0031] 3) The output of the calibration cell is connected to the input of the phase-locked loop circuit module PLL, and the frequency of the output signal is locked to β·γ Hz by the phase-locked loop circuit module PLL, where γ is a constant value, such as γ = 10 in the embodiment;

[0032] 4) The output of the phase-locked loop circuit module PLL is connected to the input of the counter module Counter, and the counter module Counter outputs a unique binary count δ in a unit time t, which is the digital output DigitalOutput, where t can be understood as the period of a single conversion, and t is 0.1 ms in the embodiment.

[0033] The phase-locked loop circuit module PLL includes a phase-frequency detector module PFD, a charge pump module CP, a low-pass filter module LPF, a second voltage controlled oscillator module VCO2, and a frequency divider module Divider. The first input of the phase-frequency detector module PFD is the input of the phase-locked loop circuit module PLL, the input of the charge pump module CP is connected to the output of the phase-frequency detector module PFD, the input of the low-pass filter module LPF is connected to the output of the charge pump module CP, the input of the second voltage controlled oscillator module VCO2 is connected to the output of the low-pass filter module LPF, the input of the frequency divider module Divider is connected to the output of the second voltage controlled oscillator module VCO2, the frequency division number of the frequency divider Divider is γ, the second input of the phase-frequency detector module PFD is connected to the output of the frequency divider module Divider, and the output of the frequency divider module Divider is the output of the phase-locked loop circuit module PLL. If the VCO2 uses the structure of LOOP-VCO, a plurality of Phases with consistent frequency and different phases are generated, and then one or more Phases are output to an equal number of counter modules Counters through the frequency divider module Divider. Finally, the count values of the one or more counter modules Counters in a unit time t are all added to obtain the final count output.

[0034] Embodiment One

[0035] In order to facilitate understanding that the present application has a large input voltage amplitude range, in this embodiment, the direct current bias of the input sinusoidal analog signal Analog Input is 1.5V, and the amplitude is 0.5V. The sample and hold circuit S / H performs sample and hold operation on the input analog signal, and outputs a stepped signal. For each segment of the stepped signal output by the sample and hold circuit S / H, the holding time interval can be equivalent to a direct current input, Figure 3 For the input and output waveform diagram of the embodiment of the present application under the Simulink simulation environment when a sinusoidal signal with a bias of 1.5V and an amplitude of 1V is input, the upper waveform diagram is the output waveform of the sample and hold circuit S / H, and the lower waveform diagram is the output waveform of the counter Counter. The counting value at each peak position is the output digital code corresponding to the input analog signal at that time. When a sinusoidal signal with an amplitude range of 0.5V to 2.5V is input, 27 samples are performed on one period, and the output digital code basically restores the sinusoidal waveform. It can be seen that the overall amplitude range of the input sinusoidal analog signal Analog Input has a large input analog voltage amplitude: 0.5V to 2.5V. If the direct current bias of the input sinusoidal analog signal Analog Input is 1.5V, and the amplitude is 0.00005V, the overall amplitude range is 1.49995V to 1.50005V. The sample and hold circuit S / H performs sample and hold operation on the input analog signal, and outputs a stepped signal. In the holding time interval, it can be equivalent to a direct current input, Figure 4 For the input and output waveform diagram of the embodiment of the present application under the Simulink simulation environment when a sinusoidal signal with a bias of 1.5V and an amplitude of 1V is input, the upper waveform diagram is the output waveform of the sample and hold circuit S / H, and the lower waveform diagram is the output waveform of the counter Counter. The counting value at each peak position is the output digital code corresponding to the input analog signal at that time. When a sinusoidal signal with an amplitude range of 0.5V to 2.5V is input, 27 samples are performed on one period, and the output digital code basically restores the sinusoidal waveform. It can be seen that the overall amplitude range of the input sinusoidal analog signal Analog Input has a large input analog voltage amplitude: 0.5V to 2.5V. If the direct current bias of the input sinusoidal analog signal Analog Input is 1.5V, and the amplitude is 0.00005V, the overall amplitude range is 1.49995V to 1.50005V. The sample and hold circuit S / H performs sample and hold operation on the input analog signal, and outputs a stepped signal. In the holding time interval, it can be equivalent to a direct current input,

[0036] Embodiment two

[0037] A ramp analog signal Analog Input with an amplitude range of 0.5V to 2.5V is input. The sample and hold circuit S / H performs sample and hold operation on the input signal, and outputs a stepped signal. In the holding time interval, it can be equivalent to a direct current input, Figure 5For the input and output waveform graphs of the specific embodiment of the present application in the Simulink simulation environment, the slope signal has an amplitude range of 0.5V to 2.5V, the upper waveform graph is the output waveform of the sample and hold circuit S / H, and the lower waveform graph is the output waveform of the counter Counter, wherein the count value at each peak position is the output digital code corresponding to the input analog signal at the moment. It can be known that when the input analog signal amplitudes are 0.5V, 0.6V, 0.7V, 0.8V, 0.9V, 1.0V, 1.1V, 1.2V, 1.3V, 1.4V, 1.5V, 1.6V, 1.7V, 1.8V, 1.9V, 2.0V, 2.1V, 2.2V, 2.3V, 2.4V, and 2.5V, the output digital code of the phase-locked loop-based analog-to-digital converter (since the simulator records data to three digits after the decimal point, the latter part is omitted, and the fault tolerance is increased) is 1250, 1490, 1740, 1989, 2239, 2488, 2737, 2987, 3235, 3487, 3736, 3986, 4233, 4483, 4733, 4979, 5233, 5480, 5731, 5980, and 6229, respectively. The increment of each output digital code is 240, 250, 249, 250, 249, 249, 250, 248, 252, 249, 250, 247, 250, 250, 246, 254, 247, 251, 249, and 249, respectively. The results show that it has good linearity in the amplitude range of 0.5V to 2.5V.

[0038] Finally, it should be noted that the purpose of the disclosed embodiments is to help further understand the present application, but those skilled in the art can understand that various replacements and modifications are possible without departing from the spirit and scope of the present application and the appended claims, therefore, the present application should not be limited to the disclosed content, and the scope of protection of the present application is defined by the scope of the claims.

Claims

1. A method for implementing analog-to-digital conversion based on a phase-locked loop, comprising the steps of: 1) analog signal Analog Input is input into sample hold circuit module S / H, amplitude of analog signal Analog Input is V, output end of sample hold circuit module S / H is connected with input end of voltage controlled oscillator VCO1, output signal frequency of voltage controlled oscillator VCO1 is positive linear relation with input signal amplitude, and a fixed frequency signal is output; 2) the output of the voltage controlled oscillator VCOl is connected to the output of the calibration cell, the frequency of the output signal of the voltage controlled oscillator VCOl is fixed to 25 MHz = 25 MHz / V; 3) the output of the calibration cell is connected to the input of a phase-locked loop module PLL, which locks the frequency of the output signal to Hz Hz, a constant value; 4) the output of the phase-locked loop circuit module PLL is connected with the input of the counter module Counter, the counter module Counter outputs a binary count only corresponding to the unit time as the digital output Digital Output;​ wherein the phase-locked loop circuit module PLL comprises a phase-frequency detector module PFD, a charge pump module CP, a low-pass filter module LPF, a voltage-controlled oscillator module VCO2 and a frequency divider module Divider, wherein a first input terminal of the phase-frequency detector module PFD serves as an input terminal of the phase-locked loop circuit module PLL, an output terminal of the phase-frequency detector module PFD is connected with an input terminal of the charge pump module CP, an output terminal of the charge pump module CP is connected with an input terminal of the low-pass filter module LPF, an output terminal of the low-pass filter module LPF is connected with an input terminal of the voltage-controlled oscillator module VCO2, an input terminal of the frequency divider module Divider is connected with an output terminal of the voltage-controlled oscillator module VCO2, a second input terminal of the phase-frequency detector module PFD is connected with an output terminal of the frequency divider module Divider, and an output terminal of the frequency divider module Divider serves as an output terminal of the phase-locked loop circuit module PLL.

2. The phase-locked loop based analog-to-digital conversion implementation method of claim 1, wherein, The V ranges between 0.5V and 2.5V.

3. The phase-locked loop based analog-to-digital conversion implementation method of claim 1, wherein, The input analog signal Analog Input is a sine waveform signal or a ramp analog signal.

4. The method of claim 1, wherein the phase-locked loop-based analog-to-digital conversion implementation is characterized by, The The division numbers of the dividers Divider are the same.

5. The phase-locked loop based analog-to-digital conversion implementation method of claim 1, wherein, The phase-locked loop module is a charge pump phase-locked loop or other type of phase-locked loop.

6. The phase-locked loop based analog-to-digital conversion implementation method of claim 1, wherein, The VCO2 uses the structure of LOOP-VCO to generate multiple Phases with consistent frequency and different phase, and then outputs one or more Phases to an equal number of counter modules Counter through a frequency divider module Divider. Finally, the counting values of one or more counter modules Counter in a unit time are all accumulated to obtain the final counting output. The VCO2 uses the structure of LOOP-VCO to generate multiple Phases with consistent frequency and different phase, and then outputs one or more Phases to an equal number of counter modules Counter through a frequency divider module Divider. Finally, the counting values of one or more counter modules Counter in a unit time are all accumulated to obtain the final counting output.

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