Phase-locked loop circuit and image sensor
By using the binary search rule to adjust the digital code value in the phase-locked loop circuit, the problem of low calibration efficiency in traditional phase-locked loop circuits is solved, and fast frequency calibration is achieved.
Patent Information
- Application Number
- CN202520169594.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-23
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2035-01-23
AI Technical Summary
The calibration efficiency of the automatic frequency control circuit in traditional phase-locked loop circuits is low, requiring multiple bit-by-bit changes of the digital code value for frequency comparison, resulting in a long calibration time.
The digital code value is changed using a binary division rule. In calibration mode, the automatic frequency control circuit compares the frequency difference between the clock reference signal and the output signal of the phase-locked loop circuit. The value of the digital code value is adjusted according to the absolute value of the difference. The capacitance of the voltage-controlled oscillator is changed by a switching circuit to quickly adjust the frequency.
The calibration efficiency of the phase-locked loop circuit is improved, the calibration time is reduced, and the capacitor size is quickly changed by the binary search rule to make the output signal frequency close to the clock reference signal frequency.
Smart Images
Figure CN223942693U_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of image sensor technology, and particularly relates to a phase-locked loop circuit and an image sensor. Background Technology
[0002] Phase-locked loop (PLL) circuits are found in a variety of high-frequency applications, from simple clock cleanup circuits to local oscillators (LOs) used in high-performance radio communication links, as well as ultrafast switching frequency synthesizers in vector network analyzers (VNAs), image sensors, and more.
[0003] Phase-locked loop (PLL) circuits typically consist of a feedback loop comprised of a phase and frequency detector, a charge pump circuit, and a voltage-controlled oscillator (VCO). Compared to ring oscillators, inductor-capacitor VCOs offer better phase noise performance and are commonly used in jitter-sensitive circuits. Since the oscillation frequency range adjustable solely by the loop control voltage is relatively small, an automatic frequency control circuit is usually added to the PLL circuit to expand the oscillation frequency range and improve the frequency adjustment range.
[0004] The phase-locked loop (PLL) circuit with added automatic frequency control mainly includes a calibration phase and a fine-tuning phase after calibration. During the calibration phase, the automatic frequency control circuit compares the frequency of the PLL output signal with the frequency of the clock reference signal and outputs a digital code value. This changes the capacitance in the inductor-capacitor voltage-controlled oscillator (VCO) to make the output signal frequency close to the clock reference signal frequency. After calibration, the frequency and phase detector and charge pump circuit output an adjustment voltage and change the capacitance in the VCO, ultimately making the output signal frequency equal to the clock reference signal frequency.
[0005] The digital code value output by the automatic frequency control circuit is a binary value. When the frequency of the output signal differs greatly from the frequency of the clock reference signal, the automatic frequency control circuit changes the digital code value bit by bit, for example, changing it bit by bit in sequence according to 1000, 1001, 1010, 1100, 1101, and 1110. This requires multiple comparisons to complete the calibration, resulting in low calibration efficiency. Utility Model Content
[0006] The purpose of this invention is to provide a phase-locked loop circuit that aims to solve the problem of low calibration efficiency of the automatic frequency control circuit in traditional phase-locked loop circuits.
[0007] A first aspect of this utility model provides a phase-locked loop circuit, comprising:
[0008] A frequency and phase detector is configured to detect the frequencies of a clock reference signal and the output signal of the phase-locked loop circuit, and generate a control signal.
[0009] A charge pump circuit, connected to the frequency and phase detector, is configured to receive the control signal and charge / discharge it, and output a first voltage signal that changes in relation to the control signal.
[0010] A switching circuit, connected to the charge pump circuit and the reference voltage terminal, is configured to switch the output of the voltage reference signal of the reference voltage terminal by a first switching signal, and to switch the output of the first voltage signal by a second switching signal.
[0011] An inductor-capacitor voltage-controlled oscillator is connected to the switching circuit and the frequency and phase detector. The inductor-capacitor voltage-controlled oscillator is configured to adjust the size of its internal capacitor according to the corresponding signal in the received voltage reference signal, the first voltage signal and the digital code value, so as to adjust the frequency and phase of the output signal of the phase-locked loop circuit.
[0012] The automatic frequency control circuit, connected to both the switching circuit and the inductor-capacitor voltage-controlled oscillator, is configured as follows:
[0013] In calibration mode, the first switching signal is output, and the frequencies of the clock reference signal and the output signal of the phase-locked loop circuit are compared. When the absolute value of the difference between the frequency of the clock reference signal and the frequency of the output signal is greater than a preset difference, the corresponding digital code value is generated. When the absolute value of the difference is less than the preset difference, the second switching signal is switched and the digital code value is latched and output. The digital code value changes according to the binary search rule.
[0014] A second aspect of this invention provides an image sensor, including a phase-locked loop circuit as described above.
[0015] The beneficial effects of this utility model embodiment compared with the prior art are as follows: The above-mentioned phase-locked loop circuit includes a frequency and phase detector, a charge pump circuit, a switching circuit, an inductor-capacitor voltage-controlled oscillator, and an automatic frequency control circuit. In calibration mode, the automatic frequency control circuit controls the switching circuit to output a voltage reference signal to change the frequency of the output signal of the phase-locked loop circuit. The frequency of the output signal is compared with the clock reference signal, and the corresponding changing digital code value is output according to the comparison result. The digital code value changes according to the binary division rule, thereby quickly changing the capacitance and frequency of the inductor-capacitor voltage-controlled oscillator and improving the calibration efficiency. After calibration, the frequency and phase detector and the charge pump circuit output a changing first voltage signal, and change the capacitance of the inductor-capacitor voltage-controlled oscillator and the frequency of the output signal of the phase-locked loop circuit. Attached Figure Description
[0016] Figure 1 A schematic diagram of the first structure of the phase-locked loop circuit provided in this embodiment of the present invention;
[0017] Figure 2 This is a schematic diagram of a second structure of a phase-locked loop circuit provided in an embodiment of the present invention;
[0018] Figure 3 A schematic diagram of a third structure of a phase-locked loop circuit provided in an embodiment of this utility model;
[0019] Figure 4 A first circuit diagram of an inductor-capacitor voltage-controlled oscillator provided for an embodiment of this utility model;
[0020] Figure 5 A second circuit diagram of an inductor-capacitor voltage-controlled oscillator provided in an embodiment of this utility model;
[0021] Figure 6 A circuit diagram of a capacitor array provided in an embodiment of this utility model;
[0022] Figure 7 A schematic diagram of a first structure of the automatic frequency control circuit provided in an embodiment of this utility model;
[0023] Figure 8 A second structural schematic diagram of the automatic frequency control circuit provided in an embodiment of this utility model;
[0024] Figure 9 A schematic diagram of a third structure of the automatic frequency control circuit provided in an embodiment of this utility model;
[0025] Figure 10 This is a schematic diagram of the fourth structure of the automatic frequency control circuit provided in the embodiment of this utility model. Detailed Implementation
[0026] To make the technical problems, technical solutions, and beneficial effects of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the present utility model.
[0027] Furthermore, the terms "first" and "second" are configured for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, "a plurality of" means two or more, unless otherwise explicitly specified.
[0028] The first aspect of this utility model embodiment provides a phase-locked loop circuit, such as... Figure 1 As shown, in this embodiment, the phase-locked loop circuit includes:
[0029] The frequency and phase detector 10 is configured to detect the frequencies of the clock reference signal clk_ref and the output signal clk_o of the phase-locked loop circuit, and generate control signals.
[0030] The charge pump circuit 20, connected to the frequency and phase detector 10, is configured to receive control signals and charge and discharge, and output a first voltage signal Vout that changes in relation to the control signals.
[0031] The switching circuit 30, connected to the charge pump circuit 20 and the reference voltage terminal, is configured to switch the voltage reference signal vref_afc of the output reference voltage terminal by a first switching signal, and to switch the output first voltage signal Vout by a second switching signal.
[0032] The inductor-capacitor voltage-controlled oscillator 40 is connected to the switching circuit 30 and the frequency and phase detector 10. The inductor-capacitor voltage-controlled oscillator 40 is configured to adjust the size of the internal capacitor according to the corresponding signal in the received voltage reference signal vref_afc, the first voltage signal Vout and the digital code value C_ctl, so as to adjust the frequency and phase of the output signal clk_o of the phase-locked loop circuit.
[0033] Automatic frequency control circuit 50, connected to switching circuit 30 and inductor-capacitor voltage-controlled oscillator 40 respectively, is configured as follows:
[0034] In calibration mode, a first switching signal is output, and the frequencies of the clock reference signal clk_ref and the output signal clk_o of the phase-locked loop circuit are compared. When the absolute value of the difference between the frequency of the clock reference signal clk_ref and the frequency of the output signal clk_o is greater than a preset difference, a digital code value C_ctl of the corresponding size is generated. When the absolute value of the difference is less than the preset difference, a second switching signal is output and the output digital code value C_ctl is latched. The digital code value C_ctl is a binary digital code value, and the digital code value C_ctl changes according to the binary division rule.
[0035] In this embodiment, the first input terminal of the inductor-capacitor voltage-controlled oscillator 40 is connected to the output terminal of the switching circuit 30, the second input terminal of the inductor-capacitor voltage-controlled oscillator 40 is connected to the second output terminal of the automatic frequency control circuit 50, and the control terminal of the switching circuit 30 is connected to the first output terminal of the automatic frequency control circuit 50.
[0036] The switching circuit 30 can select the output voltage reference signal vref_afc or the first voltage signal Vout output by the charge pump circuit 20 under the control of the switching signal loop_ctl. The switching signal loop_ctl may include a first switching signal and a second switching signal, and the first switching signal and the second switching signal may be opposite level signals.
[0037] The frequency of the output signal of the inductor-capacitor voltage-controlled oscillator 40 is: Where f is the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40, i.e., the frequency of the output signal clk_o of the phase-locked loop circuit; L is the inductance value inside the inductor-capacitor voltage-controlled oscillator 40, which can be a fixed value or a variable. In this embodiment, the inductance value is a fixed value; C is the capacitance value inside the inductor-capacitor voltage-controlled oscillator 40, which is a variable and is related to the magnitude of the second voltage signal Vctrl input to the first input terminal and the digital code value C_ctl input to the first input terminal. When the second voltage signal Vctrl changes, the capacitance value inside the inductor-capacitor voltage-controlled oscillator 40 changes positively or negatively, and correspondingly, the frequency of the output signal clk_o changes negatively with the capacitance. When the digital code value C_ctl changes, the capacitance value inside the inductor-capacitor voltage-controlled oscillator 40 changes positively or negatively, and correspondingly, the frequency of the output signal clk_o changes negatively with the capacitance. Therefore, the frequency of the phase-locked loop circuit can be changed by adjusting the capacitance value.
[0038] The phase-locked loop circuit operates in calibration mode and fine-tuning mode after calibration mode. In calibration mode, the automatic frequency control circuit 50 first outputs a first switching signal. The first switching signal controls the switching circuit 30 to switch between the reference voltage terminal and the first input terminal of the inductor-capacitor voltage-controlled oscillator 40. The second voltage signal Vctrl input to the inductor-capacitor voltage-controlled oscillator 40 is the voltage reference signal vref_afc. The voltage reference signal vref_afc first adjusts the capacitor inside the inductor-capacitor voltage-controlled oscillator to the reference capacitance value corresponding to the voltage reference signal vref_afc, and adjusts the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40 to the reference frequency. Then, the adjusted reference frequency is compared with the clock reference signal clk_ref. By comparing the magnitudes of the two frequencies, the magnitude of the output digital code value C_ctl is changed.
[0039] The digital code value C_ctl is a multi-bit binary value, such as a four-bit binary value 1100. The digital code value C_ctl changes positively or negatively with the equivalent capacitance of the automatic frequency control circuit 50. The equivalent capacitance of the automatic frequency control circuit 50 changes negatively with the frequency of the output signal clk_o.
[0040] That is, the larger the digital code value C_ctl, the larger the equivalent capacitance of the automatic frequency control circuit 50 can be, and the lower the frequency of the output signal clk_o; conversely, the smaller the digital code value C_ctl, the smaller the equivalent capacitance of the automatic frequency control circuit 50 can be, and the higher the frequency of the output signal clk_o; or, the larger the digital code value C_ctl, the smaller the equivalent capacitance of the automatic frequency control circuit 50 can be, and the higher the frequency of the output signal clk_o; conversely, the smaller the digital code value C_ctl, the larger the equivalent capacitance of the automatic frequency control circuit 50 can be, and the lower the frequency of the output signal clk_o.
[0041] For each single bit change in the digital code value C_ctl, the equivalent capacitance of the automatic frequency control circuit 50 can change according to the same capacitance difference or different capacitance differences. Correspondingly, the frequency of the output signal clk_o can change according to the same frequency difference or different frequency differences.
[0042] Taking the case where the equivalent capacitance of the automatic frequency control circuit 50 changes by the same capacitance difference and the frequency of the output signal clk_o changes by the same frequency difference when a single bit changes, and the larger the digital code value C_ctl is, the smaller the capacitance of the equivalent capacitance is, and the larger the frequency of the output signal clk_o is, as an example.
[0043] In the calibration mode, the original automatic frequency control circuit 50 uses a unit bit change in the digital code value C_ctl. When the frequency of the output signal clk_o is less than the frequency of the clock reference signal clk_ref and the difference is large, the automatic frequency control circuit 50 changes bit by bit, sequentially according to 1000, 1001, 1010, 1100, 1101, and 1110. When the digital code value C_ctl is between 1000 and 1101, the absolute value of the difference between the frequency of the clock reference signal clk_ref and the frequency of the output signal clk_o is greater than a preset difference. And when the digital code value C_ctl is 1110, the absolute value of the difference between the frequency of the clock reference signal clk_ref and the frequency of the output signal clk_o is less than a preset difference. The calibration is then complete. The automatic frequency control circuit 50 latches the digital code value C_ctl of the previous moment of 1101 and switches the output to the second switching signal.
[0044] When using bit-by-bit changes to the digital code value C_ctl, the automatic frequency control circuit 50 needs to change the digital code value C_ctl multiple times and perform frequency comparisons multiple times, resulting in low calibration efficiency.
[0045] In this embodiment, the automatic frequency control circuit 50 changes the value of the digital code C_ctl according to the binary division rule. For example, when the frequency of the output signal clk_o is less than the frequency of the clock reference signal clk_ref and the difference is large, the output is 1000 and 1100 respectively. When the digital code value C_ctl is 1100, and the frequency of the output signal clk_o is still less than the frequency of the clock reference signal clk_ref, the output of the digital code value C_ctl of 1110 is continued according to the binary division rule. When the digital code value C_ctl is 1110, and the frequency of the output signal clk_o is greater than the frequency of the clock reference signal clk_ref, the output of the digital code value C_ctl of 1101 is selected according to the binary division rule. When the frequency of the output signal clk_o is less than the frequency of the clock reference signal clk_ref, the calibration is completed, the automatic frequency control circuit 50 latches the output of the digital code value C_ctl of 1101, and switches the output of the second switching signal.
[0046] The difference can be positive or negative. The automatic frequency control circuit 50 compares the absolute value of the difference with the preset difference and adjusts the direction of change of the digital code value C_ctl. For example, when the frequency of the output signal clk_o is detected to be less than the frequency of the clock reference signal clk_ref and the difference is large, the difference is negative. In this case, the automatic frequency control circuit 50 gradually increases the digital code value C_ctl according to the binary division method, thereby gradually increasing the frequency of the output signal clk_o. Alternatively, when the frequency of the output signal clk_o is detected to be greater than the frequency of the clock reference signal clk_ref and the difference is large, the difference is positive. In this case, the automatic frequency control circuit 50 gradually decreases the digital code value C_ctl according to the binary division method, thereby gradually decreasing the frequency of the output signal clk_o, until the absolute value of the difference signal is less than the preset difference.
[0047] Alternatively, when the frequency of the output signal clk_o is detected to be less than the frequency of the clock reference signal clk_ref, and the difference is large, the difference is negative. In this case, the automatic frequency control circuit 50 gradually decreases the digital code value C_ctl according to the binary division method, thereby gradually increasing the frequency of the output signal clk_o. Or, when the frequency of the output signal clk_o is detected to be greater than the frequency of the clock reference signal clk_ref, and the difference is large, the difference is positive. In this case, the automatic frequency control circuit 50 gradually increases the digital code value C_ctl according to the binary division method, thereby gradually decreasing the frequency of the output signal clk_o, until the absolute value of the difference signal is less than the preset difference value.
[0048] As can be seen from the above analysis, if the digital code value C_ctl needs to change from 1000 to 1101, the original automatic frequency control circuit 50 needs to perform seven counting comparisons. However, by adopting the binary search rule, the digital code value C_ctl only needs four counting comparisons to complete the calculation, thus improving the calibration efficiency.
[0049] When the switching circuit 30 receives the second switching signal, it switches the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40. At the same time, in the fine-tuning mode after the calibration mode, the frequency and phase detector 10 further compares the frequency of the output signal clk_o with the frequency of the clock reference signal clk_ref, and outputs a changing control signal to the charge pump circuit 20. The charge pump circuit 20 charges or discharges, thereby outputting a changing first voltage signal Vout.
[0050] The frequency and phase detector 10 compares the rising edge of the output signal clk_o with the rising edge of the clock reference signal clk_ref, and obtains the first control signal and the second control signal based on the comparison of their frequency and phase difference. Specifically, in the phase-locked loop circuit, if the clock reference signal clk_ref has a rising edge but the output signal clk_o does not, the first control signal is high and the second control signal is low. If both the clock reference signal clk_ref and the output signal clk_o have a rising edge, the frequency and phase detector 10 simultaneously outputs the first and second control signals at low levels. If the clock reference signal clk_ref does not have a rising edge but the output signal clk_o has a rising edge, the first control signal is low and the second control signal is high.
[0051] The charge pump circuit 20 charges and discharges according to the high and low levels of the first control signal and the second control signal. When the first control signal is high and the second control signal is low, the charge pump circuit 20 charges, and the output first voltage signal Vout increases. When the first control signal is low and the second control signal is high, the charge pump circuit 20 discharges, and the output first voltage signal Vout decreases. When the first control signal and the second control signal are both high or low, the charge pump circuit 20 charges and discharges simultaneously, or is simultaneously cut off from charging and discharging. At this time, the charge pump circuit 20 outputs a constant first voltage signal Vout, which can be zero voltage or a preset voltage.
[0052] When the frequency of the output signal clk_o does not reach the frequency of the clock reference signal clk_ref, the first voltage signal Vout changes. Correspondingly, the capacitance of the inductor-capacitor voltage-controlled oscillator 40 changes, and the frequency of the output signal clk_o changes and gradually approaches the frequency of the clock reference signal clk_ref until the frequencies of the two are the same. At this time, the first control signal and the second control signal are at the same level, the frequency and phase detector 10 is reset, and the frequency discrimination and phase-locked loop operation is completed. At this time, the capacitance value of the inductor-capacitor voltage-controlled oscillator 40 is stable at the preset capacitance value.
[0053] Among them, the frequency and phase detector 10 can be composed of D flip-flops, logic gates and other structures, and the charge pump circuit 20 can be composed of current sources, controllable switches and energy storage elements.
[0054] The switching circuit 30 can be a corresponding switching switch, multi-channel selector, etc.; the inductor-capacitor voltage-controlled oscillator 40 can be an inductor, capacitor and corresponding oscillation circuit; and the automatic frequency control circuit 50 can be a corresponding comparator circuit, logic circuit, etc.
[0055] like Figure 2 As shown, in an optional embodiment, the switching circuit 30 includes a first switch S1 and a second switch S2;
[0056] The first terminal of the first switch S1 is connected to the reference voltage terminal. The second terminals of the first switch S1 and the second terminals of the second switch S2 are connected to the first input terminal of the inductor-capacitor voltage-controlled oscillator 40. The first terminal of the second switch S2 is connected to the output terminal of the charge pump circuit 20. The control terminals of the first switch S1 and the second switch S2 are connected to the first output terminal of the automatic frequency control circuit 50.
[0057] In this embodiment, in calibration mode, the automatic frequency control circuit 50 first outputs a first switching signal, the first switch S1 is turned on, the second switch S2 is turned off, and the first switch S1 connects the reference voltage terminal and the first input terminal of the inductor-capacitor voltage-controlled oscillator 40.
[0058] After calibration, the automatic frequency control circuit switches to output a second switching signal, the first switch S1 is turned off, the second switch S2 is turned off, and the second switch S2 connects the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40.
[0059] The first switch S1 and the second switch S2 can be switching devices of opposite switch types. In an optional embodiment, the first switch S1 is an N-channel transistor and the second switch S2 is a P-channel transistor. When a high-level first switching signal is output, the first switch S1 is turned on and the second switch S2 is turned off. When a low-level second switching signal is output, the first switch S1 is turned off and the second switch S2 is turned on.
[0060] In another alternative embodiment, such as Figure 3 As shown, in order to increase the frequency of the loop output signal clk_o, the phase-locked loop circuit also includes:
[0061] Frequency divider 60 has its input terminal connected to the output terminal of inductor-capacitor voltage-controlled oscillator 40, and its output terminal connected to the input terminal of frequency and phase detector 10 and the input terminal of automatic frequency control circuit 50, respectively. Frequency divider 60 is configured to divide the output signal clk_o of inductor-capacitor voltage-controlled oscillator 40 and output the divided feedback signal clk_fb to frequency and phase detector 10 and automatic frequency control circuit 50.
[0062] In this embodiment, the automatic frequency control circuit 50 compares the frequency of the feedback signal clk_fb with the frequency of the clock reference signal clk_ref in calibration mode, and the frequency and phase detector 10 compares the frequency of the feedback signal clk_fb with the frequency of the clock reference signal clk_ref in fine-tuning mode. When the phase-locked loop circuit is locked, the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40 is equal to the frequency of the clock reference signal clk_ref after being divided by the frequency divider 60. Therefore, the phase-locked loop circuit achieves the function of multiplying the frequency by N times. The final frequency of the phase-locked loop circuit is determined by the division ratio of the frequency divider 60.
[0063] In an optional embodiment, the capacitor control logic corresponding to the digital code value C_ctl and the second voltage signal Vctrl is as follows: Figure 4 As shown, the inductor-capacitor voltage-controlled oscillator 40 includes an inductor L1, an adjustable capacitor unit 41, a capacitor array 42, a first switch M1, a second switch M2, and a third switch M3.
[0064] Inductor L1, adjustable capacitor unit 41, and capacitor array 42 are connected in parallel between the first output terminal out_p and the second output terminal out_n of inductor-capacitor voltage-controlled oscillator 40. The first terminal of the first switch M1, the control terminal of the second switch M2, and the first output terminal out_p of the inductor-capacitor voltage-controlled oscillator 40 are connected. The first terminal of the second switch M2, the control terminal of the first switch M1, and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40 are connected. The second terminal of the first switch M1, the second terminal of the second switch M2, and the first terminal of the third switch M3 are connected. The second terminal of the third switch M3 is grounded. The control terminal of the third switch M3 is used to receive the reference voltage Vbias. The control terminal of the adjustable capacitor unit 41 constitutes the first input terminal of the inductor-capacitor voltage-controlled oscillator 40. The control terminal of the capacitor array 42 constitutes the second input terminal of the inductor-capacitor voltage-controlled oscillator 40.
[0065] The adjustable capacitor unit 41 is configured to switch the output capacitor of different sizes according to the voltage reference signal vref_afc or the first voltage signal Vout;
[0066] Capacitor array 42, such as Figure 6 As shown, a capacitor array 42 includes multiple capacitor units 421 with preset capacitance values, and is configured to switch different numbers of capacitor units 421 connected between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40 according to the digital code value C_ctl.
[0067] In this embodiment, the adjustable capacitor unit 41 and the capacitor array 42 are connected in parallel to form an equivalent capacitor unit 421. The equivalent capacitor unit 421, the inductor, and multiple switching transistors form an LC oscillator, the oscillation frequency of which is determined by the inductance of the inductor L1 and the capacitance of the equivalent capacitor unit 421.
[0068] In calibration mode, the adjustable capacitor unit 41 receives the voltage reference signal vref_afc and adjusts it to the first capacitance value corresponding to the voltage reference signal vref_afc, thereby switching the frequency of the output signal clk_o of the inductor-capacitor voltage-controlled oscillator 40 to the first frequency.
[0069] The automatic frequency control circuit 50 compares the frequency of the output signal clk_o with the frequency of the clock reference signal clk_ref, and outputs the changing digital code value C_ctl to the inductor-capacitor voltage-controlled oscillator 40 according to the binary search rule. When the digital code value C_ctl changes, different capacitor units 421 in the capacitor array 42 can be connected in series and parallel to the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40. For example, assuming there are four capacitor units 421 connected in parallel, each capacitor unit 421 has a preset capacitance value, and the capacitance values of each capacitor unit 421 can be equal or unequal. When the digital code value C_ctl of 1000 is received, the first capacitor unit 421 is turned on and connected to the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40, while the second to fourth capacitor units 421 are turned off. At this time, the output capacitance value of the capacitor array 42 is the first preset capacitance value corresponding to the first capacitor. Alternatively, when the digital code value C_ctl of 1001 is received, the first capacitor unit 421 and the fourth capacitor unit 421 are turned on and connected in parallel between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40, while the second capacitor unit 421 and the third capacitor unit 421 are turned off. At this time, the output capacitance value of the capacitor array 42 is the equivalent capacitance value of the parallel connection of the first preset capacitance value corresponding to the first capacitor unit 421 and the fourth preset capacitance value corresponding to the fourth capacitor unit 421. By changing the digital code value C_ctl, the equivalent capacitance value of the capacitor array 42 can be changed, thereby changing the capacitance value of the equivalent capacitor unit 421 and the oscillation frequency of the inductor-capacitor voltage-controlled oscillator 40, that is, changing the frequency of the output signal clk_o of the phase-locked loop circuit until it approaches the frequency of the clock reference signal clk_ref.
[0070] Then, after the calibration mode ends, the capacitor array 42 maintains the current capacitance value, the adjustable capacitor unit 41 receives the first voltage signal Vout output by the charge pump circuit 20, and changes the internal capacitance to the second capacitance value according to the first voltage signal Vout. Under the loop control of the frequency and phase detector 10, the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40, the first voltage signal Vout gradually approaches the preset voltage, thereby adjusting the frequency of the output signal clk_o to be equal to the frequency of the clock reference signal clk_ref.
[0071] The adjustable capacitor unit 41 can be composed of multiple switching devices and multiple capacitor units 421, or it can be an adjustable capacitor, such as... Figure 5 As shown, in an optional embodiment, the adjustable capacitor unit 41 includes a first capacitor C1, a first adjustable capacitor CX1, a second adjustable capacitor CX2, and a second capacitor C2 connected in series between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40.
[0072] The control terminals of the first adjustable capacitor CX1 and the second adjustable capacitor CX2 are used to receive the voltage reference signal vref_afc or the first voltage signal Vout.
[0073] In this embodiment, the capacitance value of the adjustable capacitor unit 41 is equal to the series equivalent capacitance value of the first capacitor C1, the second capacitor C2, the first adjustable capacitor CX1, and the second adjustable capacitor CX2. When the first adjustable capacitor CX1 and the second adjustable capacitor CX2 receive voltage reference signals vref_afc or the first voltage signal Vout of different magnitudes, their capacitance values change accordingly, thereby changing the series equivalent capacitance value.
[0074] In practical circuit applications, adjustable capacitors can be classified into surface-mount adjustable capacitors and through-hole adjustable capacitors according to their packaging method, and into ceramic adjustable capacitors, PVC adjustable capacitors, and air adjustable capacitors according to their manufacturing materials.
[0075] The capacitor units 421 in the capacitor array 42 can be connected in series and parallel, and the capacitor units 421 can adopt corresponding selection switches and capacitors. In an optional embodiment, such as... Figure 6 As shown, the capacitor array 42 includes multiple capacitor units 421 connected in parallel between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40;
[0076] Each capacitor unit 421 includes a third capacitor C3, a fourth capacitor C4, a fourth switch M4, a fifth switch M5, and a sixth switch M6;
[0077] The first terminal of the third capacitor C3 is connected to the first output terminal of the inductor-capacitor voltage-controlled oscillator 40. The second terminal of the third capacitor C3, the first terminal of the fourth switch M4, and the fifth switch M5 are connected. The second terminal of the fourth switch M4, the first terminal of the fourth capacitor C4, and the first terminal of the sixth switch M6 are connected. The second terminal of the fourth capacitor C4 is connected to the second output terminal of the inductor-capacitor voltage-controlled oscillator 40. The control terminal of the fourth switch M4 is used to receive one bit of the digital signal in the digital code value C_ctl. The second terminals of the fifth switch M5 and the sixth switch M6 are grounded. The control terminals of the fifth switch M5 and the sixth switch M6 are connected and receive a digital signal with an opposite level to the control terminal of the fourth switch M4.
[0078] In this embodiment, the maximum capacitance of each capacitor unit 421 is the total capacitance of the third capacitor C3 and the fourth capacitor C4. The capacitance of the third capacitor C3 in each capacitor unit 421 may be equal or unequal, and the capacitance of the fourth capacitor C4 in each capacitor unit 421 may be equal or unequal.
[0079] Assuming the array comprises four parallel capacitor units 421, when a digital code value C_ctl of 1000 is received, the fourth switch M4 of the first capacitor unit 421 is turned on, and the fifth switch M5 and the sixth switch M6 of the first capacitor unit 421 are turned off. The third capacitor C3 and the fourth capacitor C4 of the first capacitor unit 421 are connected in series and then in parallel between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40. The fourth switch M4 of the second to fourth capacitor units 421 is turned off, and the fifth switch M5 and the sixth switch M6 of the second to fourth capacitor units 421 are turned on. The second to fourth capacitor units 421 have no equivalent capacitance output. At this time, the output capacitance value of the capacitor array 42 is the first preset capacitance value corresponding to the first capacitor unit 421.
[0080] Alternatively, when the digital code value C_ctl of 1001 is received, the fourth switch M4 of the first capacitor unit 421 and the fourth capacitor unit 421 is turned on, the fifth switch M5 and the sixth switch M6 of the first capacitor unit 421 and the fourth capacitor unit 421 are turned off, the third capacitor C3 and the fourth capacitor C4 of the first capacitor unit 421 and the fourth capacitor unit 421 are connected in series and then connected in parallel between the first output terminal out_p and the second output terminal out_n of the inductor-capacitor voltage-controlled oscillator 40, the fourth switch M4 of the second capacitor unit 421 and the third capacitor unit 421 is turned off, the fifth switch M5 and the sixth switch M6 of the second capacitor unit 421 and the third capacitor unit 421 are turned on, and the second capacitor unit 421 and the third capacitor unit 421 have no equivalent capacitance output. At this time, the output capacitance value of the capacitor array 42 is the first preset capacitance value corresponding to the first capacitor unit 421 and the fourth capacitor unit 421.
[0081] By changing the digital code value C_ctl, the number of capacitor units 421 connected in parallel can be changed, thereby changing the equivalent capacitance of the capacitor array 42 and the oscillation frequency of the inductor-capacitor voltage-controlled oscillator 40, that is, changing the frequency of the output signal clk_o of the phase-locked loop circuit until it approaches the frequency of the clock reference signal clk_ref.
[0082] The automatic frequency control circuit 50 can employ corresponding digital circuits, logic circuits, etc., as shown in an optional embodiment, such as... Figure 7 As shown, the automatic frequency control circuit includes:
[0083] The first counter 51 is configured to periodically count the number of pulses of the clock reference signal clk_ref within a preset time period and output the first count value cnt_ref;
[0084] The second counter 52 is configured to periodically count the number of pulses of the output signal clk_o of the phase-locked loop circuit within a preset time, and output the second count value cnt_fb;
[0085] The difference circuit 53 is configured to compare the first count value cnt_ref and the second count value cnt_fb, and output the difference signal comp_out;
[0086] The bit adjustment circuit 54, connected to the difference circuit 53, the switching circuit 30, and the inductor-capacitor voltage-controlled oscillator 40, is configured to output a first switching signal in calibration mode, output a changing digital code value C_ctl when the absolute value of the difference signal comp_out is greater than a preset difference, and switch to output a second switching signal and latch the output digital code value C_ctl when the absolute value of the difference signal comp_out is less than a preset difference, wherein the digital code value C_ctl changes according to the binary search rule.
[0087] In this embodiment, under the initial calibration state, the bit adjustment circuit 54 outputs a first switching signal to the switching circuit 30. The switching circuit 30 outputs a voltage reference signal vref_afc to the inductor-capacitor voltage-controlled oscillator 40 and changes the frequency of the output signal clk_o. The first counter 51 performs periodic pulse counting on the clock reference signal clk_ref, and the second counter 52 performs periodic pulse counting on the output signal clk_o. The higher the frequency of the output signal clk_o, the more pulses per unit time. The difference circuit 53 compares the difference between the two pulse counts and obtains the difference signal comp_out.
[0088] In calibration mode, the bit adjustment circuit 54 adjusts the output of the digital code value C_ctl according to the magnitude of the difference signal comp_out. When the difference between the first count value cnt_ref and the second count value cnt_fb is large, that is, when the absolute value of the difference signal comp_out is greater than the preset difference, the bit adjustment circuit 54 outputs the changing digital code value C_ctl according to the binary division rule. When the frequency of the output signal clk_o is close to the frequency of the clock reference signal clk_ref, and the second count value cnt_fb is close to the first count value cnt_ref, the absolute value of the difference signal comp_out is less than the preset difference. At this time, the calibration mode ends, and the bit adjustment circuit 54 selects to latch and output the digital code value C_ctl of the previous moment. Simultaneously, the second switching signal is switched out, and the switching circuit 30 is connected to the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40. The frequency and phase detector 10, the charge pump circuit 20 and the inductor-capacitor voltage-controlled oscillator 40 complete the subsequent frequency adjustment work until the frequency of the output signal clk_o reaches the frequency of the clock reference signal clk_ref, and the bit adjustment circuit 54 cuts off the output digital code value C_ctl. The digital code value C_ctl can be latched by the latch circuit (not shown in the figure) and output to the inductor-capacitor voltage-controlled oscillator 40.
[0089] The difference circuit 53 can employ a subtractor, flip-flop, or similar structure to adjust the output of the digital code value C_ctl based on the difference. In an optional embodiment, such as... Figure 10 As shown, the difference circuit 53 includes a subtractor 531, which is configured to perform a subtraction operation on the first count value cnt_ref and the second count value cnt_fb, and output a difference signal comp_out. The difference signal comp_out can be positive or negative. The bit adjustment circuit 54 compares the absolute value of the difference signal comp_out with a preset difference value and adjusts the direction of change of the digital code value C_ctl. For example, when it is detected that the frequency of the output signal clk_o is less than the frequency of the clock reference signal clk_ref, and the difference is large, the difference signal comp_out... When mp_out is negative, the bit adjustment circuit 54 gradually increases the digital code value C_ctl according to the binary division method, thereby gradually increasing the frequency of the output signal clk_o. Alternatively, when the frequency of the output signal clk_o is detected to be greater than the frequency of the clock reference signal clk_ref and the difference is large, the difference signal comp_out is positive. At this time, the bit adjustment circuit 54 gradually decreases the digital code value C_ctl according to the binary division method, thereby gradually decreasing the frequency of the output signal clk_o until the absolute value of the difference signal comp_out is less than the preset difference, and the calibration work ends.
[0090] The bit adjustment circuit 54 can adopt a corresponding digital control logic circuit, which may include a corresponding digital circuit, analog-to-digital conversion circuit, and digital-to-analog conversion circuit, etc.
[0091] Furthermore, since the bit adjustment circuit 54 ultimately takes the value of the preceding digital code value C_ctl, its adjusted frequency may be closer to the clock reference signal clk_ref or further away from it compared to the adjusted frequency corresponding to the following digital code value C_ctl. Therefore, it is impossible to determine which digital code value C_ctl has a better adjustment effect, resulting in poor calibration accuracy. To improve calibration accuracy, in an optional embodiment, the automatic frequency control circuit 50 further includes:
[0092] Comparison circuit 55 is connected to difference circuit 53 and bit adjustment circuit 54. Comparison circuit 55 is configured to compare the absolute values of two difference signals comp_out output by difference circuit 53 in two preset time intervals and output a comparison signal.
[0093] The bit adjustment circuit 54 is also configured to determine the absolute value of the difference signal comp_out with the minimum value based on the comparison signal, and output the target digital code value C_ctl, which is the digital code value C_ctl corresponding to the difference signal comp_out with the minimum absolute value.
[0094] In this embodiment, the difference signal comp_out is used to compare the size of two count values, and the comparison signal is output to the bit adjustment circuit 54. The bit adjustment circuit 54 outputs the corresponding digital code value C_ctl according to the size of the comparison signal and the comparison result with the difference signal comp_out using the binary search method.
[0095] Simultaneously, the comparator circuit 55 compares the absolute values of two adjacent difference signals comp_out and outputs a comparison signal. The bit adjustment circuit 54 selects and locks the corresponding digital code value C_ctl according to the comparison signal. Among them, compared with the frequency of the output signal clk_o corresponding to other digital code values C_ctl, the frequency of the adjusted output signal clk_o corresponding to the final output digital code value C_ctl is closer to the frequency of the reference clock signal.
[0096] For example, assuming the output digital code value C_ctl is 1000, the frequency of the output signal clk_o is f1, and the corresponding count value is count1. Then, when the output digital code value C_ctl is 1100, the frequency of the output signal clk_o is f2, and the count value is count2. When the output digital code value C_ctl is 1101, the frequency of the output signal clk_o is f3, and the count value is count3. Finally, when the output digital code value C_ctl is 1110, the frequency of the output signal clk_o is f4, and the count value is count4.
[0097] Assuming the clock reference signal clk_ref has a frequency of f0 and a count value of count0, correspondingly, when the digital code value C_ctl is 1000, the first difference signal comp_out is count1-count0, the second difference signal comp_out is count2-count0, the third difference signal comp_out is count3-count0, and the fourth difference signal comp_out is count4-count0.
[0098] The comparator circuit 55 compares the adjacent difference signals comp_out. When the absolute value of the third difference signal comp_out is the smallest, it indicates that the frequency of the output signal clk_o after the digital code value C_ctl of 1101 is closer to the frequency of the clock reference signal clk_ref. Then, after calibration, the output digital code value C_ctl of 1101 is locked. Alternatively, when the absolute value of the fourth difference signal comp_out is the smallest, it indicates that the frequency of the output signal clk_o after the digital code value C_ctl of 1110 is closer to the frequency of the clock reference signal clk_ref. Then, after calibration, the output digital code value C_ctl of 1110 is locked. This improves the adjustment efficiency when switching to the frequency and phase detector 10 and the charge pump circuit 20 for frequency adjustment.
[0099] For example, assuming the clock reference signal clk_ref has a frequency of 10 and a count value of 10, when the output digital code value C_ctl is 1000, the output signal clk_o has a frequency of 53Hz, a count value of 53, and the first difference signal comp_out is 43. Then, when the output digital code value C_ctl is 1100, the output signal clk_o has a frequency of 30Hz, a count value of 30, and the second difference signal comp_out is 20. When the output digital code value C_ctl is 1101, the output signal clk_o has a frequency of 18Hz, a count value of 18, and the third difference signal comp_out is 8. When the output digital code value C_ctl is 1110, the output signal clk_o has a frequency of 8Hz, a count value of 8, and the fourth difference signal comp_out is -2. Therefore, it can be seen that when the digital code value C_ctl is 1110, the frequency of the output signal clk_o is closer to the frequency of the clock reference signal clk_ref. At this time, the digital code value C_ctl with an output of 1110 can be locked to the inductor-capacitor voltage-controlled oscillator, and the calibration can be ended to improve the calibration accuracy.
[0100] The comparator circuit 55 is used to compare the absolute values of the two difference signals comp_out. To achieve this comparison of absolute values, in an optional real-time example, such as... Figure 10 As shown, the comparator circuit 55 includes:
[0101] The memory 551 is configured to store and output the difference signal comp_out output at the previous preset time.
[0102] The absolute value comparator 552, connected to the difference circuit 53, the memory 551, and the bit adjustment circuit 54, is configured to compare the absolute value of the difference signal comp_out between two preset time intervals with a reference value, and output the comparison signal with the smallest absolute value to the bit adjustment circuit 54. The reference value is the value of the pulse change generated by the inductor-capacitor voltage-controlled oscillator when the bit adjustment circuit 54 changes the digital code value C_ctl by one bit.
[0103] In this embodiment, after the difference circuit 53 outputs a difference signal comp_out, the difference signal comp_out is simultaneously output to the bit adjustment circuit 54, the memory 551, and the absolute value comparator 552. The bit adjustment circuit 54 adjusts the output digital code value C_ctl according to the difference signal comp_out and adjusts the frequency of the output signal clk_o. Then, when the difference circuit 53 outputs another difference signal comp_out, the memory 551 outputs the previously received difference signal comp_out to the absolute value comparator 552. The absolute value comparator 552 compares the two adjacent difference signals comp_out with the reference value respectively and outputs the comparison signal with the smallest absolute value to the bit adjustment circuit 54. After receiving the comparison signal with the smallest absolute value, the bit adjustment circuit 54 determines the corresponding digital code value C_ctl and ends the calibration.
[0104] The reference value is the pulse change value generated by the inductor-capacitor voltage-controlled oscillator 40 when the digital code value C_ctl changes by one bit. As described above, in the capacitor array 42, the capacitance changes by the same amount for each bit change. Correspondingly, the frequency of the output signal clk_o and the second count value cnt_fb caused by each bit change change by the same difference. Therefore, the count value change caused by a 1-bit change can be determined as the reference value.
[0105] For example, the change in the second count value cnt_fb caused by a 1-bit change is defined as cnt_1bit. For the above digital code values C_ctl, which are 1000, 1100, 1101, and 1110, the corresponding count value changes are 5.3*cnt_1bit, 1.3*cnt_1bit, -0.7*cnt_1bit, and 0.3*cnt_1bit, respectively. Since the absolute value of 0.3*cnt_1bit is less than the absolute value of -0.7*cnt_1bit, it can be seen that the ideal output is closer to 1110 than 1101. Therefore, the optimal value can be selected for output from the final two digital code values C_ctl.
[0106] The absolute value comparator 552 can be made from corresponding digital circuits or logic circuits, and its specific structure is not limited.
[0107] Furthermore, after calibration, the automatic frequency control circuit 50 completes its work, and the frequency fine-tuning is performed by the frequency and phase detector 10, the charge pump circuit 20, and the inductor-capacitor voltage-controlled oscillator 40. Since the frequency adjustment range of the frequency and phase detector 10 and the charge pump circuit 20 is limited, when a large disturbance occurs, the frequency and phase detector 10 and the charge pump circuit 20 cannot achieve effective frequency adjustment, resulting in the phase-locked loop circuit being unable to achieve a reliable output of the target frequency.
[0108] Therefore, such as Figure 9 As shown, in an optional embodiment, the automatic frequency control circuit 50 further includes:
[0109] The judgment circuit 56 is connected to the difference circuit 53 and the bit adjustment circuit 54. The judgment circuit 56 is configured to compare the absolute value of the difference signal comp_out with the reference value, and output a first judgment signal when the absolute value of the difference signal comp_out is greater than the reference value, and output a second judgment signal when the absolute value of the difference signal comp_out is less than the reference value.
[0110] The bit adjustment circuit 54 is also configured to output a digital code value C_ctl by changing the value of the difference signal comp_out by one bit when the first judgment signal is received, and to latch the output of the digital code value C_ctl of the previous moment when the second judgment signal is received.
[0111] In this embodiment, after calibration, the system enters a fine-tuning mode, where the frequency and phase detector 10, charge pump circuit 20, and inductor-capacitor voltage-controlled oscillator 40 complete the subsequent frequency fine-tuning. At the same time, the automatic frequency control circuit 50 continues to perform counting and comparison.
[0112] When the difference signal comp_out is less than the reference value, it indicates that the frequency of the current output signal clk_o has not fluctuated significantly, that is, no external signal interference has been received. At this time, the judgment circuit 56 outputs the second judgment signal, and the output signal clk_o of the bit adjustment circuit 54 remains unchanged, that is, it continues to select the digital code value C_ctl of the previous moment to output.
[0113] When the absolute value of the difference signal comp_out is detected to be greater than the reference value, it indicates that the frequency of the current output signal clk_o is fluctuating significantly, and the phase-locked loop circuit is being interfered with by external signals. At this time, the judgment circuit 56 selects to output the first judgment signal. After receiving the first judgment signal, the bit adjustment circuit 54 adjusts the digital code value C_ctl. Meanwhile, since the frequency change caused by the interference signal is not very strong, when the binary method is used to adjust the output digital code value C_ctl, there is a problem of frequency overshoot. Therefore, the bit adjustment circuit 54 switches the output rule of the digital code value C_ctl and adjusts the output digital code value C_ctl bit by bit to avoid the problem of frequency overshoot. After the absolute value of the difference signal comp_out is less than the reference value, the current digital code value C_ctl is locked and output.
[0114] The judgment circuit 56 can adopt a comparator, subtractor 531, or other structures. In an optional embodiment, such as... Figure 10As shown, the judgment circuit 56 includes a code value comparator 561. The code value comparator 561 is configured to perform code value calculation on the absolute value of the difference signal comp_out and the reference value, and output a judgment signal of the corresponding size. When the absolute value of the difference signal comp_out is greater than the reference value, it outputs a first judgment signal, and when the absolute value of the difference signal comp_out is less than the reference value, it outputs a second judgment signal.
[0115] The code value comparator 561 can be made using corresponding digital circuits, logic circuits, etc.
[0116] The beneficial effects of this utility model embodiment compared with the prior art are as follows: The above-mentioned phase-locked loop circuit includes a frequency and phase detector 10, a charge pump circuit 20, a switching circuit 30, an inductor-capacitor voltage-controlled oscillator 40, and an automatic frequency control circuit 50. In calibration mode, the automatic frequency control circuit 50 controls the switching circuit 30 to output a voltage reference signal vref_afc to change the frequency of the output signal clk_o of the phase-locked loop circuit. The frequency of the output signal clk_o is compared with the clock reference signal clk_ref. Based on the comparison result, a corresponding change in digital code value C_ctl is output. The digital code value C_ctl changes according to the binary division rule, thereby quickly changing the capacitance and frequency of the inductor-capacitor voltage-controlled oscillator 40, improving calibration efficiency. After calibration, the frequency and phase detector 10 and the charge pump circuit 20 output a changed first voltage signal Vout, and change the capacitance of the inductor-capacitor voltage-controlled oscillator 40 and the frequency of the output signal of the phase-locked loop circuit.
[0117] A second aspect of this utility model provides an image sensor, which includes a phase-locked loop (PLL) circuit. The specific structure of the PLL circuit is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it possesses at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be elaborated upon here. The PLL circuit, as a high-speed clock generator, provides clock signals to the image sensor to meet the operating requirements of each module.
[0118] The above-described embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model, and should all be included within the protection scope of this utility model.
Claims
1. A phase-locked loop circuit, characterized in that, include: A frequency and phase detector is configured to detect the frequencies of a clock reference signal and the output signal of the phase-locked loop circuit, and generate a control signal. A charge pump circuit, connected to the frequency and phase detector, is configured to receive the control signal and charge / discharge it, and output a first voltage signal that changes in relation to the control signal. A switching circuit, connected to the charge pump circuit and the reference voltage terminal, is configured to switch the output of the voltage reference signal of the reference voltage terminal by a first switching signal, and to switch the output of the first voltage signal by a second switching signal. An inductor-capacitor voltage-controlled oscillator is connected to the switching circuit and the frequency and phase detector, respectively. The inductor-capacitor voltage-controlled oscillator is configured to adjust the size of its internal capacitor according to the corresponding signal in the received voltage reference signal, the first voltage signal and the digital code value, so as to adjust the frequency and phase of the output signal of the phase-locked loop circuit. The automatic frequency control circuit, connected to both the switching circuit and the inductor-capacitor voltage-controlled oscillator, is configured as follows: In calibration mode, the first switching signal is output, and the frequencies of the clock reference signal and the output signal of the phase-locked loop circuit are compared. When the absolute value of the difference between the frequency of the clock reference signal and the frequency of the output signal is greater than a preset difference, the corresponding digital code value is generated. When the absolute value of the difference is less than the preset difference, the second switching signal is switched and the digital code value is latched and output. The digital code value changes according to the binary search rule.
2. The phase-locked loop circuit as described in claim 1, characterized in that, The automatic frequency control circuit includes: The first counter is configured to periodically count the number of pulses of the clock reference signal within a preset time period and output a first count value; The second counter is configured to periodically count the number of pulses of the output signal of the phase-locked loop circuit within a preset time period and output a second count value. The difference circuit is configured to compare the first count value and the second count value and output a difference signal; A bit adjustment circuit, connected to the difference circuit, the switching circuit, and the inductor-capacitor voltage-controlled oscillator, is configured to output a first switching signal in calibration mode, output a changing digital code value when the absolute value of the difference signal is greater than a preset difference, and switch to output a second switching signal and latch the digital code value when the absolute value of the difference signal is less than the preset difference, wherein the digital code value changes according to a binary search rule.
3. The phase-locked loop circuit as described in claim 2, characterized in that, The difference circuit includes a subtractor configured to perform a subtraction operation on the first count value and the second count value, and output a difference signal.
4. The phase-locked loop circuit as described in claim 3, characterized in that, The automatic frequency control circuit also includes: A comparison circuit is connected to the difference circuit and the bit adjustment circuit. The comparison circuit is configured to compare the absolute values of two difference signals output by the difference circuit within two preset time periods and output a comparison signal. The bit adjustment circuit is further configured to determine the absolute value of the difference signal with the minimum value based on the comparison signal, and output a target digital code value, wherein the target digital code value is the digital code value corresponding to the difference signal with the minimum absolute value.
5. The phase-locked loop circuit as described in claim 4, characterized in that, The comparison circuit includes: The memory is configured to store and output the difference signal output at the previous preset time. An absolute value comparator, connected to the difference circuit, the memory, and the bit adjustment circuit, is configured to compare the absolute values of the difference signals within two preset time intervals with a reference value, and output the comparison signal with the smallest absolute value to the bit adjustment circuit. The reference value is the value of the pulse change generated by the inductor-capacitor voltage-controlled oscillator when the bit adjustment circuit changes the digital code value by one bit.
6. The phase-locked loop circuit as described in claim 5, characterized in that, The automatic frequency control circuit also includes: A judgment circuit is connected to the difference circuit and the bit adjustment circuit. The judgment circuit is configured to compare the absolute value of the difference signal with the reference value, and output a first judgment signal when the absolute value of the difference signal is greater than the reference value, and output a second judgment signal when the absolute value of the difference signal is less than the reference value. The bit adjustment circuit is further configured to output the digital code value by a one-bit change according to the magnitude of the difference signal when the first judgment signal is received, and to latch and output the digital code value of the previous moment when the second judgment signal is received.
7. The phase-locked loop circuit as described in claim 6, characterized in that, The judgment circuit includes a code value comparator, which is configured to perform code value calculation on the absolute value of the difference signal and the reference value, and output a judgment signal of corresponding magnitude.
8. The phase-locked loop circuit as described in any one of claims 1 to 7, characterized in that, The switching circuit includes a first switch and a second switch; The first terminal of the first switch is connected to the reference voltage terminal, the second terminal of the first switch and the second terminal of the second switch are connected to the first input terminal of the inductor-capacitor voltage-controlled oscillator, the first terminal of the second switch is connected to the output terminal of the charge pump circuit, and the control terminal of the first switch and the control terminal of the second switch are connected to the first output terminal of the automatic frequency control circuit.
9. The phase-locked loop circuit according to any one of claims 1 to 7, characterized in that, The inductor-capacitor voltage-controlled oscillator includes an inductor, an adjustable capacitor unit, a capacitor array, a first switch, a second switch, and a third switch. The inductor, the adjustable capacitor unit, and the capacitor array are connected in parallel between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator. The first terminal of the first switch, the control terminal of the second switch, and the first output terminal of the inductor-capacitor voltage-controlled oscillator are connected. The first terminal of the second switch, the control terminal of the first switch, and the second output terminal of the inductor-capacitor voltage-controlled oscillator are connected. The second terminal of the first switch, the second terminal of the second switch, and the first terminal of the third switch are connected. The second terminal of the third switch is grounded. The control terminal of the third switch is configured to receive a reference voltage. The control terminal of the adjustable capacitor unit constitutes the first input terminal of the inductor-capacitor voltage-controlled oscillator. The control terminal of the capacitor array constitutes the second input terminal of the inductor-capacitor voltage-controlled oscillator. The adjustable capacitor unit is configured to switch the output capacitance of different sizes according to the voltage reference signal or the first voltage signal; The capacitor array includes multiple capacitor units with preset capacitance values. The capacitor array is configured to switch different numbers of capacitor units connected in parallel between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator according to the digital code value.
10. The phase-locked loop circuit as described in claim 9, characterized in that, The adjustable capacitor unit includes a first capacitor, a first adjustable capacitor, a second adjustable capacitor, and a second capacitor connected in series between the first output terminal and the second output terminal of the inductor-capacitor voltage-controlled oscillator. The control terminals of the first adjustable capacitor and the second adjustable capacitor are configured to receive the voltage reference signal or the first voltage signal.
11. The phase-locked loop circuit as described in claim 9, characterized in that, The capacitor array includes multiple capacitor units connected in parallel between the first and second output terminals of the inductor-capacitor voltage-controlled oscillator. Each of the capacitor units includes a third capacitor, a fourth capacitor, a fourth switch, a fifth switch, and a sixth switch; The first terminal of the third capacitor is connected to the first output terminal of the inductor-capacitor voltage-controlled oscillator. The second terminal of the third capacitor, the first terminal of the fourth switch, and the fifth switch are connected. The second terminal of the fourth switch, the first terminal of the fourth capacitor, and the first terminal of the sixth switch are connected. The second terminal of the fourth capacitor is connected to the second output terminal of the inductor-capacitor voltage-controlled oscillator. The control terminal of the fourth switch is configured to receive one bit of the digital code value. The second terminals of the fifth and sixth switches are grounded. The control terminals of the fifth and sixth switches are connected and receive a digital signal with an opposite level to the control terminal of the fourth switch.
12. An image sensor, characterized in that, Includes the phase-locked loop circuit as described in any one of claims 1 to 11.