A parallel system with ring communication

Abstract

The present invention discloses a parallel system with ring communication, comprising a master and a slave, each of which is a circuit unit; the circuit unit includes an optical fiber module, a bidirectional signal conversion module, and a processor; the circuit units are sequentially connected via an optical fiber transmission channel to form a communication loop; the optical fiber module of the circuit unit receives an optical signal from a previous communication node on the communication loop, converts it into a digital signal, and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the digital signal into an LVDS signal and sends it to the processor; the processor integrates circuit information into the LVDS signal to obtain a new LVDS signal, which is sent to the bidirectional signal conversion module; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal and sends it to the optical fiber module; the optical fiber module converts the parallel data signal into an optical signal and sends it to the next communication node via the communication loop. The parallel system of the present invention has good anti-interference performance and is suitable for long-distance data communication.

Description

Technical Field

[0001] The present invention relates to the technical field of parallel systems, and in particular to a parallel system with ring communication. Background Art

[0002] In existing parallel systems for power supplies, loads, and source-load products, data transmission is primarily achieved physically through analog media parallel networking. This suffers from poor interference resistance, numerous wiring harnesses, limited drive capability, and the inability to network over long distances. Compared to analog media, optical fiber offers the advantages of high bandwidth, high speed, and strong interference resistance. Prior art 201610257991.0 discloses a high-speed, real-time power supply parallel system that utilizes optical fiber for communication. However, this invention utilizes three pairs of optical modules for communication in the network topology, resulting in waste and increased system instability.

[0003] In the existing power supply, load and source-load product systems, phase synchronization is physically achieved mainly through analog medium parallel networking. The host obtains a synchronous phase pulse after dividing the real-time host main frequency, and sends it to the parallel bus through the analog medium. In addition, both the host and the slave obtain synchronous phase pulses from the parallel bus. The disadvantages of this are poor anti-interference performance, more wiring harnesses, limited driving capabilities, and inability to network over long distances. Prior art 202210792612.3 discloses a multi-machine phase synchronization system and method based on optical fiber transmission, which uses optical fiber for phase synchronization. The disadvantage of this invention is that the digital reference source is directly sent as a synchronous phase signal and used as the digital reference source phase of the local machine after the slave receives it. When it is a reference source at the MHZ unit level, it occupies too much bandwidth. At the same time, the higher the frequency, the more unstable the transmission recognition, resulting in the scale limitation of the network and the disadvantage of phase error caused by the slave losing the clock.

[0004] The parallel operation of circuit units enables modularization and high-capacity of power supplies, loads, and source-load products, and is the key to realizing combined high-power, high-voltage systems. When power supplies, loads, and source-load products are connected in parallel to expand current and capacity, current-sharing measures need to be implemented to achieve current-sharing control when the circuit units are connected in parallel. Furthermore, the current of each unit and the total current after parallel connection need to be measured and counted. When power supplies, loads, and source-load products are connected in series to expand voltage and capacity, voltage-sharing measures need to be implemented to achieve voltage-sharing control when the circuit units are connected in series. Furthermore, the voltage of each unit and the total voltage after parallel connection need to be measured and counted.

[0005] Currently, current sharing control and current summation measurement are primarily implemented using hardware circuits. For example, in prior art 201610257991.0, a slave device transmits its current information to a master device via a sampling circuit. The master device then receives the current information from each slave device and sends it to the input of an adder to obtain the total current at that moment. In this solution, analog signals are transmitted in the link, resulting in complex hardware circuits, poor anti-interference capabilities, and large measurement errors.

[0006] Currently, current sharing control and current summation measurement are also implemented through software transmission. Slaves transmit their local current information to the switchboard through sampling circuits and A / D conversion circuits. The master receives the current information from each slave and also uses its own circuits through sampling circuits and internal A / D conversion circuits to convert it into a digital signal. The host software then digitally sums the signals from the master and all slaves to obtain the total current at that moment. In this solution, digital signals are transmitted in the link, which has moderate anti-interference capabilities. However, the timing is difficult to align during measurement, resulting in large errors in instantaneous value measurements.

[0007] Currently, current sharing control and current summation measurement are achieved by using similar high-speed transceiver module technology for master-slave serial connection. For example, the prior art 201610257991.0 discloses a high-speed real-time power supply parallel system. The disadvantage of this invention is that the slave machine is required to sum up the data of the previous module in sequence, thereby increasing the amount of calculation of the slave machine and summing up the data layer by layer in the entire system, reducing the reliability of the data. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a parallel system with ring communication, which has good anti-interference performance and is suitable for long-distance data communication.

[0009] In order to solve the above technical problems, the present invention discloses a parallel system with ring communication, including a master and multiple slaves, the master and the slaves are each a circuit unit, connected in series; the circuit unit is a power supply, a load or a source-load;

[0010] Each circuit unit is provided with a first optical fiber module, a bidirectional signal conversion module and a processor; the processor obtains circuit information of the circuit unit in real time;

[0011] Each of the circuit units is connected in sequence through an optical fiber transmission channel to form a first communication loop, and each of the circuit units serves as a communication node on the first communication loop;

[0012] For each of the circuit units, the first optical fiber module of the circuit unit receives the optical signal emitted by the previous communication node on the first communication loop, converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the digital signal into an LVDS signal and sends the LVDS signal to the processor; the processor integrates the circuit information of the circuit unit into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal and sends it to the first optical fiber module; the first optical fiber module converts the parallel data signal into an optical signal and sends it to the next communication node through the first communication loop.

[0013] As an optional implementation manner, the number of the first communication loops is at least two, and the communication nodes where the hosts on each of the first communication loops are located are sequentially connected via an optical fiber transmission channel to form a second communication loop, and the circuit unit corresponding to each of the hosts on the first communication loop serves as a communication node on the second communication loop;

[0014] The host on the first communication loop is any circuit unit on the first communication loop, wherein the circuit unit further includes a second optical fiber module, and the processor of the circuit unit obtains circuit information on the first communication loop in real time;

[0015] For each circuit unit corresponding to the host on the first communication loop, the second optical fiber module of the circuit unit receives the optical signal emitted by the previous communication node on the second communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor of the circuit unit; the processor integrates the circuit information on the first communication loop into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the second optical fiber module of the circuit unit; the second optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node on the second communication loop through the second communication loop.

[0016] As another optional implementation manner, the circuit information of each circuit unit includes current value information of the circuit unit;

[0017] The processor of the circuit unit corresponding to each host on the first communication loop further performs a current summary calculation:

[0018] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and adds the current values ​​of all other circuit units to the current value of the circuit unit to obtain the current total current value of the first communication loop.

[0019] As another optional implementation, the processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for current sharing:

[0020] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and finds the target circuit unit corresponding to the minimum current value through a sorting algorithm, calculates the current value difference between the target circuit unit and the current value of the circuit unit corresponding to the host, and determines whether the current value difference exceeds a preset value. If so, a first control signal is generated, and the first control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the voltage according to the first control signal.

[0021] As another optional implementation manner, the circuit information of each circuit unit includes voltage value information of the circuit unit;

[0022] The processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for voltage balancing:

[0023] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the voltage value information sent by all other circuit units on the first communication loop, finds the target circuit unit corresponding to the minimum voltage value through a sorting algorithm, calculates the voltage value difference between the target circuit unit and the voltage value of the circuit unit corresponding to the host, and determines whether the voltage value difference exceeds a preset value. If so, a second control signal is generated, and the second control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the current threshold according to the second control signal.

[0024] As another optional embodiment, the circuit information on the first communication loop includes at least one of the current value of each circuit unit on the first communication loop, the total value of the current values ​​of all circuit units on the first communication loop, and the voltage value of each circuit unit on the first communication loop.

[0025] As another optional implementation, the number of the slaves does not exceed 255.

[0026] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0027] In an embodiment of the present invention, the information collected by each circuit unit is modulated into an optical fiber medium via a digital signal for transmission. Since the link transmits digital signals, it has strong anti-interference capabilities. In addition, the optical fiber medium has a fast transmission speed and is suitable for long-distance transmission and scenarios with high real-time requirements. Physical electrical isolation between the host and each slave is achieved through the optical fiber module, which can also protect the circuit equipment. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is a schematic structural diagram of a parallel system with ring communication disclosed in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of a signal conversion process within a circuit unit A disclosed in an embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of data bit allocation of an LVDS signal disclosed in an embodiment of the present invention;

[0032] Figure 4 This is a structural diagram of another parallel system with ring communication disclosed in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0034] Example 1

[0035] See also Figures 1-3 The embodiment of the present invention discloses a parallel system with ring communication, including a master and multiple slaves, wherein the master and the slaves are each a circuit unit connected in series; the circuit unit is a power supply, a load, or a source-load; wherein:

[0036] Each circuit unit is provided with a first optical fiber module, a bidirectional signal conversion module and a processor; the processor obtains circuit information of the circuit unit in real time;

[0037] Each of the circuit units is connected in sequence through an optical fiber transmission channel to form a first communication loop, and each of the circuit units serves as a communication node on the first communication loop;

[0038] For each of the circuit units, the first optical fiber module of the circuit unit receives the optical signal emitted by the previous communication node on the first communication loop, converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the digital signal into an LVDS signal and sends the LVDS signal to the processor; the processor integrates the circuit information of the circuit unit into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal and sends it to the first optical fiber module; the first optical fiber module converts the parallel data signal into an optical signal and sends it to the next communication node through the first communication loop.

[0039] In this embodiment, the bidirectional signal conversion module is not limited to being an independent chip or being integrated into a processor to run as an algorithm.

[0040] In this embodiment, during system operation, one power module in the loop is designated as the master, and the remaining are slaves. The master transmits its own current information. Assuming the master is numbered 1, the high-speed receiving module of slave number N receives parameter information for the first N-1 parallel power modules, while its high-speed transmitting module transmits parameter information for the Nth parallel power module. This completes the loop, collecting parameter readbacks from all devices in the loop and transmitting them back to the master device. Current information, as one of the parameters in the parameter readback, is ultimately transmitted back to the master device. The master's digital processor then sums the currents of each slave to obtain the total system current. The measured data here includes, but is not limited to, current, resistance, power, and voltage, and the corresponding summed information can be obtained using the aforementioned method. When the system output is in series connection, the voltage readback is transmitted from the master device, and the master's digital processor sums it to obtain the total system voltage. The timing error of this execution is the same as described above, and the optimization measures are the same.

[0041] Specifically, the input optical signal is originally parallel digital information. After the optical fiber module restores it to parallel digital information, the bidirectional signal conversion module converts the parallel data signal into an LVDS signal. This is not only for anti-interference considerations, but also because the LVDS signal helps the processor read and write data, thereby improving processing speed: see Figure 3LVDS is a serial signal, and the data bits of each master and slave machine are reserved in advance in the data. The processor only needs to read the data of different data bits to know the data of each master and slave machine. The processor only needs to write the local information directly in the corresponding position; after the processor sends the information to the bidirectional signal conversion module, the bidirectional signal conversion module converts the LVDS signal into a parallel signal. The purpose is to maximize the use of the large bandwidth of the optical fiber to achieve large flow and high-speed information transmission.

[0042] In an embodiment of the present invention, the information collected by each circuit unit is modulated into an optical fiber medium via a digital signal for transmission. Since the link transmits digital signals, it has strong anti-interference capabilities. In addition, the optical fiber medium has a fast transmission speed and is suitable for long-distance transmission and scenarios with high real-time requirements. Physical electrical isolation between the host and each slave is achieved through the optical fiber module, which can also protect the circuit equipment.

[0043] In an optional embodiment, the circuit information of each circuit unit includes current value information of the circuit unit;

[0044] The processor of the circuit unit corresponding to each host on the first communication loop further performs a current summary calculation:

[0045] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and adds the current values ​​of all other circuit units to the current value of the circuit unit to obtain the current total current value of the first communication loop.

[0046] In yet another optional embodiment, the processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for current sharing:

[0047] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and finds the target circuit unit corresponding to the minimum current value through a sorting algorithm, calculates the current value difference between the target circuit unit and the current value of the circuit unit corresponding to the host, and determines whether the current value difference exceeds a preset value. If so, a first control signal is generated, and the first control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the voltage according to the first control signal.

[0048] In this embodiment, the host communicates via a ring fiber optic cable to obtain the current data of all slaves and its own host current, and the sum of these data is performed in the host processor. All slave currents are sorted using a sorting algorithm to determine the slave with the lowest current. This is then compared with the master current, and the voltage of the slave with the lowest current is fine-tuned. Once a defined threshold is reached, the process continues with the next step until all slaves have completed their sorting. If the minimum value is within a defined range, the process is interrupted and awaits the next condition to be triggered.

[0049] In yet another optional embodiment, the circuit information of each circuit unit includes voltage value information of the circuit unit;

[0050] The processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for voltage balancing:

[0051] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the voltage value information sent by all other circuit units on the first communication loop, finds the target circuit unit corresponding to the minimum voltage value through a sorting algorithm, calculates the voltage value difference between the target circuit unit and the voltage value of the circuit unit corresponding to the host, and determines whether the voltage value difference exceeds a preset value. If so, a second control signal is generated, and the second control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the current threshold according to the second control signal.

[0052] In this embodiment, if the output mode of the parallel system is voltage, it is determined whether to enter the constant current mode. If so, all the slave voltages here are sorted by the algorithm to obtain the slave number of the minimum voltage, which is then compared with the master voltage, and the current limit of the slave with the minimum voltage is slightly increased. After reaching the defined point, the next process is entered again to continue sorting until all slaves have completed the sorting. If the minimum value is within the defined range, the process is interrupted and waits for the next condition to be triggered.

[0053] In another optional embodiment, the circuit information on the first communication loop includes at least one of the current value of each circuit unit on the first communication loop, the total value of the current values ​​of all circuit units on the first communication loop, and the voltage value of each circuit unit on the first communication loop.

[0054] In yet another optional embodiment, the number of the slaves does not exceed 255.

[0055] In the embodiment of the present invention, the circuit information transmitted from the previous circuit unit module includes the global control information of the system and the current information uploaded by the previous circuit unit modules, and the current information includes the independent current information of all the previous circuit units.

[0056] The fiber-optic ring communication parallel system of the present invention utilizes multiple circuit units with fiber-optic modules to form a high-speed ring communication structure. The master's digital reference source is divided down to twice or more the system's output-stage PWM drive frequency, generating a phase-synchronized clock pulse. This is then coupled to the high-bandwidth fiber-optic ring communication line via a bidirectional signal conversion module (parallel-to-LVDS circuit or chip logic algorithm). The slaves then decouple the phase-synchronized clock from the fiber-optic ring line via the bidirectional signal conversion module, multiply it, and use it as their own clock. This process continues in this order. Finally, the master uses the same method to obtain the same synchronized clock pulse from the last slave, which serves as its own clock. Because coupling / decoupling can typically be performed at speeds of tens of MHz or higher, with execution time of a few microseconds, and because fiber latency is minimal, various system synchronization control functions and instantaneous measurement can be performed in real time.

[0057] In this embodiment of the present invention, control instructions and phase synchronization pulses are broadcast to all slave devices via a fiber optic ring communication system, ultimately reaching the master. After the slaves are connected to the optical fiber, they are transmitted via an optical fiber module and a bidirectional signal conversion module to the slave processor, where control parameters are executed. A synchronously decoupled phase synchronization clock serves as the slave's digital reference source. This continues in this order. The last slave sends the broadcast control instructions from the optical fiber transmission module to a fiber optic receiving module in the master. The instructions are then transmitted via the master's LVDS-to-parallel module to the master processor for execution. The synchronously decoupled phase synchronization clock serves as the master's digital reference source. The time error during this execution is t = N * ((T1 + T2) * 2), where T1 is the parallel-to-LVDS or LVDS-to-parallel data cycle, T2 is the LVDS-to-optical signal conversion time, and N is the number of circuit unit modules in the system. The optical fiber modules utilize fiber optic communication ports. The circuit units achieve real-time data transmission through a loop communication structure.

[0058] Example 2

[0059] See also Figures 2-4 The embodiment of the present invention discloses a parallel system with ring communication. Compared with the first embodiment, a larger-scale parallel system can be realized. The embodiment also has the following features:

[0060] There are at least two first communication loops, and the communication nodes where the hosts on each of the first communication loops are located are sequentially connected via an optical fiber transmission channel to form a second communication loop, and the circuit unit corresponding to each of the hosts on the first communication loop serves as a communication node on the second communication loop;

[0061] The host on the first communication loop is any circuit unit on the first communication loop, wherein the circuit unit further includes a second optical fiber module, and the processor of the circuit unit obtains circuit information on the first communication loop in real time;

[0062] For each circuit unit corresponding to the host on the first communication loop, the second optical fiber module of the circuit unit receives the optical signal emitted by the previous communication node on the second communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor of the circuit unit; the processor integrates the circuit information on the first communication loop into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the second optical fiber module of the circuit unit; the second optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node on the second communication loop through the second communication loop.

[0063] This embodiment implements dual communication loops by adding a second communication loop. Compared with the single communication loop of the first embodiment, it only requires adding a pair of optical fiber modules to the host of each first communication loop, which can achieve a power-order expansion of the number of parallel systems and greatly improve the scope of application.

[0064] In an embodiment of the present invention, control instructions and phase synchronization pulses are sent to all slave machines in a broadcast manner, reach the slave machines via fiber optic ring communication, and are finally transmitted to the master machine. After the slave machine is connected to the optical fiber, it is transmitted to the slave machine's processor via an optical fiber module and a bidirectional signal conversion module, executes the control parameters, and synchronously decouples the phase synchronization clock as the slave machine's digital reference source. Similarly, the last slave machine sends the broadcast control instructions from the optical fiber sending module to a fiber optic receiving module of the master machine, which is transmitted to the master machine's processor via the master machine's LVDS to parallel module for execution, and synchronously decouples the phase synchronization clock as the master machine's digital reference source. The time error of this execution is t=N*((T1+T2)*2), where T1 is the parallel to LVDS or LVDS to parallel data cycle, T2 is the conversion time between LVDS and optical signals, and N is the number of circuit unit modules in the entire system. The optical fiber module adopts an optical fiber communication port.

[0065] After expanding the number of circuit unit modules through a second ring communication structure, the execution time error is t = (N + 1) * ((T1 + T2) * 2). For more stringent timing synchronization requirements, this time error can be reduced more precisely by implementing a fixed algorithm in the slave and master, using a known number of modules to perform a fixed deduction. For example, if 100 circuit unit modules form a 10x10 matrix, the execution time error is t = (10 + 1) * ((T1 + T2) * 2). This execution time error only increases the conversion time of one unit.

[0066] In an optional embodiment, the circuit information of each circuit unit includes current value information of the circuit unit;

[0067] The processor of the circuit unit corresponding to each host on the first communication loop further performs a current summary calculation:

[0068] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and adds the current values ​​of all other circuit units to the current value of the circuit unit to obtain the current total current value of the first communication loop.

[0069] In yet another optional embodiment, the processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for current sharing:

[0070] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and finds the target circuit unit corresponding to the minimum current value through a sorting algorithm, calculates the current value difference between the target circuit unit and the current value of the circuit unit corresponding to the host, and determines whether the current value difference exceeds a preset value. If so, a first control signal is generated, and the first control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the voltage according to the first control signal.

[0071] In yet another optional embodiment, the circuit information of each circuit unit includes voltage value information of the circuit unit;

[0072] The processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for voltage balancing:

[0073] After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the voltage value information sent by all other circuit units on the first communication loop, finds the target circuit unit corresponding to the minimum voltage value through a sorting algorithm, calculates the voltage value difference between the target circuit unit and the voltage value of the circuit unit corresponding to the host, and determines whether the voltage value difference exceeds a preset value. If so, a second control signal is generated, and the second control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the current threshold according to the second control signal.

[0074] In another optional embodiment, the circuit information on the first communication loop includes at least one of the current value of each circuit unit on the first communication loop, the total value of the current values ​​of all circuit units on the first communication loop, and the voltage value of each circuit unit on the first communication loop.

[0075] In yet another optional embodiment, the number of the slaves does not exceed 255.

[0076] The contents disclosed in the embodiments of the present invention only disclose preferred embodiments of the present invention, which are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features therein can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A parallel system with ring communication, comprising a master and multiple slaves, each of which is a circuit unit connected in series; the circuit unit is a power supply, a load, or a source-load; It is characterized in that Each circuit unit is provided with a first optical fiber module, a bidirectional signal conversion module and a processor; the processor obtains circuit information of the circuit unit in real time; Each of the circuit units is connected in sequence through an optical fiber transmission channel to form a first communication loop, and each of the circuit units serves as a communication node on the first communication loop; For each of the circuit units, the first optical fiber module of the circuit unit receives an optical signal sent by a previous communication node on the first communication loop, converts the optical signal into a digital signal, and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor; the processor integrates the circuit information of the circuit unit into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the first optical fiber module; the first optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node via the first communication loop; There are at least two first communication loops, and the communication nodes where the hosts on each of the first communication loops are located are sequentially connected via an optical fiber transmission channel to form a second communication loop, and the circuit unit corresponding to each of the hosts on the first communication loop serves as a communication node on the second communication loop; The host on the first communication loop is any circuit unit on the first communication loop, wherein the circuit unit further includes a second optical fiber module, and the processor of the circuit unit obtains circuit information on the first communication loop in real time; For each circuit unit corresponding to the host on the first communication loop, the second optical fiber module of the circuit unit receives the optical signal sent by the previous communication node on the second communication loop, and converts the optical signal into a digital signal and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the digital signal into an LVDS signal, and sends the LVDS signal to the processor of the circuit unit; the processor integrates the circuit information on the first communication loop into the LVDS signal to obtain a new LVDS signal, and sends it to the bidirectional signal conversion module of the circuit unit; the bidirectional signal conversion module converts the new LVDS signal into a parallel data signal, and sends it to the second optical fiber module of the circuit unit; the second optical fiber module converts the parallel data signal into an optical signal, and sends it to the next communication node on the second communication loop through the second communication loop; The circuit information of each circuit unit includes current value information of the circuit unit; The processor of the circuit unit corresponding to each host on the first communication loop further performs a current summary calculation: After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal to obtain current value information sent by all other circuit units on the first communication loop, and adds the current values ​​of all other circuit units to the current value of the circuit unit to obtain a current total current value of the first communication loop; The circuit information on the first communication loop includes at least one of a current value of each circuit unit on the first communication loop, a total value of current values ​​of all circuit units on the first communication loop, and a voltage value of each circuit unit on the first communication loop.

2. The parallel system according to claim 1, characterized in that: The processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for current sharing: After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the current value information sent by all other circuit units on the first communication loop, and finds the target circuit unit corresponding to the minimum current value through a sorting algorithm, calculates the current value difference between the target circuit unit and the current value of the circuit unit corresponding to the host, and determines whether the current value difference exceeds a preset value. If so, a first control signal is generated, and the first control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the voltage according to the first control signal.

3. The parallel system according to claim 1, characterized in that: The circuit information of each circuit unit includes voltage value information of the circuit unit; The processor of the circuit unit corresponding to each host on the first communication loop further outputs a control signal for voltage balancing: After the processor receives the LVDS signal sent by the bidirectional signal conversion module, the processor parses the LVDS signal, obtains the voltage value information sent by all other circuit units on the first communication loop, finds the target circuit unit corresponding to the minimum voltage value through a sorting algorithm, calculates the voltage value difference between the target circuit unit and the voltage value of the circuit unit corresponding to the host, and determines whether the voltage value difference exceeds a preset value. If so, a second control signal is generated, and the second control signal is output to the target circuit unit through the first communication loop so that the target circuit unit increases the current threshold according to the second control signal.

4. The parallel system according to claim 1, characterized in that: The number of the slaves does not exceed 255.

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