Offset voltage calibration circuit, method, and transmitter local oscillator leakage calibration system

Abstract

This application provides an offset voltage calibration circuit and method. A comparator compares two differential output signals of the analog circuit to be calibrated. Before the second offset voltage calibration circuit calibrates the offset voltage of the analog circuit, the first offset voltage calibration circuit calibrates the offset voltage generated by the comparator. This effectively avoids the influence of the comparator's own offset voltage on the calibration accuracy of the analog circuit, resulting in more accurate calibration results. This application also provides a transmitter local oscillator leakage calibration system. The two offset voltage calibration circuits respectively calibrate the offset voltage of the I-phase signal modulation circuit and the Q-quadrature signal modulation circuit, thereby calibrating the local oscillator leakage of the RF transmitter link. The calibration accuracy is high, and the two offset voltage calibration circuits can be integrated into the original RF transceiver chip, occupying a small chip area and suitable for mass production.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, in particular to a misadjustment voltage calibration circuit, method and transmitter local oscillator leakage calibration system. BACKGROUND

[0002] In a radio frequency transmitting circuit, if the local oscillator signal of a mixer leaks to a radio frequency output end, it is called transmitter local oscillator leakage. The transmitter local oscillator leakage will cause the output signal of the transmitter to have an unwanted radio frequency component, affect the quality of the transmitted signal, cause the radio frequency receiving end to be difficult to correctly demodulate the signal, and thus affect the communication quality, and also possibly violate the radio transmission protocol specification and interfere with other communication channels. The transmitter local oscillator leakage is mainly due to the deviation in the process manufacturing process, causing the differential signal output by the low-pass filter in the circuit to have a direct current misadjustment voltage. The greater the direct current misadjustment voltage, the greater the local oscillator leakage.

[0003] The existing transmitter local oscillator leakage calibration scheme mainly includes: using two analog-to-digital converters to sample the direct current misadjustment voltage generated by each low-pass filter in the I in-phase signal modulation circuit and the Q quadrature signal modulation circuit, and convert it into a digital signal; filtering the output digital signal through a low-pass filter and inputting it to a local oscillator leakage calibration algorithm module for misadjustment voltage calibration, and determining the optimal misadjustment voltage compensation direction and compensation value through a microcontroller; outputting the optimal misadjustment voltage compensation direction and compensation value to the current array of the radio frequency transmitting circuit through a serial peripheral interface, so as to compensate for the misadjustment voltage generated by each low-pass filter.

[0004] However, on the one hand, the analog-to-digital converter for sampling in the transmitter local oscillator leakage calibration scheme will generate a new misadjustment voltage, so that the output misadjustment voltage compensation value is not the optimal value, which seriously affects the calibration accuracy of the transmitter local oscillator leakage in the radio frequency transmitting circuit; on the other hand, the local oscillator leakage calibration circuit composed of the analog-to-digital converter, the low-pass filter, the local oscillator leakage calibration algorithm module, the microcontroller and the serial peripheral interface of the transmitter local oscillator leakage calibration scheme needs to be realized by an additional chip, which is not suitable for use in large-scale production; and if the local oscillator leakage calibration circuit is integrated in the original radio frequency transceiver chip, the chip area is large, increasing the chip cost. SUMMARY

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a misadjustment voltage calibration circuit, method and transmitter local oscillator leakage calibration system, which solves the problems of low transmitter local oscillator leakage calibration accuracy and large chip area and high cost in the prior art.

[0006] To achieve the above and other related objectives, a first aspect of this application provides an offset voltage calibration circuit for calibrating the offset voltage of an analog circuit to be calibrated. The circuit includes a comparator, a calibration algorithm control circuit, a first offset voltage calibration circuit, and a second offset voltage calibration circuit. The input terminal of the calibration algorithm control circuit is connected to the output terminal of the comparator, and the two output terminals of the calibration algorithm control circuit are respectively connected to the input terminals of the first offset voltage calibration circuit and the second offset voltage calibration circuit. The output terminal of the first offset voltage calibration circuit is also connected to the comparator. The two input terminals of the comparator are respectively connected to the two differential output terminals of the analog circuit to be calibrated, and the output terminal of the second offset voltage calibration circuit is also connected to the analog circuit to be calibrated. The calibration algorithm control circuit controls the comparator, the first offset voltage calibration circuit, and the second offset voltage calibration circuit to calibrate the offset voltage of the analog circuit to be calibrated. The calibration method includes controlling the calibration algorithm... The circuit controls the comparator to disconnect from the analog circuit to be calibrated, and controls the two input terminals of the comparator to short-circuit, inputting a test voltage signal to determine the voltage direction of the first offset voltage generated by the comparator based on the output result of the comparator; through the calibration algorithm control circuit, the first offset voltage calibration circuit is controlled to determine its compensation direction based on the voltage direction of the first offset voltage, and generates a corresponding compensation current to calibrate the first offset voltage; through the calibration algorithm control circuit, the two input terminals of the comparator are disconnected from the short-circuit, and the two input terminals of the comparator are reconnected to the two differential output terminals of the analog circuit to be calibrated; the comparator compares the two differential signals output by the analog circuit to be calibrated to determine the voltage direction of the second offset voltage generated by the analog circuit to be calibrated; through the calibration algorithm control circuit, the second offset voltage calibration circuit is controlled to determine its compensation direction based on the voltage direction of the second offset voltage, and generates a corresponding compensation current to calibrate the second offset voltage.

[0007] In some embodiments of the first aspect of this application, the comparator has two input terminals, including a non-inverting input terminal and an inverting input terminal; the analog circuit to be calibrated has two differential output terminals, including a positive output terminal and a negative output terminal; a first switch is connected between the non-inverting input terminal of the comparator and the positive output terminal of the analog circuit to be calibrated, a second switch is connected between the inverting input terminal of the comparator and the negative output terminal of the analog circuit to be calibrated, and a third switch is connected between the non-inverting input terminal and the inverting input terminal of the comparator; the method of controlling the comparator to be short-circuited by the calibration algorithm control circuit includes: controlling the... The first and second switches are opened, and the third switch is closed to short-circuit the non-inverting and inverting input terminals of the comparator and receive the test voltage signal. The method of controlling the connection between the input terminal of the comparator and the output terminal of the analog circuit to be calibrated by the calibration algorithm control circuit includes: controlling the third switch to open and controlling the first and second switches to close, so as to connect the non-inverting and inverting input terminals of the comparator to the positive and negative output terminals of the analog circuit to be calibrated, respectively, and receive the differential signal output by the analog circuit to be calibrated.

[0008] In some embodiments of the first aspect of this application, the first offset voltage calibration circuit includes: a first compensation value calculation circuit and a second compensation value calculation circuit; wherein, the first compensation value calculation circuit is connected to the output terminal of the calibration algorithm control circuit and connected to the non-inverting compensation input terminal in the comparator; the second compensation value calculation circuit is connected to the output terminal of the calibration algorithm control circuit and connected to the inverting compensation input terminal in the comparator; the calibration algorithm control circuit controls the first offset voltage calibration circuit to determine its compensation direction according to the voltage direction of the first offset voltage and generate a corresponding compensation current to compensate the offset voltage. The method for calibrating the first offset voltage includes: determining the compensation direction of the first offset voltage based on its voltage direction using the calibration algorithm control circuit, and determining whether the compensation direction is positive or negative; if the compensation direction is positive, controlling the first compensation value calculation circuit to generate a compensation current for the first offset voltage to negatively compensate the voltage at the in-phase compensation input terminal using the calibration algorithm control circuit; if the compensation direction is negative, controlling the second compensation value calculation circuit to generate a compensation current for the first offset voltage to negatively compensate the voltage at the in-phase compensation input terminal using the calibration algorithm control circuit.

[0009] In some embodiments of the first aspect of this application, the first compensation value calculation circuit and the second compensation value calculation circuit adopt the same compensation value calculation circuit structure to generate the compensation current of the first offset voltage; wherein, the compensation value calculation circuit structure includes: a first compensation value calculation sub-circuit, a second compensation value calculation sub-circuit, a third compensation value calculation sub-circuit, and a fourth compensation value calculation sub-circuit connected in parallel; one end of the first compensation value calculation sub-circuit, the second compensation value calculation sub-circuit, the third compensation value calculation sub-circuit, and the fourth compensation value calculation sub-circuit is connected to the non-inverting compensation input terminal or the inverting compensation input terminal in the comparator, and the other end is grounded; the first compensation value calculation sub-circuit, the second compensation value calculation sub-circuit, the third compensation value calculation sub-circuit, and the fourth compensation value calculation sub-circuit each include a current array and a switch, for outputting a preset first compensation current, a second compensation current, a third compensation current, and a fourth compensation current respectively after being turned on; the switch in each compensation value calculation sub-circuit is connected to the calibration algorithm control circuit, for closing or opening under the control of the calibration algorithm control circuit; the first compensation current is greater than the second compensation current, the second compensation current is greater than the third compensation current, and the third compensation current is greater than the fourth compensation current.

[0010] In some embodiments of the first aspect of this application, the method of generating a compensation current for the first offset voltage by controlling the compensation value calculation circuit structure through the calibration algorithm control circuit includes: after determining the compensation direction of the first offset voltage, controlling the first compensation value calculation sub-circuit in the designated compensation value calculation circuit to be turned on through the calibration algorithm control circuit, and using its output first binary code as the primary compensation value of the offset voltage, thereby generating a corresponding compensation current signal; determining whether to increase or decrease the compensation current based on the output result of the comparator received again; if the compensation current needs to be increased, controlling the corresponding second compensation value calculation sub-circuit to be turned on through the calibration algorithm control circuit; if the compensation current needs to be decreased, controlling the corresponding first compensation value calculation sub-circuit to be turned off through the calibration algorithm control circuit, and controlling the corresponding second compensation value calculation sub-circuit to be turned on; adding the compensation currents output by each turned-on circuit and updating the primary compensation current; according to the third received Based on the output of the comparator received, it is determined again whether the compensation current needs to be increased or decreased. If the compensation current needs to be increased, the calibration algorithm control circuit controls the corresponding third compensation value calculation sub-circuit to be turned on. If the compensation current needs to be decreased, the calibration algorithm control circuit controls the corresponding second compensation value calculation sub-circuit to be turned off and controls the corresponding third compensation value calculation sub-circuit to be turned on. The compensation currents output by each turned-on circuit are summed to update the primary compensation current. Based on the output of the comparator received for the fourth time, it is determined again whether the compensation current needs to be increased or decreased. If the compensation current needs to be increased, the calibration algorithm control circuit controls the corresponding fourth compensation value calculation sub-circuit to be turned on. If the compensation current needs to be decreased, the calibration algorithm control circuit controls the corresponding third compensation value calculation sub-circuit to be turned off and controls the corresponding fourth compensation value calculation sub-circuit to be turned on. The compensation currents output by each turned-on circuit are summed to obtain the optimal compensation current output for the first offset voltage.

[0011] In some embodiments of the first aspect of this application, the second offset voltage calibration circuit includes: a third compensation value calculation circuit and a fourth compensation value calculation circuit; wherein, the third compensation value calculation circuit is connected to the output terminal of the calibration algorithm control circuit and connected to the positive compensation input terminal in the analog circuit to be calibrated; the fourth compensation value calculation circuit is connected to the output terminal of the calibration algorithm control circuit and connected to the negative compensation input terminal in the analog circuit to be calibrated; the calibration algorithm control circuit controls the second offset voltage calibration circuit to determine its compensation direction according to the voltage direction of the second offset voltage and generate a corresponding compensation current, so as to calibrate the second offset voltage in the following manner: the calibration algorithm control circuit determines the compensation direction according to the voltage direction of the second offset voltage. The voltage direction is determined to establish the compensation direction for the second offset voltage, and it is determined whether the compensation direction is positive or negative. If the compensation direction is positive, the calibration algorithm control circuit controls the third compensation value calculation circuit to generate a fifth compensation current for the second offset voltage to positively compensate the positive terminal of the compensation input; simultaneously, the fourth compensation value calculation circuit is controlled to generate a sixth compensation current for the offset voltage to negatively compensate the negative terminal of the compensation input. If the compensation direction is negative, the calibration algorithm control circuit controls the third compensation value calculation circuit to generate a seventh compensation current for the second offset voltage to negatively compensate the positive terminal of the compensation input; simultaneously, the fourth compensation value calculation circuit is controlled to generate an eighth compensation current for the second offset voltage to positively compensate the negative terminal of the compensation input.

[0012] In some embodiments of the first aspect of this application, the third compensation value calculation circuit includes: a first compensation unit and a second compensation unit; the fourth compensation value calculation circuit includes: a third compensation unit and a fourth compensation unit; wherein each compensation unit includes a fifth compensation value calculation sub-circuit, a sixth compensation value calculation sub-circuit, a seventh compensation value calculation sub-circuit, and an eighth compensation value calculation sub-circuit; the compensation value calculation sub-circuits of the first compensation unit are connected in parallel, one end of which is connected to a power supply, and the other end of which is connected to the positive compensation input terminal of the analog circuit to be calibrated; the compensation value calculation sub-circuits of the second compensation unit are connected in parallel, one end of which is connected to the positive compensation input terminal of the analog circuit to be calibrated. The positive terminal of the compensation input in the calibration simulation circuit is grounded at the other end; the compensation value calculation sub-circuits of the third compensation unit are connected in parallel, with one end connected to a power supply and the other end connected to the negative terminal of the compensation input in the simulation circuit to be calibrated; the compensation value calculation sub-circuits of the fourth compensation unit are connected in parallel, with one end connected to the negative terminal of the compensation input in the simulation circuit to be calibrated and the other end grounded; each compensation value calculation sub-circuit includes a current array and a switch, which are used to output a preset compensation current after being turned on. The switches in each compensation value calculation sub-circuit are connected to the calibration algorithm control circuit and are used to close or open under the control of the calibration algorithm control circuit.

[0013] In some embodiments of the first aspect of this application, the calibration algorithm control circuit controls the second offset voltage calibration circuit to determine its compensation direction based on the voltage direction of the second offset voltage and generate a corresponding compensation current to calibrate the second offset voltage. This includes: when the compensation direction of the second offset voltage is positive, the calibration algorithm control circuit controls the switch of the fifth compensation value calculation sub-circuit in the first compensation unit to close, and controls the switch of the fifth compensation value calculation sub-circuit in the second compensation unit to open, so that the third compensation value calculation circuit positively compensates the positive terminal of the compensation input; simultaneously, the switch of the fifth compensation value calculation sub-circuit in the third compensation unit is opened, controlling the third compensation value calculation circuit to... The switch of the fifth compensation value calculation subcircuit in the four compensation units is closed to compensate the negative terminal of the compensation input in the negative direction through the fourth compensation value calculation circuit. When the compensation direction of the second offset voltage is negative, the calibration algorithm control circuit controls the switch of the fifth compensation value calculation subcircuit in the first compensation unit to open and controls the switch of the fifth compensation value calculation subcircuit in the second compensation unit to close, so as to compensate the positive terminal of the compensation input in the negative direction through the third compensation value calculation circuit. At the same time, the switch of the fifth compensation value calculation subcircuit in the third compensation unit is closed, and the switch of the fifth compensation value calculation subcircuit in the fourth compensation unit is opened, so as to compensate the negative terminal of the compensation input in the positive direction through the fourth compensation value calculation circuit.

[0014] To achieve the above and other related objectives, a second aspect of this application provides an offset voltage calibration method. This method is used to calibrate the offset voltage of an analog circuit to be calibrated using the offset voltage calibration circuit described in the above embodiments. The method includes: controlling the comparator to disconnect from the analog circuit to be calibrated via the calibration algorithm control circuit, and short-circuiting the two input terminals of the comparator to input a test voltage signal, so as to determine the voltage direction of the first offset voltage generated by the comparator based on the output result of the comparator; and controlling the first offset voltage calibration circuit to determine its compensation direction based on the voltage direction of the first offset voltage via the calibration algorithm control circuit. The calibration algorithm control circuit controls the two input terminals of the comparator to disconnect and short-circuit, and controls the two input terminals of the comparator to reconnect to the two differential output terminals of the analog circuit to be calibrated. The comparator compares the two differential signals output by the analog circuit to be calibrated to determine the voltage direction of the second offset voltage generated by the analog circuit to be calibrated. The calibration algorithm control circuit controls the second offset voltage calibration circuit to determine its compensation direction according to the voltage direction of the second offset voltage, and generates a corresponding compensation current to calibrate the second offset voltage.

[0015] To achieve the above and other related objectives, a third aspect of this application provides a transmitter local oscillator leakage calibration system, comprising: an I-in-phase signal calibration module, including the offset voltage calibration circuit described in the above embodiments, used to perform offset voltage calibration on the I-in-phase signal modulation circuit to calibrate the local oscillator leakage of the radio frequency transmitter link; wherein, the comparator in the offset voltage calibration circuit is connected to the output terminal of the low-pass filter in the I-in-phase signal modulation circuit, and the second offset voltage calibration circuit in the offset voltage calibration circuit is connected to the input terminal of the operational amplifier in the low-pass filter; and a Q-quadrature signal calibration module, including the offset voltage calibration circuit described in the above embodiments, used to perform offset voltage calibration on the Q-quadrature signal modulation circuit to further calibrate the local oscillator leakage of the radio frequency transmitter link; wherein, the comparator in the offset voltage calibration circuit is connected to the output terminal of the low-pass filter in the Q-quadrature signal modulation circuit, and the second offset voltage calibration circuit in the offset voltage calibration circuit is connected to the input terminal of the operational amplifier in the low-pass filter.

[0016] As described above, this application has the following beneficial effects: This application provides an offset voltage calibration circuit and method, which compares two output signals of the analog circuit to be calibrated by a comparator, and first calibrates the offset voltage generated by the comparator by the first offset voltage calibration circuit before calibrating the offset voltage of the analog circuit to be calibrated by the second offset voltage calibration circuit. This effectively avoids the influence of the comparator's own offset voltage on the calibration accuracy of the analog circuit to be calibrated, making the calibration result more accurate. This application also provides a transmitter local oscillator leakage calibration system, which uses the two offset voltage calibration circuits to calibrate the offset voltage of the I in-phase signal modulation circuit and the Q quadrature signal modulation circuit respectively, thereby calibrating the local oscillator leakage of the RF transmitter link. The calibration accuracy is high, and the two offset voltage calibration circuits can be integrated into the original RF transceiver chip, occupying a small chip area, and can be used in mass production. Attached Figure Description

[0017] Figure 1 The diagram shown is a schematic representation of the offset voltage calibration circuit in one embodiment of this application.

[0018] Figure 2 The diagram shown is a schematic representation of the comparator in one embodiment of this application.

[0019] Figure 3 The diagram shown is a flowchart of an offset voltage calibration method according to an embodiment of this application.

[0020] Figure 4 The diagram shows the connection between the calibration algorithm control circuit and the first offset voltage calibration circuit in one embodiment of this application.

[0021] Figure 5 The diagram shows the connection between the calibration algorithm control circuit and the second offset voltage calibration circuit in one embodiment of this application.

[0022] Figure 6 The diagram shown is a schematic representation of a transmitter local oscillator leakage calibration system according to an embodiment of this application. Detailed Implementation

[0023] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0024] This application provides an offset voltage calibration circuit, method, and transmitter local oscillator leakage calibration system, aiming to solve the problems of low calibration accuracy and large chip area and high cost of transmitter local oscillator leakage in the prior art, effectively improve the calibration accuracy of transmitter local oscillator leakage, and the offset voltage calibration circuit provided by this application can be integrated into the original RF transceiver chip, occupying a small chip area, and can be used in large-scale mass production.

[0025] Meanwhile, to make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application are further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only for explaining this application and are not intended to limit the invention.

[0026] like Figure 1 The diagram shows a schematic representation of an offset voltage calibration circuit according to an embodiment of this application. The offset voltage calibration circuit in this embodiment includes: a comparator 1, a calibration algorithm control circuit 2, a first offset voltage calibration circuit 3, and a second offset voltage calibration circuit 4.

[0027] The input terminal of the calibration algorithm control circuit 2 is connected to the output terminal of the comparator 1. The two output terminals of the calibration algorithm control circuit 2 are respectively connected to the input terminals of the first offset voltage calibration circuit 3 and the second offset voltage calibration circuit 4. The output terminal of the first offset voltage calibration circuit 3 is also connected to the comparator 1. The two input terminals of the comparator 1 are respectively connected to the two differential output terminals of the analog circuit to be calibrated. The output terminal of the second offset voltage calibration circuit 4 is also connected to the analog circuit to be calibrated.

[0028] In one embodiment, comparator 1 has two input terminals, including a non-inverting input terminal and an inverting input terminal, used to compare the magnitudes of two input voltages and output a binary signal based on the comparison result; specifically, when the voltage at the non-inverting input terminal is higher than the voltage at the inverting input terminal, a high-level signal is output, and vice versa. The two differential output terminals of the analog circuit to be calibrated include a positive output terminal and a negative output terminal. For example... Figure 1 As shown, a first switch 5 is connected between the non-inverting input terminal of comparator 1 and the positive output terminal of the analog circuit to be calibrated, a second switch 6 is connected between the inverting input terminal of comparator 1 and the negative output terminal of the analog circuit to be calibrated, and a third switch 7 is connected between the non-inverting input terminal and the inverting input terminal of comparator 1.

[0029] In a preferred embodiment, such as Figure 2 As shown, comparator 1 employs a complementary push-pull structure using NMOS (N-type metal-oxide-semiconductor) and PMOS (P-type metal-oxide-semiconductor). To improve the small-signal gain of the comparator, the intermediate stage uses a common-source, common-gate architecture. Comparator 1 includes: input NMOS transistors MN0 and MN1, input PMOS transistors MP0 and MP1, current sink MN2 for input NMOS transistors MN0 and MN1, current source MP2 for input PMOS transistors MP0 / MP1, current sources MP3 and MP4 for the folded common-source, common-gate stage, current sinks MN3 and MN4 for the folded common-source, common-gate stage, common-gate transistors MP5 and MP6 for the PMOS folded common-source, common-gate stage, common-gate transistors MN5 and MN6 for the NMOS folded common-source, common-gate stage, and buffers for providing a large-swing output, which include MN7, MN8, MP7, and MP8.

[0030] Specifically, the non-inverting input of comparator 1 is Figure 2 The VIP shown has an inverting input terminal as follows: Figure 2The diagram shows VIN. VIP is connected to the gates of MN0 / MP0 simultaneously, VIN is connected to the gates of MN1 / MP1 simultaneously, VBP0 is connected to the gates of MP2 / MP3 / MP4 simultaneously, VBN0 is connected to the gate of MN2, the drain of MN2 is connected to the source of both MN0 and MN1, the drain of MP2 is connected to the source of both MP0 and MP1 simultaneously, the drain of MN0 is connected to the drain of both MP3 and MP5 simultaneously, the drain of MN1 is connected to the drain of both MP4 and MP6 simultaneously, the drain of MP0 (VIP_I) is connected to the drain of both MN3 and MN5 simultaneously, and the drain of MP1 (VIN_I) is connected to the drain of both MN4 and MN5 simultaneously. The source of MN6 and the gate of MN3 are simultaneously connected to the drain of MP5, the drain of MN5 and the gate of MN4. VBN1 is simultaneously connected to the gates of MN5 and MN6. VBP1 is simultaneously connected to the gates of MP5 and MP6. The drain of MN6 is simultaneously connected to the gates of MN7, MP6 and MP7. The drain of MN7 is simultaneously connected to the drain of MP7, the gate of MN8 and the gate of MP8. The output VOUT is simultaneously connected to the drains of MN8 and MP8. AVDD is simultaneously connected to the source of MP2 / MP3 / MP4 / MP7 / MP8. AGND is simultaneously connected to the source of MN2 / MN3 / MN4 / MN7 / MN8.

[0031] The drains VIP_I and VIN_I of the folded common source and common gate current sinks MN3 and MN4 can be used as non-inverting compensation input terminals and inverting compensation input terminals, respectively, to connect to the output terminal of the first offset voltage calibration circuit 3 and calibrate the first offset voltage of comparator 1.

[0032] It should be noted that the specific structure of comparator 1 can be set according to requirements, such as using only NMOS or only PMOS structure.

[0033] The calibration algorithm control circuit 2 is used to control the comparator 1, the first offset voltage calibration circuit 3, and the second offset voltage calibration circuit 4 to perform offset voltage calibration on the analog circuit to be calibrated. The calibration method is as follows: Figure 3 As shown, it includes steps S1 to S4.

[0034] Step S1: The calibration algorithm control circuit controls the comparator to disconnect from the analog circuit to be calibrated, and controls the two input terminals of the comparator to be short-circuited, inputting a test voltage signal to determine the voltage direction of the first offset voltage generated by the comparator based on the output result of the comparator.

[0035] In one specific embodiment, the method of controlling the comparator 1 to be short-circuited by the calibration algorithm control circuit 2 includes: controlling the first switch 5 and the second switch 6 to be open and controlling the third switch 7 to be closed, so as to short-circuit the non-inverting input terminal and the inverting input terminal of the comparator 1 and receive the test voltage signal.

[0036] It should be understood that, ideally, when the voltages at the two input terminals of comparator 1 are equal, its output should be 1 / 2. However, due to deviations in the manufacturing process, comparator 1 has an offset voltage, which affects the output of comparator 1. Therefore, comparator 1 needs to be calibrated for the offset voltage.

[0037] A test voltage signal is input by connecting the non-inverting and inverting inputs of comparator 1 in parallel. Based on the output of comparator 1, the direction of the first offset voltage generated by the comparator is determined. Specifically, when the output of comparator 1 is a high-level signal, i.e., when the output result of comparator 1 is 1, the direction of the first offset voltage is determined to be positive; when the output of comparator 1 is a low-level signal, i.e., when the output result of comparator 1 is 0, the direction of the first offset voltage is determined to be negative.

[0038] Step S2: The calibration algorithm control circuit controls the first offset voltage calibration circuit to determine its compensation direction according to the voltage direction of the first offset voltage and generate a corresponding compensation current to calibrate the first offset voltage.

[0039] In one embodiment, such as Figure 4 As shown, the first offset voltage calibration circuit 3 includes a first compensation value calculation circuit 31 and a second compensation value calculation circuit 32. The first compensation value calculation circuit 31 is connected to the output terminal of the calibration algorithm control circuit 2 and to the non-inverting compensation input terminal VIP_I in the comparator 1; the second compensation value calculation circuit 32 is connected to the output terminal of the calibration algorithm control circuit 2 and to the inverting compensation input terminal VIN_I in the comparator 1.

[0040] In this embodiment, step S2, the method of calibrating the first offset voltage by controlling the first compensation value calculation circuit 31 and the second compensation value calculation circuit 32 through the calibration algorithm control circuit 2 includes: determining the compensation direction of the first offset voltage according to the voltage direction of the first offset voltage through the calibration algorithm control circuit 2, and determining whether the compensation direction is positive or negative; if the compensation direction is positive, then the calibration algorithm control circuit 2 controls the first compensation value calculation circuit 31 to generate a compensation current for the first offset voltage to negatively compensate the voltage of the in-phase compensation input terminal VIP_I; if the compensation direction is negative, then the calibration algorithm control circuit 2 controls the second compensation value calculation circuit 32 to generate a compensation current for the first offset voltage to negatively compensate the voltage of the in-phase compensation input terminal VIN_I.

[0041] In one embodiment, determining the compensation direction of the first offset voltage based on its voltage direction includes: if the voltage direction of the first offset voltage is positive, then the compensation direction is determined to be negative; if the voltage direction of the first offset voltage is negative, then the compensation direction is determined to be positive. Combining the output of comparator 1, when comparator 1 outputs a high-level signal (i.e., when the output of comparator 1 is 1), the voltage direction of the first offset voltage is positive, and the compensation direction is determined to be negative; when comparator 1 outputs a low-level signal (i.e., when the output of comparator 1 is 0), the voltage direction of the first offset voltage is negative, and the compensation direction is determined to be positive.

[0042] In detail, when the output of comparator 1 is 1, the calibration algorithm control circuit 2 controls the second compensation value calculation circuit 32 to generate a compensation current for the first offset voltage, so as to negatively compensate the voltage of the inverting compensation input terminal VIN_I; when the output of comparator 1 is 0, the calibration algorithm control circuit 2 controls the first compensation value calculation circuit 31 to generate a compensation current for the first offset voltage, so as to negatively compensate the voltage of the non-inverting compensation input terminal VIP_I.

[0043] In one specific embodiment, the first compensation value calculation circuit 31 and the second compensation value calculation circuit 32 use the same compensation value calculation circuit structure to generate the compensation current for the first offset voltage.

[0044] like Figure 4 As shown, the compensation value calculation circuit structure includes: a first compensation value calculation sub-circuit, a second compensation value calculation sub-circuit, a third compensation value calculation sub-circuit, and a fourth compensation value calculation sub-circuit connected in parallel. One end of each of the first, second, third, and fourth compensation value calculation sub-circuits is connected to the non-inverting compensation input terminal VIP_I or the inverting compensation input terminal VIN_I within comparator 1, and the other end is grounded. Each of the first, second, third, and fourth compensation value calculation sub-circuits includes a current array and a switch, used to output preset first, second, third, and fourth compensation currents respectively after being turned on. One end of the switch in each compensation value calculation sub-circuit is connected to the corresponding current array, and the other end is grounded and connected to the calibration algorithm control circuit, used to control the closing or opening of the calibration algorithm control circuit, thereby turning each compensation value calculation sub-circuit on or off. The first compensation current is greater than the second compensation current, the second compensation current is greater than the third compensation current, and the third compensation current is greater than the fourth compensation current.

[0045] In a preferred embodiment, the first compensation value calculation circuit 31 and the second compensation value calculation circuit 32 can be implemented using a 4-bit digital-to-analog converter. After the first compensation value calculation sub-circuit is turned on, the first compensation current output is 8 times the minimum compensation current; after the second compensation value calculation sub-circuit is turned on, the second compensation current output is 4 times the minimum compensation current; after the third compensation value calculation sub-circuit is turned on, the third compensation current output is 2 times the minimum compensation current; and after the fourth compensation value calculation sub-circuit is turned on, the fourth compensation current output is the minimum compensation current. Figure 4 As shown, the minimum compensation current supported by the first compensation value calculation circuit 31 and the second compensation value calculation circuit 32 is I, and the compensation currents output by each compensation value calculation sub-circuit are I, 2I, 4I and 8I.

[0046] It should be noted that the first compensation value calculation circuit 31 and the second compensation value calculation circuit 32 can be configured with different numbers of compensation value calculation sub-circuits as needed, and this application does not limit the number of compensation value calculation sub-circuits.

[0047] The method by which the calibration algorithm control circuit 2 controls the compensation value calculation circuit structure to generate the compensation current for the first offset voltage includes the following steps.

[0048] ① After determining the compensation direction of the first offset voltage, the calibration algorithm control circuit 2 controls the first compensation value calculation sub-circuit in the specified compensation value calculation circuit to be turned on, and the first compensation current output by it is used as the primary compensation current output of the first offset voltage.

[0049] ② Based on the output result of comparator 1 received again, determine whether the compensation current needs to be increased or decreased; if the compensation current needs to be increased, control the corresponding second compensation value calculation sub-circuit to be turned on through calibration algorithm control circuit 2; if the compensation current needs to be decreased, control the corresponding first compensation value calculation sub-circuit to be turned off through calibration algorithm control circuit 2, and control the corresponding second compensation value calculation sub-circuit to be turned on; add the compensation current output by each turned circuit and update the primary compensation current.

[0050] ③ Based on the output result of comparator 1 received for the third time, determine again whether to increase or decrease the compensation current; if the compensation current needs to be increased, control the corresponding third compensation value calculation sub-circuit to be turned on through calibration algorithm control circuit 2; if the compensation current needs to be decreased, control the corresponding second compensation value calculation sub-circuit to be turned off through calibration algorithm control circuit 2, and control the corresponding third compensation value calculation sub-circuit to be turned on; add the compensation currents output by each turned-on circuit and update the primary compensation current.

[0051] ④ Based on the output result of comparator 1 received for the fourth time, determine again whether to increase or decrease the compensation current; if the compensation current needs to be increased, control the corresponding fourth compensation value calculation sub-circuit to be turned on through calibration algorithm control circuit 2; if the compensation current needs to be decreased, control the corresponding third compensation value calculation sub-circuit to be turned off through calibration algorithm control circuit 2, and control the corresponding compensation value calculation sub-circuit to be turned on; add the compensation currents output by each turned-on circuit and use it as the optimal compensation current output for the first offset voltage.

[0052] For example, when the compensation direction of the first offset voltage is positive, the calibration algorithm control circuit 2 controls the switch of the first compensation value calculation sub-circuit in the first compensation value calculation circuit 31 to close. At this time, the output compensation current is 8I (where I is the minimum compensation current supported by the first compensation value calculation circuit 31). The direction of this compensation current is from the non-inverting compensation input terminal VIP_I of the comparator 1 to the first compensation value calculation circuit, which can negatively compensate the voltage of the non-inverting compensation input terminal VIP_I, thereby calibrating the first offset voltage.

[0053] After the first offset voltage is calibrated, the output of comparator 1 determines whether the compensation current needs to be increased or decreased. Specifically, if comparator 1 outputs a high-level signal (i.e., the output of comparator 1 is 1), it indicates that the compensation current needs to be decreased; conversely, if comparator 1 outputs a low-level signal (i.e., the output of comparator 1 is 0), it indicates that the compensation current needs to be increased.

[0054] If an increase in compensation current is required, the calibration algorithm control circuit 2 controls the switch of the second compensation value calculation sub-circuit in the first compensation value calculation circuit 31 to close, updating the compensation current to 8I + 4I = 12I. Following the same steps, when the output result from comparator 1 is received for the third time, it is determined whether to continue increasing or decreasing the compensation current. If comparator 1 outputs a high-level signal, the compensation current needs to be decreased. The switch of the second compensation value calculation sub-circuit in the first compensation value calculation circuit 31 is opened, and the switch of its third compensation value calculation sub-circuit is closed, updating the compensation current to 8I + 2I = 10I.

[0055] Repeat the above operation. If the output of the fourth comparator 1 is still a high-level signal, then control the switch of the third compensation value calculation sub-circuit in the first compensation value calculation circuit 31 to open, and control the switch of its fourth compensation value calculation sub-circuit to close, updating the compensation current to 8I+I=9I, that is, the optimal compensation current of the first offset voltage is 9I, which can accurately compensate the voltage of the non-inverting compensation input terminal VIP_I in the negative direction, so as to accurately calibrate the first offset voltage.

[0056] Step S3: Through the calibration algorithm control circuit, the two input terminals of the comparator are disconnected and short-circuited, and the two input terminals of the comparator are reconnected to the two differential output terminals of the analog circuit to be calibrated; the two differential signals output by the analog circuit to be calibrated are compared by the comparator to determine the voltage direction of the second offset voltage generated by the analog circuit to be calibrated.

[0057] In this embodiment, the analog circuit to be calibrated uses differential output. Differential output is crucial in high-speed communication and precise signal transmission. It primarily uses paired wires to transmit signals, with equal amplitude but opposite phase on these wires. Differential output offers strong anti-interference capabilities and can suppress electromagnetic interference. The receiver of the differential signal, such as comparator 1, determines the logic state by comparing the voltage difference between the two wires, which is more accurate than single-ended signals.

[0058] In one specific embodiment, the method of connecting the input terminal of comparator 1 to the output terminal of the analog circuit to be calibrated by the calibration algorithm control circuit 2 includes: controlling the third switch 7 to open and controlling the first switch 5 and the second switch 6 to close, so as to connect the non-inverting input terminal and the inverting input terminal of comparator 1 to the positive output terminal and the negative output terminal of the analog circuit to be calibrated, respectively, and receiving the differential signal output by the analog circuit to be calibrated.

[0059] Comparator 1 compares the differential signals of the two output signals of the analog circuit to be calibrated, and outputs a high-level signal or a low-level signal based on the voltage difference between them. If a high-level signal is output, that is, the output result of comparator 1 is 1, then the voltage direction of the second offset voltage generated by the analog circuit to be calibrated is determined to be positive; if a low-level signal is output, that is, the output result of comparator 1 is 0, then the voltage direction of the second offset voltage is determined to be negative.

[0060] Step S4: The calibration algorithm control circuit controls the second offset voltage calibration circuit to determine its compensation direction according to the voltage direction of the second offset voltage and generate a corresponding compensation current to calibrate the second offset voltage.

[0061] The purpose of this design in this embodiment is that, before calibrating the offset voltage of the analog circuit to be calibrated, the first offset voltage calibration circuit 3 first calibrates the offset voltage of the added comparator 1 to avoid the influence of the offset voltage of the comparator 1 itself on the calibration accuracy of the analog circuit to be calibrated, thus making the calibration result of the analog circuit to be calibrated more accurate. Furthermore, this embodiment uses comparator 1 instead of the analog-to-digital converter in the prior art, resulting in a smaller chip area and lower chip cost.

[0062] In one embodiment, such as Figure 5As shown, the second offset voltage calibration circuit 4 includes a third compensation value calculation circuit 41 and a fourth compensation value calculation circuit 42. The third compensation value calculation circuit 41 is connected to the output terminal of the calibration algorithm control circuit 2 and to the positive compensation input terminal IOUT_P in the analog circuit to be calibrated; the fourth compensation value calculation circuit 42 is connected to the output terminal of the calibration algorithm control circuit 2 and to the negative compensation input terminal IOUT_N in the analog circuit to be calibrated.

[0063] In one specific embodiment, the third compensation calculation circuit 41 includes a first compensation unit 411 and a second compensation unit 412; the fourth compensation value calculation circuit 42 includes a third compensation unit 421 and a fourth compensation unit 422. Each compensation unit includes a fifth compensation value calculation subcircuit, a sixth compensation value calculation subcircuit, a seventh compensation value calculation subcircuit, and an eighth compensation value calculation subcircuit. Each compensation value calculation subcircuit outputs a preset compensation current after being turned on. The compensation current output by the fifth compensation value calculation subcircuit of different compensation units is greater than the compensation current output by its sixth compensation value calculation subcircuit, the compensation current output by the sixth compensation value calculation subcircuit of different compensation units is greater than the compensation current output by its seventh compensation value calculation subcircuit, and the compensation current output by the seventh compensation value calculation subcircuit of different compensation units is greater than the compensation current output by its eighth compensation value calculation subcircuit. In a preferred embodiment, the compensation current output by each fifth compensation value calculation subcircuit is 8I (where I is the preset minimum compensation current); the compensation current output by each sixth compensation value calculation subcircuit is 4I; the compensation current output by each seventh compensation value calculation subcircuit is 2I; and the compensation current output by each eighth compensation value calculation subcircuit is I.

[0064] like Figure 5 As shown, the compensation value calculation subcircuits of the first compensation unit 411 are connected in parallel, with one end connected to a power supply and the other end connected to the positive compensation input IOUT_P in the analog circuit to be calibrated; the compensation value calculation subcircuits of the second compensation unit 412 are connected in parallel, with one end connected to the positive compensation input IOUT_P in the analog circuit to be calibrated and the other end grounded; the compensation value calculation subcircuits of the third compensation unit 421 are connected in parallel, with one end connected to a power supply and the other end connected to the negative compensation input IOUT_N in the analog circuit to be calibrated; the compensation value calculation subcircuits of the fourth compensation unit 422 are connected in parallel, with one end connected to the negative compensation input IOUT_N in the analog circuit to be calibrated and the other end grounded. Each compensation value calculation subcircuit includes a current array and a switch, which output a preset compensation current after being turned on. The switches in each compensation value calculation subcircuit are connected to the calibration algorithm control circuit, which controls the opening or closing of the calibration algorithm control circuit, thereby controlling the on or off of each compensation value calculation subcircuit.

[0065] It should be noted that each compensation unit can be configured with a different number of compensation value calculation sub-circuits as needed, and this application does not limit the number of compensation value calculation sub-circuits.

[0066] The method for calibrating the second offset voltage in this embodiment includes the following steps.

[0067] ① The calibration algorithm control circuit 2 determines the compensation direction of the second offset voltage based on the voltage direction of the second offset voltage, and determines whether the compensation direction is positive or negative.

[0068] In one specific embodiment, if the voltage direction of the second offset voltage is positive, then its compensation direction is determined to be negative; if the voltage direction of the second offset voltage is negative, then its compensation direction is determined to be positive. Combining the output of comparator 1, when comparator 1 outputs a high-level signal, i.e., when the output of comparator 1 is 1, the voltage direction of the second offset voltage is positive, and its compensation direction is determined to be negative; when comparator 1 outputs a low-level signal, i.e., when the output of comparator 1 is 0, the voltage direction of the second offset voltage is negative, and its compensation direction is determined to be positive.

[0069] ② If the compensation direction is positive, the calibration algorithm control circuit 2 controls the third compensation value calculation circuit 41 to generate the fifth compensation current of the second offset voltage to compensate the positive input terminal IOUT_P in a positive direction; at the same time, the fourth compensation value calculation circuit 42 controls the sixth compensation current of the offset voltage to compensate the negative input terminal IOUT_N in a negative direction.

[0070] Specifically, when the output of comparator 1 is 0, the third compensation value calculation circuit 41 is controlled to generate the fifth compensation current of the second offset voltage to positively compensate the positive input terminal IOUT_P; at the same time, the fourth compensation value calculation circuit 42 is controlled to generate the sixth compensation current of the offset voltage to negatively compensate the negative input terminal IOUT_N.

[0071] In one embodiment, the specific implementation includes: controlling the switch of the fifth compensation value calculation sub-circuit in the first compensation unit 411 to close, and controlling the switch of the fifth compensation value calculation sub-circuit in the second compensation unit 412 to open, so as to positively compensate the positive input terminal IOUT_P through the third compensation value calculation circuit 41; at the same time, controlling the switch of the fifth compensation value calculation sub-circuit in the third compensation unit 421 to open, and controlling the switch of the fifth compensation value calculation sub-circuit in the fourth compensation unit 422 to close, so as to negatively compensate the negative input terminal IOUT_N through the fourth compensation value calculation circuit 42.

[0072] ③ If the compensation direction is negative, the calibration algorithm control circuit 2 controls the third compensation value calculation circuit 41 to generate the seventh compensation current of the second offset voltage to compensate the positive input terminal IOUT_P in a negative direction; at the same time, the fourth compensation value calculation circuit 42 controls the fourth compensation value calculation circuit 42 to generate the eighth compensation current of the second offset voltage to compensate the negative input terminal IOUT_N in a positive direction.

[0073] Specifically, when the output of comparator 1 is 1, the third compensation value calculation circuit 41 is controlled to generate the seventh compensation current of the second offset voltage to compensate the positive input terminal IOUT_P in the negative direction; at the same time, the fourth compensation value calculation circuit 42 is controlled to generate the eighth compensation current of the second offset voltage to compensate the negative input terminal IOUT_N in the positive direction.

[0074] In one embodiment, the specific implementation includes: controlling the switch of the fifth compensation value calculation sub-circuit in the first compensation unit 411 to be turned off by the calibration algorithm control circuit 2, and controlling the switch of the fifth compensation value calculation sub-circuit in the second compensation unit 412 to be turned off, so as to compensate the positive terminal IOUT_P of the third compensation value calculation circuit 41 in a negative manner; at the same time, controlling the switch of the fifth compensation value calculation sub-circuit in the third compensation unit 421 to be turned off, and controlling the switch of the fifth compensation value calculation sub-circuit in the fourth compensation unit 422 to be turned off, so as to compensate the negative terminal IOUT_N of the fourth compensation value calculation circuit 42 in a positive manner.

[0075] In a preferred embodiment, the third compensation value calculation circuit 41 and the fourth compensation value calculation circuit 42 can be implemented using a 4-bit digital-to-analog converter. The method by which the calibration algorithm control circuit 2 controls each compensation value calculation sub-circuit to generate the corresponding compensation current is the same as the method for generating the compensation current for the first offset voltage provided in the above embodiments, and will not be described again in this application for the sake of simplicity.

[0076] like Figure 3 The diagram illustrates a flowchart of an offset voltage calibration method according to an embodiment of this application. This offset voltage calibration method is applied to the offset voltage calibration circuits of the above embodiments and includes steps S1 to S4.

[0077] Step S1: The calibration algorithm control circuit controls the comparator to disconnect from the analog circuit to be calibrated, and controls the comparator to be short-circuited, inputting a test voltage signal to determine the voltage direction of the first offset voltage generated by the comparator based on the output result of the comparator.

[0078] Step S2: The calibration algorithm control circuit controls the first offset voltage calibration circuit to determine its compensation direction according to the voltage direction of the first offset voltage and generate a corresponding compensation current to calibrate the first offset voltage.

[0079] Step S3: Through the calibration algorithm control circuit, the two input terminals of the comparator are disconnected and short-circuited, and the two input terminals of the comparator are reconnected to the two differential output terminals of the analog circuit to be calibrated; the two differential signals output by the analog circuit to be calibrated are compared by the comparator to determine the voltage direction of the second offset voltage generated by the analog circuit to be calibrated.

[0080] Step S4: The calibration algorithm control circuit controls the second offset voltage calibration circuit to determine its compensation direction according to the voltage direction of the second offset voltage and generate a corresponding compensation current to calibrate the second offset voltage.

[0081] It should be understood that each step of the offset voltage calibration method has been described in detail in the above circuit embodiments, and will not be repeated here for the sake of brevity.

[0082] like Figure 6 The diagram shown illustrates the structure of a transmitter local oscillator leakage calibration system according to an embodiment of this application. The transmitter local oscillator leakage calibration system includes:

[0083] The I-in-phase signal calibration module 601 includes the offset voltage calibration circuit provided in the above embodiments, used to perform offset voltage calibration on the I-in-phase signal modulation circuit to calibrate the local oscillator leakage of the RF transmitter link; wherein, as... Figure 6 As shown, the comparator in the offset voltage calibration circuit is connected to the output of the low-pass filter in the I in-phase signal modulation circuit, and the second offset voltage calibration circuit in the offset voltage calibration circuit is connected to the input of the operational amplifier in the low-pass filter.

[0084] The Q-quadrature signal calibration module 602 includes the offset voltage calibration circuit provided in the above embodiments, used to perform offset voltage calibration on the Q-quadrature signal modulation circuit to further calibrate the local oscillator leakage of the RF transmitter link; wherein, as shown... Figure 6 As shown, the comparator in the offset voltage calibration circuit is connected to the output of the low-pass filter in the Q quadrature signal modulation circuit, and the second offset voltage calibration circuit in the offset voltage calibration circuit is connected to the input of the operational amplifier in the low-pass filter.

[0085] It should be noted that in this embodiment, the I in-phase signal calibration module 601 and the Q quadrature signal calibration module 602 can be integrated with the I in-phase signal modulation circuit and the Q quadrature signal modulation circuit into the original RF transceiver chip. They occupy a small chip area and can support large-scale mass production of the chip.

[0086] It should be understood that the structure of the offset voltage calibration circuit in the I-in-phase signal calibration module 601 and the Q-quadrature signal calibration module 602, as well as the steps for performing offset voltage calibration on the I-in-phase signal modulation circuit and the Q-quadrature signal modulation circuit respectively using the corresponding offset voltage calibration circuit, have been described in detail in the above circuit embodiments, and will not be repeated here for the sake of brevity.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0088] In summary, this embodiment provides an offset voltage calibration circuit and method. It compares the two output signals of the analog circuit to be calibrated using a comparator. Before performing offset voltage calibration on the analog circuit to be calibrated using the second offset voltage calibration circuit, the first offset voltage calibration circuit calibrates the offset voltage generated by the comparator. This effectively avoids the influence of the comparator's own offset voltage on the calibration accuracy of the analog circuit to be calibrated, resulting in more accurate calibration results. This application also provides a transmitter local oscillator leakage calibration system. It utilizes two offset voltage calibration circuits to perform offset voltage calibration on the I-phase signal modulation circuit and the Q-quadrature signal modulation circuit respectively, thereby calibrating the local oscillator leakage of the RF transmitter link. The calibration accuracy is high, and the two offset voltage calibration circuits can be integrated into the original RF transceiver chip, occupying a small chip area and enabling mass production.

[0089] Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0090] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A misregulation voltage calibration circuit, comprising: The application discloses a method for calibrating a to-be-calibrated analog circuit, and relates to the technical field of analog circuit calibration. The input end of the calibration algorithm control circuit is connected with the output end of the comparator, two output ends of the calibration algorithm control circuit are respectively connected with the input end of the first offset voltage calibration circuit and the input end of the second offset voltage calibration circuit, the output end of the first offset voltage calibration circuit is further connected with the comparator, the two input ends of the comparator are respectively connected with two differential output ends of the to-be-calibrated analog circuit, and the output end of the second offset voltage calibration circuit is further connected with the to-be-calibrated analog circuit. The calibration algorithm control circuit is used for controlling the comparator, the first offset voltage calibration circuit and the second offset voltage calibration circuit to calibrate the to-be-calibrated analog circuit, and the calibration mode comprises the following steps. The calibration algorithm control circuit controls the comparator to be disconnected with the to-be-calibrated analog circuit, controls the two input ends of the comparator to be short-circuited, inputs a test voltage signal, and determines the voltage direction of a first offset voltage generated by the comparator according to the output result of the comparator. The calibration algorithm control circuit controls the first offset voltage calibration circuit to determine the compensation direction according to the voltage direction of the first offset voltage, and generates a corresponding compensation current to calibrate the first offset voltage. The calibration algorithm control circuit controls the two input ends of the comparator to be disconnected and controls the two input ends of the comparator to be connected with the two differential output ends of the to-be-calibrated analog circuit again, and the comparator compares two differential signals output by the to-be-calibrated analog circuit to determine the voltage direction of a second offset voltage generated by the to-be-calibrated analog circuit. The calibration algorithm control circuit controls the second offset voltage calibration circuit to determine the compensation direction according to the voltage direction of the second offset voltage, and generates a corresponding compensation current to calibrate the second offset voltage.

2. The misregulation voltage calibration circuit of claim 1, wherein, The two input ends of the comparator comprise a non-inverting input end and an inverting input end, and the two differential output ends of the to-be-calibrated analog circuit comprise an output positive end and an output negative end. The non-inverting input end of the comparator is connected with the output positive end of the to-be-calibrated analog circuit through a first switch, the inverting input end of the comparator is connected with the output negative end of the to-be-calibrated analog circuit through a second switch, and the non-inverting input end and the inverting input end of the comparator are connected through a third switch. The calibration algorithm control circuit controls the comparator to be short-circuited, which comprises the following steps. The calibration algorithm control circuit controls the first switch and the second switch to be disconnected, controls the third switch to be connected, and short-circuits the non-inverting input end and the inverting input end of the comparator to receive the test voltage signal. The manner of controlling the input end of the comparator to be connected with the output end of the analog circuit to be calibrated by the calibration algorithm control circuit comprises: controlling the third switch to be disconnected and the first switch and the second switch to be connected by the calibration algorithm control circuit, so that the non-inverting input end and the inverting input end of the comparator are connected with the output positive terminal and the output negative terminal of the analog circuit to be calibrated respectively, and the differential signal output by the analog circuit to be calibrated is received.

3. The misregulation voltage calibration circuit of claim 1, wherein, The first offset voltage calibration circuit comprises a first compensation value calculation circuit and a second compensation value calculation circuit. The first compensation value calculation circuit is connected with the output end of the calibration algorithm control circuit and connected to the non-inverting compensation input end in the comparator, and the second compensation value calculation circuit is connected with the output end of the calibration algorithm control circuit and connected to the inverting compensation input end in the comparator. The manner of controlling the first offset voltage calibration circuit to determine the compensation direction of the first offset voltage according to the voltage direction of the first offset voltage and generate a corresponding compensation current to calibrate the first offset voltage by the calibration algorithm control circuit comprises: The calibration algorithm control circuit determines the compensation direction of the first offset voltage according to the voltage direction of the first offset voltage, and judges whether the compensation direction is positive or negative. If the compensation direction is positive, the calibration algorithm control circuit controls the first compensation value calculation circuit to generate the compensation current of the first offset voltage to negatively compensate the voltage of the non-inverting compensation input end. If the compensation direction is negative, the calibration algorithm control circuit controls the second compensation value calculation circuit to generate the compensation current of the first offset voltage to negatively compensate the voltage of the inverting compensation input end.

4. The misregulation voltage calibration circuit of claim 3, wherein, The first compensation value calculation circuit and the second compensation value calculation circuit generate the compensation current of the first offset voltage by using the same compensation value calculation circuit structure. The compensation value calculation circuit structure comprises: first compensation value calculation sub-circuits, second compensation value calculation sub-circuits, third compensation value calculation sub-circuits and fourth compensation value calculation sub-circuits connected in parallel; one end of the first compensation value calculation sub-circuits, the second compensation value calculation sub-circuits, the third compensation value calculation sub-circuits and the fourth compensation value calculation sub-circuits is connected with the non-inverting compensation input end or the inverting compensation input end in the comparator, and the other end is grounded. The first compensation value calculation sub-circuits, the second compensation value calculation sub-circuits, the third compensation value calculation sub-circuits and the fourth compensation value calculation sub-circuits each comprise a current array and a switch for turning on to output preset first compensation current, second compensation current, third compensation current and fourth compensation current respectively; the switch in each compensation value calculation sub-circuit is connected with the calibration algorithm control circuit for being controlled to be closed or disconnected by the calibration algorithm control circuit. The first compensation current is greater than the second compensation current, the second compensation current is greater than the third compensation current, and the third compensation current is greater than the fourth compensation current.

5. The misregulation voltage calibration circuit of claim 4, wherein, The manner in which the calibration algorithm control circuit controls the compensation value calculation circuit structure to generate the compensation current of the first offset voltage comprises: After determining the compensation direction of the first offset voltage, the calibration algorithm control circuit controls a first compensation value calculation sub-circuit in the specified compensation value calculation circuit to be turned on, and outputs a first binary code as a primary compensation value of the offset voltage, based on which a corresponding compensation current signal is generated; According to the output result of the comparator received again, it is determined whether the compensation current needs to be increased or decreased; if the compensation current needs to be increased, the corresponding second compensation value calculation sub-circuit is turned on through the calibration algorithm control circuit; if the compensation current needs to be decreased, the corresponding first compensation value calculation sub-circuit is turned off through the calibration algorithm control circuit, and the corresponding second compensation value calculation sub-circuit is turned on; the compensation currents output by the turned-on circuits are added to update the primary compensation current; According to the output result of the comparator received again, it is determined whether the compensation current needs to be increased or decreased; if the compensation current needs to be increased, the corresponding second compensation value calculation sub-circuit is turned on through the calibration algorithm control circuit; if the compensation current needs to be decreased, the corresponding first compensation value calculation sub-circuit is turned off through the calibration algorithm control circuit, and the corresponding second compensation value calculation sub-circuit is turned on; the compensation currents output by the turned-on circuits are added to update the primary compensation current; According to the output result of the comparator received again, it is determined whether the compensation current needs to be increased or decreased; if the compensation current needs to be increased, the corresponding second compensation value calculation sub-circuit is turned on through the calibration algorithm control circuit; if the compensation current needs to be decreased, the corresponding first compensation value calculation sub-circuit is turned off through the calibration algorithm control circuit, and the corresponding second compensation value calculation sub-circuit is turned on; the compensation currents output by the turned-on circuits are added to update the primary compensation current; 6. The misregulation voltage calibration circuit of claim 1, wherein, The second offset voltage calibration circuit comprises a third compensation value calculation circuit and a fourth compensation value calculation circuit; The third compensation value calculation circuit is connected to the output end of the calibration algorithm control circuit and connected to the compensation input positive terminal in the analog circuit to be calibrated; the fourth compensation value calculation circuit is connected to the output end of the calibration algorithm control circuit and connected to the compensation input negative terminal in the analog circuit to be calibrated; The manner in which the calibration algorithm control circuit controls the second offset voltage calibration circuit to determine the compensation direction of the second offset voltage according to the voltage direction of the second offset voltage and generate a corresponding compensation current to calibrate the second offset voltage comprises: The calibration algorithm control circuit determines the compensation direction of the second offset voltage according to the voltage direction of the second offset voltage, and determines whether the compensation direction is positive or negative; If the compensation direction is positive, the third compensation value calculation circuit generates a fifth compensation current of the second offset voltage to positively compensate the compensation input positive end, and the fourth compensation value calculation circuit generates a sixth compensation current of the second offset voltage to negatively compensate the compensation input negative end, through the control of the calibration algorithm control circuit. If the compensation direction is negative, the third compensation value calculation circuit generates a seventh compensation current of the second offset voltage to negatively compensate the compensation input positive end, and the fourth compensation value calculation circuit generates an eighth compensation current of the second offset voltage to positively compensate the compensation input negative end, through the control of the calibration algorithm control circuit.

7. The misregulation voltage calibration circuit of claim 6, wherein, The third compensation value calculation circuit comprises a first compensation unit and a second compensation unit, and the fourth compensation value calculation circuit comprises a third compensation unit and a fourth compensation unit. Each compensation unit comprises a fifth compensation value calculation sub-circuit, a sixth compensation value calculation sub-circuit, a seventh compensation value calculation sub-circuit and an eighth compensation value calculation sub-circuit. The compensation value calculation sub-circuits of the first compensation unit are connected in parallel, one end of which is connected to a power supply and the other end of which is connected to the compensation input positive end of the analog circuit to be calibrated; the compensation value calculation sub-circuits of the second compensation unit are connected in parallel, one end of which is connected to the compensation input positive end in the analog circuit to be calibrated and the other end of which is grounded; the compensation value calculation sub-circuits of the third compensation unit are connected in parallel, one end of which is connected to a power supply and the other end of which is connected to the compensation input negative end in the analog circuit to be calibrated; the compensation value calculation sub-circuits of the fourth compensation unit are connected in parallel, one end of which is connected to the compensation input negative end in the analog circuit to be calibrated and the other end of which is grounded; each compensation value calculation sub-circuit comprises a current array and a switch, which are used to output preset compensation currents after being turned on; the switches in each compensation value calculation sub-circuit are connected to the calibration algorithm control circuit, which are used to be closed or opened through the control of the calibration algorithm control circuit.

8. The misregulation voltage calibration circuit of claim 7, wherein, The compensation direction of the second offset voltage is determined according to the voltage direction of the second offset voltage, and corresponding compensation currents are generated to calibrate the second offset voltage, through the calibration algorithm control circuit, in the following manner: When the compensation direction of the second offset voltage is positive, the switch of the fifth compensation value calculation sub-circuit in the first compensation unit is closed and the switch of the fifth compensation value calculation sub-circuit in the second compensation unit is opened, through the calibration algorithm control circuit, to positively compensate the compensation input positive end through the third compensation value calculation circuit; meanwhile, the switch of the fifth compensation value calculation sub-circuit in the third compensation unit is opened and the switch of the fifth compensation value calculation sub-circuit in the fourth compensation unit is closed, through the calibration algorithm control circuit, to negatively compensate the compensation input negative end through the fourth compensation value calculation circuit. When the compensation direction of the second offset voltage is negative, the calibration algorithm control circuit controls the switch of the fifth compensation value calculation sub-circuit in the first compensation unit to be open and controls the switch of the fifth compensation value calculation sub-circuit in the second compensation unit to be closed, so as to compensate the positive end of the compensation input in the negative direction through the third compensation value calculation circuit; meanwhile, the switch of the fifth compensation value calculation sub-circuit in the third compensation unit is controlled to be closed and the switch of the fifth compensation value calculation sub-circuit in the fourth compensation unit is controlled to be open, so as to compensate the negative end of the compensation input in the positive direction through the fourth compensation value calculation circuit.

9. A method of calibrating a misregulated voltage, the method comprising: The offset voltage calibration method for calibrating an analog circuit to be calibrated by the offset voltage calibration circuit according to any one of claims 1 to 8, the offset voltage calibration method comprising: The calibration algorithm control circuit controls the comparator to be disconnected with the analog circuit to be calibrated and controls the two input ends of the comparator to be short-circuited and input a test voltage signal, so as to determine the voltage direction of the first offset voltage generated by the comparator according to the output result of the comparator; The calibration algorithm control circuit controls the first offset voltage calibration circuit to determine the compensation direction thereof according to the voltage direction of the first offset voltage and generates a corresponding compensation current, so as to calibrate the first offset voltage; The calibration algorithm control circuit controls the two input ends of the comparator to be disconnected and controls the two input ends of the comparator to be connected to the two differential output ends of the analog circuit to be calibrated again; the comparator compares the two differential signals output by the analog circuit to be calibrated, so as to determine the voltage direction of the second offset voltage generated by the analog circuit to be calibrated; The calibration algorithm control circuit controls the second offset voltage calibration circuit to determine the compensation direction thereof according to the voltage direction of the second offset voltage and generates a corresponding compensation current, so as to calibrate the second offset voltage.

10. A transmitter local oscillator leakage calibration system, characterized by, Comprise: The I in-phase signal calibration module comprises the offset voltage calibration circuit according to any one of claims 1 to 8, and is used for calibrating an I in-phase signal modulation circuit to calibrate the local oscillator leakage of a radio frequency transmitter chain; wherein the comparator in the offset voltage calibration circuit is connected to the output end of a low-pass filter in the I in-phase signal modulation circuit, and the second offset voltage calibration circuit in the offset voltage calibration circuit is connected to the input end of an operational amplifier in the low-pass filter; The Q quadrature signal calibration module comprises the offset voltage calibration circuit according to any one of claims 1 to 8, and is used for calibrating a Q quadrature signal modulation circuit to further calibrate the local oscillator leakage of a radio frequency transmitter chain; wherein the comparator in the offset voltage calibration circuit is connected to the output end of a low-pass filter in the Q quadrature signal modulation circuit, and the second offset voltage calibration circuit in the offset voltage calibration circuit is connected to the input end of an operational amplifier in the low-pass filter.

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