A time synchronization method, system and node device based on a shach bus

Abstract

The application discloses a time synchronization method and system based on a Shach bus and a node device, and the optimal synchronization master clock can be dynamically selected, the optimal synchronization master clock is determined in the process of network automatic reconstruction, the network reconstruction process is multiplexed, and communication pressure is reduced; in addition, the optimal master clock is taken as the center, the outer second node device performs clock counting synchronization to the secondary outer first node device through the optimal path port connected with the optimal master clock, clock synchronization is only performed between two adjacent nodes, information does not need to be directly sent to the optimal synchronization master clock, and network communication bandwidth resource consumption caused by time synchronization is reduced; further, in the interval period of twice interactive synchronization, the second node device calculates a compensation ratio through a recorded period clock number and a clock cumulative deviation, and the compensation is performed when it is predicted that 1 clock deviation is reached, so that high-precision clock synchronization is realized.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly to a time synchronization method, system, and node device based on the Shake bus. Background Technology

[0002] Precise time synchronization is a basic requirement for many industrial communication networks. Without precise time synchronization, network nodes cannot achieve efficient measurement, control, scheduling, and collaborative work.

[0003] Currently, in the network topology of a communication system composed of various network node devices, if a node device needs to achieve time synchronization, it needs to request data from a node device with a precise clock through other node devices. In this process, the data transmitted needs to pass through at least one node device, which results in a long data transmission process and different path lengths. Therefore, the accuracy of time synchronization achieved in this way is low. Summary of the Invention

[0004] In view of this, this application provides a time synchronization method, system, and node device based on the Shark bus, the specific solution of which is as follows:

[0005] A time synchronization method based on the Shark bus, applied to a second-node device, includes:

[0006] At each first time interval, the parameter information of the master clock contention vector is output to other node devices in the network, wherein at each first time interval, the network performs a reconstruction process;

[0007] Obtain the parameter information of the master clock contention vector output by each node device in the network, wherein the parameter information of the master clock contention vector includes at least the clock accuracy level, clock priority and average distance of all node devices to the current node device of the corresponding node device;

[0008] The sum of distances between each node and other node devices is determined based on the parameter information of the master clock contention vector of each node device in the network.

[0009] The node device with the smallest sum of distances to other node devices in the network is determined as the optimal node device with the optimal synchronization master clock, and the port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device is determined as the clock synchronization port.

[0010] The second node device and the node devices connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

[0011] Furthermore, the step of synchronizing the clock of the second node device and the node devices connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device includes:

[0012] If the second node device is the optimal node device, every second time interval, it outputs a clock count to other node devices connected to the second node device through the clock synchronization port, so that other node devices connected to the second node device through the clock synchronization port can adjust their clock counts to synchronize with the clock counts of the second node device;

[0013] Specifically, when the second node device synchronizes its clock with other connected node devices through its clock synchronization port, other node devices in the network synchronize their clocks with the node devices they are connected to through their clock synchronization ports.

[0014] Furthermore, the step of synchronizing the clock of the second node device and the node devices connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device includes:

[0015] If the second node device is a non-optimal node device, every second time interval, based on the clock count of the first node device connected to the clock synchronization port of the second node device, the clock count of the second node device is adjusted so that the adjusted clock count of the second node device is synchronized with the clock count of the first node device.

[0016] Furthermore, adjusting the clock count of the second node device based on the clock count of the first node device connected to the clock synchronization port of the second node device includes:

[0017] At a second moment, a clock synchronization command output by the first node device is obtained, the clock synchronization command carrying the first moment at which the first node device outputs the clock synchronization command;

[0018] At the third moment, feedback information based on the clock synchronization command is output to the first node device;

[0019] Obtain notification information output by the first node device, the notification information including at least: the fourth moment when the first node device obtains the feedback information;

[0020] Based on the first, second, third, and fourth time points, the clock count of the second node device is adjusted to synchronize with the clock count of the first node device.

[0021] Furthermore, the step of synchronizing the clock count of the second node device with the clock count of the first node device based on the first time point, the second time point, the third time point, and the fourth time point includes:

[0022] The offset of the clock signal of the second node device relative to the clock count of the first node device is determined based on the first time point, the second time point, the third time point, and the fourth time point.

[0023] The clock count of the second node device is adjusted based on the offset to synchronize the clock count of the second node device with that of the first node device.

[0024] Furthermore, the step of synchronizing the clock count of the second node device with the clock count of the first node device based on the first time point, the second time point, the third time point, and the fourth time point includes:

[0025] Based on the first, second, third, and fourth moments, the port module of the second node device adjusts the clock count of the second node device to synchronize with the clock count of the first node device. The port module of the second node device is different from the kernel of the second node device.

[0026] Furthermore, it also includes:

[0027] Based on the first time point, the second time point, the third time point, and the fourth time point, determine the interval time required for the clock count of the second node device and the clock count of the first node device to achieve error compensation;

[0028] When the interval duration is determined to be met, the clock count of the second node device is adjusted based on the compensation error to reduce the error between the adjusted clock count of the second node device and the clock count of the first node device.

[0029] Furthermore, determining the interval required for the second node device and the first node device to achieve error compensation based on the first time point, the second time point, the third time point, and the fourth time point includes:

[0030] A first time difference is determined between the first moments of two consecutive clock synchronization commands output by the first node device. The first node device outputs a clock synchronization command every clock cycle, and the duration of the clock cycle is equal to the first time difference.

[0031] Determine the second time difference between two consecutive moments when the second node device receives the clock synchronization command output by the first node device;

[0032] Determine the percentage difference between the clock count of the second node device and the clock count of the first node device based on the first time difference and the second time difference;

[0033] The number of counter counts required to compensate for a cumulative error of ±1 clock cycle or more is determined based on the percentage difference between the clock count of the second node device and the clock count of the first node device.

[0034] A second node device, comprising:

[0035] The first port module includes multiple first ports, each capable of connecting to different node devices. It is used to output the parameter information of the master clock contention vector to other node devices in the network through different first ports at intervals of a first time duration. During each first time interval, the network performs a reconstruction process. The module obtains the parameter information of the master clock contention vector output by each node device in the network. The parameter information of the master clock contention vector includes at least the clock accuracy level, clock priority, and average distance from all node devices to the current node device. Based on the parameter information of the master clock contention vector of each node device in the network, it determines the sum of distances between each node device and other node devices. The node device with the smallest sum of distances to other node devices is determined as the optimal node device with the optimal synchronization master clock. The first port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device is determined as the clock synchronization port. The second node device and the node devices connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

[0036] The first kernel is used to perform other signal processing operations besides the time synchronization process described above.

[0037] A time synchronization system based on the Shark bus includes:

[0038] Multiple node devices, wherein the multiple node devices include at least: a first node device and a second node device;

[0039] Every first time interval, the second node device outputs the parameter information of the master clock contention vector to other node devices in the network. Every first time interval, the network performs a reconstruction process. The network obtains the parameter information of the master clock contention vector output by each node device in the network. The parameter information of the master clock contention vector includes at least the clock accuracy level, clock priority, and average distance from all node devices to the current node device. Based on the parameter information of the master clock contention vector of each node device in the network, the network determines the sum of distances between each node device and other node devices. The node device with the smallest sum of distances to other node devices is determined as the optimal node device with the optimal master clock. The port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device is determined as the clock synchronization port. The second node device and the node devices connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

[0040] Specifically, when the second node device and the node device connected to the second node device through the clock synchronization port are performing clock synchronization, other node devices among the plurality of node devices perform clock synchronization with the node devices connected to them through the clock synchronization ports of the other node devices.

[0041] As can be seen from the above technical solutions, the time synchronization method, system, and node device based on the Shake bus disclosed in this application outputs the parameter information of the master clock contention vector to other node devices in the network at each first time interval. During each first time interval, the network performs a reconstruction process; obtains the parameter information of the master clock contention vector output by each node device in the network; determines the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock contention vector of each node device in the network; determines the port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device as the clock synchronization port; and performs clock synchronization on the second node device and the node devices connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device. This scheme dynamically selects the optimal master clock for synchronization. Furthermore, the optimal master clock is determined during the automatic network reconfiguration process, reusing the network reconfiguration process and reducing communication pressure. In addition, with the optimal master clock as the center, the outermost second node device performs clock counting synchronization to the next outermost first node device through the optimal path port linked to the optimal master clock. This ensures that clock synchronization only occurs between two adjacent nodes, without needing to directly send information to the optimal master clock, thus reducing the consumption of network-wide communication bandwidth resources caused by time synchronization. Moreover, within the interval between two interactive synchronization cycles, the second node device calculates the compensation ratio by recording the number of clock cycles and the cumulative clock deviation, and supplements the clock when a deviation of one clock cycle is expected, thereby achieving high-precision clock synchronization. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a flowchart of a time synchronization method based on the Shark bus disclosed in an embodiment of this application;

[0044] Figure 2 This is a schematic diagram of a clock synchronization process between a first node device and a second node device disclosed in an embodiment of this application;

[0045] Figure 3 A flowchart illustrating another time synchronization method based on the Sarker bus disclosed in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of a network topology of a Sarker bus disclosed in an embodiment of this application;

[0047] Figure 5 A flowchart illustrating yet another time synchronization method based on the Shark bus disclosed in this application;

[0048] Figure 6 This is a schematic diagram illustrating the data flow when the clocks of a first node device and a second node device are synchronized, as disclosed in an embodiment of this application.

[0049] Figure 7 A flowchart illustrating another time synchronization method based on the Sarker bus disclosed in an embodiment of this application;

[0050] Figure 8 This is a schematic diagram of a synchronization process that includes at least two adjacent clock synchronization cycles, as disclosed in an embodiment of this application.

[0051] Figure 9 This is a schematic diagram of the structure of a second node device disclosed in an embodiment of this application;

[0052] Figure 10 This is a schematic diagram of the structure of a time synchronization system based on the Shake bus disclosed in an embodiment of this application. Detailed Implementation

[0053] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is for explaining specific embodiments only and is not intended to limit the scope of this application.

[0054] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0055] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0056] This application discloses a time synchronization method based on the Sarker bus, applied to a second node device, the flowchart of which is shown below. Figure 1 As shown, it includes:

[0057] Step S11: Every first time interval, output the parameter information of the master clock contention vector to other node devices in the network, wherein every first time interval, the network performs a reconstruction process;

[0058] Step S12: Obtain the parameter information of the master clock contention vector output by each node device in the network. The parameter information of the master clock contention vector includes at least the clock accuracy level, clock priority, and average distance from all node devices to the current node device.

[0059] Step S13: Determine the sum of distances between each node device and other node devices based on the parameter information of the master clock contention vector of each node device in the network;

[0060] Step S14: Determine the node device with the smallest sum of distances to other node devices in the network as the optimal node device with the optimal synchronization master clock, and determine the port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device as the clock synchronization port.

[0061] Step S15: Synchronize the clock of the second node device and the node devices connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device.

[0062] The Sark bus, short for Free Topology Automatic Reconfiguration Network, is a high-speed, real-time, self-constructing network fieldbus. This bus adopts a specially designed network structure, which can realize end-to-end high-speed transmission and support multi-terminal parallel transmission within the network, thereby improving the total network throughput.

[0063] Time synchronization is the foundation for high-precision measurement, control, and scheduling in industrial networks. Currently, in networks composed of multiple nodes, if a node needs to achieve time synchronization, it needs to request data from a node with a precise clock through other nodes. This process requires the data to pass through at least one node, resulting in a long data transmission process and significant differences in path length. Consequently, the accuracy of time synchronization achieved in this way is relatively low.

[0064] To avoid this problem, this scheme determines the optimal master clock every first time interval, so that clock synchronization between two adjacent devices can be performed based on the optimal master clock. The optimal master clock is determined during the automatic network reconfiguration process, reusing the network reconfiguration process and reducing communication pressure. In addition, based on the progressive method of adjacent hierarchical clock synchronization, clock counting synchronization between adjacent node devices is achieved. This ensures that clock synchronization is performed only between two adjacent nodes, without the need to directly send information to the optimal master clock, thus reducing the consumption of network-wide communication bandwidth resources caused by time synchronization.

[0065] Specifically, at each first time interval, the network performs a reconstruction process. During the reconstruction process, the optimal synchronization master clock is re-determined to reuse the network reconstruction process. At the same time, no communication overhead is added during this process.

[0066] The network contains multiple nodes, each with no priority. Whenever the network is reconfigured after a first time interval, each node sends the master clock contention vector parameters to other nodes in the network. In other words, each node sends master clock contention vector parameters to other nodes, and simultaneously receives master clock contention vector parameters from all other nodes in the network.

[0067] The parameter information of the master clock contention vector output by each node device may include at least: forced master clock setting, clock priority setting, clock accuracy level, total distance, path information, ID identifier, etc., and different priority orders are assigned according to the impact of each parameter on the final synchronization effect.

[0068] Each node receives the parameter information of the master clock contention vector sent by other node devices in the network. Then, each node device can determine the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock contention vector of other node devices it receives and the parameter information of its own master clock contention vector. That is, each node device can determine the same optimal node device.

[0069] Once the optimal node device is determined, each node device can assign a clock synchronization port. This clock synchronization port is the port through which the node device receives the parameter information of the master clock contention vector output by the optimal node device. Each node device has multiple ports, and different ports can communicate with different node devices. However, if a node device wants to communicate with the nearest node to the optimal node device, it needs to do so through the clock synchronization port.

[0070] After determining the clock synchronization port of each node device, clock synchronization can be performed once every second time interval. Each clock synchronization is performed between two adjacent node devices. For example, the second node device synchronizes its clock count with the first node device. The clock synchronization port of the second node device is connected to the first node device, and the clock synchronization port of the first node device is connected to other node devices that are closer to the optimal node device. Ultimately, the optimal node device can be indirectly connected to the optimal node device through its clock synchronization port, so that the optimal node device can synchronize its clock with its adjacent node devices. The node device adjacent to the optimal node device can synchronize its clock with its own adjacent node devices, until the second node device synchronizes its clock with the first node device.

[0071] For example, if the second node is not the optimal node, the shortest path between the second and optimal nodes needs to be determined. For instance, if the second node's clock synchronization port is connected to the first node, the first node's clock synchronization port is connected to the third node, and the third node's clock synchronization port is connected to the optimal node, then the optimal node's clock count is the most accurate relative to the other nodes. Therefore, the third node first synchronizes its clock with the optimal node through its own clock synchronization port to ensure a more accurate clock signal. Then, the first node synchronizes its clock with the third node through its own clock synchronization port, and finally, the second node synchronizes its clock with the first node through its own clock synchronization port.

[0072] In addition, if the second node device is the optimal node device, then after determining that the second node device is the optimal node device, the node devices directly connected to the second node device will synchronize with the second node device. After that, time synchronization will be performed layer by layer outward. For example, if the second node device is the optimal node device, the clock synchronization port of the third node device is directly connected to the second node device, and the clock synchronization port of the fourth node device is directly connected to the third node device, then the third node device will first synchronize with the second node device, and then the fourth node device will synchronize with the third node device, so as to achieve clock synchronization layer by layer.

[0073] Specifically, the optimal node device with the optimal synchronization master clock is determined based on the parameter information of the master clock contention vector of each node device in the network. This includes: determining the sum of the distances between each node device and other node devices based on the parameter information of the master clock contention vector of each node device in the network; and determining the node device with the smallest sum of distances between it and other node devices as the optimal node device with the optimal synchronization master clock.

[0074] Each node device compares the sum of the distances between itself and other nodes in the network to determine the node device with the shortest distance. This node device is then identified as the optimal node device, and its clock count is determined as the optimal synchronization master clock.

[0075] After determining the optimal node device and the clock synchronization port of each node device, the second node device and the node devices connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

[0076] If the second node device is the optimal node device, then every second time interval, the clock count is output to other node devices connected to the second node device through the clock synchronization port, so that other node devices connected to the second node device through the clock synchronization port can adjust their clock count to synchronize with the clock count of the second node device.

[0077] For example, if the first node device is connected to the second node device through a clock synchronization port, the second node device outputs a clock count to the first node device every second time interval. The first node device synchronizes its clock count with that of the second node device based on this clock synchronization signal.

[0078] If the second node device is a non-optimal node device, every second time interval, based on the clock count of the first node device connected to the clock synchronization port of the second node device, the clock count of the second node device is adjusted so that the adjusted clock count of the second node device is synchronized with the clock count of the first node device.

[0079] If the second node device is a non-optimal node device, then the second node device has a clock synchronization port. In this case, the second node device can directly connect to the optimal node device through the clock synchronization port. Then the second node device can directly obtain the clock count output by the optimal node device every second time interval, thereby realizing the synchronization of the second node device to the optimal node device.

[0080] If the second node is not the optimal node and is not directly connected to the optimal node, the optimal node can first send clock counts to the node directly connected to it. After the node directly connected to the optimal node completes clock synchronization with the optimal node, the node directly connected to the optimal node will send clock counts to the node directly connected to it to achieve layer-by-layer clock synchronization. For example, if the third node is directly connected to the optimal node and the second node is directly connected to the third node, the optimal node will send clock counts to the third node. After the third node completes clock synchronization with the optimal node based on the clock counts, the third node can output clock counts, such as outputting clock counts to the second node. The second node can then complete clock synchronization based on the clock counts output by the third node.

[0081] It should be noted that regardless of whether the second node device is the optimal node device, while the second node device is synchronizing its clock with a certain node device, other nodes in the network can also synchronize their clocks with the connected node devices through their clock synchronization ports. This allows each node device in the network to synchronize its clock with its adjacent node devices. Therefore, during the clock synchronization process, the clock synchronization between different node devices does not interfere with each other. It is not necessary for a certain node device to synchronize its clock with the optimal node device while not directly connected to it, thus avoiding the problem of consuming too much bandwidth and causing an increase in uncertain latency.

[0082] Furthermore, adjusting the clock count of the second node device based on the clock count of the first node device connected to the clock synchronization port of the second node device can be achieved as follows:

[0083] At the second moment, the clock synchronization command output by the first node device is obtained, and the clock synchronization command carries the first moment of the clock synchronization command output by the first node device; at the third moment, feedback information based on the clock synchronization command is output to the first node device; notification information output by the first node device is obtained, and the notification information includes at least the fourth moment when the first node device obtains the feedback information; the clock count of the second node device is adjusted to synchronize with the clock count of the first node device based on the first moment, the second moment, the third moment and the fourth moment.

[0084] For any node device in the network topology, it can be designated as the second node device. The node device connected to the clock synchronization port of the second node device can be designated as the first node device. In the network topology, a device does not always act as the first node device or always as the second node device. Whether a device is the first or second node device depends on the accuracy of its current clock count and the relative positional relationship between the nodes. For example, when a device synchronizes towards the optimal master clock, it is a second node device, but when an outer device synchronizes towards it, it acts as the first device. Also, after a certain optimal master clock determination process, the relationship between the first and second node devices is fixed, but when the optimal master clock is updated, the relationship between the first and second node devices may change.

[0085] This can be done as follows: Clock synchronization between adjacent node devices is performed once every second time interval. At this time, the first node device can initiate port probe to all valid ports and send instruction pack1 to the node device connected to the port of the first node device; the connected node device returns information pack2 to the first node device. This process enables the first node device to determine whether the port is valid.

[0086] If the clock synchronization port of the second node device is the same port it connects to the first node device, then the second node device will mark a time synchronization request in the return information pack2. Upon receiving return information pack2, the first node device completes a port probe. However, if the time synchronization request mark in return information pack2 is valid, the first node device will send information pack3 to the second node device. In this case, the clock synchronization instructions required for time synchronization between the second and first node devices can reuse instruction pack1, the feedback information can reuse return information pack2, and the notification information can reuse pack3. This reuse reduces communication overhead. Furthermore, since the time synchronization process only occurs between two adjacent nodes, there is no need to directly send information to the master clock, greatly reducing the consumption of network-wide communication bandwidth resources caused by time synchronization.

[0087] When a second node device receives a clock synchronization command from its neighboring first node device, the moment when the second node device receives the clock synchronization command is recorded and designated as the second time T2. The first time T1 is the moment when the first node device outputs the clock synchronization command; that is, when the first node device outputs the clock synchronization command, it adds the first time of its output command to the clock synchronization command, or it outputs the first time and the clock synchronization command simultaneously to the second node device. Therefore, the first time is the moment determined by the first node device's clock count when it outputs the clock synchronization command, while the second time is the moment determined by the second node device's clock count when it receives the clock synchronization command.

[0088] After receiving the clock synchronization command from the first node device, the second node device will output feedback information based on the clock synchronization command to the first node device at a third time T3. This feedback information is only used to send a message to the first node device after determining that synchronization is needed based on the clock synchronization command, so as to determine when the first node device receives the feedback information. The third time T3 is the time at which the second node device outputs the feedback information, determined by its clock count.

[0089] The time difference between the third time T3 and the second time T2 is used to store the received clock synchronization instruction in the register.

[0090] The first node device receives the feedback information. The first node device itself knows that the feedback information was received at the fourth time T4 according to the clock count of the first node device. In order for the second node device to also know the time when the first node device received the feedback information, it is necessary to send the timestamp information of the fourth time T4 to the second node device. This allows the second node device to know when the first node device received the feedback information. Specifically, the first node device outputs a notification information at the fifth time T5 according to the clock count of the first node device. This notification information includes at least the fourth time T4. The second node device receives the notification information at the sixth time T6 according to its own clock count.

[0091] After the above process is completed, the second node device will determine at least four times: the first time T1, the second time T2, the third time T3, and the fourth time T4. The first time T1 and the fourth time T4 are determined according to the clock count of the first node device, while the second time T2 and the third time T3 are determined according to the clock count of the second node device.

[0092] Specifically, such as Figure 2 As shown, it includes: the clock of the first node device and the clock of the second node device. The first node device outputs a clock synchronization command at a first time T1 on its clock. The second node device receives the clock synchronization command at a second time T2 on its clock. Then, when the clock of the second node device is at a third time T3, the second node device outputs feedback information to the first node device. The first node device receives the feedback information when the clock of the first node device is at a fourth time T4. Then, when the clock of the first node device is at a fifth time T5, the first node device sends a notification message to the second node device, which includes at least the fourth time T4. The second node device receives the notification message when the clock of the second node device is at a sixth time T6.

[0093] By determining the four times when the clock counts of the two node devices are determined, the clock count of the second node device can be synchronized with the clock count of the first node device, so that the clock counts of the second node device and the clock counts of the first node device can remain synchronized.

[0094] The time synchronization method based on the Shake bus disclosed in this embodiment outputs the parameter information of the master clock contention vector to other node devices in the network at each first time interval. During each first time interval, the network performs a reconstruction process. The method obtains the parameter information of the master clock contention vector output by each node device in the network. The parameter information of the master clock contention vector includes at least the clock accuracy level and clock priority of the corresponding node device. Based on the parameter information of the master clock contention vector of each node device in the network, the method determines the sum of the distances between each node device and other node devices. The node device with the smallest sum of distances to other node devices is determined as the optimal node device with the optimal synchronization master clock. The port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device is determined as the clock synchronization port. The second node device and the node devices connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device. In this scheme, the optimal synchronization master clock is dynamically adjusted, and the optimal synchronization master clock is determined during the automatic network reconfiguration process, reusing the network reconfiguration process and reducing communication pressure. In addition, with the optimal master clock as the center, the outer second node device performs clock counting synchronization to the next outer first node device through the optimal path port connected to the optimal master clock (the clock on the optimal node device is the optimal master clock). This realizes that clock synchronization only occurs between two adjacent nodes, without the need to send information directly to the optimal synchronization master clock, thus reducing the consumption of network-wide communication bandwidth resources caused by time synchronization.

[0095] This embodiment discloses a time synchronization method based on the Sarker bus, applied to a second node device, and its flowchart is as follows: Figure 3 As shown, it includes:

[0096] Step S31: Determine the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock contention vector of each node device in the network, and determine the port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device as the clock synchronization port.

[0097] Step S32: Obtain the clock synchronization command output by the first node device at the second time. The clock synchronization command carries the first time of the clock synchronization command output by the first node device.

[0098] Step S33: At the third moment, output feedback information based on the clock synchronization command to the first node device;

[0099] Step S34: Obtain the notification information output by the first node device. The notification information shall include at least the fourth moment when the first node device receives the feedback information.

[0100] Step S35: Determine the offset of the clock count of the second node device relative to the clock count of the first node device based on the first time, the second time, the third time, and the fourth time.

[0101] Step S36: Adjust the clock count of the second node device based on the offset to synchronize the clock signal of the second node device with the clock count of the first node device.

[0102] When the second node device determines the first and fourth moments of the clock count based on the clock synchronization command output by the first node device, and the second and third moments of the clock signal based on the first node device, the second node device can determine the offset of the clock count of the second node device relative to the clock signal of the first node device based on the above four moments, that is, the deviation between the clock count of the second node device and the clock count of the first node device.

[0103] Specifically, according to Figure 2 The clock synchronization process between the first node device and the second node device shown can be obtained as follows:

[0104] Formula (1)

[0105] in, The deviation between the clock count of the first node device and the clock count of the second node device. Given the time required for data transmission between the first node device and the second node device, the deviation between the clock count of the first node device and the clock count of the second node device can be determined based on the above formula (1):

[0106]

[0107] The deviation between the clock count of the first node and the clock count of the second node. This refers to the offset of the clock count of the second node device relative to the clock count of the first node device. Adjusting this offset based on the clock count of the second node device will yield a clock count that is synchronized with the clock count of the first node device.

[0108] Furthermore, since the time synchronization method disclosed in this embodiment is for time synchronization of two directly cascaded node devices, if a problem is detected in any node device in the network topology, or if dynamic route reconstruction is performed at the end of a time synchronization period, any routing device and its downstream node devices may form a new topology. Each topology can be time synchronized independently according to the above scheme, without affecting each other.

[0109] The time synchronization method based on the Sarker bus disclosed in this embodiment obtains a clock synchronization command output by a first node device at a second time. The clock synchronization command carries the first time at which the first node device outputs the clock synchronization command. The first node device is a node device directly connected to a second node device. Feedback information based on the clock synchronization command is output to the first node device at a third time. Notification information output by the first node device is obtained. The notification information includes at least the fourth time at which the first node device obtains the feedback information. The offset of the clock count of the second node device relative to the clock count of the first node device is determined based on the first, second, third, and fourth times. The clock count of the second node device is adjusted based on the offset to synchronize the clock count of the second node device with the clock count of the first node device. In this scheme, a node device whose current clock counting accuracy is greater than a preset threshold sends a clock synchronization command to a directly connected node device. This allows a second directly connected node device to adjust its clock count based on the clock count of the first node device, achieving clock synchronization between the second and first node devices. The scheme ensures that any node device adjacent to a node with an accuracy greater than the preset threshold can complete clock counting synchronization, improving accuracy. It also avoids the problems of long data transmission times and low clock synchronization accuracy caused by data transfer through several node devices during clock counting synchronization. The offset between the clock counts of the second and first node devices can be determined at the first, second, third, and fourth moments, allowing for adjustment of the second node device's clock count and ensuring accurate clock synchronization.

[0110] Furthermore, in the time synchronization method based on the Shake bus disclosed in this embodiment, the first node device can be a node device that does not require clock synchronization, or a node device that completes clock synchronization within a time period of a first preset duration from the first time point.

[0111] Specifically, such as Figure 4 The diagram shown is a network topology of the Shakebus, which includes a routing device and a terminal. The routing device includes a top node device 401 and an intermediate node device 402. The terminal is represented by 403 in the network topology. Figure 4 The network topology shown consists of seven layers, including routing devices and terminals. The top node device 401 is located in the first layer from top to bottom, and so on. The terminal 403 is located in the seventh layer from top to bottom.

[0112] SharkNet can be configured into any topology through arbitrary plug-in connections. Figure 4This is just one example, and it does not limit all network topologies.

[0113] exist Figure 4 This paper presents a top-down, periodic, progressive network node time synchronization scheme (in a free topology, this is a clock synchronization scheme for network nodes that is progressive from the inside out, centered on the optimal master clock). In this scheme, only two directly cascaded network node devices are synchronized at a time. Within each cycle, synchronization proceeds from the top node downwards, that is, clock synchronization commands are output from the first-layer node device to the second-layer node device to adjust the clock count of the second-layer node device so that it is synchronized with the clock count of the first-layer node device. After the clock synchronization of the second-layer node device is completed, clock synchronization commands are output from the second-layer node device to the third-layer node device to adjust the clock count of the third-layer node device so that it is synchronized with the clock count of the second-layer node device. This process continues until the clock counts of the seventh-layer terminal and the sixth-layer node device are synchronized, thus completing one cycle of clock synchronization for all node devices in the network architecture.

[0114] In the entire network topology, if the clock signal of the top node device is determined to be the most accurate based on the parameter information of the master clock contention vector, then if the first node device is the optimal master clock device, i.e., the optimal node device, then the first node device is a node device that does not need to perform clock synchronization. Therefore, when performing time synchronization in the entire network topology, the first node device first outputs a clock synchronization signal to the second-layer node device directly cascaded with it so that the second-layer node device can complete clock synchronization. Then, the second-layer node device outputs a clock synchronization signal to the third-layer node device directly cascaded with it so that the third-layer node device can complete clock synchronization, until all node devices in the network topology have completed clock synchronization.

[0115] If a particular intermediate node is determined to have the most accurate clock count, then during time synchronization, this intermediate node first outputs a clock synchronization signal to the directly cascaded nodes, enabling them to synchronize their clocks. Then, the synchronization extends outwards to synchronize all nodes in the network topology. It's important to note that the outward synchronization behavior of each layer of nodes is independent of other nodes; each node synchronizes independently and in parallel during its own period.

[0116] Furthermore, the first node device may not necessarily be the node device with the most accurate clock count in the entire network topology. That is, when the entire network topology performs clock synchronization, the node device with the most accurate clock count in the network topology is first determined. Then, this node device first outputs a clock synchronization signal to the node device directly cascaded with it. If the node device directly cascaded with it completes clock synchronization, when this node device outputs a clock synchronization signal, it is not the node device with the most accurate clock count in the entire network topology, but rather a node device that completed clock synchronization within a period of a first preset time interval from the first time point. That is, this node device is a node device that has just completed clock synchronization. At this time, it can also output a clock synchronization command to the node device directly cascaded with it to complete the clock synchronization between each pair of node devices in the entire network topology. The information used for time synchronization does not need to be transmitted between many devices, which greatly enhances the time synchronization rate and reliability of the network topology.

[0117] This embodiment discloses a time synchronization method based on the Sarker bus, applied to a second node device, and its flowchart is as follows: Figure 5 As shown, it includes:

[0118] Step S51: Based on the parameter information of the master clock contention vector of each node device in the network, determine the optimal node device where the optimal synchronization master clock is located, and determine the port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device as the clock synchronization port.

[0119] Step S52: Obtain the clock synchronization command output by the first node device at the second time. The clock synchronization command carries the first time of the clock synchronization command output by the first node device.

[0120] Step S53: At the third moment, output feedback information based on the clock synchronization command to the first node device;

[0121] Step S54: Obtain the notification information output by the first node device. The notification information shall include at least the fourth moment when the first node device receives the feedback information.

[0122] Step S55: Based on the first time, second time, third time and fourth time, adjust the clock count of the second node device in the port module of the second node device to synchronize with the clock count of the first node device. The port module of the second node device is different from the kernel of the second node device.

[0123] In the time synchronization method based on the Shake bus disclosed in this embodiment, any node device in the network topology includes a kernel and a port module. The time synchronization method disclosed in this embodiment is applied to the port module in the second node device.

[0124] Specifically, any node device can include a kernel, a data buffer, and a port module. The port module can directly connect to other node devices. The kernel processes the data within the node device, the data buffer caches the data, and the port module processes the data that needs to be transmitted during time synchronization. This allows data to be transmitted directly after processing by the port module, bypassing the kernel and thus increasing network throughput by eliminating the need for kernel processing time.

[0125] When the first node device and the second node device synchronize their time, the schematic diagram is as follows: Figure 6 As shown, it includes: a first node device and a second node device, wherein the second node device includes: a first kernel 61, a first data cache 62, and a first port module 63, and the first node device includes: a second kernel 64, a second data cache 65, and a second port module 66.

[0126] The first kernel is connected to the first data buffer, the first data buffer is connected to the first port module, the second kernel is connected to the second data buffer, the second data buffer is connected to the second port module, and the first port module is connected to the second port module.

[0127] In the time synchronization process disclosed in this embodiment, all operations are performed at the port module of the node device. That is, the information exchange and execution during the time synchronization process are carried out between the second port module of the first node device and the first port module of the second node device. The information exchanged during the time synchronization process does not need to be transmitted to the first kernel and the second kernel.

[0128] In the second node device, the first port module of the second node device obtains the clock synchronization command output by the first node device at the second time. The first port module outputs feedback information based on the clock synchronization command to the first node device at the third time. The feedback information is also generated by the first port module based on the clock synchronization command. The first port module obtains the notification information output by the first node device. Furthermore, the clock count of the second node device is synchronized with the clock count of the first node device by the first port module based on the first time, the second time, the third time, and the fourth time.

[0129] Similarly, in the first node device, the second port module of the first node outputs a clock synchronization command carrying the clock of the first moment to the second node device at the first moment. The second port module receives feedback information at the fourth moment and outputs notification information including at least the fourth moment to the second node device. The generation of the notification information is also implemented by the second port module.

[0130] During time synchronization, both information exchange and the generation of instructions or information are implemented in the port module, independent of the node device's kernel. Data does not enter the node device's kernel, which improves the efficiency of time synchronization. Furthermore, by timestamping at the port layer (i.e., the physical layer) and returning the timestamp to the port layer of the node device with which it is synchronizing, the accuracy of time synchronization can be improved.

[0131] The time synchronization method based on the Sarker bus disclosed in this embodiment obtains a clock synchronization command output by a first node device at a second time. The clock synchronization command carries the first time at which the first node device outputs the clock synchronization command. The first node device is a node device directly connected to a second node device. Feedback information based on the clock synchronization command is output to the first node device at a third time. Notification information output by the first node device is obtained. The notification information includes at least the fourth time at which the first node device obtains the feedback information. Based on the first, second, third, and fourth times, the clock count of the second node device is adjusted in the port module of the second node device to synchronize with the clock count of the first node device. In this scheme, the first node device sends a clock synchronization command to the node device directly connected to it, so that the second node device directly connected to it can adjust its clock count based on the clock count of the first node device, thereby achieving clock count synchronization between the second node device and the first node device. This scheme ensures clock count synchronization and improves synchronization accuracy by having a node device with a clock count accuracy greater than a preset threshold actively request time synchronization from its neighboring node devices. At the same time, it avoids the problem of long data transmission process and low clock synchronization accuracy caused by the need to transmit data through several node devices when performing clock count synchronization. In addition, when performing time synchronization between node devices, any information transmitted during the time synchronization process does not pass through the node device kernel, but is directly synchronized at the port module of the node device that can connect to other node devices, thereby improving information transmission efficiency, avoiding the occupation of the node device kernel processing time, and improving the throughput of the entire network architecture.

[0132] This embodiment discloses a time synchronization method based on the Sarker bus, applied to a second node device, and its flowchart is as follows: Figure 7 As shown, it includes:

[0133] Step S71: Determine the optimal node device where the optimal synchronization master clock is located based on the parameter information of the master clock contention vector of each node device in the network, and determine the port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device as the clock synchronization port.

[0134] Step S72: Obtain the clock synchronization command output by the first node device at the second time. The clock synchronization command carries the first time of the clock synchronization command output by the first node device.

[0135] Step S73: At the third moment, output feedback information based on the clock synchronization command to the first node device;

[0136] Step S74: Obtain the notification information output by the first node device. The notification information shall include at least the fourth moment when the first node device receives the feedback information.

[0137] Step S75: Determine the time interval required to compensate for the error between the clock count of the second node device and the clock count of the first node device based on the first time, the second time, the third time, and the fourth time.

[0138] Step S76: When the interval duration is determined to be met, adjust the clock count of the second node device based on the compensation error so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced.

[0139] The main body of the Shake bus consists of a routing device and an interface board. A crystal oscillator is used to provide the reference frequency for the system. However, since the crystal oscillator itself has errors, the clock error between the routing device and the interface board will gradually increase with the increase of working time. Moreover, this error will always exist and is constantly changing.

[0140] To mitigate the clock counting errors between adjacent nodes caused by inherent errors in the crystal oscillator, this solution adds dynamic time compensation to the periodic clock synchronization based on clock synchronization commands. This improves the synchronization accuracy between nodes within the network structure, achieving nanosecond-level synchronization requirements for bus communication. Furthermore, the improved synchronization accuracy during the interval between two interactive synchronizations depends on the internal compensation of the node, rather than on the first node device.

[0141] The synchronization process of a single clock synchronization cycle is as follows: Figure 2 As shown, data exchange occurs between T1 and T6 to achieve clock synchronization between two node devices within this clock synchronization cycle. For synchronization processes that include at least two adjacent clock synchronization cycles, as shown... Figure 8 As shown, it includes: a first clock synchronization period 801 and a second clock synchronization period 802.

[0142] The first clock synchronization cycle 801 includes: information sent by the first node device to the second node device from the first time point T1 to the sixth time point T6, until the first node device reaches the next first time point T1 after a second time interval, and also includes information sent by the second node device to the first node device during this time interval; the second clock synchronization cycle 802 includes: the second time point T2 after the second node device receives the clock synchronization command sent by the first node device, until the next second time point T2 after a certain time interval, and also includes the above information interaction process. Of course, in the network architecture, interaction time synchronization is performed periodically, and does not only include two clock synchronization cycles. Figure 8 The following explanation uses two clock synchronization cycles as an example. In addition, since the network architecture includes multiple node devices, different node devices in the same network architecture synchronize with their respective first node devices according to this rule.

[0143] At regular intervals, the first node device sends a clock synchronization command to the second node device. The interval is defined relative to the clock count of the first node device.

[0144] Within each clock synchronization cycle, from the first time T1 to the second time T2, the clock synchronization command of the first node device is output to the second node device. After receiving the clock synchronization command at the second time T2, the second node device immediately outputs feedback information at the third time T3. After receiving the feedback information at the fourth time T4, the first node device immediately sends a notification information at the fifth time T5. After a certain interval, the next time clock synchronization command is sent, the first time T1 is reached. No other processing is performed in between. This makes the time required for the interactive synchronization process within the entire clock synchronization cycle shorter, increasing the stability and reliability of the entire system.

[0145] After interactive synchronization, due to the inherent error of the crystal oscillator, each clock synchronization process will generate errors. After a period of time, these errors will accumulate significantly, affecting the communication process. Therefore, the longer the interval between two adjacent clock synchronization cycles, the greater the error generated by the crystal oscillator will be. To reduce the error between the two node devices during clock synchronization between two adjacent clock synchronization cycles, dynamic time compensation is added.

[0146] Time compensation within the two interactive synchronization time intervals is implemented independently by the second node device. Based on the first, second, third, and fourth moments obtained in each clock synchronization cycle, the error between the clock count of the second node device and the clock count of the first node device can be determined. Meanwhile, the second clock synchronization period is obtained from the count between the two T2 times, and time compensation is performed based on these two parameters.

[0147] Specifically, the first time difference between the first moments when the first node device outputs clock synchronization commands in two consecutive instances is determined. The first node device outputs clock synchronization commands every clock synchronization cycle, and the duration of one clock cycle is equal to the first time difference. The second time difference ΔT2 between the second moments when the second node device receives the clock synchronization commands output by the first node device in two consecutive instances is determined. The second time difference is approximately equal to the first time difference. The clock counting deviation between the two node devices is determined based on the aforementioned interactive synchronization algorithm, i.e., the number of interactive synchronization clock deviations N. The number of counter counts m required to achieve error compensation is determined based on the second time difference ΔT2 and the number of interactive synchronization clock deviations N.

[0148] m = △T² / ABS(N)

[0149] Where ABS(N) represents the absolute value of the number N of interactive synchronization clock deviations.

[0150] That is, when the clock count of the second node device increases by m, it automatically increases or decreases the count by 1 according to the sign of N to compensate. This makes the clock count of the second node device approximately within ±1 clock cycle of the clock count of the first node device.

[0151] Multiple dynamic time compensations are performed between every two adjacent clock synchronization cycles, dynamically calibrating the time error between the first node device and the second node device, thereby improving the accuracy and reliability of the Shaker bus communication system.

[0152] The time synchronization method based on the Sarker bus disclosed in this application obtains a clock synchronization command output by a first node device at a second time, the clock synchronization command carrying the first time of the clock synchronization command output by the first node device, the first node device being a node device directly connected to a second node device; outputs feedback information based on the clock synchronization command to the first node device at a third time; obtains notification information output by the first node device, the notification information including at least a fourth time in which the first node device obtains the feedback information; determines the interval length required to compensate for the error between the clock signal of the second node device and the clock count of the first node device based on the first time, second time, third time, and fourth time; when the interval length is determined to be satisfied, adjusts the clock count of the second node device based on the error compensation, so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced. In this scheme, a node device whose current clock counting accuracy is greater than a preset threshold sends a clock synchronization command to a directly connected node device. This allows a second directly connected node device to adjust its clock count based on the first node device's clock count, achieving clock synchronization between the second and first node devices. This scheme, where the first node device actively requests time synchronization from adjacent node devices, ensures clock signal synchronization, improves synchronization accuracy, and avoids the problems of long data transmission processes and low clock synchronization accuracy caused by data transmission through several node devices during clock counting synchronization. Furthermore, this scheme, besides using clock synchronization commands... In addition to periodic time synchronization, this system can also adjust the clock count of the second node device by compensating for errors when the interval between the clock counts of the two node devices reaches the required interval duration. Specifically, within the interval between two interactive synchronization cycles, the second node device calculates the compensation ratio by recording the number of periodic clocks and the cumulative clock deviation, and supplements the clock when it is expected to reach one clock deviation. This enables dynamic time compensation in addition to periodic time synchronization, dynamically calibrating the clock error between the two node devices, increasing the accuracy and reliability of communication between node devices, reducing the accumulation of errors caused by crystal oscillators, and achieving high-precision clock synchronization.

[0153] This embodiment discloses a second node device, the structural schematic diagram of which is shown below. Figure 9 As shown, it includes:

[0154] First port module 91 and first kernel 92.

[0155] The first port module 91 includes multiple first ports, each capable of connecting to different node devices. It is used to output the parameter information of the master clock contention vector to other node devices in the network through different first ports at intervals of a first duration. During each first duration interval, the network performs a reconstruction process. The module obtains the parameter information of the master clock contention vector output by each node device in the network. The parameter information of the master clock contention vector includes at least the clock accuracy level, clock priority, and average distance from all node devices to the current node device. Based on the parameter information of the master clock contention vector of each node device in the network, the module determines the sum of distances between each node device and other node devices. The node device with the smallest sum of distances to other node devices is determined as the optimal node device with the optimal synchronization master clock. The first port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device is determined as the clock synchronization port. The second node device and the node devices connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

[0156] The first core 92 is used to perform other signal processing operations besides the time synchronization process described above.

[0157] Furthermore, the first port module is used for:

[0158] If the second node device is the optimal node device, every second time interval, the clock count is output to other node devices connected to the second node device through the clock synchronization port, so that other node devices connected to the second node device through the clock synchronization port can adjust their clock count to synchronize with the clock count of the second node device;

[0159] Specifically, when the second node device synchronizes its clock with other connected node devices through its clock synchronization port, other node devices in the network synchronize their clocks with the node devices they are connected to through their clock synchronization ports.

[0160] Furthermore, the first port module is used for:

[0161] If the second node device is a non-optimal node device, every second time interval, based on the clock count of the first node device connected to the clock synchronization port of the second node device, the clock count of the second node device is adjusted so that the adjusted clock count of the second node device is synchronized with the clock count of the first node device.

[0162] Furthermore, the first port module is used for:

[0163] Based on the parameter information of the master clock contention vector of each node device in the network, the sum of the distances between each node device and other node devices is determined; the node device with the smallest sum of distances between it and other node devices in the network is determined as the optimal node device with the optimal synchronized master clock.

[0164] Furthermore, the first port module is used for:

[0165] At a second time, the clock synchronization command output by the first node device is obtained, and the clock synchronization command carries the first time of the clock synchronization command output by the first node device; at a third time, feedback information based on the clock synchronization command is output to the first node device; notification information output by the first node device is obtained, and the notification information includes at least: the fourth time when the first node device obtains the feedback information; and the clock count of the second node device is adjusted to synchronize with the clock count of the first node device based on the first time, the second time, the third time and the fourth time.

[0166] Furthermore, the first port module is used for:

[0167] The offset of the clock count of the second node device relative to the clock count of the first node device is determined based on the first time point, the second time point, the third time point, and the fourth time point; the clock count of the second node device is adjusted based on the offset to synchronize the clock count of the second node device with the clock count of the first node device.

[0168] Furthermore, the first port module is used for:

[0169] Based on the first, second, third, and fourth time points, the port module of the second node device adjusts the clock count of the second node device to synchronize with the clock count of the first node device.

[0170] Furthermore, the first port module is also used for:

[0171] Based on the first, second, third, and fourth time points, determine the interval required to compensate for the error between the clock count of the second node device and the clock count of the first node device; when the interval is determined to be satisfied, adjust the clock count of the second node device based on the error compensation so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced.

[0172] Furthermore, the first port module is used for:

[0173] Determine the first time difference between the first moments when the first node device outputs a clock synchronization command on two consecutive occasions. The first node device outputs a clock synchronization command every clock cycle, and the duration of one clock cycle is equal to the first time difference. Determine the second time difference between the second moments when the second node device receives the clock synchronization command output by the first node device on two consecutive occasions. Based on the first and second time differences, determine the percentage difference between the clock count of the second node device and the clock count of the first node device. Based on the percentage difference between the clock count of the second node device and the clock count of the first node device, determine the number of counter counts required to achieve error compensation.

[0174] The kernel can be the processor inside the node device, such as the CPU.

[0175] The second node device disclosed in this embodiment is implemented based on the time synchronization method based on the Shake bus disclosed in the above embodiment, and will not be described again here.

[0176] The second node device disclosed in this embodiment outputs the parameter information of the master clock contention vector to other node devices in the network at each first time interval. During each first time interval, the network performs a reconstruction process. It obtains the parameter information of the master clock contention vector output by each node device in the network, where the parameter information includes at least the clock accuracy level and clock priority of the corresponding node device. Based on the parameter information of the master clock contention vector of each node device in the network, it determines the sum of the distances between each node device and other node devices. The node device with the smallest sum of distances to other node devices in the network is determined as the optimal node device with the optimal synchronization master clock. The port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device is determined as the clock synchronization port. The second node device and the node devices connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device. In this scheme, the optimal master clock is dynamically adjusted, and the optimal master clock is determined during the automatic network reconfiguration process, reusing the network reconfiguration process and reducing communication pressure. In addition, with the optimal master clock as the center, the outer second node device performs clock counting synchronization to the next outer first node device through the optimal path port linked to the optimal master clock. This realizes that clock synchronization only occurs between two adjacent nodes, without the need to send information directly to the optimal master clock, reducing the consumption of network-wide communication bandwidth resources caused by time synchronization. Furthermore, within the interval between two interactive synchronization cycles, the second node device calculates the compensation ratio by recording the number of periodic clocks and the cumulative clock deviation, and supplements when it is expected to reach 1 clock deviation, thereby achieving high-precision clock synchronization.

[0177] This embodiment discloses a time synchronization system based on the Shake bus, the schematic diagram of which is shown below. Figure 10 As shown, it includes:

[0178] Multiple node devices, including at least: a first node device 101 and a second node device 102.

[0179] Every first time interval, the second node device outputs the parameter information of the master clock contention vector to other node devices in the network. During this first time interval, the network performs a reconstruction process. The network obtains the parameter information of the master clock contention vector output by each node device in the network. This parameter information includes at least the clock accuracy level, clock priority, and average distance from all node devices to the current node device. Based on the parameter information of the master clock contention vector of each node device in the network, the network determines the sum of distances between each node device and other node devices. The node device with the smallest sum of distances to other node devices is determined as the optimal node device with the optimal master clock. The port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device is determined as the clock synchronization port. The second node device and the node devices connected to it through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device.

[0180] Specifically, when the second node device and the node devices connected to the second node device through the clock synchronization port perform clock synchronization, other node devices among the multiple node devices perform clock synchronization with the node devices connected to them through the clock synchronization ports of other node devices.

[0181] The specific network architecture block diagram of the time synchronization system based on the Shake bus disclosed in this embodiment can be seen as follows: Figure 4 As shown.

[0182] The time synchronization system based on the Shark bus disclosed in this embodiment is implemented based on the time synchronization method based on the Shark bus disclosed in the above embodiment, and will not be described again here.

[0183] The time synchronization system based on the Shake bus disclosed in this embodiment outputs the parameter information of the master clock contention vector to other node devices in the network at each first time interval. During each first time interval, the network performs a reconstruction process. The system obtains the parameter information of the master clock contention vector output by each node device in the network. The parameter information of the master clock contention vector includes at least the clock accuracy level and clock priority of the corresponding node device. Based on the parameter information of the master clock contention vector of each node device in the network, the system determines the sum of the distances between each node device and other node devices. The node device with the smallest sum of distances to other node devices in the network is determined as the optimal node device with the optimal synchronization master clock. The port in the second node device used to obtain the parameter information of the master clock contention vector output by the optimal node device is determined as the clock synchronization port. The second node device and the node devices connected to the second node device through the clock synchronization port are clock synchronized to achieve clock synchronization with the optimal node device. In this scheme, the optimal master clock is dynamically adjusted, and the optimal master clock is determined during the automatic network reconfiguration process, reusing the network reconfiguration process and reducing communication pressure. In addition, with the optimal master clock as the center, the outer second node device performs clock counting synchronization to the next outer first node device through the optimal path port linked to the optimal master clock. This realizes that clock synchronization only occurs between two adjacent nodes, without the need to send information directly to the optimal master clock, reducing the consumption of network-wide communication bandwidth resources caused by time synchronization. Furthermore, within the interval between two interactive synchronization cycles, the second node device calculates the compensation ratio by recording the number of periodic clocks and the cumulative clock deviation, and supplements when it is expected to reach 1 clock deviation, thereby achieving high-precision clock synchronization.

[0184] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0185] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0186] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.

[0187] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A time synchronization method based on the Shark bus, applied to a second node device, characterized in that, The method comprises: outputting parameter information of a master clock competition vector to other node devices in the network every first time interval, wherein the network performs a reconstruction process every first time interval; obtaining parameter information of the master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector at least includes a clock accuracy level, a clock priority of the corresponding node device, and an average distance from all node devices to the current node device; determining a sum of distances between each node device and other node devices in the network based on the parameter information of the master clock competition vector of each node device in the network; determining a node device with the smallest sum of distances between the node device and other node devices in the network as an optimal node device where an optimal synchronization master clock is located, and determining a port in the second node device used to obtain the parameter information of the master clock competition vector output by the optimal node device as a clock synchronization port; performing clock synchronization on the second node device and node devices connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device; Further, if the second node device is a non-optimal node device and the first node device is a node device connected to the second node device through the clock synchronization port, the method further comprises: determining a first time difference between a first time point when the first node device outputs clock synchronization instructions adjacent to each other, wherein the first node device outputs clock synchronization instructions every clock period, and a length of the clock period is equal to the first time difference; determining a second time difference between a second time point when the second node device obtains clock synchronization instructions output by the first node device adjacent to each other; determining a percentage of a clock count difference between the second node device and the first node device based on the first time difference and the second time difference; determining a count number of a counter required for a cumulative error to reach ±1 clock period or more based on the percentage of the clock count difference between the second node device and the first node device, and determining the count number as an interval length; when it is determined that the interval length is met, adjusting the clock count of the second node device based on the cumulative error to reduce an error between the adjusted clock count of the second node device and the clock count of the first node device.

2. The method of claim 1, wherein the clock synchronization on the second node device and node devices connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device comprises: if the second node device is an optimal node device, outputting a clock count to other node devices connected to the second node device through the clock synchronization port every second time interval, so that other node devices connected to the second node device through the clock synchronization port can adjust the clock count to synchronize with the clock signal of the second node device. In the second node device synchronizes the clock with other node devices connected to the second node device through the clock synchronization port of the second node device, other node devices in the network synchronize the clock with node devices connected to the other node devices through the clock synchronization port of the other node devices.

3. The method of claim 1, wherein the second node device and the node device connected to the second node device through the clock synchronization port are synchronized with the optimal node device, comprising: if the second node device is a non-optimal node device, adjusting the clock count of the second node device based on the clock count of the first node device connected to the clock synchronization port of the second node device every second time interval, so that the adjusted clock count of the second node device is synchronized with the clock count of the first node device.

4. The method of claim 3, wherein, The adjusting of the clock count of the second node device based on the clock count of the first node device connected to the clock synchronization port of the second node device, comprising: obtaining a clock synchronization instruction output by the first node device at a second time, the clock synchronization instruction carrying a first time at which the first node device outputs the clock synchronization instruction; outputting feedback information based on the clock synchronization instruction to the first node device at a third time; obtaining notification information output by the first node device, the notification information including at least a fourth time at which the first node device obtains the feedback information; adjusting the clock count of the second node device to be synchronized with the clock count of the first node device based on the first time, the second time, the third time, and the fourth time.

5. The method of claim 4, wherein, The adjusting of the clock count of the second node device to be synchronized with the clock count of the first node device based on the first time, the second time, the third time, and the fourth time, comprising: determining an offset of the clock signal of the second node device relative to the clock count of the first node device based on the first time, the second time, the third time, and the fourth time; adjusting the clock count of the second node device based on the offset, so that the clock count of the second node device is synchronized with the clock count of the first node device.

6. The method of claim 4, wherein, The adjusting of the clock count of the second node device to be synchronized with the clock count of the first node device based on the first time, the second time, the third time, and the fourth time, comprising: adjusting the clock count of the second node device to be synchronized with the clock count of the first node device at a port module of the second node device based on the first time, the second time, the third time, and the fourth time, the port module of the second node device being different from the core of the second node device.

7. A second node device based on a shach bus, characterized in that comprising: The first port module includes a plurality of first ports capable of being connected with different node devices respectively, and is configured to output parameter information of a master clock competition vector to other node devices in the network through different first ports respectively every first time interval, wherein the network performs a reconstruction process every first time interval; obtain parameter information of a master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector at least includes clock accuracy level, clock priority of the corresponding node device, and average distance from all node devices to the current node device; determine the sum of distances between each node device and other node devices based on the parameter information of the master clock competition vector of each node device in the network; determine the node device with the smallest sum of distances to other node devices in the network as an optimal node device where an optimal synchronization master clock is located, and determine a first port in the second node device used to obtain the parameter information of the master clock competition vector output by the optimal node device as a clock synchronization port; perform clock synchronization between the second node device and the node device connected with the second node device through the clock synchronization port to realize clock synchronization with the optimal node device; Further, if the second node device is a non-optimal node device, the first node device is a node device connected with the second node device through the clock synchronization port, and the method further includes: The first port module determines a first time difference between first time points at which the first node device outputs clock synchronization instructions adjacent to each other, the first node device outputs a clock synchronization instruction every clock cycle, and the length of the clock cycle is equal to the first time difference; determines a second time difference between second time points at which the second node device obtains the clock synchronization instruction output by the first node device adjacent to each other; determines a percentage of a clock count difference value between the second node device and the first node device based on the first time difference and the second time difference; determines a count number of a counter required when a cumulative error compensation reaches ±1 clock cycle or more based on the percentage of the clock count difference value between the second node device and the first node device, and determines the count number as an interval length; when it is determined that the interval length is met, adjusts the clock count of the second node device based on the compensation error, so that the error between the adjusted clock count of the second node device and the clock count of the first node device is reduced. The first kernel is configured to perform other signal processing operations except the time synchronization process.

8. A Grandmaster-based time synchronization system, characterized in that, The method includes: The plurality of node devices at least include a first node device and a second node device. The second node device outputs parameter information of a master clock competition vector to other node devices in the network every first time interval, wherein the network performs a reconstruction process every first time interval; obtains parameter information of a master clock competition vector output by each node device in the network, wherein the parameter information of the master clock competition vector at least includes a clock accuracy level, a clock priority of the corresponding node device, and an average distance from all node devices to the current node device; determines a sum of distances between each node device and other node devices in the network based on the parameter information of the master clock competition vector of each node device in the network; determines a node device with the smallest sum of distances to other node devices in the network as an optimal node device where an optimal synchronization master clock is located, and determines a port in the second node device used to obtain parameter information of a master clock competition vector output by the optimal node device as a clock synchronization port; and performs clock synchronization between the second node device and node devices connected to the second node device through the clock synchronization port to achieve clock synchronization with the optimal node device. Wherein, when the second node device and node devices connected to the second node device through the clock synchronization port perform clock synchronization, other node devices in the plurality of node devices perform clock synchronization to node devices connected thereto through clock synchronization ports of the other node devices. Further, if the second node device is a non-optimal node device and the first node device is a node device connected to the second node device through the clock synchronization port, the method further comprises: The second node device determines a first time difference between first time instants when the first node device outputs clock synchronization instructions adjacent to each other, the first node device outputs a clock synchronization instruction every clock cycle, and a length of the clock cycle is equal to the first time difference; determines a second time difference between second time instants when the second node device obtains clock synchronization instructions output by the first node device adjacent to each other; determines a percentage of a clock count difference between the second node device and the first node device based on the first time difference and the second time difference; determines a count number of a counter required when a cumulative error is compensated by more than ±1 clock cycle based on the percentage of the clock count difference between the second node device and the first node device, and determines the count number as an interval length; and adjusts the clock count of the second node device based on the compensated error when it is determined that the interval length is met, so that an error between the adjusted clock count of the second node device and the clock count of the first node device is reduced.

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