Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The method comprises the steps that a substrate structure is provided, the substrate structure is provided with an array region, a peripheral region and a first dielectric layer, and a contact plug is arranged in the first dielectric layer; forming a second dielectric layer on the first dielectric layer; etching the second dielectric layer in the array area and the peripheral area to a preset depth to form a first groove which correspondingly covers the contact plug, and the preset depth is smaller than the height of the second dielectric layer; forming a first spin-coating layer in the first groove; etching the first spin-coating layer in the first groove in the peripheral region to form a second groove, and exposing the second dielectric layer at the bottom of the first groove; etching the second dielectric layer in the second groove until the contact plug is exposed, and forming a filling hole; the remaining first spin-coating layer is removed, a diffusion barrier layer is conformally formed in the first trench and the filling hole, the diffusion barrier layer is connected with the contact plug, and a metal layer is formed on the diffusion barrier layer. According to the method, the electrical performance and the yield of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the back-end process of DRAM (Dynamic Random Access Memory), trenches to be filled with metal interconnects are first formed in the peripheral area, and then a spin-coated layer with a certain thickness is formed in the active area and the peripheral area. The spin-coated layer fills the trenches, and the spin-coated layer can be used as a mask in the active area to form another shallower trench in the active area.

[0003] However, since the aspect ratio of the trench in the peripheral area is relatively large, when the spin-coated layer is removed, the spin-coated layer at the bottom of the trench will remain. As a result, the metal interconnection line formed in the trench cannot be electrically connected to the conductive parts such as the plug below, affecting the electrical performance of the semiconductor structure and reducing the yield.

[0004] The above information disclosed in this background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the relevant technology that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which can completely remove the first spin-coated layer, and the metal layer can be connected to the contact plug, thereby improving the electrical performance and yield of the semiconductor structure.

[0006] The present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate structure, the substrate structure having an array region and a peripheral region, the substrate structure having a first dielectric layer, and the first dielectric layer having a contact plug; forming a second dielectric layer on the first dielectric layer located in the array region and the peripheral region; etching the second dielectric layer located in the array region and the peripheral region to a preset depth to form a first groove, the first groove correspondingly covering at least a portion of the contact plug in a vertical direction, the preset depth being less than the height of the second dielectric layer in the vertical direction; forming a first spin-coated layer on the remaining second dielectric layer and in the first groove; etching the first spin-coated layer located in the peripheral region and in the first groove to form a second groove, exposing the second dielectric layer located at the bottom of the first groove; etching the second dielectric layer in the second groove until the contact plug is exposed to form a filling hole; removing the remaining first spin-coated layer, conformally forming a diffusion barrier layer in the first groove located in the array region and the peripheral region and in the filling hole located in the peripheral region, the diffusion barrier layer being connected to the contact plug, and forming a metal layer on the diffusion barrier layer.

[0007] In some embodiments of the present disclosure, after etching the first spin-coated layer located in the peripheral area and in the first groove to form a second groove and expose the second dielectric layer located at the bottom of the first groove, it also includes: forming a protective layer on the sidewalls of the second groove formed by the first spin-coated layer and the bottom wall of the second groove formed by the exposed second dielectric layer, the material of the protective layer being different from the material of the first spin-coated layer; etching the second dielectric layer in the second groove until the contact plug is exposed to form a filling hole, including: etching to remove the protective layer, and etching the second dielectric layer until the contact plug is exposed to form the filling hole.

[0008] In some embodiments of the present disclosure, the filling hole is located in the middle of the first groove in the horizontal direction; and / or the size of the second groove in the horizontal direction is smaller than the size of the first groove in the horizontal direction.

[0009] In some embodiments of the present disclosure, a size of the first trench located in the peripheral region in the horizontal direction is greater than a size of the first trench located in the array region in the horizontal direction.

[0010] In some embodiments of the present disclosure, a second dielectric layer is formed on the first dielectric layer located in the array area and the peripheral area, including: forming an isolation layer on the first dielectric layer located in the array area and the peripheral area; forming the second dielectric layer on the isolation layer; etching the second dielectric layer in the second trench until the contact plug is exposed to form a filling hole, including: etching the second dielectric layer and the isolation layer in the second trench until the contact plug is exposed to form the filling hole.

[0011] In some embodiments of the present disclosure, etching the second dielectric layer located in the array area and the peripheral area to a preset depth before forming the first groove further includes: forming an etch stop layer on the second dielectric layer; forming an initial spin-coated layer on the etch stop layer; forming an initial mask layer on the initial spin-coated layer; and forming an initial photoresist layer on the initial mask layer.

[0012] In some embodiments of the present disclosure, etching the second dielectric layer located in the array area and the peripheral area to a preset depth to form a first groove includes: forming a first groove pattern in the initial photoresist layer; transferring the first groove pattern to the initial mask layer, the initial spin-coated layer, the etch stop layer and the second dielectric layer in sequence; removing the remaining initial photoresist layer, the initial mask layer, the initial spin-coated layer and the etch stop layer to form the first groove in the second dielectric layer.

[0013] In some embodiments of the present disclosure, before etching the first spin-coated layer located in the peripheral area and in the first groove to form a second groove and expose the second dielectric layer located at the bottom of the first groove, it also includes: forming a first mask layer on the first spin-coated layer; forming a first photoresist layer on the first mask layer; etching the first spin-coated layer located in the peripheral area and in the first groove to form a second groove and expose the second dielectric layer located at the bottom of the first groove, including: forming a second groove pattern in the first photoresist layer; transferring the second groove pattern to the first mask layer; etching the first spin-coated layer located in the peripheral area and in the first groove according to the second groove pattern in the first mask layer to form the second groove.

[0014] In some embodiments of the present disclosure, a metal layer is formed on the diffusion barrier layer, comprising: filling the metal layer in the first groove and the filling hole in which the diffusion barrier layer is formed; and grinding the metal layer and the diffusion barrier layer located on the second dielectric layer using a chemical mechanical grinding process to make the surfaces of the second dielectric layer, the metal layer and the diffusion barrier layer flush.

[0015] The present disclosure also provides a semiconductor structure, including: a substrate structure, the substrate structure having an array region and a peripheral region, the substrate structure having a first dielectric layer, the first dielectric layer having a contact plug; a second dielectric layer, located on the first dielectric layer in the array region and the peripheral region; in the array region and the peripheral region, the second dielectric layer having a first trench of a preset depth, the preset depth being less than the height of the second dielectric layer in the vertical direction, and in the peripheral region, the second dielectric layer located below the first trench is provided with a filling hole connecting the contact plug and the first trench; a diffusion barrier layer, located in the first trench and the filling hole; and a metal layer, located in the first trench having the diffusion barrier layer and the filling hole.

[0016] It can be seen from the above technical solutions that the method for preparing a semiconductor structure according to the embodiment of the present disclosure has at least one of the following advantages and positive effects:

[0017] In the disclosed embodiment, the second dielectric layer located in the array area and the peripheral area is etched to a preset depth to form a first groove, and the preset depth is less than the height of the second dielectric layer in the vertical direction, so that the depth-to-width ratio of the first groove located in the peripheral area is reduced, thereby reducing the height-to-width ratio of the first spin-coated layer located in the first groove, and the first spin-coated layer can be completely removed in the subsequent process to avoid residue. In addition, the first spin-coated layer located in the peripheral area and in the first groove is etched to form a second groove, exposing the second dielectric layer located at the bottom of the first groove, and the second dielectric layer in the second groove is etched until the contact plug is exposed to form a filling hole. Since there is no first spin-coated layer in the filling hole, and the first spin-coated layer in the first groove can be completely removed in the subsequent process, the diffusion barrier layer and the metal layer formed in the first groove and the filling hole can be completely connected to the contact plug, thereby improving the electrical performance and yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.

[0019] Figure 1 is a schematic diagram of a semiconductor structure having a spin-coated layer residue in a groove in the related art;

[0020] Figure 2 A schematic diagram showing that a metal interconnection line formed in the related art cannot be connected to a lower plug due to residual coating;

[0021] Figure 3 A flow chart of a method for preparing a semiconductor structure according to some embodiments of the present disclosure;

[0022] Figure 4 A schematic diagram showing the formation of a second dielectric layer, an etch stop layer, an initial spin-coated layer, an initial mask layer and an initial photoresist layer on a substrate structure according to some embodiments of the present disclosure;

[0023] Figure 5 A schematic diagram showing the transfer of a first groove pattern of an initial photoresist to an initial spin-coated layer according to some embodiments of the present disclosure;

[0024] Figure 6 A schematic diagram showing a method of forming a first trench in a second dielectric layer according to some embodiments of the present disclosure;

[0025] Figure 7 A schematic diagram showing a method of forming a first spin-coated layer in a second dielectric layer and a first trench according to some embodiments of the present disclosure;

[0026] Figure 8 A schematic diagram showing etching a first spin-coated layer in a first groove to form a second groove according to some embodiments of the present disclosure;

[0027] Fig. 9 A schematic diagram of forming a protective layer according to some embodiments of the present disclosure;

[0028] Fig.10 A schematic diagram showing etching a second dielectric layer in a second trench to form a filling hole according to some embodiments of the present disclosure;

[0029] Fig.11 A schematic diagram of removing a first spin-coated layer according to some embodiments of the present disclosure;

[0030] Fig.12 A schematic diagram showing forming a diffusion barrier layer and a metal seed layer in a first trench and a filling hole according to some embodiments of the present disclosure;

[0031] Fig.13 A schematic diagram of forming a metal layer according to some embodiments of the present disclosure;

[0032] Fig.14 Schematic diagram of using a chemical mechanical polishing process to grind a metal layer flat according to some embodiments of the present disclosure.

[0033] Description of reference numerals:

[0034] 1', metal interconnect; 2', trench; 3', plug; 4', spin coating;

[0035] 1. Base structure; 101. First dielectric layer; 102. Contact plug; 2. Isolation layer; 3. Second dielectric layer; 4. Etch stop layer; 5. Initial spin-coated layer; 6. Initial mask layer; 7. Initial photoresist layer; 8. First trench; 9. First spin-coated layer; 10. First mask layer; 11. First photoresist layer; 12. Second trench; 13. Protective layer; 14. Filling hole; 15. Diffusion barrier layer; 16', Metal seed layer; 16. Metal layer; A. Array area; P. Peripheral area; X. Horizontal direction; Y. Vertical direction. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0037] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which different exemplary structures that can implement multiple aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional direction of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as marks and are not numerical limitations on their objects.

[0038] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0039] In addition, in the description of the present disclosure, “plurality” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0040] In the back-end process of DRAM, it is necessary to form metal interconnection lines 1', which are electrically connected to semiconductor devices (such as capacitors, transistors, etc.) formed in the front-end process. In the process of preparing metal interconnection lines 1', Figure 1 As shown, it is necessary to first form a trench 2' to be filled with a metal interconnection line 1' in the peripheral area P, and expose the plug 3' in the lower dielectric layer at the bottom of the trench 2', and then form a spin-coated layer 4' with a certain thickness in the array area A and the peripheral area P, and the spin-coated layer 4' fills the trench 2'. The spin-coated layer 4' can be used as a mask layer in the array area A, so that another shallower trench is formed in the array area A for forming the metal interconnection line 1' in the active area.

[0041] Continue to refer Figure 1 Since the aspect ratio of the trench 2' in the peripheral region P is relatively large, when the spin coating layer 4' in the trench 2' in the peripheral region P is removed by etching, the spin coating layer 4' at the bottom of the trench 2' will remain. Figure 2 After the metal interconnection line 1' is formed in the trench 2', due to the influence of the residual spin-coated layer 4', the metal interconnection line 1' cannot be electrically connected to the conductive member such as the plug 3' below, thereby affecting the electrical performance of the semiconductor structure and reducing the yield.

[0042] Based on this, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, which can avoid the generation of spin-coated layer residues, enable the metal layer to be connected to the contact plug, and improve the electrical performance and yield of the semiconductor structure.

[0043] like Figure 3 As shown, the method for preparing a semiconductor structure provided by the embodiment of the present disclosure includes the following steps S110 to S170.

[0044] S110 : providing a substrate structure 1 , wherein the substrate structure 1 has an array region A and a peripheral region P, and the substrate structure 1 has a first dielectric layer 101 , and the first dielectric layer 101 has a contact plug 102 .

[0045] S120 : forming a second dielectric layer 3 on the first dielectric layer 101 located in the array region A and the peripheral region P.

[0046] S130: Etching the second dielectric layer 3 in the array area A and the peripheral area P to a preset depth to form a first trench 8, wherein the first trench 8 covers at least a portion of the contact plug 102 in the vertical direction Y, and the preset depth is less than the height of the second dielectric layer 3 in the vertical direction Y.

[0047] S140 : forming a first spin-coated layer 9 on the remaining second dielectric layer 3 and in the first trench 8 .

[0048] S150 : etching the first spin-coated layer 9 located in the peripheral region P and in the first trench 8 to form a second trench 12 , exposing the second dielectric layer 3 located at the bottom of the first trench 8 .

[0049] S160 : etching the second dielectric layer 3 in the second trench 12 until the contact plug 102 is exposed, thereby forming a filling hole 14 .

[0050] S170: Remove the remaining first spin-coated layer 9, conformally form a diffusion barrier layer 15 in the first trenches 8 located in the array area A and the peripheral area P and the filling holes 14 located in the peripheral area P, the diffusion barrier layer 15 is connected to the contact plug 102, and a metal layer 16 is formed on the diffusion barrier layer 15.

[0051] In the embodiment of the present disclosure, the second dielectric layer 3 located in the array area A and the peripheral area P is etched to a preset depth to form a first groove 8. The preset depth is less than the height of the second dielectric layer 3 in the vertical direction Y, so that the depth-to-width ratio of the first groove 8 located in the peripheral area P is reduced, thereby reducing the height-to-width ratio of the first spin-coated layer 9 located in the first groove 8. The first spin-coated layer 9 can be completely removed in the subsequent process to avoid residue. In addition, the first spin-coated layer 9 located in the peripheral area P and in the first groove 8 is etched to form a second groove 12, exposing the second dielectric layer 3 located at the bottom of the first groove 8. The second dielectric layer 3 in the second groove 12 is etched until the contact plug 102 is exposed to form a filling hole 14. Since there is no first spin-coated layer 9 in the filling hole 14, and the first spin-coated layer 9 in the first groove 8 can be completely removed in the subsequent process, the diffusion barrier layer 15 and the metal layer 16 formed in the first groove 8 and the filling hole 14 can be completely connected to the contact plug 102, thereby improving the electrical performance and yield of the semiconductor structure.

[0052] The following is a detailed description of the method for preparing the semiconductor structure according to the embodiment of the present disclosure.

[0053] S110 : providing a substrate structure 1 , wherein the substrate structure 1 has an array region A and a peripheral region P, and the substrate structure 1 has a first dielectric layer 101 , and the first dielectric layer 101 has a contact plug 102 .

[0054] like Figure 4 As shown, the base structure 1 may include a substrate and a device located on or in the substrate (not shown in the figure). Shallow trench isolation is formed in the substrate, and an active area is provided between the shallow trench isolations. A word line structure (not shown in the figure) and a bit line structure are also provided in the substrate, and the word line structure and the bit line structure are provided at different heights of the substrate, and both the word line structure and the bit line structure are connected to the active area.

[0055] In addition, the substrate includes an array region A and a peripheral region P. Devices such as transistor structures and capacitor structures (not shown in the figure) can be arranged in the array region A of the substrate, and peripheral circuits are formed in the peripheral region P. The base structure 1 also has a first dielectric layer 101, which is used for insulation isolation between devices, and contact plugs 102 and conductive leads are arranged in the first dielectric layer 101 to achieve electrical connection between various devices.

[0056] In some embodiments, the material of the substrate may be silicon, silicon carbide, silicon on insulator, silicon on insulator, silicon germanium on insulator, silicon germanium on insulator, or germanium on insulator, etc. The substrate may also be implanted with certain doping particles to change electrical parameters according to design requirements.

[0057] The substrate structure 1 is a structure prepared in the front-end process of a semiconductor manufacturing process, and its specific structure and preparation process are not described in detail here.

[0058] S120 : forming a second dielectric layer 3 on the first dielectric layer 101 located in the array region A and the peripheral region P.

[0059] like Figure 4 As shown, a deposition process may be used to form the second dielectric layer 3 on the first dielectric layer 101. The material of the second dielectric layer 3 may be silicon oxide or a low-K dielectric material.

[0060] In some embodiments, Figure 4 As shown, forming the second dielectric layer 3 on the first dielectric layer 101 located in the array area A and the peripheral area P includes: forming an isolation layer 2 on the first dielectric layer 101 located in the array area A and the peripheral area P; and forming the second dielectric layer 3 on the isolation layer 2.

[0061] The isolation layer 2 can be formed by deposition on the surface of the first dielectric layer 101 by a deposition process. The material of the isolation layer 2 may include silicon nitride. The silicon nitride material has a good isolation effect and can reduce parasitic capacitance. The thickness of the isolation layer 2 is less than the thickness of the second dielectric layer 3, which is conducive to the subsequent process on the basis of achieving its isolation performance.

[0062] S130: Etching the second dielectric layer 3 in the array area A and the peripheral area P to a preset depth to form a first trench 8, wherein the first trench 8 covers at least a portion of the contact plug 102 in the vertical direction Y, and the preset depth is less than the height of the second dielectric layer 3 in the vertical direction Y.

[0063] like Figure 4 As shown, before etching the second dielectric layer 3 located in the array area A and the peripheral area P to a preset depth to form the first groove 8, it also includes: forming an etching stop layer 4 on the second dielectric layer 3; forming an initial spin-coated layer 5 on the etching stop layer 4; forming an initial mask layer 6 on the initial spin-coated layer 5; and forming an initial photoresist layer 7 on the initial mask layer 6.

[0064] A second dielectric layer 3 may be deposited on the isolation layer 2 by a deposition process. An etch stop layer 4 is formed on the second dielectric layer 3, and the material of the etch stop layer 4 may be silicon oxynitride. An initial spin coating layer 5 is formed on the etch stop layer 4 by a spin coating process. The material of the initial spin coating layer 5 may be spin on organic carbon (SOC) or spin on hard mask (SOH). An initial mask layer 6 and an initial photoresist layer 7 are sequentially formed on the initial spin coating layer 5 by a deposition process. The material of the initial mask layer 6 may include silicon oxynitride.

[0065] The second dielectric layer 3 located in the array area A and the peripheral area P is etched to a preset depth to form a first trench 8, including the following contents A1-A3.

[0066] A1: forming a first groove pattern in the initial photoresist layer 7 .

[0067] like Figure 4 As shown, a first trench pattern may be formed in the initial photoresist located in the array region A and the peripheral region P by using a photolithography process.

[0068] A2: The first groove pattern is transferred to the initial mask layer 6, the initial spin-coated layer 5, the etching stop layer 4 and the second dielectric layer 3 in sequence.

[0069] The first groove pattern in the initial photoresist layer 7 can be transferred to the initial mask layer 6 by dry etching process. The silicon oxynitride material in the initial mask layer 6 can be used as an anti-reflection film in the photolithography process to prevent the photolithography process from damaging the initial spin-coated layer 5, thereby ensuring that the first groove pattern can be accurately transferred. Figure 5 As shown, the first groove pattern is transferred from the initial mask layer 6 to the initial spin-coated layer 5, and the etching stops at the etch stop layer 4. Figure 6 As shown, the first trench pattern can be transferred from the etching stop layer 4 to the second dielectric layer 3 by a dry etching process, so that the first trench 8 is formed in the second dielectric layer 3 located in the array area A and the peripheral area P.

[0070] A3: removing the remaining initial photoresist layer 7 , the initial mask layer 6 , the initial spin-coated layer 5 and the etching stop layer 4 , and forming a first trench 8 in the second dielectric layer 3 .

[0071] like Figure 5 As shown, after the first groove pattern is transferred to the initial spin-coated layer 5, the initial photoresist layer 7 and the initial mask layer 6 are removed, as shown in FIG. Figure 6 As shown, after forming the first trench 8 in the second dielectric layer 3, the initial spin-coated layer 5 and the etch stop layer 4 may be removed.

[0072] like Figure 6 As shown, the first trench 8 corresponds to covering at least a portion of the contact plug 102 in the vertical direction Y, and the preset depth is less than the height of the second dielectric layer 3 in the vertical direction Y. In other words, the projection of the first trench 8 on the substrate structure 1 along the vertical direction Y covers at least a portion of the contact plug 102, so that the filling hole 14 formed in the subsequent process can expose the contact plug 102, so that the metal layer 16 formed subsequently can be connected to the contact plug 102.

[0073] Continue to refer Figure 6 The preset depth can be understood as the depth of the first groove 8, which is less than the height of the second dielectric layer 3 in the vertical direction Y. That is to say, the first groove 8 does not penetrate the second dielectric layer 3, so that the aspect ratio of the first groove 8 can be reduced.

[0074] In some embodiments, the size of the first trench 8 in the peripheral area P in the horizontal direction X is greater than the size of the first trench 8 in the array area A in the horizontal direction X. That is, the critical size of the first trench 8 in the peripheral area P is increased, and at the same time, since the depth of the first trench 8 is less than the height of the second dielectric layer 3, the aspect ratio of the first trench 8 in the peripheral area P can be further reduced, so that the first spin-coated layer 9 formed in the first trench 8 can be completely removed later to avoid residue.

[0075] It should be noted that the "vertical direction Y" in the embodiment of the present disclosure is a direction perpendicular to the surface of the substrate structure 1, and can also be understood as the stacking direction of the second dielectric layer 3, the etching stop layer 4 and the initial spin-coated layer 5. The "horizontal direction X" is a direction parallel to the surface of the substrate structure 1, and the horizontal direction X is perpendicular to the vertical direction Y. The terms "vertical direction Y" and "horizontal direction X" are merely for convenience of description and have no limiting meaning.

[0076] S140 : forming a first spin-coated layer 9 on the remaining second dielectric layer 3 and in the first trench 8 .

[0077] like Figure 7 As shown, a first spin-coated layer 9 is formed on the second dielectric layer 3 and in the first groove 8 by a spin coating process, and the first spin-coated layer 9 fills the first groove 8 located in the array area A and the peripheral area P and is higher than the surface of the second dielectric layer 3. The material of the first spin-coated layer 9 may include spin-coated organic carbon or spin-coated hard mask.

[0078] S150 : etching the first spin-coated layer 9 located in the peripheral region P and in the first trench 8 to form a second trench 12 , exposing the second dielectric layer 3 located at the bottom of the first trench 8 .

[0079] Continue to refer Figure 7 Before performing S150 , the method further includes: forming a first mask layer 10 on the first spin-coated layer 9 ; and forming a first photoresist layer 11 on the first mask layer 10 .

[0080] The material of the first mask layer 10 may include silicon oxynitride. In the subsequent process of performing photolithography on the first photoresist to form the second groove pattern, the first mask layer 10 can be used as an anti-reflection film in the photolithography process to prevent the photolithography from damaging the first spin-coated layer 9. In addition, the second groove pattern can also be transferred to the first mask layer 10, so that the first mask layer 10 can continue to transfer the second groove pattern downward.

[0081] It should be noted that "upper" and "lower" in the embodiments of the present disclosure are technical terms indicating directions, for example, the direction from the first dielectric layer 101 to the second dielectric layer 3 is upward, and the reverse direction is downward, such as the second dielectric layer 3 is located below the etching stop layer 4. This is only for the convenience of description and does not have a limiting meaning.

[0082] In some embodiments, S150 may include the following contents B1 to B3.

[0083] B1: forming a second groove pattern in the first photoresist layer 11 .

[0084] For example, a mask layer having a second groove pattern may be formed on the first photoresist layer 11, and the second groove pattern may be formed in the first photoresist layer 11 by using light irradiation and development technology. Figure 7 As shown, the second trench pattern is only formed in the peripheral region P, and the second trench pattern corresponds to the first trench 8 in the vertical direction Y.

[0085] B2: transferring the second trench pattern into the first mask layer 10 .

[0086] The second trench pattern in the first photoresist layer 11 may be transferred to the first mask layer 10 by an etching process, so that the first mask layer 10 serves as a mask to continue to transfer the second trench pattern downward.

[0087] B3: According to the second trench pattern in the first mask layer 10 , the first spin-coated layer 9 located in the peripheral region P and in the first trench 8 is etched to form a second trench 12 .

[0088] like Figure 8 As shown, in some embodiments, the size of the second trench 12 along the horizontal direction X is smaller than the size of the first trench 8 along the horizontal direction X, that is, the critical size of the second trench 12 is smaller than the critical size of the first trench 8, and the sidewall of the second trench 12 is formed by the first spin-coated layer 9. After the second dielectric layer 3 is etched to form the filling hole 14 in the subsequent process, the critical size of the filling hole 14 can be smaller than the critical size of the first trench 8. Since the critical size of the first trench 8 is larger, the aspect ratio of the first trench 8 is reduced, and it is easy to completely remove the first spin-coated layer 9 located in the first trench 8. Since the first spin-coated layer 9 does not exist in the filling hole 14, there will be no residue of the first spin-coated layer 9 in the finally formed first trench 8 and the filling hole 14. Moreover, the critical size of the filling hole 14 is smaller than the critical size of the first trench 8, which can also meet the requirements of high density and further improve the electrical performance of the semiconductor structure.

[0089] In addition, the critical dimension of the second groove 12 is smaller than the critical dimension of the first groove 8, and the sidewall of the second groove 12 is the first spin-coated layer 9. In the process of etching the second dielectric layer 3 to form the filling hole 14 in the subsequent process, the sidewall of the second groove 12 (the first spin-coated layer 9) can protect the sidewall of the first groove 8 (the second dielectric layer 3) to prevent the sidewall of the first groove 8 from being damaged.

[0090] In some embodiments, Fig. 9As shown, after etching the first spin-coated layer 9 located in the peripheral region P and in the first trench 8 to form the second trench 12 and expose the second dielectric layer 3 located at the bottom of the first trench 8, the method further includes: forming a protective layer 13 on the sidewalls of the second trench 12 formed by the first spin-coated layer 9 and the bottom wall of the second trench 12 formed by the exposed second dielectric layer 3, wherein the material of the protective layer 13 is different from that of the first spin-coated layer 9. The material of the protective layer 13 may be the same as that of the second dielectric layer 3.

[0091] Since the second dielectric layer 3 exposed in the second trench 12 needs to be etched to form a filling hole 14 in the subsequent process, the protective layer 13 can protect the sidewalls of the second trench 12 to avoid damaging the sidewalls of the second trench 12 during the etching process. The material of the protective layer 13 is different from that of the first spin-coated layer 9. The material of the protective layer 13 can be silicon oxide or a low-K dielectric material, and the protective layer 13 can be formed by an atomic layer deposition process. Among them, the first spin-coated layer 9 can protect the sidewalls of the first trench 8. Since the material of the protective layer 13 is different from that of the first spin-coated layer 9, when etching the protective layer 13, the impact on the first spin-coated layer 9 is small, that is, the sidewalls of the second trench 12 are protected. At the same time, since the material of the protective layer 13 and the second dielectric layer 3 is the same, when etching the protective layer 13, the first spin-coated layer 9 can prevent the etching gas from etching the sidewalls of the first trench 8, thereby avoiding the increase of the critical dimension of the first trench 8, and even causing the sidewalls of the first trench 8 to be completely etched, resulting in the connection of the two first trenches 8.

[0092] S160 : etching the second dielectric layer 3 in the second trench 12 until the contact plug 102 is exposed, thereby forming a filling hole 14 .

[0093] In some embodiments, S160 may include etching to remove the protection layer 13 , and etching the second dielectric layer 3 until the contact plug 102 is exposed, so as to form a filling hole 14 .

[0094] like Fig.10 As shown, in the process of etching to form the filling hole 14, the protective layer 13 can be etched away at the same time. In the etching process, the etching speed of the protective layer 13 and the second dielectric layer 3 located on the bottom wall of the second trench 12 is greater than the etching speed of the protective layer 13 located on the side wall of the second trench 12. Therefore, while forming the contact hole, the protective layer 13 on the side wall can also be removed to expose the side wall of the second trench 12.

[0095] In some other embodiments, the protection layer 13 is not formed, and the exposed second dielectric layer 3 can be directly etched in the second trench 12 to form the filling hole 14 .

[0096] In some embodiments, since an isolation layer 2 is formed between the second dielectric layer 3 and the first dielectric layer 101 , etching the second dielectric layer 3 in the second trench 12 until the contact plug 102 is exposed to form a filling hole 14 includes: etching the second dielectric layer 3 and the isolation layer 2 in the second trench 12 until the contact plug 102 is exposed to form a filling hole 14 .

[0097] In some embodiments, Fig.11 As shown, the filling hole 14 is located in the middle of the first trench 8 in the horizontal direction X. Aligning the filling hole 14 to the middle of the first trench 8 can ensure that the contact plug 102 is fully exposed in the filling hole 14 and avoid deviation of the subsequently formed metal layer 16.

[0098] S170: Remove the remaining first spin-coated layer 9, conformally form a diffusion barrier layer 15 in the first trenches 8 located in the array area A and the peripheral area P and the filling holes 14 located in the peripheral area P, the diffusion barrier layer 15 is connected to the contact plug 102, and a metal layer 16 is formed on the diffusion barrier layer 15.

[0099] like Fig.11 As shown, the remaining first spin-coated layer 9 can be removed by a wet etching process. Since the aspect ratio of the first trench 8 is small and the critical dimension of the first trench 8 located in the peripheral region P is larger, the first spin-coated layer 9 can be completely removed. Fig.11 As shown, no first spin-coated layer 9 remains in the first trench 8 and the filling hole 14 .

[0100] like Fig.12 As shown, a diffusion barrier layer 15 can be conformally formed in the first trench 8 in the array region A and the peripheral region P and the filling hole 14 in the peripheral region P by a deposition process. The material of the diffusion barrier layer 15 can be titanium nitride to block the diffusion of the subsequently formed metal layer 16 to ensure the stability of the electrical performance of the semiconductor structure. The diffusion barrier layer 15 is connected to the contact plug 102 to ensure that the metal layer 16 can be electrically connected to the contact plug 102.

[0101] In some embodiments, forming a metal layer 16 on the diffusion barrier layer 15 includes: filling the metal layer 16 in the first trench 8 and the filling hole 14 in which the diffusion barrier layer 15 is formed; and grinding the metal layer 16 and the diffusion barrier layer 15 located on the second dielectric layer 3 using a chemical mechanical grinding process to make the surfaces of the second dielectric layer 3, the metal layer 16 and the diffusion barrier layer 15 flush.

[0102] like Fig.12 As shown, a metal seed layer 16' can be conformally formed on the diffusion barrier layer 15 by using an atomic layer deposition process, as shown in FIG. Fig.13As shown, the metal layer 16 may be formed by electroplating. The metal seed layer 16' and the metal layer 16 may be made of the same material to facilitate the formation of a uniform metal layer 16. In some embodiments, the metal seed layer 16' and the metal layer 16 may be made of copper or tungsten.

[0103] like Fig.14 As shown, after the metal layer 16 is formed, the metal layer 16 and the diffusion barrier layer 15 on the second dielectric layer 3 can be polished by chemical mechanical polishing process to make the surfaces of the second dielectric layer 3, the metal layer 16 and the diffusion barrier layer 15 flush, which is convenient for subsequent processes.

[0104] In an embodiment of the present disclosure, the deposition process may be at least one of a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

[0105] In summary, the method of the embodiment of the present disclosure reduces the aspect ratio of the first trench 8, thereby reducing the aspect ratio of the first spin-coated layer 9 in the first trench 8, and the first spin-coated layer 9 can be completely removed in the subsequent process to avoid residue. In addition, there is no first spin-coated layer 9 in the filling hole 14, so the diffusion barrier layer 15 and the metal layer 16 formed in the first trench 8 and the filling hole 14 can be completely connected to the contact plug 102, thereby improving the electrical performance and yield of the semiconductor structure.

[0106] The present disclosure also provides a semiconductor structure, such as Fig.14 As shown, the semiconductor structure includes a substrate structure 1 , a second dielectric layer 3 , a diffusion barrier layer 15 and a metal layer 16 .

[0107] like Fig.14 As shown, the substrate structure 1 has an array area A and a peripheral area P, and the substrate structure 1 has a first dielectric layer 101, and the first dielectric layer 101 has a contact plug 102. The substrate structure 1 may include a substrate and a device located on or in the substrate (not shown in the figure). The substrate also includes a first dielectric layer 101, and the first dielectric layer 101 has a contact plug 102, which is electrically connected to each device. The substrate structure 1 is the same as the method embodiment, and will not be repeated here.

[0108] Continue to refer Fig.14 The second dielectric layer 3 is located on the first dielectric layer 101 in the array region A and the peripheral region P; in the array region A and the peripheral region P, the second dielectric layer 3 has a first trench 8 with a preset depth (reference Fig.11 ), the preset depth is less than the height of the second dielectric layer 3 in the vertical direction Y, that is, the first trench 8 does not penetrate the second dielectric layer 3. In the peripheral area P, a filling hole 14 connecting the contact plug 102 and the first trench 8 is provided in the second dielectric layer 3 below the first trench 8.

[0109] In some embodiments, the critical dimension of the filling hole 14 is smaller than the critical dimension of the first trench 8, wherein the critical dimension of the first trench 8 is the dimension of the first trench 8 along the horizontal direction X. The critical dimension of the filling hole 14 is smaller than the critical dimension of the first trench 8, which can meet the high density requirements of the semiconductor structure and improve the electrical performance of the semiconductor structure. At the same time, part of the metal layer 16 is located in the first trench 8, which can increase the conductive area of ​​the metal layer 16 and further improve the electrical performance.

[0110] In some embodiments, the filling hole 14 is located in the middle of the first trench 8 in the horizontal direction X. That is, the filling hole 14 is connected to the middle position of the bottom of the first trench 8, which can ensure that the metal layer 16 in the filling hole 14 can be connected to the plug in the first dielectric layer 101, thereby ensuring the stability of the electrical performance.

[0111] like Fig.14 As shown, the diffusion barrier layer 15 is located in the first trench 8 of the array region A and the peripheral region P and the first filling hole 14 of the peripheral region P, for preventing the diffusion of the metal in the metal layer 16. The metal layer 16 is located in the first trench 8 and the filling hole 14 having the diffusion barrier layer 15. In some embodiments, the material of the metal layer 16 may include at least one of copper and tungsten.

[0112] In some embodiments, Fig.14 As shown, the top surfaces of the second dielectric layer 3, the diffusion barrier layer 15 and the metal layer 16 are flush, so as to facilitate other semiconductor processes on the semiconductor structure.

[0113] In summary, in the semiconductor structure of the embodiment of the present disclosure, there is no spin-coated layer residue between the metal layer 16 and the contact plug 102 , so that the metal layer 16 can fully contact the contact plug 102 , thereby improving the electrical performance and yield of the semiconductor structure.

[0114] It should be understood that the present disclosure does not limit its application to the detailed structure and arrangement of the components proposed in this specification. The present disclosure can have other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to adopt the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate structure, wherein the substrate structure has an array region and a peripheral region, the substrate structure has a first dielectric layer, and the first dielectric layer has a contact plug; forming a second dielectric layer on the first dielectric layer located in the array region and the peripheral region; Etching the second dielectric layer located in the array area and the peripheral area to a preset depth to form a first trench, wherein the first trench corresponds to and covers at least a portion of the contact plug in a vertical direction, and the preset depth is less than a height of the second dielectric layer in the vertical direction; forming a first spin-coated layer on the remaining second dielectric layer and in the first trench; Etching the first spin-coated layer located in the peripheral area and in the first trench to form a second trench, exposing the second dielectric layer located at the bottom of the first trench; Etching the second dielectric layer in the second trench until the contact plug is exposed to form a filling hole; The remaining first spin-coated layer is removed, a diffusion barrier layer is conformally formed in the first trenches located in the array region and the peripheral region and the filling hole located in the peripheral region, the diffusion barrier layer is connected to the contact plug, and a metal layer is formed on the diffusion barrier layer.

2. The method according to claim 1, characterized in that After etching the first spin-coated layer located in the peripheral area and in the first trench to form a second trench and expose the second dielectric layer located at the bottom of the first trench, the method further includes: forming a protective layer on the sidewalls of the second groove formed by the first spin-coated layer and the bottom wall of the second groove formed by the exposed second dielectric layer, wherein the material of the protective layer is different from that of the first spin-coated layer; Etching the second dielectric layer in the second trench until the contact plug is exposed to form a filling hole, comprising: The protection layer is removed by etching, and the second dielectric layer is etched until the contact plug is exposed to form the filling hole.

3. The method according to claim 1, characterized in that The filling hole is located in the middle of the first groove in the horizontal direction; and / or, A dimension of the second groove in a horizontal direction is smaller than a dimension of the first groove in the horizontal direction.

4. The method according to claim 1, characterized in that A size of the first trench located in the peripheral region in the horizontal direction is greater than a size of the first trench located in the array region in the horizontal direction.

5. The method according to claim 1, characterized in that Forming a second dielectric layer on the first dielectric layer located in the array area and the peripheral area, comprising: forming an isolation layer on the first dielectric layer located in the array area and the peripheral area; forming the second dielectric layer on the isolation layer; Etching the second dielectric layer in the second trench until the contact plug is exposed to form a filling hole, comprising: The second dielectric layer and the isolation layer in the second trench are etched until the contact plug is exposed to form the filling hole.

6. The method according to claim 1, characterized in that Before etching the second dielectric layer located in the array area and the peripheral area to a preset depth to form a first trench, the method further includes: forming an etch stop layer on the second dielectric layer; forming an initial spin-coated layer on the etch stop layer; forming an initial mask layer on the initial spin-coated layer; An initial photoresist layer is formed on the initial mask layer.

7. The method according to claim 6, characterized in that Etching the second dielectric layer located in the array area and the peripheral area to a preset depth to form a first trench, comprising: forming a first groove pattern in the initial photoresist layer; transferring the first groove pattern to the initial mask layer, the initial spin-coated layer, the etch stop layer and the second dielectric layer in sequence; The remaining initial photoresist layer, the initial mask layer, the initial spin-coated layer and the etch stop layer are removed to form the first trench in the second dielectric layer.

8. The method according to claim 1, characterized in that Before etching the first spin-coated layer located in the peripheral area and in the first trench to form a second trench and expose the second dielectric layer located at the bottom of the first trench, the method further includes: forming a first mask layer on the first spin-coated layer; forming a first photoresist layer on the first mask layer; Etching the first spin-coated layer located in the peripheral area and in the first trench to form a second trench and expose the second dielectric layer located at the bottom of the first trench, comprising: forming a second trench pattern in the first photoresist layer; transferring the second groove pattern into the first mask layer; The first spin-coated layer located in the peripheral region and in the first trench is etched according to the second trench pattern in the first mask layer to form the second trench.

9. The method according to any one of claims 1 to 8, characterized in that Forming a metal layer on the diffusion barrier layer, comprising: filling the metal layer in the first trench and the filling hole in which the diffusion barrier layer is formed; The metal layer and the diffusion barrier layer on the second dielectric layer are ground by using a chemical mechanical grinding process to make the surfaces of the second dielectric layer, the metal layer and the diffusion barrier layer flush.

10. A semiconductor structure, characterized in that: include: A substrate structure, wherein the substrate structure has an array region and a peripheral region, the substrate structure has a first dielectric layer, and the first dielectric layer has a contact plug; A second dielectric layer, located on the first dielectric layer in the array region and the peripheral region; In the array region and the peripheral region, the second dielectric layer has a first trench of a preset depth, the preset depth is less than the height of the second dielectric layer in the vertical direction, and in the peripheral region, the second dielectric layer located below the first trench is provided with a filling hole connecting the contact plug and the first trench; a diffusion barrier layer located in the first trench and the filling hole; A metal layer is located in the first trench having the diffusion barrier layer and the filling hole.

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