Preparation method of semiconductor structure
By separately forming and doping conductive layers on the substrate of the semiconductor memory, and using ion doping methods with different conductive layer thicknesses, the performance and reliability problems caused by the difference in conductive layer thickness during the memory preparation process are solved, and a more efficient Semiconductor structure preparation.
Patent Information
- Application Number
- CN202411447983.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-16
- Publication Date
- 2025-01-24
AI Technical Summary
The prior art combines the preparation process of the memory array and the peripheral circuits with each other when preparing a memory, resulting in a difference in the thickness of the semiconductor layer in the bit line structure, affecting the transistor performance and reliability in the peripheral circuits.
By forming and doping the first electrical layer and the second electrical layer on the first and second districts of the base, the ion doping method of the thickness of different conductive layers is used to ensure that the conductive layer is uniformly doped to avoid doping ion diffusion To the base.
Improve the reliability of the semiconductor structure, ensure the uniform mixing and sufficient ion injection of the conductive layer, and improve the performance and reliability of the transistor.
Smart Images
Figure CN119364761A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor memory structure. Background Art
[0002] A memory (e.g., a dynamic random access memory DRAM) includes a memory cell array for storing data, and a peripheral circuit located outside the memory cell array. The memory cell array is composed of a plurality of memory cells arranged in an array, and the corresponding memory cells are selected by bit lines and word lines. In the current memory preparation process, in order to simplify the process and save costs, the preparation processes of the memory cell array and the peripheral circuit are usually combined with each other. However, due to the differences between the memory cell array and the peripheral circuit, such as the difference in thickness of the semiconductor layer in the bit line structure in the memory cell array and the peripheral circuit, the device performance and reliability of some transistors in the peripheral circuit formed by combining the preparation processes of the memory cell array and the peripheral circuit will be further reduced. Summary of the invention
[0003] The object of the present invention is to provide a method for preparing a semiconductor structure to avoid the problem in the prior art of simultaneously ion doping the first conductive layer and the second conductive layer in the second zone and the second conductive layer in the first zone, whereby the doped ions derived therefrom diffuse through the second conductive layer in the first zone into the substrate thereunder, thereby causing failure of the semiconductor structure.
[0004] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor structure, which may at least include:
[0005] providing a substrate comprising a first region and a second region;
[0006] forming a first conductive layer on the first region and the second region;
[0007] Performing first ion doping on a portion of the first conductive layer in the second region to form a first doped region;
[0008] removing the first conductive layer on the first region;
[0009] forming a second conductive layer on the first region and the second region;
[0010] A second ion doping is performed on a portion of the second conductive layer in the second region to form a second doping region, wherein the second doping region is located in the first doping region and is doped with the same ion type as the first doping region.
[0011] Optionally, the first conductive layer and the second conductive layer may be made of the same material, and the first conductive layer may be made of single crystal silicon, polycrystalline silicon or amorphous silicon.
[0012] Optionally, a natural oxide layer may be formed on both the first conductive layer and the second conductive layer.
[0013] Optionally, the thickness of the first conductive layer in the vertical direction may be greater than the thickness of the second conductive layer in the vertical direction.
[0014] Optionally, the implantation dose and implantation energy of the implanted ions during the first ion doping and the second ion doping may be different.
[0015] Optionally, after forming the second doping region, the preparation method provided by the present invention may further include: performing third ion doping on the second conductive layer in the first region.
[0016] Optionally, after performing the third ion doping, the preparation method provided by the present invention may further include: performing a fourth ion doping on the remaining portion of the second conductive layer in the second region.
[0017] Optionally, the types of ions implanted during the first ion doping to the third ion doping may be the same.
[0018] Optionally, the ions implanted during the first ion doping to the third ion doping may be P-type ions, and the P-type ions may include boron ions.
[0019] Optionally, before forming the first conductive layer, the preparation method provided by the present invention may further include:
[0020] A plurality of buried word line structures are formed in the substrate in the first region.
[0021] In the present invention, on the one hand, for the alignment area of the first conductive layer and the second conductive layer serving as the gate of the transistor (e.g., NMOS tube) in the peripheral circuit, ion doping with different implantation doses and implantation energies based on the thickness of different conductive layers is adopted, so as to ensure that both the first conductive layer and the second conductive layer are sufficiently implanted with ions; on the other hand, the single ion doping of the second conductive layer in the first region and the second region with the same implantation ion type is decomposed into multiple ion dopings, so as to avoid the problem that the doped ions caused by the single ion doping will pass through the second conductive layer in the first region and diffuse into the substrate thereunder due to the total thickness of the conductive layer in the second region being greater than the total thickness of the conductive layer in the first region, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:
[0023] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in one embodiment of the present invention;
[0024] Figure 2 to Figure 9 The figure is a schematic structural diagram of a method for preparing a semiconductor structure during the preparation process provided in one embodiment of the present invention.
[0025] Wherein, the accompanying drawings are marked as follows:
[0026] 100-substrate, 100A-first region, 100B-second region, 101-trench isolation, 110-buried word line structure, 120-insulating layer, 121-first oxide layer, 122-second nitride layer, 123-third oxide layer, 130-first conductive layer, 131-first natural oxide layer, 130a-first doped region, 140-first photoresist layer, 150-second conductive layer, 151-second natural oxide layer, 150a-second doped region, 160-second photoresist layer, 170-third photoresist layer, 180-fourth photoresist layer, P1-first ion doping, P2-second ion doping, P3-third ion doping, P4-fourth ion doping.
[0027] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION
[0028] In order to make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.
[0029] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer according to the following description and claims. It should be noted that the accompanying drawings are all in very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It is understood that the meanings of "on", "above" and "above" in the present invention should be interpreted in the broadest way, so that "on" not only means that it is "on" something and there are no intervening features or layers (i.e. directly on something), but also includes the meaning of being "on" something and having intervening features or layers.
[0030] In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions recorded in the embodiments of the present invention can be combined arbitrarily without conflict.
[0031] Please refer to Figure 1 , Figure 1 The schematic diagram of the process of preparing the semiconductor structure provided in this embodiment. Figure 1 As shown, the method for preparing the semiconductor structure provided in this embodiment at least includes the following steps:
[0032] Step S101 , providing a substrate, wherein the substrate includes a first region and a second region.
[0033] Step S102 , forming a first conductive layer on the first region and the second region.
[0034] Step S103 , performing first ion doping on a portion of the first conductive layer in the second region to form a first doped region.
[0035] Step S104 , removing the first conductive layer on the first region.
[0036] Step S105 , forming a second conductive layer on the first region and the second region.
[0037] Step S106 , performing second ion doping on a portion of the second conductive layer in the second region to form a second doping region, wherein the second doping region is located in the first doping region and is doped with the same ion type as the first doping region.
[0038] In order to enable a person skilled in the art to which the present invention relates to easily understand the method for preparing the semiconductor structure in the embodiment of the present invention, the method for preparing the semiconductor structure proposed in the present invention will be further described below in conjunction with various structural schematic diagrams of the preparation method during the preparation process.
[0039] Figure 2 to Figure 9 The figure is a schematic structural diagram of a method for preparing a semiconductor structure during the preparation process provided in one embodiment of the present invention.
[0040] Please refer to Figure 2 , perform the above step S101: provide a substrate 100 as a setting basis for the semiconductor structure in the embodiment of the present invention, and divide the substrate 100 into a first area 100A and a second area 100B. In one embodiment, the substrate 100 can be any suitable substrate material known in the art, for example, it can be a silicon substrate, a silicon-containing substrate or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited to this. The first area 100A is, for example, a storage area (cell region) of the semiconductor structure, and the second area 100B is, for example, a peripheral region (periphery region) of the semiconductor structure, and the second area 100B is, for example, arranged adjacent to the first area 100A, but not limited to this. Further, the substrate 100 of the first area 100A and the second area 100B can also be provided with a plurality of trench isolations 101 arranged in sequence, so as to define a plurality of active areas (active area, AA, not shown in the figure) on the first area 100A, and define a plurality of transistor device areas on the second area 100B, but not limited to this. Furthermore, a plurality of buried word line structures 110 are disposed in the substrate 100 of the first region 100A, and an insulating layer 120 is disposed on the surface of the substrate 100 and the surface of the substrate 100 of the second region 100B.
[0041] In one embodiment, the trench isolation 101 may include a single layer or multiple layers of dielectric material, such as silicon oxide or silicon nitride, the buried word line structure 110 may include a gate dielectric layer, a work function layer, a conductive layer and a cap layer, the insulating layer 120 may be a single layer structure, such as a silicon oxide layer or a silicon nitride layer, or a composite layer, such as an ONO composite layer composed of a first oxide layer 121 (material such as silicon dioxide), a second nitride layer 122 (material such as silicon nitride) and a third oxide layer 123 (material such as silicon dioxide) stacked in sequence from bottom to top, but not limited to this. It should be understood that after the insulating layer 120 is formed on the surface of the substrate 100 of the second region 100B, part of the stacked layers may be further removed, such as removing the third oxide layer 123 and the second nitride layer 122, so as to meet the thickness requirements of the subsequent formation of the semiconductor structure in the second region 100B, forming Figure 2 The insulating layer shown covers the first oxide layer 121 only on the surface of the substrate 100 in the second region 100B, but the present invention is not limited thereto.
[0042] Please refer to Figure 3, perform the above step S102: using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc., to simultaneously form a first conductive layer 130 with a similar thickness on the surface of the entire substrate 100 in the first area 100A and the second area 100B. In one embodiment, the first conductive layer 130 can be used as a bottom conductive layer in the bit line structure, such as a semiconductor layer, and its material can include single crystal silicon (crystalline silicon), polycrystalline silicon (poly silicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable semiconductor materials, but not limited thereto. Under this setting, due to the material particularity of the first conductive layer 130 and the process environment, it is inevitable to encounter air or oxygen. Therefore, after the first conductive layer 130 is prepared, a thin natural oxide layer (such as silicon dioxide) will be formed on part of its surface. Exemplarily, the present invention represents the natural oxide layer located on the first conductive layer 120 as the first natural oxide layer 131; in one embodiment, the thickness of the first conductive layer 130 in the direction perpendicular to the surface of the substrate 100 (hereinafter referred to as the vertical direction) can be approximately The thickness of the first natural oxide layer 131 formed on the surface is approximately But it is not limited to this.
[0043] Please refer to Figure 4 , perform the above step S103: first use a coating process to form a first photoresist layer 140 with an opening on the first natural oxide layer 131 of the first area 100A and the second area 100B. Specifically, the bottom of the opening of the first photoresist layer 140 exposes a partial area of the first natural oxide layer 131 of the second area 100B to facilitate the subsequent ion implantation process. In one embodiment, the structural area corresponding to the first doping area 130a is specifically used to form an NMOS transistor, so the first photoresist layer 140 can be used as a mask, and along the opening, the first conductive layer 130 below the first natural oxide layer 131 exposed at the bottom of the opening is doped with a first ion P1 of a P-type ion (such as a boron ion) to form a first doping area 130a in the first conductive layer 130 of the partial area.
[0044] It should be understood that the first ion doping P1 performed in this step can be adjusted based on the thickness of the first conductive layer 130 and the type of transistor corresponding to the region, and the corresponding parameters of the P1 process thereof.
[0045] Please refer to Figure 5, perform the above step S104: after removing the first photoresist layer 140, an etching process such as at least one of dry etching or wet etching, or a grinding process can be used again to selectively remove the first natural oxide layer 131 and the first conductive layer 130 deposited on the first area 100A to expose the insulating layer 120 thereunder, so as to prepare for the subsequent formation of the second conductive layer 150.
[0046] Please refer to Figure 6 , perform the above step S105: use a deposition process to conformally form a second conductive layer 150 of similar thickness on the insulating layer 120 of the first area 100A and the first natural oxide layer 131 of the second area 100B. In one embodiment, the material of the second conductive layer 150 may be the same as that of the first conductive layer 130, for example, polysilicon; and like the first conductive layer 130, a natural oxide layer is also formed on its surface. Exemplarily, the present invention refers to the natural oxide layer located on the second conductive layer 150 as the second natural oxide layer 151; however, the thickness of the second conductive layer 150 may be different from that of the first conductive layer 130, for example, the thickness of the second conductive layer 150 in the vertical direction may be less than the thickness of the first conductive layer 130 in the vertical direction; Exemplarily, the thickness of the second conductive layer 150 may be approximately The thickness of the second natural oxide layer 151 formed on the surface can be approximately But it is not limited to this.
[0047] It should be understood that the sum of the thicknesses of the first conductive layer 130 and the second conductive layer 150 in the vertical direction in the embodiment of the present invention needs to meet the thickness requirement of the gate structure of the transistor corresponding to the combination of the two, and the specific thickness relationship between the two may be different from the above embodiment.
[0048] Please refer to Figure 7, perform the above step S106: use the coating process again to form a second photoresist layer 160 with an opening on the second natural oxide layer 151 of the first area 100A and the second area 100B. In addition, the bottom of the opening of the second photoresist layer 160 also exposes the area of the second natural oxide layer 151 of the second area 100B corresponding to the first doping area 130a, so as to facilitate the subsequent second ion implantation process. In one embodiment, the second photoresist layer 160 can be used as a mask, and along the opening therein, the second conductive layer 150 below the second natural oxide layer 151 exposed at the bottom of the opening is subjected to a second ion implantation P2 of a P-type ion type (for example, boron ions, the same ion type as that implanted by the first ion implantation P1), so as to form a second doping area 150a aligned with the first doping area 130a in the second conductive layer 150 above the first doping area. Similarly, the second ion implantation P2 performed in this step can also be adjusted based on the thickness of the second conductive layer 150 and the transistor type corresponding to the region, and the corresponding parameters of the P2 process performed thereon.
[0049] Obviously, the first conductive layer 130 formed by two deposition processes and the second conductive layer 150 stacked thereon in the embodiment of the present invention jointly serve as the gate of the transistor on the second area 100B, such as an NMOS tube or a PMOS tube. However, the embodiment of the present invention does not adopt the prior art to perform ion implantation on the second conductive layer 150 and a partial area of the first conductive layer 130 after forming the second conductive layer 150 to achieve doping of the gate of a certain type of transistor. Instead, after forming the first conductive layer 130 and the second conductive layer 150, ion doping with the same ion type is performed on the corresponding areas thereof respectively, and the process parameters of each ion doping, such as the implantation dose and the implantation energy, are adjusted based on the different thicknesses of the corresponding doped conductive layers, so that the influence of the natural oxide layer on the surface of the first conductive layer 130 and the second conductive layer 150 on the ion doping can be ignored, so that sufficient ion implantation can be obtained, and the doping concentration is uniform, and other areas will not be damaged, that is, the performance of the semiconductor structure is guaranteed.
[0050] Please refer to Figure 8, following the above step S106: the second photoresist layer 160 can be removed first, and a third photoresist layer 170 can be further formed. At this time, the third photoresist layer 170 shields the entire surface of the second natural oxide layer 151 of the second area 100B, and exposes the entire surface of the second natural oxide layer 151 of the first area 100A; then, the ion implantation process, i.e., the third ion doping P3, can be used again to perform P-type ion doping on the exposed second conductive layer 150 of the first area 100A, so as to achieve ion doping of the second conductive layer 150 of the first area 100A as the bottom conductive layer of the bit line structure, so as to reduce its corresponding resistance value. Obviously, in the embodiment of the present invention, unlike in the prior art, after the second conductive layer 150 is synchronously formed on the first area 100A and the second area 100B, partial areas of the second conductive layer 150 of the first area 100A and the second area 100B are synchronously ion implanted to achieve ion doping of the corresponding parts, but ion doping is performed on the aligned areas of the first conductive layer 130 and the second conductive layer 150 of the second area 100B respectively, and ion doping of the same ion type is performed on the corresponding second conductive layers 150 of the first area 100A and the second area 100B, respectively, thereby avoiding the problems of doping contamination and damage to the substrate under the thin conductive layer in the first area 100A caused by the implantation dose and the implantation process with a large implantation concentration required to meet the doping concentration requirement of the thicker conductive layer in the second area 100B in the prior art.
[0051] Please refer to Fig. 9 , following the above step S106: after removing the third photoresist layer 170, a fourth photoresist layer 180 with an opening may be further formed to perform fourth ion doping P4 of N-type (e.g., phosphorus ions) on the second conductive layer 150 of the remaining portion of the second region 100B, so as to complete ion doping of the gate of the PMOS transistor in the corresponding region of the second region 100B.
[0052] It should be understood that the “common shape” in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the morphological similarities and associations between two or more shapes.
[0053] In summary, in the present invention, on the one hand, for the alignment areas of the first conductive layer and the second conductive layer serving as the gate of the transistor (e.g., NMOS tube) in the peripheral circuit, ion doping with different implantation doses and implantation energies based on the thickness of different conductive layers is adopted, so as to ensure that the first conductive layer and the second conductive layer are both sufficiently implanted with ions; on the other hand, the single ion doping of the second conductive layer in the first region and the second region with the same implantation ion type is decomposed into multiple ion dopings, so as to avoid the problem that the doped ions caused by the single ion doping will pass through the second conductive layer in the first region and diffuse into the substrate thereunder due to the total thickness of the conductive layer in the second region being greater than the total thickness of the conductive layer in the first region, thereby improving the reliability of the semiconductor structure.
[0054] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate comprising a first region and a second region; forming a first conductive layer on the first region and the second region; Performing first ion doping on a portion of the first conductive layer in the second region to form a first doped region; removing the first conductive layer on the first region; forming a second conductive layer on the first region and the second region; A second ion doping is performed on a portion of the second conductive layer in the second region to form a second doping region, wherein the second doping region is located in the first doping region and is doped with the same ion type as the first doping region.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The first conductive layer and the second conductive layer are made of the same material. The first conductive layer is made of single crystal silicon, polycrystalline silicon or amorphous silicon.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that: A natural oxide layer is formed on both the first conductive layer and the second conductive layer.
4. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the first conductive layer in the vertical direction is greater than the thickness of the second conductive layer in the vertical direction.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The implantation dosage and implantation energy of the implanted ions during the first ion doping and the second ion doping are different.
6. The method for preparing a semiconductor structure according to claim 1, wherein: After forming the second doping region, the method further includes: The second conductive layer in the first region is subjected to third ion doping.
7. The method for preparing a semiconductor structure according to claim 6, characterized in that: After performing the third ion doping, the method further includes: The remaining portion of the second region of the second conductive layer is subjected to fourth ion doping.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The types of ions implanted during the first ion doping to the third ion doping are the same.
9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The ions implanted during the first ion doping to the third ion doping are P-type ions, and the P-type ions include boron ions.
10. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the first conductive layer, the method further includes: A plurality of buried word line structures are formed in the substrate in the first region.