Semiconductor memory device and method of manufacturing semiconductor memory device

Abstract

The invention provides a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a lower interlayer insulating layer, an upper interlayer insulating layer, a channel pattern passing through the lower interlayer insulating layer and the upper interlayer insulating layer, a conductive layer facing the channel pattern between the lower interlayer insulating layer and the upper interlayer insulating layer, and a memory pattern disposed in a lateral groove, the lateral groove is defined between the conductive layer and the channel pattern by a lower interlayer insulating layer and an upper interlayer insulating layer protruding beyond the conductive layer toward the channel pattern, wherein a distance from the conductive layer to the channel pattern decreases toward an end of the lateral groove.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to electronic devices and methods of manufacturing the same, and more particularly, to a semiconductor memory device and a method of manufacturing the same. Background Art

[0002] Semiconductor memory devices are used in electronic devices in various fields such as automobiles, medical treatments, and data centers, as well as small electronic devices. Therefore, the demand for semiconductor memory devices is increasing.

[0003] A semiconductor memory device may include a memory cell for storing data. A three-dimensional semiconductor memory device has been proposed to realize a large-capacity semiconductor memory device. A three-dimensional semiconductor memory device may include a plurality of memory cells arranged three-dimensionally. Summary of the invention

[0004] According to an embodiment, a semiconductor memory device may include: a lower interlayer insulating layer overlapping a center line, the center line extending in a plane parallel to the lower interlayer insulating layer; an upper interlayer insulating layer spaced apart from the lower interlayer insulating layer in a direction intersecting the plane; a first channel pattern and a second channel pattern extending to pass through the lower interlayer insulating layer and the upper interlayer insulating layer, the first channel pattern being spaced apart from the second channel pattern, and the center line being interposed between the first channel pattern and the second channel pattern; a conductive layer arranged between the lower interlayer insulating layer and the upper interlayer insulating layer, the conductive layer including a first region facing the first channel pattern, a second region facing the second channel pattern, and a third region connecting the first region to the second region; and a first data storage pattern formed in a first lateral groove, the first lateral groove being defined between the conductive layer and the first channel pattern by the lower interlayer insulating layer and the upper interlayer insulating layer, the upper interlayer insulating layer and the lower interlayer insulating layer protruding beyond the conductive layer toward the first channel pattern, wherein a variable width of the first lateral groove in the plane decreases toward an end of the first lateral groove.

[0005] According to an embodiment, a semiconductor memory device may include: a first lower interlayer insulating pattern and a second lower interlayer insulating pattern, which are spaced apart from each other and have a center line interposed therebetween, the center line extending in a direction in a plane parallel to each of the first lower interlayer insulating pattern and the second lower interlayer insulating pattern; a first upper interlayer insulating pattern, which is spaced apart from the first lower interlayer insulating pattern in a direction crossing the plane; a second upper interlayer insulating pattern, which is spaced apart from the second lower interlayer insulating pattern in a direction crossing the plane; a first channel pattern and a second channel pattern, which extend to pass from between the first lower interlayer insulating pattern and the second lower interlayer insulating pattern to between the first upper interlayer insulating pattern and the second upper interlayer insulating pattern , the first channel pattern and the second channel pattern are spaced apart from each other and a center line is interposed therebetween; a first conductive pattern is arranged between a first lower interlayer insulating pattern and a first upper interlayer insulating pattern; a second conductive pattern is arranged between the second lower interlayer insulating pattern and the second upper interlayer insulating pattern; and a first data storage pattern is formed in a first lateral groove, the first lateral groove being defined between the first conductive pattern and the first channel pattern by the first lower interlayer insulating pattern and the first upper interlayer insulating pattern, the first lower interlayer insulating pattern and the first upper interlayer insulating pattern each protruding beyond the first conductive pattern toward the first channel pattern, wherein a variable width of the first lateral groove in a plane decreases toward an end of the first lateral groove.

[0006] According to an embodiment, a semiconductor memory device may include: a first lower interlayer insulating pattern and a second lower interlayer insulating pattern, which are spaced apart from each other and have a center line interposed therebetween, the center line extending in a direction in a plane parallel to each of the first lower interlayer insulating pattern and the second lower interlayer insulating pattern; a first upper interlayer insulating pattern, which is spaced apart from the first lower interlayer insulating pattern in a direction crossing the plane; a second upper interlayer insulating pattern, which is spaced apart from the second lower interlayer insulating pattern in a direction crossing the plane; a channel layer, which extends to pass from between the first lower interlayer insulating pattern and the second lower interlayer insulating pattern to the first upper interlayer insulating pattern and a second upper interlayer insulation pattern; a first conductive pattern arranged between the first lower interlayer insulation pattern and the first upper interlayer insulation pattern; a second conductive pattern arranged between the second lower interlayer insulation pattern and the second upper interlayer insulation pattern; and a first data storage pattern formed in a first lateral groove, the first lateral groove being defined between the first conductive pattern and the channel layer by the first lower interlayer insulation pattern and the first upper interlayer insulation pattern, the first lower interlayer insulation pattern and the first upper interlayer insulation pattern each protruding beyond the first conductive pattern toward the channel layer, wherein a variable width of the first lateral groove in a plane decreases toward an end of the first data storage pattern.

[0007] According to an embodiment, a method for manufacturing a semiconductor memory device may include the following steps: forming a preliminary stacking structure including a plurality of first material layers and a plurality of second material layers alternately stacked with each other; forming a hole passing through the plurality of first material layers and the plurality of second material layers, the hole including a long axis along a first direction in a plane and a short axis along a second direction intersecting the long axis; forming a first etching barrier pattern extending along a first inner wall of the hole and a second etching barrier pattern extending along a second inner wall of the hole, the first inner wall and the second inner wall being opposite to each other in the first direction in the hole, the first etching barrier pattern and the second etching barrier pattern blocking the plurality of first material layers and the plurality of second material layers; forming a first lateral groove and a second lateral groove adjacent to each other in the second direction between two first material layers adjacent to each other in the stacking direction among the plurality of first material layers by etching the plurality of second material layers exposed through a third inner wall and a fourth inner wall facing each other in the second direction in the hole; and forming a first data storage pattern in the first lateral groove and a second data storage pattern in the second lateral groove. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present disclosure;

[0009] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure;

[0010] Figure 3A and Figure 3B is a diagram showing a vertical arrangement of a semiconductor memory device according to an embodiment of the present disclosure;

[0011] Figure 4 , Figure 5A , Figure 5B , Figure 5C , Fig. 6A and Figure 6B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure;

[0012] Figure 7 , Fig. 8A and Figure 8B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure;

[0013] Fig. 9A and Fig. 9B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure;

[0014] Fig.10 , Fig.11A and Fig. 11B It is shown Fig. 9A or Fig. 9BA diagram of a semiconductor memory device shown;

[0015] Fig.12 , Fig.13A and Fig. 13B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure;

[0016] Fig.14 , Fig.15A and Fig. 15B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure;

[0017] Fig.16 , Fig.17 , Fig.18A and Fig.18B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure;

[0018] Fig.19 , Fig. 20A , Fig. 20B , Fig.21 , Fig.22A , Fig. 22B , Fig.23 , Fig.24A , Fig. 24B , Fig.25 , Fig.26A , Fig.26B , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32A , Fig.32B , Fig.33 , Fig.34A , Fig.34B , Fig.35A and Fig.35B is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0019] Fig.36A and Fig.36B is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0020] Fig.37A and Fig.37B is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0021] Fig.38 , Fig.39A , Fig.39B , Fig.40 , Fig.41A , Fig.41B and Fig.42is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0022] Fig.43 is a plan view showing a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0023] Fig.44 , Fig.45A , Fig.45B , Fig.46 , Fig.47A , Fig.47B , Fig.48 , Fig.49A and Fig.49B is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0024] Fig.50 , Fig.51 , Fig.52 , Fig.53 , Fig.54 , Fig.55 , Fig.56 and Fig.57 is a diagram showing a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0025] Fig.58 is a plan view showing a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure; and

[0026] Fig.59 is a block diagram illustrating an electronic system including a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Specific structural or functional descriptions of examples of implementations of the concepts disclosed in this specification are only shown to describe examples of implementations according to the concepts, and examples of implementations according to the concepts may be implemented in various forms, but the descriptions are not limited to the examples of implementations described in this specification.

[0028] In the following, the use of ordinal numbers such as "first", "second", etc. in the claims to modify claim elements does not itself imply any priority, preference or order of one claim element relative to another claim element or the temporal order of performance of method actions. These terms are merely used as labels to distinguish one claim element with a particular name from another element with the same name (but using ordinal numbers).

[0029] Various embodiments of the present disclosure are directed to a semiconductor memory device capable of improving operation reliability and a method of manufacturing the same.

[0030] Figure 1is a block diagram showing a semiconductor memory device 50 according to an embodiment of the present disclosure.

[0031] Reference Figure 1 , the semiconductor memory device 50 may include a peripheral circuit 40 and a memory cell array 10 .

[0032] The peripheral circuit 40 may be configured to perform a program operation of storing data in the memory cell array 10, a read operation of outputting data stored in the memory cell array 10, and an erase operation of erasing data stored in the memory cell array 10. According to an embodiment, the peripheral circuit 40 may include an input / output circuit 21, a control circuit 23, a voltage generating circuit 31, a row decoder 33, a column decoder 35, a page buffer 37, and a source line driver 39.

[0033] The peripheral circuit 40 may be coupled to the memory cell array 10 through a common source line CSL, a bit line BL, a drain select line DSL, a word line WL, and a source select line SSL.

[0034] The input / output circuit 21 may transfer a command CMD and an address ADD received from an external device (eg, a memory controller) of the semiconductor memory device 50 to the control circuit 23. The input / output circuit 21 may exchange data DATA with the external device and the column decoder 35.

[0035] The control circuit 23 may output an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to a command CMD and an address ADD.

[0036] The voltage generating circuit 31 may generate various operation voltages Vop applied to perform a program operation, a read operation, and an erase operation.

[0037] The row decoder 33 may transfer an operating voltage Vop to the drain select line DSL, the word line WL, and the source select line SSL in response to the row address RADD.

[0038] In response to the column address CADD, the column decoder 35 may transfer the data DATA input from the input / output circuit 21 to the page buffer 37, or may transfer the data DATA stored in the page buffer 37 to the input / output circuit 21. The column decoder 35 may exchange the data DATA with the input / output circuit 21 through the column line CL. The column decoder 35 may exchange the data DATA with the page buffer 37 through the data line DL.

[0039] The page buffer 37 may store read data received through the bit line BL in response to the page buffer control signal PB_S. The page buffer 37 may sense a voltage or current in the bit line BL during a read operation.

[0040] The source line driver 39 may control a voltage applied to the common source line CSL in response to a source line control signal SL_S.

[0041] The memory cell array 10 may include a plurality of memory blocks. Each memory block may include a plurality of memory cells arranged in three dimensions. The plurality of memory cells may be grouped into a plurality of memory cell strings. Each memory cell may be a nonvolatile memory cell. According to an embodiment, each memory cell may be a NAND flash memory cell.

[0042] Figure 2 is a circuit diagram showing a memory cell array according to an embodiment of the present disclosure.

[0043] Reference Figure 2 , the memory cell array may include a memory cell string CS. The memory cell string CS may include at least one source selection transistor SST, a plurality of memory cells MC, and at least one drain selection transistor DST. The plurality of memory cells MC may be connected in series between the source selection transistor SST and the drain selection transistor DST. The source selection transistor SST, the plurality of memory cells MC, and the drain selection transistor DST may be connected in series through a channel pattern or a channel layer. The channel pattern or the channel layer may be used as a channel region of the memory cell string CS and include a semiconductor layer.

[0044] The common source region CSR and the bit line BL may be connected to the channel pattern or channel layer of the memory cell string CS. A voltage for discharging the potential of the channel region of the memory cell string CS may be applied to the common source region CSR. A voltage for precharging the channel region of the memory cell string CS may be applied to the bit line BL.

[0045] The plurality of memory cells MC of the memory cell string CS may be connected to the common source region CSR through a source select transistor SST. The plurality of memory cells MC of the memory cell string CS may be connected to a bit line BL through a drain select transistor DST.

[0046] The gate electrodes of the source select transistor SST, the plurality of memory cells MC, and the drain select transistor DST may form a gate stack structure. The gate stack structure may include a source select line SSL provided as a gate electrode of the source select transistor SST, a plurality of word lines WL provided as a plurality of gate electrodes of the plurality of memory cells MC, and a drain select line DSL provided as a gate electrode of the drain select transistor DST.

[0047] The common source region CSR may be electrically connected to Figure 1 A common source line CSL is shown. A common source region CSR may be formed in the doped semiconductor structure DPS.

[0048] Figure 3A and Figure 3B is a diagram showing a vertical arrangement of a semiconductor memory device according to an embodiment of the present disclosure.

[0049] Reference Figure 3A and Figure 3B , the semiconductor memory device may include a first structure ST1, a second structure ST2 and a doped semiconductor structure DSP. The first structure ST1 may include a cell array structure CAS and a bit line array structure BAS. The second structure ST2 may include a peripheral circuit structure PS.

[0050] The bit line array structure BAS may include the above-mentioned Figure 1 and Figure 2 The bit line BL is described.

[0051] The cell array structure CAS may be arranged between the bit line array structure BAS and the doped semiconductor structure DPS. The cell array structure CAS may include a plurality of gate electrodes coupled to a plurality of memory cell strings. The plurality of gate electrodes may include Figure 2 The source selection line SSL, the plurality of word lines WL and the drain selection line DSL are shown and may be spaced apart from each other in the vertical direction. The cell array structure CAS may include a channel pattern (or channel layer) passing through the plurality of gate electrodes. The plurality of gate electrodes and the channel pattern (or channel layer) may have various structures for improving the integration of the memory cell string.

[0052] The doped semiconductor structure DPS may include at least one of n-type impurities and p-type impurities. The doped semiconductor structure DPS may include Figure 2 The common source region CSR is shown as having n-type impurities. However, the present disclosure is not limited thereto. The doped semiconductor structure DPS may also include p-type impurities that provide a well region.

[0053] The peripheral circuit structure PS may include a region overlapping the doped semiconductor structure DPS, the cell array structure CAS, and the bit line array structure BAS. The peripheral circuit structure PS may include a region formed as follows Figure 1 The peripheral circuit 40 shown includes a plurality of transistors, capacitors, resistors, etc.

[0054] like Figure 3A As shown, the peripheral circuit structure PS can be used as Figure 3A The doped semiconductor structure DPS shown is adjacent to or may be adjacent to Figure 3A The bit line array structures BAS are shown adjacent to each other.

[0055] Although not shown, each of the first structure ST1 and the second structure ST2 may include at least one of a plurality of interconnections, a plurality of contacts, and a plurality of conductive bonding pads for electrical connection.

[0056] Hereinafter, the first direction DR1 may be the X-axis direction, the second direction DR2 and the third direction DR3 may correspond to the -Y-axis direction and the +Y-axis direction opposite to each other in the XY plane, respectively. In addition, the fourth direction DR4 described below may correspond to a vertical direction intersecting the XY plane, and may be, for example, the Z-axis direction.

[0057] Figure 4 , Figure 5A , Figure 5B , Figure 5C , Fig. 6A and Figure 6B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0058] Figure 4 is a perspective view showing a portion of a semiconductor memory device. Figure 4 , the semiconductor memory device may include gate stack structures 110 adjacent to each other with a slit SI interposed therebetween, a vertical structure VS passing through the respective gate stack structures 110, and a bit line array structure BAS.

[0059] Each gate stack structure 110 may include a plurality of conductive layers 113 spaced apart from each other and stacked on each other in the fourth direction DR4. Each gate stack structure 110 may also include a plurality of interlayer insulating layers 111 alternately arranged with the plurality of conductive layers 113 in the fourth direction DR4. In an embodiment, each of the plurality of conductive layers 113 and the plurality of interlayer insulating layers 111 may be formed in the shape of a plate extending along the XY plane.

[0060] The plurality of conductive layers 113 may be used as Figure 2 The plurality of word lines WL shown. Each conductive layer 113 may include at least one of a doped semiconductor layer, a metal layer, and a conductive metal nitride layer. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten, copper, molybdenum, etc. The conductive metal nitride layer may include titanium nitride, tantalum nitride, etc. The plurality of interlayer insulating layers 111 may include a silicon oxide layer, etc.

[0061] The vertical structure VS may extend in the fourth direction DR4 to pass through the plurality of conductive layers 113 and the plurality of interlayer insulating layers 111 of the gate stack structure 110. On the XY plane, the vertical structure VS may have a width in the first direction DR1 greater than that in the second direction DR2. The vertical structure VS may include an insulating column 135, a semiconductor oxide layer 141, a first channel pattern 131A, and a second channel pattern 131B. The first channel pattern 131A and the second channel pattern 131B may be separated from each other on the XY plane with the insulating column 135 and the semiconductor oxide layer 141 interposed therebetween. The insulating column 135 may include a first outer wall facing the second direction DR2 and a second outer wall facing the third direction DR3. The second direction DR2 and the third direction DR3 are opposite to each other on the XY plane. The first channel pattern 131A may extend in the fourth direction DR4 along the first outer wall of the insulating column 135. The second channel pattern 131B may extend in the fourth direction DR4 along the second outer wall of the insulating column 135. Each of the first channel pattern 131A and the second channel pattern 131B may be used as a channel of a memory cell string corresponding thereto. Each of the first channel pattern 131A and the second channel pattern 131B may include a semiconductor material. According to an embodiment, each of the first channel pattern 131A and the second channel pattern 131B may include silicon (Si), germanium (Ge) or a mixture thereof. The semiconductor oxide layer 141 may be obtained by oxidation of the semiconductor material of each of the first channel pattern 131A and the second channel pattern 131B.

[0062] The first memory cell MC[A] may be defined at the intersection between each conductive layer 113 and the first channel pattern 131A. The second memory cell MC[B] may be defined at the intersection between each conductive layer 113 and the second channel pattern 131B. FIG. 5A to FIG. 5C and Fig. 6A and Figure 6B The structure of each of the first memory cell MC[A] and the second memory cell MC[B] will be described.

[0063] The bit line array structure BAS may include a plurality of bit lines 151. Each bit line 151 may include a region overlapping the slit S1 and a region extending from the overlapping region in the second direction DR2 and the third direction DR3. The plurality of bit lines 151 may include a first bit line 151A connected to the first channel pattern 131A and a second bit line 151B connected to the second channel pattern 131B. The first channel pattern 131A and the second channel pattern 131B controlled by the same conductive layer 113 may be controlled by the first bit line 151A and the second bit line 151B separated from each other, respectively.

[0064] Although not shown, the first doped capping pattern may be coupled to an end of the first channel pattern 131A toward the bit line array structure BAS, and the second doped capping pattern may be coupled to an end of the second channel pattern 131B toward the bit line array structure BAS. Each of the first doped capping pattern and the second doped capping pattern may include a semiconductor layer including at least one of an n-type impurity and a p-type impurity. According to an embodiment, each of the first doped capping pattern and the second doped capping pattern may include an n-type impurity as a majority carrier.

[0065] Figure 5A It is shown in Figure 4 FIG. 1 is a plan view of a semiconductor memory device at a height where an interlayer insulating layer 111 is arranged. Figure 5B It is shown in Figure 4 A plan view of a semiconductor memory device at a height where the conductive layer 113 is arranged is shown. Figure 5C yes Figure 5B An enlarged plan view of a portion of the structure shown.

[0066] Reference FIG. 5A to FIG. 5C , each of the conductive layer 113 and the interlayer insulating layer 111 of the gate stack structure 110 may extend in the second direction DR2 and the third direction DR3 based on the center line L. The center line L may extend in the first direction DR1 on a plane. The conductive layer 113 may overlap the interlayer insulating layer 111 of the gate stack structure 110 in the fourth direction DR4. The interlayer insulating layer 111 may protrude beyond the conductive layer 113 toward the first channel pattern 131A and the second channel pattern 131B. As a result, a first transverse groove 110P1 and a second transverse groove 110P2 may be defined in the gate stack structure 110. The first transverse groove 110P1 and the second transverse groove 110P2 may be symmetrical with respect to each other about the center line L. Each of the first transverse groove 110P1 and the second transverse groove 110P2 may have a substantially semi-elliptical shape.

[0067] The conductive layer 113 may include a first region 113AR1, a second region 113AR2, and a third region 113AR3. The first region 113AR1 may face the first channel pattern 131A, and the second region 113AR2 may face the second channel pattern 131B. The first region 113AR1 may include a side portion bent along the first transverse groove 110P1. In an embodiment, the first region 113AR1 may include a side portion bent along the first transverse groove 110P1 and facing the convex side portion of the first channel pattern 131A, such as Figure 5C As shown. The second region 113AR2 may include a side portion bent along the second transverse groove 110P2. In an embodiment, the second region 113AR2 may include a side portion bent along the second transverse groove 110P2 and facing the convex side portion of the second channel pattern 131B, as shown. Figure 5C The third region 113AR3 may couple the first region 113AR1 and the second region 113AR2 to each other and extend between the vertical structure VS and another vertical structure VS adjacent thereto in the first direction DR1.

[0068] The vertical structure VS may include a tunnel insulating layer 129 having a substantially tubular shape. The tunnel insulating layer 129 may extend to cover an outer wall of the first channel pattern 131A toward the first region 113AR1 of the conductive layer 113 and an outer wall of the second channel pattern 131B toward the second region 113AR2. The tunnel insulating layer 129 may extend between the third region 113AR3 of the conductive layer 113 and the semiconductor oxide layer 141 of the vertical structure VS. The tunnel insulating layer 129 may include an insulating material that allows charge tunneling. According to an embodiment, the tunnel insulating layer 129 may include an oxide such as a silicon oxide layer.

[0069] The insulating pillar 135 of the vertical structure VS may be disposed at a central region of the tunnel insulating layer 129 having a substantially tubular shape. The insulating pillar 135 may overlap the center line L. The insulating pillar 135 may protrude toward the second direction DR2 and the third direction DR3 relative to the center line L. In a plan view, the insulating pillar 135 may have an elliptical shape, and the center line L may overlap a major axis of the insulating pillar 135.

[0070] The semiconductor oxide layer 141 of the vertical structure VS may overlap the center line L and be disposed between ends of the first channel pattern 131A and the second channel pattern 131B. The semiconductor oxide layer 141 of the vertical structure VS may be interposed between the tunnel insulating layer 129 and the insulating pillar 135 .

[0071] The first channel pattern 131A may be separated from the second channel pattern 131B due to the semiconductor oxide layer 141 and the insulating pillar 135 disposed along the center line L being interposed therebetween. Each of the first and second channel patterns 131A and 131B may be bent along a convex outer wall of the insulating pillar 135 corresponding thereto.

[0072] The first memory cell MC[A] may include a first data storage pattern 127A disposed in the first transverse groove 110P1. The second memory cell MC[B] may also include a second data storage pattern 127B disposed in the second transverse groove 110P2. The first data storage pattern 127A may be disposed between the first region 113AR1 of the conductive layer 113 and the first channel pattern 131A, thereby forming the first memory cell MC[A] controlled by the conductive layer 113 and the first channel pattern 131A. The second data storage pattern 127B may be disposed between the second region 113AR2 of the conductive layer 113 and the second channel pattern 131B, thereby forming the second memory cell MC[B] controlled by the conductive layer 113 and the second channel pattern 131B.

[0073] The first data storage pattern 127A and the second data storage pattern 127B may be symmetrical to each other about the center line L. Each of the first data storage pattern 127A and the second data storage pattern 127B may have a shape corresponding to the shape of the lateral groove to which it corresponds. According to an embodiment, the distance between the conductive layer 113 and each of the first channel pattern 131A and the second channel pattern 131B may decrease toward the center line L. For example, in an embodiment, the variable distance between the first channel pattern 131A and the conductive layer 113 decreases as the distance between the first channel pattern 131A and the conductive layer 113 from the center line L decreases, as shown in FIG. Figure 5C For example, in an embodiment, the variable distance between the second channel pattern 131B and the conductive layer 113 decreases as the distance between the second channel pattern 131B and the conductive layer 113 and the center line L decreases, as shown in FIG. Figure 5C Therefore, in an embodiment, as the distance between the conductive layer 113 and the first channel pattern 131A is measured closer to the center line L, the distance between the conductive layer 113 and the first channel pattern 131A decreases, as shown in FIG. Figure 5C Therefore, in an embodiment, as the distance between the conductive layer 113 and the second channel pattern 131B is measured closer to the center line L, the distance between the conductive layer 113 and the second channel pattern 131B decreases, as shown in FIG. Figure 5CAs shown. Therefore, in a plan view, the width of each of the first lateral groove 110P1 and the second lateral groove 110P2 may decrease toward the center line L. Therefore, the width of each of the first data storage pattern 127A and the second data storage pattern 127B may decrease toward the center line L. For example, in an embodiment, the width of the first data storage pattern 127A decreases as the distance of the first data storage pattern 127A from the center line L decreases. For example, in an embodiment, the width of the second data storage pattern 127B decreases as the distance of the second data storage pattern 127B from the center line L decreases. According to an embodiment, in a plan view, the variable width W1 of the first lateral groove 110P1 between the conductive layer 113 and the first channel pattern 131A may decrease toward the end of the first lateral groove 110P1. In addition, in an embodiment, in a plan view, the variable width W2 of the second lateral groove 110P2 between the conductive layer 113 and the second channel pattern 131B may decrease toward the end of the second lateral groove 110P2. Therefore, in an embodiment, as the first data storage pattern 127A is disposed closer to the center line L, the width of the first data storage pattern 127A may decrease, such as Figure 5C Likewise, in an embodiment, as the second data storage pattern 127B is disposed closer to the center line L, the width of the second data storage pattern 127B may decrease, as shown in FIG. Figure 5C shown.

[0074] According to the above-described embodiment of the present disclosure, the data storage pattern 127A or 127B may have an inner wall toward the channel pattern 131A or 131B and an outer wall toward the conductive layer 113. In an embodiment, the width of the data storage pattern 127A or 127B may decrease toward the end, such as Figure 5C As shown. Although not shown, contrary to the embodiments of the present disclosure, when the uniform width of the data storage pattern is maintained, the electric field between the channel pattern 131A or 131B and the conductive layer 113 can be reduced toward the end of the data storage pattern. According to the embodiments of the present disclosure, since the width of the data storage pattern 127A or 127B decreases toward the end as the end is disposed closer to the center line L, the electric field between the channel pattern 131A or 131B and the conductive layer 113 can be prevented or mitigated from decreasing toward the end. Therefore, in the embodiments, the operational reliability of the semiconductor memory device can be improved.

[0075] Each of the first data storage pattern 127A and the second data storage pattern 127B may include a material layer storing data that changes using Fowler-Nordheim tunneling. According to an embodiment, each of the first data storage pattern 127A and the second data storage pattern 127B may include a charge trapping insulating layer, a floating gate layer, or an insulating layer including conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. The floating gate layer may include a silicon layer. However, embodiments are not limited thereto. Each of the first data storage pattern 127A and the second data storage pattern 127B may include a material layer storing information based on other operating principles other than Fowler-Nordheim tunneling. According to an embodiment, each of the first data storage pattern 127A and the second data storage pattern 127B may include a phase change material layer, a ferroelectric layer, etc.

[0076] The semiconductor memory device may further include a blocking insulating layer 120 extending along the side of each of the first region 113AR1 and the second region 113AR2 of the conductive layer 113. The blocking insulating layer 120 may include a first dielectric layer 121, a second dielectric layer 123A or 123B, and a third dielectric layer 125A or 125B. The first dielectric layer 121 may extend along the side of the third region 113AR3 of the conductive layer 113 and be interposed between the third region 113AR3 of the conductive layer 113 and the tunnel insulating layer 129. The first dielectric layer 121 may include an oxide layer such as a silicon oxynitride layer and a silicon oxide layer. The second dielectric layer 123A or 123B may include a nitride layer such as a silicon nitride layer. The third dielectric layer 125A or 125B may include an oxide layer such as a silicon oxynitride layer. Each of the second and third dielectric layers may be separated into a first pattern 123A or 125A between the first region 113AR1 of the conductive layer 113 and the first data storage pattern 127A and a second pattern 123B or 125B between the second region 113AR2 of the conductive layer 113 and the second data storage pattern 127B. A tunnel insulating layer 129 may extend between the first pattern 123A or 125A and the second pattern 123B or 125B of each of the second and third dielectric layers.

[0077] Fig. 6A It is along Figure 4 A cross-sectional view of a semiconductor memory device taken along line Ia-Ia'. Figure 6B It is shown along Figure 4 A cross-sectional view of the semiconductor memory device taken along line IIa-IIa'.

[0078] Reference Fig. 6A and Figure 6B , the first memory cell string CS1 and the second memory cell string CS2 may be formed at both sides of the vertical structure VS.

[0079] The first channel pattern 131A of the first memory cell string CS1 may be formed by Figure 4 The first bit line 151A shown in FIG. 1 controls the second channel pattern 131B of the second memory cell string CS2. Figure 4 The second bit line 151B shown controls.

[0080] The plurality of conductive layers 113 of the gate stack structure 110 may be used as a plurality of word lines. A plurality of first memory cells of the first memory cell string CS1 may be formed between the plurality of conductive layers 113 and the first channel pattern 131A. A plurality of second memory cells of the second memory cell string CS2 may be formed between the plurality of conductive layers 113 and the second channel pattern 131B.

[0081] A plurality of first data storage patterns 127A of a plurality of first memory cells may be respectively disposed in a plurality of first transverse grooves 110P1 separated from each other by a plurality of interlayer insulating layers 111 along a fourth direction DR4. A plurality of second data storage patterns 127B of a plurality of second memory cells may be respectively disposed in a plurality of second transverse grooves 110P2 separated from each other by a plurality of interlayer insulating layers 111 along a fourth direction DR4. For example, the plurality of interlayer insulating layers 111 may include a lower interlayer insulating layer LI and an upper interlayer insulating layer UI separated from the lower interlayer insulating layer LI in the fourth direction DR4. The lower interlayer insulating layer LI and the upper interlayer insulating layer UI may protrude toward the first channel pattern 131A and the second channel pattern 131B beyond the conductive layer 113 therebetween. As a result, a first transverse groove 110P1 may be defined between the conductive layer 113 and the first channel pattern 131A, and a second transverse groove 110P2 may be defined between the conductive layer 113 and the second channel pattern 131B. The first and second transverse grooves 110P1 and 110P2 may be separated from each other by a vertical structure VS.

[0082] According to an embodiment of the present disclosure, charges stored in the first and second data storage patterns 127A and 127B may be prevented or mitigated from moving in the fourth direction DR4 , so that operational reliability of the semiconductor memory device may be improved.

[0083] The first dielectric layer 121 of the blocking insulating layer 120 may have a ring shape formed along the sides of the first region 113AR1, the second region 113AR2, and the third region 113AR312 of each conductive layer 113. The second dielectric layer 123A or 123B and the third dielectric layer 125A or 125B of the blocking insulating layer 120 may be interposed between the corresponding data storage pattern 127A or 127B and the first dielectric layer 121, and may extend between the corresponding data storage pattern 127A or 127B and the interlayer insulating layer 111. The interlayer insulating layer 111 may contact the second dielectric layer 123A or 123B without interposing the first dielectric layer 121. The interlayer insulating layer 111 may contact the vertical structure VS without interposing the blocking insulating layer 120.

[0084] Each of the tunnel insulating layer 129 , the first channel pattern 131A, the insulating pillar 135 , the semiconductor oxide layer 141 , and the second channel pattern 131B may extend in the fourth direction DR4 to pass through the plurality of interlayer insulating layers 111 and the plurality of conductive layers 113 .

[0085] Figure 7 , Fig. 8A and Figure 8B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0086] Figure 7 is a plan view showing a semiconductor memory device. Fig. 8A It is along Figure 7 A cross-sectional view of a semiconductor memory device taken along line Ib-Ib'. Figure 8B It is shown along Figure 7 A cross-sectional view of a semiconductor memory device taken along line IIb-IIb'. Figure 4 , FIG. 5A to FIG. 5C as well as Fig. 6A and Figure 6B Descriptions of configurations that are the same as those described are simplified or omitted.

[0087] Reference Figure 7 , Fig. 8A and Figure 8B , the gate stack structure 110 of the semiconductor memory device may include a plurality of interlayer insulating layers 111 and a plurality of conductive layers 113 alternately stacked in the fourth direction DR4. The gate stack structure 110 may be penetrated by the vertical structure VS.

[0088] The vertical structure VS may include an insulating partition wall 143, a first channel pattern 131A, a second channel pattern 131B, a pillar pattern 135A or 135B, and a tunnel insulating layer 129. Each of the insulating partition wall 143, the first channel pattern 131A, the second channel pattern 131B, the pillar pattern 135A or 135B, and the tunnel insulating layer 129 may extend in a fourth direction DR4 to pass through the plurality of conductive layers 113 and the plurality of interlayer insulating layers 111.

[0089] The insulating partition wall 143 may extend in the first direction DR1 and overlap with a center line L passing through the center of the vertical structure VS. The insulating partition wall 143 may be wider in the first direction DR1 than in the second direction DR2.

[0090] The first channel pattern 131A and the second channel pattern 131B may be separated from each other while interposing the insulating partition wall 143. The pillar pattern 135A or 135B may be interposed between the insulating partition wall 143 and each of the first channel pattern 131A and the second channel pattern 131B. The pillar pattern 135A or 135B and the insulating partition wall 143 may include the same or different materials from each other. The pillar pattern 135A or 135B may include a side portion protruding toward the channel pattern 131A or 131B corresponding thereto.

[0091] The tunnel insulating layer 129 may be separated into a first tunnel insulating pattern 129A and a second tunnel insulating pattern 129B by the insulating partition wall 143. The first tunnel insulating pattern 129A may extend along the outer wall of the first channel pattern 131A toward the first region 113AR1 of the conductive layer 113. The second tunnel insulating pattern 129B may extend along the outer wall of the second channel pattern 131B toward the second region 113AR2 of the conductive layer 113. However, the embodiments of the present disclosure are not limited thereto. According to another embodiment, the tunnel insulating layer 129 may extend between the third region 113AR3 of the conductive layer 113 and the insulating partition wall 143 and have a substantially tubular shape, such as FIG. 5A to FIG. 5C shown.

[0092] The plurality of interlayer insulating layers 111 may protrude toward the first and second channel patterns 131A and 131B beyond the plurality of conductive layers 113 . As a result, first and second lateral grooves 110P1 and 110P2 may be defined in the gate stack structure 110 .

[0093] The first channel pattern 131A may be separated from the second channel pattern 131B by an insulating partition wall 143 arranged along the center line L. The first channel pattern 131A may serve as a channel region of the first memory cell string CS1. The second channel pattern 131B may serve as a channel region of the second memory cell string CS2.

[0094] The first memory cell of the first memory cell string CS1 may include a first data storage pattern 127A disposed in the first lateral groove 110P1. The second memory cell of the second memory cell string CS2 may include a second data storage pattern 127B disposed in the second lateral groove 110P2. The first data storage pattern 127A may be disposed between the first region 113AR1 of the conductive layer 113 and the first channel pattern 131A, thereby forming a first memory cell controlled by the conductive layer 113 and the first channel pattern 131A. The second data storage pattern 127B may be disposed between the second region 113AR2 of the conductive layer 113 and the second channel pattern 131B, thereby forming a second memory cell controlled by the conductive layer 113 and the second channel pattern 131B.

[0095] The width of each of the first lateral groove 110P1 , the second lateral groove 110P2 , the first data storage pattern 127A, and the second data storage pattern 127B may decrease toward the center line L. As shown in FIG.

[0096] The blocking insulating layer 120 of the semiconductor memory device may include a first dielectric layer 121 extending along the side of each of the first region 113AR1 and the second region 113AR2. The first dielectric layer 121 of the blocking insulating layer 120 may extend along the side of the third region 113AR3 of the conductive layer 113 and have a ring shape. However, the embodiments of the present disclosure are not limited thereto. According to another embodiment, the insulating partition wall 143 may extend toward the third region 113AR3 of the conductive layer 113 to pass through the first dielectric layer 121 of the blocking insulating layer 120. The first dielectric layer 121 of the blocking insulating layer 120 may be separated into a first pattern located between the first region 113AR1 of the conductive layer 113 and the first data storage pattern 127A and a second pattern located between the second region 113AR2 of the conductive layer 113 and the second data storage pattern 127B. The blocking insulating layer 120 may also include a second dielectric layer and a third dielectric layer. Each of the second and third dielectric layers of the blocking insulating layer 120 may be separated into a first pattern 123A or 125A between the first region 113AR1 of the conductive layer 113 and the first data storage pattern 127A and a second pattern 123B or 125B between the second region 113AR2 of the conductive layer 113 and the second data storage pattern 127B. The tunnel insulating layer 129 may extend between the first and second patterns 123A or 125A and 123B or 125B of each of the second and third dielectric layers.

[0097] The first channel pattern 131A of the first memory cell string CS1 and the second channel pattern 131B of the second memory cell string CS2 may be controlled by the first bit line 151A and the second bit line 151B, respectively. Figure 4 shown.

[0098] Fig. 9A and Fig. 9B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0099] Reference Fig. 9A and Fig. 9B , the semiconductor memory device may include a gate stack structure 110 , a first vertical structure VS1 , a second vertical structure VS2 , an insulating partition wall 145 , and a bit line array structure BAS.

[0100] The gate stack structure 110 may be Figure 4 The gate stack structure 110 may include a first sub-stack 110A and a second sub-stack 110B separated from each other by an insulating partition wall 145. The insulating partition wall 145 may cross the gate stack structure 110 and extend in a first direction DR1. The first sub-stack 110A may extend from the insulating partition wall 145 in a second direction DR2. The second sub-stack 110B may extend from the insulating partition wall 145 in a third direction DR3.

[0101] The first sub-stack 110A may include a plurality of first conductive patterns 113A stacked separately from each other in the fourth direction DR4. The second sub-stack 110B may include a plurality of second conductive patterns 113B stacked separately from each other in the fourth direction DR4. The first sub-stack 110A may also include a plurality of first interlayer insulating patterns 111A arranged alternately with the plurality of first conductive patterns 113A in the fourth direction DR4. The second sub-stack 110B may also include a plurality of second interlayer insulating patterns 111B arranged alternately with the plurality of second conductive patterns 113B in the fourth direction DR4. Each of the plurality of first conductive patterns 113A, the plurality of second conductive patterns 113B, the plurality of first interlayer insulating patterns 111A, and the plurality of second interlayer insulating patterns 111B may have a plate shape extending along a plane. Each of the plurality of first conductive patterns 113A and the plurality of second conductive patterns 113B may be used as Figure 2 The word line WL is shown.

[0102] The plurality of first conductive patterns 113A and the plurality of second conductive patterns 113B may include Figure 4 The conductive materials of the plurality of conductive layers 113 shown illustrate various conductive materials. The plurality of first interlayer insulating patterns 111A and the plurality of second interlayer insulating patterns 111B may include a silicon oxide layer.

[0103] The first vertical structure VS1 may extend in the fourth direction DR4 to pass through the plurality of first conductive patterns 113A and the plurality of first interlayer insulating patterns 111A of the first sub-stack 110A. The second vertical structure VS2 may extend in the fourth direction DR4 to pass through the plurality of second conductive patterns 113B and the plurality of second interlayer insulating patterns 111B of the second sub-stack 110B. Each of the first vertical structure VS1 and the second vertical structure VS2 may include a partition wall side lateral portion contacting the insulating partition wall 145. The first vertical structure VS1 and the second vertical structure VS2 may extend in the second direction DR2 and the third direction DR3 opposite to each other based on the insulating partition wall 145. The first vertical structure VS1 may include a gate side lateral portion protruding in the second direction DR2. The second vertical structure VS2 may include a gate side lateral portion protruding in the third direction DR3.

[0104] The first vertical structure VS1 may include a first channel pattern 131A, and the second vertical structure VS2 may include a second channel pattern 131B. Each of the first vertical structure VS1 and the second vertical structure VS2 may further include a pillar pattern 135A or 135B disposed between the corresponding channel pattern 131A or 131B and the insulating partition wall 145. The pillar pattern 135A or 135B may include an insulating material that is the same as or different from the insulating material of the insulating partition wall 145. Each of the first channel pattern 131A and the second channel pattern 131B may serve as a channel of the corresponding memory cell string. Each of the first channel pattern 131A and the second channel pattern 131B may include a first channel pattern 131A or a second channel pattern 131B as described above with reference to Figure 4 The first channel pattern 131A and the second channel pattern 131B may be connected to a plurality of bit lines 151 of the bit line array structure BAS in various ways.

[0105] Reference Fig. 9A , the plurality of bit lines 151 may include a first bit line 151A connected to the first channel pattern 131A and a second bit line 151B connected to the second channel pattern 131B. Therefore, the first channel pattern 131A may be controlled by the first bit line 151A and the first conductive pattern 113A. The second channel pattern 131B may be controlled by the second bit line 151B and the second conductive pattern 113B.

[0106] Reference Fig. 9B , each bit line 151 may be connected to the first channel pattern 131A and the second channel pattern 131B facing each other. The first channel pattern 131A and the second channel pattern 131B connected to the same bit line 151 may be controlled by the first conductive pattern 113A and the second conductive pattern 113B, respectively.

[0107] The first channel pattern 131A may be used as a channel region of a first memory cell. The second channel pattern 131B may be used as a channel region of a second memory cell. A first data storage pattern of the first memory cell may be disposed in a first transverse groove between the first vertical structure VS1 and each first conductive pattern 113A. A second data storage pattern of the second memory cell may be disposed in a second transverse groove between the second vertical structure VS2 and each second conductive pattern 113B. Fig.10 , Fig.11A and Fig. 11B The structures of the first data storage pattern and the second data storage pattern are described.

[0108] Fig.10 , Fig.11A and Fig. 11B It is shown Fig. 9A or Fig. 9B A diagram of a semiconductor memory device is shown.

[0109] Fig.10 It is shown Fig. 9A or Fig. 9B The following is a plan view of a semiconductor memory device as shown in FIG. FIG. 5A to FIG. 5C Descriptions of components that are the same as those in the described embodiments will be simplified or omitted.

[0110] Reference Fig.10 , the center line L may be defined in the first direction DR1 along the insulating partition wall 145. The first conductive pattern 113A of the first sub-stack 110A and the second conductive pattern 113B of the second sub-stack 110B may extend in the second direction DR2 and the third direction DR3 opposite to each other with respect to the center line L. In a plan view, the center line L may be interposed between the first conductive pattern 113A and the second conductive pattern 113B. Fig. 9A or Fig. 9B The first interlayer insulating pattern 111A and the first sub-stack 110A are shown Fig. 9A or Fig. 9B The second interlayer insulating pattern 111B of the second sub-stack 110B shown may extend in the second direction DR2 and the third direction DR3 opposite to each other with respect to the center line L. In a plan view, the center line L may be inserted between Fig. 9A or Fig. 9B The first interlayer insulating pattern 111A and Fig. 9A or Fig. 9B The second interlayer insulating pattern 111B is shown. Fig. 9A or Fig. 9BThe first interlayer insulating pattern 111A of the first sub-stack 110A shown may protrude beyond the first conductive pattern 113A toward the first vertical structure VS1. As a result, a first transverse groove 110P1 may be defined in the first sub-stack 110A. Fig. 9A or Fig. 9B The second interlayer insulating pattern 111B of the second sub-stack 110B shown may protrude beyond the second conductive pattern 113B toward the second vertical structure VS2. As a result, a second transverse groove 110P2 may be defined in the second sub-stack 110B. The first transverse groove 110P1 and the second transverse groove 110P2 may have the same shape as described above with reference to FIG. FIG. 5A to FIG. 5C Same structure as described.

[0111] The first conductive pattern 113A may include a side portion bent along the first transverse groove 110P1. The second conductive pattern 113B may include a side portion bent along the second transverse groove 110P2. The first data storage pattern 127A and the first blocking insulating pattern 120A may be arranged in the first transverse groove 110P1. The second data storage pattern 127B and the second blocking insulating pattern 120B may be arranged in the second transverse groove 110P2.

[0112] The first blocking insulating pattern 120A may extend along the inner wall of the first conductive pattern 113A toward the first channel pattern 131A. The second blocking insulating pattern 120B may extend along the inner wall of the second conductive pattern 113B toward the second channel pattern 131B. Each of the first blocking insulating pattern 120A and the second blocking insulating pattern 120B may include a first dielectric layer 121A or 121B, a second dielectric layer 123A or 123B, and a third dielectric layer 125A or 125B. The first dielectric layer 121A or 121B, the second dielectric layer 123A or 123B, and the third dielectric layer 125A or 125B may include the above-mentioned FIG. 5A to FIG. 5C Each of the first dielectric layer 121A or 121B, the second dielectric layer 123A or 123B, and the third dielectric layer 125A or 125B may be separated into a first pattern 121A, 123A, or 125A and a second pattern 121B, 123B, or 125B.

[0113] The insulating partition wall 145 may pass between the pillar pattern 135A of the first vertical structure VS1 and the pillar pattern 135B of the second vertical structure VS2 and pass through the first channel pattern 131A and the second channel pattern 131B. The insulating partition wall 145 may pass between the first blocking insulating pattern 120A and the second blocking insulating pattern 120B and pass through the first conductive pattern 113A and the second conductive pattern 113B.

[0114] The first vertical structure VS1 may further include a first tunnel insulation pattern 129A, and the second vertical structure VS2 may further include a second tunnel insulation pattern 129B. The first tunnel insulation pattern 129A may surround an outer wall of the first channel pattern 131A facing the first conductive pattern 113A. The second tunnel insulation pattern 129B may surround an outer wall of the second channel pattern 131B. Each of the first tunnel insulation pattern 129A and the second tunnel insulation pattern 129B may include an insulating material that allows charge tunneling.

[0115] The first data storage pattern 127A may be interposed between the first blocking insulating pattern 120A and the first tunnel insulating pattern 129A. The second data storage pattern 127B may be interposed between the second blocking insulating pattern 120B and the second tunnel insulating pattern 129B. The first data storage pattern 127A and the second data storage pattern 127B may be symmetrical to each other about the center line L. Each of the first data storage pattern 127A and the second data storage pattern 127B may have a shape corresponding to the shape of the lateral groove to which it corresponds. According to an embodiment, the distance between the first channel pattern 131A and the first conductive pattern 113A and the distance between the second channel pattern 131B and the second conductive pattern 113B may decrease toward the center line L. For example, in an embodiment, the variable distance between the first channel pattern 131A and the first conductive pattern 113A decreases as the distance between the first channel pattern 131A and the first conductive pattern 113A from the center line L decreases. For example, in an embodiment, the variable distance between the second channel pattern 131B and the second conductive pattern 113B decreases as the distance of the second channel pattern 131B and the second conductive pattern 113B from the center line L decreases. In response, the width of each of the first lateral groove 110P1 and the second lateral groove 110P2 may decrease toward the center line L. Therefore, the width of each of the first data storage pattern 127A and the second data storage pattern 127B may decrease toward the center line L. The first data storage pattern 127A and the second data storage pattern 127B may include the above reference FIG. 5A to FIG. 5C Materials as described.

[0116] Fig.11A It is along Fig.10 A cross-sectional view of a semiconductor memory device taken along line Ic-Ic'. Fig. 11B It is shown along Fig.10 A cross-sectional view of a semiconductor memory device taken along line IIc-IIc'. Fig. 6A and Figure 6B Descriptions of components that are the same as those in the described embodiments will be simplified or omitted.

[0117] Reference Fig.11A and Fig. 11B, the first memory cell string CS1' may be defined along the first vertical structure VS1, and the second memory cell string CS2' may be defined along the second vertical structure VS2. The first blocking insulating pattern 120A, the first data storage pattern 127A, the first tunnel insulating pattern 129A, and the first channel pattern 131A of the first memory cell string CS1' may be separated from the second blocking insulating pattern 120B, the second data storage pattern 127B, the second tunnel insulating pattern 129B, and the second channel pattern 131B of the second memory cell string CS2' by the insulating partition wall 145. Therefore, interference between the operations of the first memory cell string CS1' and the second memory cell string CS2' may be reduced, so that the operational reliability of the semiconductor memory device may be improved.

[0118] The first conductive pattern 113A of the first sub-stack 110A and the second conductive pattern 113B of the second sub-stack 110B may be separated from each other by the insulating partition wall 145. The first interlayer insulating pattern 111A of the first sub-stack 110A and the second interlayer insulating pattern 111B of the second sub-stack 110B may be separated from each other by the insulating partition wall 145.

[0119] The first memory cell string CS1' may include a plurality of first memory cells connected in series through a first channel pattern 131A. A plurality of first data storage patterns 127A of the plurality of first memory cells may be respectively disposed in a plurality of first transverse grooves 110P1 separated from each other by a plurality of first interlayer insulation patterns 111A along a fourth direction DR4. For example, the plurality of first interlayer insulation patterns 111A may include a first lower interlayer insulation pattern LI1 and a first upper interlayer insulation pattern UI1 separated from the first lower interlayer insulation pattern LI1 in the fourth direction DR4. The first lower interlayer insulation pattern LI1 and the first upper interlayer insulation pattern UI1 may protrude toward the first channel pattern 131A beyond the first conductive pattern 113A therebetween. Therefore, a first transverse groove 110P1 may be defined between the first conductive pattern 113A and the first channel pattern 131A. In an embodiment, since the first data storage patterns 127A adjacent to each other in the fourth direction DR4 are separated from each other, the charges stored in the respective first memory cells may be prevented or mitigated from moving in the fourth direction DR4.

[0120] The second memory cell string CS2' may include a plurality of second memory cells connected in series through a second channel pattern 131B. A plurality of second data storage patterns 127B of the plurality of second memory cells may be respectively disposed in a plurality of second transverse grooves 110P2 separated from each other by a plurality of second interlayer insulation patterns 111B along a fourth direction DR4. For example, the plurality of second interlayer insulation patterns 111B may include a second lower interlayer insulation pattern LI2 and a second upper interlayer insulation pattern UI2 separated from the second lower interlayer insulation pattern LI2 in the fourth direction DR4. The second lower interlayer insulation pattern LI2 and the second upper interlayer insulation pattern UI2 may protrude toward the second channel pattern 131B beyond the second conductive pattern 113B therebetween. Therefore, a second transverse groove 110P2 may be defined between the second conductive pattern 113B and the second channel pattern 131B. In an embodiment, since the second data storage patterns 127B adjacent to each other in the fourth direction DR4 may be separated from each other, the charges stored in the respective second memory cells may be prevented or mitigated from moving in the fourth direction DR4.

[0121] Fig.12 , Fig.13A and Fig. 13B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0122] Fig.12 is a plan view showing a semiconductor memory device. Fig.13A It is along Fig.12 A cross-sectional view of a semiconductor memory device taken along line Id-Id'. Fig. 13B It is shown along Fig.12 A cross-sectional view of a semiconductor memory device taken along line IId-IId'. Fig. 9A , Fig. 9B , Fig.10 , Fig.11A and Fig. 11B Descriptions of configurations that are the same as those described are simplified or omitted.

[0123] Reference Fig.12 , Fig.13A and Fig. 13B , the semiconductor memory device may include a vertical structure VS, an insulating partition wall 147, a first sub-stack 110A, a second sub-stack 110B, a first blocking insulating pattern 120A, a second blocking insulating pattern 120B, a first data storage pattern 127A, and a second data storage pattern 127B.

[0124] The vertical structures VS and the insulating partition walls 147 may be alternately arranged with each other on a plane along a center line L extending in the first direction DR1 . The first and second sub-stacks 110A and 110B may be separated from each other by the vertical structures VS and the insulating partition walls 147 .

[0125] The first sub-stack 110A may include a plurality of first interlayer insulating patterns 111A and a plurality of first conductive patterns 113A alternately arranged with each other in the fourth direction DR4. The second sub-stack 110B may include a plurality of second interlayer insulating patterns 111B and a plurality of second conductive patterns 113B alternately arranged with each other in the fourth direction DR4.

[0126] The first interlayer insulating pattern 111A of the first sub-stack 110A may protrude beyond the first conductive pattern 113A toward the vertical structure VS. As a result, a first transverse groove 110P1 may be defined in the first sub-stack 110A. The second interlayer insulating pattern 111B of the second sub-stack 110B may protrude beyond the second conductive pattern 113B toward the vertical structure VS. As a result, a second transverse groove 110P2 may be defined in the second sub-stack 110B. The first transverse groove 110P1 and the second transverse groove 110P2 may have the same shape as described above with reference to FIG. FIG. 5A to FIG. 5C Same structure as described.

[0127] The first conductive pattern 113A may include a side portion bent along the first transverse groove 110P1. The second conductive pattern 113B may include a side portion bent along the second transverse groove 110P2. Fig.10 As described above, the first data storage pattern 127A and the first blocking insulating pattern 120A may be disposed in the first transverse groove 110P1. The second data storage pattern 127B and the second blocking insulating pattern 120B may be disposed in the second transverse groove 110P2. Fig.10 As described, each of the first and second blocking insulating patterns 120A and 120B may include a first dielectric layer 121A or 121B, a second dielectric layer 123A or 123B, and a third dielectric layer 125A or 125B.

[0128] The vertical structure VS may include an insulating pillar 135 , a first channel pattern 131A, a second channel pattern 131B, a first tunnel insulation pattern 129A, and a second tunnel insulation pattern 129B.

[0129] The insulating pillar 135 may include an outer wall protruding in the second direction DR2 and the third direction DR3 opposite to each other in a plane. The insulating pillar 135 may include a major axis overlapping the center line L and a minor axis crossing the center line L. According to an embodiment, the insulating pillar 135 may include a substantially elliptical cross section. The insulating pillar 135 may extend from the inner wall of the first channel pattern 131A toward the inner wall of the second channel pattern 131B.

[0130] The first channel pattern 131A and the second channel pattern 131B may be separated from each other with the insulating pillar 135 interposed therebetween. The first channel pattern 131A and the second channel pattern 131B may be bent along an outer wall of the insulating pillar 135.

[0131] The first tunnel insulating pattern 129A and the second tunnel insulating pattern 129B may have the Fig.10 The same materials as described above and may have Fig.10 Same structure as described.

[0132] The insulating partition wall 147 may extend from the insulating pillar 135 to be interposed between the end of the first channel pattern 131A and the end of the second channel pattern 131B. The insulating partition wall 147 may pass between the first blocking insulating pattern 120A and the second blocking insulating pattern 120B to separate each of the second dielectric layer and the third dielectric layer into the first pattern 121A, 123A, or 125A and the second pattern 121B, 123B, or 125B. The insulating partition wall 147 may be interposed between the insulating pillars 135 adjacent to each other in the first direction DR1 and between the first sub-stack 110A and the second sub-stack 110B.

[0133] The insulating partition walls 147 may include the same material as or a different material from the insulating pillars 135 .

[0134] The first channel pattern 131A and the second channel pattern 131B may be Fig. 9A 151A and 151B, respectively, as shown, or may be connected to the first bit line 151A and the second bit line 151B as shown. Fig. 9B As shown, they are connected to the same bit line 151.

[0135] Fig.14 , Fig.15A and Fig. 15B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0136] Fig.14 is a plan view showing a semiconductor memory device. Fig.15A It is along Fig.14 A cross-sectional view of a semiconductor memory device taken along line Ie-Ie'. Fig. 15B It is shown along Fig.14A cross-sectional view of a semiconductor memory device taken along line IIe-IIe'. Fig. 9A , Fig. 9B , Fig.10 , Fig.11A and Fig. 11B Descriptions of configurations that are the same as those described are simplified or omitted.

[0137] Reference Fig.14 , Fig.15A and Fig. 15B , the semiconductor memory device may include a vertical structure VS, a first insulating partition wall 133P, a first sub-stack 110A, a second sub-stack 110B, a blocking insulating layer 120, a first data storage pattern 127A, and a second data storage pattern 127B.

[0138] The vertical structure VS may include a second insulating partition wall 149, a first channel pattern 131A, a second channel pattern 131B, a pillar pattern 135A or 135B, and a tunnel insulating layer 129. Each of the second insulating partition wall 149, the first channel pattern 131A, the second channel pattern 131B, the pillar pattern 135A or 135B, and the tunnel insulating layer 129 may extend in the fourth direction DR4.

[0139] The second insulating partition walls 149 may extend in the first direction DR1 and overlap with a center line L passing through the center of the vertical structure VS. The second insulating partition walls 149 may be wider in the first direction DR1 than in the second direction DR2. The second insulating partition walls 149 may be alternately arranged with the first insulating partition walls 133P in the first direction DR1. The second insulating partition walls 149 may extend to be interposed between an end of the first channel pattern 131A and an end of the second channel pattern 131B.

[0140] The first channel pattern 131A and the second channel pattern 131B may be separated from each other with the second insulating partition wall 149 interposed therebetween. The pillar pattern 135A or 135B may be interposed between each of the first channel pattern 131A and the second channel pattern 131B and the second insulating partition wall 149. The pillar pattern 135A or 135B may include a side protruding toward the corresponding channel pattern 131A or 131B. The first channel pattern 131A and the second channel pattern 131B may be bent along the side of the corresponding pillar pattern 135A or 135B.

[0141] The tunnel insulating layer 129 may surround the outer wall of each of the first channel pattern 131A and the second channel pattern 131B. The outer wall of the first channel pattern 131A may face the first conductive pattern 113A and the first interlayer insulating pattern 111A. The outer wall of the second channel pattern 131B may face the second conductive pattern 113B and the second interlayer insulating pattern 111B. According to an embodiment, the tunnel insulating layer 129 may extend between the first insulating partition wall 133P and the second insulating partition wall 149. However, the embodiments of the present disclosure are not limited thereto. According to another embodiment, the second insulating partition wall 149 may extend toward the blocking insulating layer 120 so that the tunnel insulating layer 129 may be separated into the first tunnel insulating pattern and the second tunnel insulating pattern.

[0142] The first insulating partition wall 133P may be interposed between the first and second sub-stacks 110A and 110B between the vertical structures VS adjacent to each other in the first direction DR1. The first insulating partition wall 133P, the pillar pattern 135A or 135B, and the second insulating partition wall 149 may include the same or different materials.

[0143] The first sub-stack 110A may include a plurality of first interlayer insulating patterns 111A and a plurality of first conductive patterns 113A alternately arranged with each other in the fourth direction DR4. The second sub-stack 110B may include a plurality of second interlayer insulating patterns 111B and a plurality of second conductive patterns 113B alternately arranged with each other in the fourth direction DR4.

[0144] The first interlayer insulating pattern 111A of the first sub-stack 110A may protrude beyond the first conductive pattern 113A toward the vertical structure VS. As a result, a first transverse groove 110P1 may be defined in the first sub-stack 110A. The second interlayer insulating pattern 111B of the second sub-stack 110B may protrude beyond the second conductive pattern 113B toward the vertical structure VS. As a result, a second transverse groove 110P2 may be defined in the second sub-stack 110B. The first transverse groove 110P1 and the second transverse groove 110P2 may have the same shape as described above with reference to FIG. FIG. 5A to FIG. 5C Same structure as described.

[0145] The first conductive pattern 113A may include a side portion bent along the first transverse groove 110P1. The second conductive pattern 113B may include a side portion bent along the second transverse groove 110P2. Fig.10 As described, the first data storage pattern 127A may be disposed in the first transverse groove 110P1 , and the second data storage pattern 127B may be disposed in the second transverse groove 110P2 .

[0146] The blocking insulating layer 120 may extend along each of the inner wall of the first conductive pattern 113A toward the first channel pattern 131A and the inner wall of the second conductive pattern 113B toward the second channel pattern 131B. FIG. 5A to FIG. 5C As described, the blocking insulating layer 120 may include a first dielectric layer 121, a second dielectric layer 123A or 123B, and a third dielectric layer 125A or 125B. The first dielectric layer 121 may extend between the first insulating partition wall 133P and the second insulating partition wall 149. Each of the second dielectric layer and the third dielectric layer may be separated into a first pattern 123A or 125A between the first conductive pattern 113A and the first data storage pattern 127A and a second pattern 123B or 125B between the second conductive pattern 113B and the second data storage pattern 127B. The tunnel insulating layer 129 may extend between the first pattern 123A or 125A and the second pattern 123B or 125B of each of the second dielectric layer and the third dielectric layer. However, the embodiments of the present disclosure may not be limited thereto. According to another embodiment, the second insulating partition wall 149 may extend to contact the first insulating partition wall 133P so that the first dielectric layer 121 of the blocking insulating layer 120 may be separated into a first pattern and a second pattern.

[0147] The first channel pattern 131A and the second channel pattern 131B may be Fig. 9A 151A and 151B, respectively, as shown, or may be connected to the first bit line 151A and the second bit line 151B as shown. Fig. 9B As shown, they are connected to the same bit line 151.

[0148] Fig.16 , Fig.17 , Fig.18A and Fig.18B is a diagram showing a semiconductor memory device according to an embodiment of the present disclosure.

[0149] Fig.16 is a perspective view showing a part of a semiconductor memory device. Fig.17 yes Fig.16 A plan view of a semiconductor memory device shown. Fig.18A It is along Fig.17 A cross-sectional view of a semiconductor memory device taken along line If-If'. Fig.18B It is shown along Fig.17 A cross-sectional view of a semiconductor memory device taken along line IIf-IIf'.

[0150] Reference Fig.16 , Fig.17 , Fig.18A and Fig.18B , the semiconductor memory device may include a gate stack structure 110, a vertical structure VS, an insulating partition wall 133P, and a bit line array structure BAS.

[0151] The gate stack structure 110 may be Figure 4 The gate stack structure 110 may include a first sub-stack 110A and a second sub-stack 110B separated from each other. The first sub-stack 110A and the second sub-stack 110B may be separated from each other by a vertical structure VS and an insulating partition wall 133P.

[0152] The vertical structures VS and the insulating partition walls 133P may be alternately arranged with each other along the first direction DR1 on a center line L extending in the first direction DR1 on a plane. The first sub-stack 110A may extend from the vertical structures VS and the insulating partition walls 133P in the second direction DR2. The second sub-stack 110B may extend from the vertical structures VS and the insulating partition walls 133P in the third direction DR3.

[0153] As mentioned above Fig. 9A and Fig. 9B As described, the first sub-stack 110A may include a plurality of first interlayer insulating patterns 111A and a plurality of first conductive patterns 113A arranged alternately with each other in the fourth direction DR4, and the second sub-stack 110B may include a plurality of second interlayer insulating patterns 111B and a plurality of second conductive patterns 113B arranged alternately with each other in the fourth direction DR4.

[0154] The vertical structure VS may include an insulating pillar 135, a channel layer 131, and a tunnel insulating layer 129. The insulating pillar 135, the channel layer 131, the tunnel insulating layer 129, and the insulating partition wall 133P of the vertical structure VS may extend in the fourth direction DR4 to pass between the plurality of first interlayer insulating patterns 111A and the plurality of second interlayer insulating patterns 111B and between the plurality of first conductive patterns 113A and the plurality of second conductive patterns 113B.

[0155] The insulating pillar 135 may protrude toward the second direction DR2 and the third direction DR3 with respect to the center line L. In a plan view, the insulating pillar 135 may have an elliptical shape, and the center line L may overlap a major axis of the insulating pillar 135 .

[0156] The channel layer 131 may extend continuously along the outer wall of the insulating pillar 135 to surround the outer wall of the insulating pillar 135. According to an embodiment, the channel layer 131 may have a substantially tubular shape. The insulating pillar 135 may be arranged in a central area of ​​the channel layer 131 having a substantially tubular shape. The channel layer 131 having a substantially tubular shape may extend between the insulating partition wall 133P and the insulating pillar 135. The channel layer 131 may include the same material as the first channel pattern 131A and the second channel pattern 131B, such as Figure 4 shown.

[0157] The tunnel insulating layer 129 may continuously extend along the outer wall of the channel layer 131 to surround the outer wall of the channel layer 131. In an embodiment, the insulating pillar 135 may be located in a central area of ​​the tunnel insulating layer 129 including a substantially tubular shape. The tunnel insulating layer 129 having a substantially tubular shape may extend between the insulating partition wall 133P and the channel layer 131. The tunnel insulating layer 129 may include the insulating pillar 135 described above. FIG. 5A to FIG. 5C Same materials as described.

[0158] The first conductive pattern 113A of the first sub-stack 110A and the second conductive pattern 113B of the second sub-stack 110B may extend in the second direction DR2 and the third direction DR3 opposite to each other with respect to the center line L. The first interlayer insulating pattern 111A of the first sub-stack 110A and the second interlayer insulating pattern 111B of the second sub-stack 110B may extend in the second direction DR2 and the third direction DR3 opposite to each other with respect to the center line L.

[0159] The first interlayer insulating pattern 111A of the first sub-stack 110A may protrude beyond the first conductive pattern 113A toward the vertical structure VS. As a result, a first transverse groove 110P1 may be defined in the first sub-stack 110A. The second interlayer insulating pattern 111B of the second sub-stack 110B may protrude beyond the second conductive pattern 113B toward the vertical structure VS. As a result, a second transverse groove 110P2 may be defined in the second sub-stack 110B. The first transverse groove 110P1 and the second transverse groove 110P2 may have the same shape as described above with reference to FIG. FIG. 5A to FIG. 5C Same structure as described.

[0160] The first conductive pattern 113A may include a side portion bent along the first transverse groove 110P1. The second conductive pattern 113B may include a side portion bent along the second transverse groove 110P2. The first data storage pattern 127A may be disposed in the first transverse groove 110P1. The second data storage pattern 127B may be disposed in the second transverse groove 110P2.

[0161] Each of the first data storage pattern 127A and the second data storage pattern 127B may have a shape corresponding to the shape of the lateral groove to which it corresponds. According to an embodiment, the distance between the first channel pattern 131A and the first conductive pattern 113A and the distance between the second channel pattern 131B and the second conductive pattern 113B may decrease toward the center line L. For example, in an embodiment, the variable distance between the first channel pattern 131A and the first conductive pattern 113A decreases as the distances of the first channel pattern 131A and the first conductive pattern 113A from the center line L decrease. For example, in an embodiment, the variable distance between the second channel pattern 131B and the second conductive pattern 113B decreases as the distances of the second channel pattern 131B and the second conductive pattern 113B from the center line L decrease. In response, the width of each of the first lateral groove 110P1 and the second lateral groove 110P2 in the plane may decrease toward the center line L. Therefore, the width of each of the first data storage pattern 127A and the second data storage pattern 127B may decrease toward the center line L. The first data storage pattern 127A and the second data storage pattern 127B may include the above-mentioned FIG. 5A to FIG. 5C Materials as described.

[0162] The first blocking insulating pattern 120A may extend along the inner wall of the first conductive pattern 113A. The second blocking insulating pattern 120B may extend along the inner wall of the second conductive pattern 113B. The inner wall of each of the first conductive pattern 113A and the second conductive pattern 113B may face the channel layer 131. Each of the first blocking insulating pattern 120A and the second blocking insulating pattern 120B may include a first dielectric layer 121A or 121B, a second dielectric layer 123A or 123B, and a third dielectric layer 125A or 125B. Each of the first dielectric layer, the second dielectric layer, and the third dielectric layer may be separated into a first pattern 121A, 123A or 125A and a second pattern 121B, 123B, or 125B by a tunnel insulating layer 129. The first dielectric layer 121A or 121B, the second dielectric layer 123A or 123B, and the third dielectric layer 125A or 125B may include the above-referenced FIG. 5A to FIG. 5C Materials as described.

[0163] The bit line array structure BAS may include a plurality of bit lines 151. Each bit line 151 may be connected to a channel layer 131 corresponding thereto.

[0164] A first portion of the channel layer 131 facing the first sub-stack 110A can be used as a channel region of a first memory cell string CS1”. A second portion of the channel layer 131 facing the second sub-stack 110B can be used as a channel region of a second memory cell string CS2”. The multiple first conductive patterns 113A that control the first memory cell string CS1” can be separated from the multiple second conductive patterns 113B that control the second memory cell string CS2” by the connection between the vertical structure VS and the insulating partition wall 133P. As a result, the first memory cell string CS1” and the second memory cell string CS2” connected to the same channel layer 131 can be respectively controlled by the first conductive patterns 113A and the second conductive patterns 113B that are separated from each other.

[0165] According to the above reference Figures 4 to 18B The data storage pattern 123A or 123B of the described embodiment may be disposed in the transverse groove 110P1 or 110P2. The transverse groove 110P1 or 110P2 may be separated in a fourth direction DR4 corresponding to a vertical direction. From a plan view, the width of the transverse groove 110P1 or 110P2 may decrease toward the end.

[0166] Hereinafter, various embodiments of a method of manufacturing a semiconductor memory device including the above-mentioned lateral groove 110P1 or 110P2 will be described below.

[0167] Fig.19 , Fig. 20A , Fig. 20B , Fig.21 , Fig.22A , Fig. 22B , Fig.23 , Fig.24A , Fig. 24B , Fig.25 , Fig.26A , Fig.26B , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32A , Fig.32B , Fig.33 , Fig.34A , Fig.34B , Fig.35A and Fig.35B 2 is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0168] Fig.19 , Fig.21 , Fig.23 , Fig.25 , Fig. 27 , Fig.29 , Fig.31 and Fig.33 is a plan view showing a process for manufacturing a semiconductor memory device. Fig. 20A , Fig.22A , Fig.24A , Fig.26A , Fig.28 , Fig.30 , Fig.32A , Fig.34A and Fig.35A They are cross-sectional views taken along line A′-A1′ of the corresponding plan view, respectively. Fig. 20B , Fig. 22B , Fig. 24B , Fig.26B , Fig.32B , Fig.34B and Fig.35B They are cross-sectional views taken along line B'-B1' of the corresponding plan view, respectively.

[0169] Fig.19 , Fig. 20A and Fig. 20B is a diagram illustrating a process of forming a preliminary stack structure 210 through which a plurality of holes 215 are formed.

[0170] Reference Fig.19 , Fig. 20A and Fig. 20B , a preliminary stacked structure 210 may be formed on a lower structure (not shown). According to an embodiment, the lower structure may be a sacrificial substrate including a silicon wafer. The sacrificial substrate may be replaced by a doped semiconductor structure during a subsequent process. According to another embodiment, the lower structure may include a structure having a peripheral circuit and a doped semiconductor structure.

[0171] The preliminary stacked structure 210 may be formed on the lower structure according to the various embodiments described above. The preliminary stacked structure 210 may be penetrated by a plurality of holes 215. From a plan view, a cross section of each hole 215 may include a major axis 215_L in the first direction DR1 and a minor axis 215_S in the third direction DR3. According to an embodiment, the cross section of the hole 215 may have a substantially elliptical shape.

[0172] The preliminary stacked structure 210 may include a plurality of first material layers 211 and a plurality of second material layers 213 alternately stacked with each other in the fourth direction DR4. The plurality of second material layers 213 may have a material having an etching selectivity with respect to the plurality of first material layers 211. According to an embodiment, the plurality of first material layers 211 may include an insulating material such as a silicon oxide layer, and the plurality of second material layers 213 may include a sacrificial insulating material such as a silicon nitride layer.

[0173] Forming the hole 215 may include forming a mask pattern (not shown) defining a cross-sectional surface of the hole 215 on the preliminary stack structure 210 and etching the plurality of first material layers 211 and the plurality of second material layers 213 by using the mask pattern as an etching barrier. After forming the hole 215, the mask pattern may be removed. The hole 215 may extend in the fourth direction DR4 to pass through the plurality of first material layers 211 and the plurality of second material layers 213.

[0174] The hole 215 may include first to fourth inner walls 215S1 to 215S4. The first inner wall 215S1 and the second inner wall 215S2 of the hole 215 may be aligned on the long axis 215_L of the hole 215 and face each other in the first direction DR1. The third inner wall 215S3 and the fourth inner wall 215S4 of the hole 215 may be aligned on the short axis 215_S of the hole 215 and may face each other in the second direction DR2 or the third direction DR3.

[0175] Subsequently, a first etch barrier pattern 501A and a second etch barrier pattern 501B may be formed to partially block a side portion of each of the plurality of first material layers 211 and the plurality of second material layers 213 exposed through the hole 215. The first etch barrier pattern 501A and the second etch barrier pattern 501B may be formed using an etch barrier layer including substantially the same material as the plurality of second material layers 213.

[0176] The process of forming the first etching barrier pattern 501A and the second etching barrier pattern 501B may include a process of forming an etching barrier layer along the hole 215 and a process of removing a portion of the etching barrier layer by an etching process to separate the etching barrier layer into the first etching barrier pattern 501A and the second etching barrier pattern 501B. Although not shown, the etching barrier layer may extend continuously along the first inner wall 215S1 to the fourth inner wall 215S4 of the hole 215 so that the central area of ​​the etching barrier layer may have an open tubular shape. An elliptical opening smaller than the elliptical shape defined by the hole 215 may be defined by the inner wall of the etching barrier layer having a tubular shape. When a portion of the etching barrier layer is removed, isotropic etching may be performed on the etching barrier layer from the elliptical opening defined by the inner wall of the etching barrier layer toward the first inner wall 215S1 to the fourth inner wall 215S4 of the hole 215. The isotropic etching may be performed by at least one of wet etching and dry etching. The area of ​​the inner wall of the etching barrier layer exposed by the etching material may vary according to the respective areas of the shape of the elliptical opening defined by the inner wall of the etching barrier layer. As a result, the closer to the short axis of the elliptical opening, the faster the etching operation may be performed from the inner wall of the etching barrier layer toward the first inner wall 215S1 to the fourth inner wall 215S4.

[0177] The third inner wall 215S3 and the fourth inner wall 215S4 of the hole 215 may be exposed using the above-mentioned isotropic etching. A portion of the etching barrier layer may remain as the first etching barrier pattern 501A and the second etching barrier pattern 501B to block the first inner wall 215S1 and the second inner wall 215S2 of the hole 215. The width of each of the remaining first etching barrier pattern 501A and the second etching barrier pattern 501B may decrease toward the short axis 215_S of the hole 215.

[0178] Fig.21 , Fig.22A and Fig. 22B 21 is a diagram showing a process of forming the first lateral groove 217A and the second lateral groove 217B.

[0179] Reference Fig.21 , Fig.22A and Fig. 22B , can be used for Fig.19 Isotropic etching is performed on a portion of each of the plurality of second material layers 213 exposed by the third inner wall 215S3 and the fourth inner wall 215S4 of the hole 215. As a result, a first transverse groove 217A and a second transverse groove 217B may be formed in the side of the preliminary stack structure 210. The first transverse groove 217A and the second transverse groove 217B may be adjacent to each other in the second direction DR2 or the third direction DR3. Each of the first transverse groove 217A and the second transverse groove 217B is disposed between two first material layers adjacent to each other in the fourth direction DR4 among the plurality of first material layers 211.

[0180] The isotropic etching may be performed by at least one of wet etching and dry etching. The etching material used for the isotropic etching may be as follows: Fig.19 As shown, the etching is introduced along the route R1 from the central area 215C of the hole 215 opened by the first etching barrier pattern 501A and the second etching barrier pattern 501B. When isotropic etching is performed, as shown in FIG. Fig.19 The first and second etch barrier patterns 501A and 501B shown including substantially the same material as the plurality of second material layers 213 may be removed. As a result, the first and second inner walls 215S1 and 215S2 of the hole 215 may be exposed.

[0181] like Fig.19 Each of the plurality of second material layers 213 shown has a portion adjacent to the first inner wall 215S1 and the second inner wall 215S2 of the hole 215 protected by the first etching barrier pattern 501A and the second etching barrier pattern 501B. Therefore, even when the first etching barrier pattern 501A and the second etching barrier pattern 501B are removed by isotropic etching for forming the first etching barrier pattern 501A and the second etching barrier pattern 501B, Fig.19 When a portion of each of the first inner wall 215S1 and the second inner wall 215S2 of the hole 215 is exposed and etched, the etching amount may also be much smaller than the etching amount in the second direction DR2 and the third direction DR3 .

[0182] Through the above process, the width can be limited to Fig.19 The first inner wall 215S1 and the second inner wall 215S2 reduce the first transverse groove 217A and the second transverse groove 217B.

[0183] Fig.23 , Fig.24A and Fig. 24B 2 is a diagram illustrating a process of forming the first dielectric layer 221 and the second dielectric layer 223 .

[0184] Reference Fig.23 , Fig.24A and Fig. 24B , a side portion of each of the plurality of second material layers 213 exposed through the hole 215 , the first transverse groove 217A, and the second transverse groove 217B may be formed. As a result, a first dielectric layer 221 may be formed in each of the plurality of second material layers 213 toward the hole 215 .

[0185] Subsequently, a second dielectric layer 223 may be formed on the surface of the first dielectric layer 221. The second dielectric layer 223 may extend along the surface of each of the first and second transverse grooves 217A and 217B and the hole 215. The second dielectric layer 223 may include a nitride layer such as a silicon nitride layer.

[0186] Subsequently, a first mask pattern 511A and a second mask pattern 511B may be formed at a central region of the first lateral groove 217A and a central region of the second lateral groove 217B opened by the second dielectric layer 223, respectively. The first mask pattern 511A and the second mask pattern 511B may include a material having an etching selectivity with respect to the first dielectric layer 221 and the second dielectric layer 223. According to an embodiment, each of the first mask pattern 511A and the second mask pattern 511B may include a silicon layer. The first mask pattern 511A and the second mask pattern 511B may be separated from each other with the hole 215 interposed therebetween. A portion of the second dielectric layer 223 may be exposed between the first mask pattern 511A and the second mask pattern 511B.

[0187] Fig.25 , Fig.26A and Fig.26B 223A1 and 223B1 are diagrams illustrating a process of separating the second dielectric layer into the first preliminary pattern 223A1 and the second preliminary pattern 223B1.

[0188] Reference Fig.25 , Fig.26A and Fig.26B , a portion of the exposed second dielectric layer may be removed by an etching process using the first mask pattern 511A and the second mask pattern 511B as etching barriers. As a result, the second dielectric layer may be separated into the first preliminary pattern 223A1 and the second preliminary pattern 223B1. The first dielectric layer 221 may be exposed between the first preliminary pattern 223A1 and the second preliminary pattern 223B1.

[0189] Subsequently, inner walls of the first and second preliminary patterns 223A1 and 223B1 may be exposed by selectively removing the first and second mask patterns 511A and 511B.

[0190] Fig. 27 and Fig.28 2 is a diagram illustrating a process of forming a first pattern 225A and a second pattern 225B of a third dielectric layer.

[0191] Reference Fig. 27 and Fig.28 ,exist Fig.25 , Fig.26A and Fig.26B After the inner walls of the first preliminary pattern 223A1 and the second preliminary pattern 223B1 are exposed, portions thereof may be oxidized. Unoxidized regions of the first preliminary pattern 223A1 and the second preliminary pattern 223B1 may remain as the first pattern 223A2 and the second pattern 223B2 of the second dielectric layer. Oxidized regions of the first preliminary pattern 223A1 and the second preliminary pattern 223B1 may form the first pattern 225A and the second pattern 225B of the third dielectric layer. The first pattern 225A and the second pattern 225B of the third dielectric layer may include an oxide layer such as a silicon oxynitride layer.

[0192] The first dielectric layer 221, the first and second patterns 223A2 and 223B2 of the second dielectric layer, and the first and second patterns 225A and 225B of the third dielectric layer may form a blocking insulating layer 220. Through the above process, the blocking insulating layer 220 may be formed on a layer where each of the plurality of second material layers 213 is arranged, and may be excluded from a layer where each of the plurality of first material layers 211 is formed. An inner wall of the blocking insulating layer 220 may be exposed in the first and second transverse grooves 217A and 217B.

[0193] Fig.29 and Fig.30 2 is a diagram illustrating a process of forming a first data storage pattern 227A and a second data storage pattern 227B.

[0194] Reference Fig.29 and Fig.30, a first data storage pattern 227A and a second data storage pattern 227B may be formed on the exposed inner wall of the blocking insulating layer 220. The process of forming the first data storage pattern 227A and the second data storage pattern 227B may include a process of forming a data storage layer to fill the first transverse groove 217A and the second transverse groove 217B and a process of removing a portion of the data storage layer so that the data storage layer can be separated into the first data storage pattern 227A and the second data storage pattern 227B. The first data storage pattern 227A may be disposed in the first transverse groove 217A. The second data storage pattern 227B may be disposed in the second transverse groove 217B.

[0195] According to an embodiment, the data storage layer may include a charge trapping insulating layer, a floating gate layer, and an insulating layer including conductive nanodots. The charge trapping insulating layer may include a silicon nitride layer. The floating gate layer may include a silicon layer. However, the present disclosure is not limited thereto. According to another embodiment, the data storage layer may include a phase change material layer, a ferroelectric layer, and the like.

[0196] Fig.31 , Fig.32A and Fig.32B is a diagram showing a process of forming a preliminary vertical structure.

[0197] Reference Fig.31 , Fig.32A and Fig.32B A tunnel insulating layer 229 may be formed along an inner wall of each of the first and second data storage patterns 227A and 227B. The tunnel insulating layer 229 may extend along a sidewall of the hole 215 between the first and second data storage patterns 227A and 227B.

[0198] The tunnel insulating layer 229 may extend to cover the first dielectric layer 221 of the blocking insulating layer 220 opened between the first data storage pattern 227A and the second data storage pattern 227B, and may have a substantially tubular shape. The tunnel insulating layer 229 may extend to be interposed between the first pattern 225A and the second pattern 225B of the third dielectric layer and between the first pattern 223A2 and the second pattern 223B2 of the second dielectric layer.

[0199] The tunnel insulating layer 229 may include an oxide layer such as a silicon oxide layer.

[0200] Subsequently, a channel layer 231 may be formed along an inner wall of the tunnel insulating layer 229. The channel layer 231 may include silicon (Si), germanium (Ge), or a mixture thereof.

[0201] The channel layer 231 may have a substantially tubular shape such that a central region of the hole 215 may be open.

[0202] Subsequently, a central region of the hole 215 opened by the channel layer 231 may be filled with an insulating material to form an insulating column 235. As a result, a preliminary vertical structure including the tunnel insulating layer 229, the channel layer 231, and the insulating column 235 may be formed. Each of the tunnel insulating layer 229, the channel layer 231, and the insulating column 235 may extend along the hole 215 in the fourth direction DR4.

[0203] Fig.33 , Fig.34A and Fig.34B 2 is a diagram showing a process of forming the semiconductor oxide layer 241 .

[0204] Reference Fig.33 , Fig.34A and Fig.34B , can form Figure 4 The slit SI shown. Figure 4 The slit SI shown may extend in the fourth direction DR4 to pass through Fig.32A and Fig.32B The plurality of first material layers 211 and the plurality of second material layers 213 are shown. The slit SI can be removed Fig.32A and Fig.32B As shown, the second material layer 213. As a result, a plurality of horizontal spaces HS may be opened between the plurality of first material layers 211.

[0205] Subsequently, HS can be selectively oxidized through multiple horizontal spaces such as Fig.31 , Fig.32A and Fig.32B A portion of the channel layer 231 shown. Selective oxidation may be performed by a wet etching process. However, the first pattern 223A2 and the second pattern 223B2 of the second dielectric layer including a nitride layer such as a silicon nitride layer are hardly oxidized and may be used as a barrier to the wet oxidation process. As a result, another portion of the channel layer 231 protected by the first pattern 223A2 and the second pattern 223B2 of the second dielectric layer may be retained as the first channel pattern 231A and the second channel pattern 231B. The oxidized region of the channel layer may be retained as the semiconductor oxide layer 241. When a portion of the channel layer 231 is selectively oxidized by a wet oxidation process performed via a route R2 as indicated by a dotted line, a semiconductor oxide layer 241 may be formed. The first channel pattern 231A and the second channel pattern 231B may be separated from each other by the semiconductor oxide layer 241.

[0206] Through the above-described processes, a vertical structure including the tunnel insulating layer 229 , the first channel pattern 231A, the second channel pattern 231B, the insulating pillar 235 , and the semiconductor oxide layer 241 may be defined.

[0207] Fig.35A and Fig.35Bis a diagram illustrating a process of forming a plurality of third material layers 313 .

[0208] Reference Fig.35A and Fig.35B , a plurality of third material layers 313 may be formed in the plurality of horizontal spaces HS, respectively. Each of the third material layers 313 may include at least one of a doped semiconductor layer, a metal layer, and a conductive metal nitride layer.

[0209] Fig.36A and Fig.36B 2 is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0210] Fig.37A and Fig.37B 2 is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0211] the following, Figures 19 to 35B Descriptions of the same processes described in will be simplified or omitted.

[0212] In execution Fig.36A or Fig.37A Before the process, you can perform the above reference Figures 19 to 32B Therefore, if Fig.31 , Fig.32A and Fig.32B As shown, a preliminary stacked structure 210 may be provided, which is penetrated by a hole 315, includes a first transverse groove 217A and a second transverse groove 217B, and includes a plurality of first material layers 211 and a plurality of second material layers 213 alternately stacked on each other. A preliminary vertical structure including a tunnel insulating layer 229, a channel layer 231, and an insulating column 235 may be formed in the hole 215. A blocking insulating layer 220 may be formed along the inner wall of the first transverse groove 217A and the second transverse groove 217B. A first data storage pattern 227A may be disposed in the first transverse groove 217A, and a second data storage pattern 227B may be disposed in the second transverse groove 217B. The blocking insulating layer 220 may include a first dielectric layer 221, first and second patterns 223A2 and 223B2 of a second dielectric layer, and first and second patterns 225A and 225B of a third dielectric layer.

[0213] Afterwards, if Fig.36A As shown, a trench 351 may be formed. After forming a mask pattern (not shown) defining the trench 351, the mask pattern may be used as an etching barrier to etch the trench 351 through an etching process. Fig.31 , Fig.32A and Fig.32B The insulating pillar 235 and the channel layer 231 are formed to form a trench 351. The trench 351 can be connected to the insulating pillar 235 and the channel layer 231 as shown. Fig.31 , Fig.32A and Fig.32B The centers of the insulating pillars 235 shown overlap and may extend in the first direction DR1 to pass through the insulating pillars 235. Fig.31 , Fig.32A and Fig.32B As a result, Fig.31 , Fig.32A and Fig.32B The insulating pillar 235 shown may be separated into a first pillar pattern 235A and a second pillar pattern 235B by a groove 351. Fig.31 , Fig.32A and Fig.32B The illustrated channel layer 231 may be separated into a first channel pattern 231A and a second channel pattern 231B by the trench 351 .

[0214] The length of the trench 351 in the first direction DR1 can be controlled so that Fig.31 , Fig.32A and Fig.32B The channel layer 231 shown may be separated into a first channel pattern 231A and a second channel pattern 231B. According to an embodiment, the length of the groove 351 may be controlled to expose Fig.31 , Fig.32A and Fig.32B The inner wall of the tunnel insulating layer 229 is shown. According to another embodiment, the length of the trench 351 can be controlled so that Fig.31 , Fig.32A and Fig.32B The illustrated tunnel insulating layer 229 may be separated into a first tunnel insulating pattern 229A and a second tunnel insulating pattern 229B. According to another embodiment, the length of the trench 351 may be controlled so that the first dielectric layer 221 of the blocking insulating layer 220 may be separated into a first pattern and a second pattern.

[0215] Reference Fig.36B , can be filled with insulating materials Fig.36A The trench 351 is shown to form the insulating partition wall 243. As a result, a vertical structure 230' including the insulating partition wall 243, the first pillar pattern 235A, the second pillar pattern 235B, the first channel pattern 231A, the second channel pattern 231B, the first tunnel insulation pattern 229A and the second tunnel insulation pattern 229B may be formed.

[0216] After forming the vertical structure 230', a Figure 4 The slit SI described. Fig.36B The second material layer 213 shown may include the Figures 19 to 20B The second material layer 213 may be replaced by the sacrificial insulating material described above. Fig.35A and Fig.35B A third material layer is described.

[0217] Fig.37A and Fig.37B FIG. 1 is a diagram showing another embodiment of a process of forming a trench and a process of forming an insulating partition wall.

[0218] Reference Fig.37A The trench 361 may extend in the first direction DR1 to pass through the first dielectric layer 321 of the blocking insulating layer 220 and the preliminary stacked structure 210 and Fig.31 , Fig.32A and Fig.32B As shown, the insulating pillar 235 and the channel layer 231 are formed. As a result, the first pillar pattern 235A, the second pillar pattern 235B, the first channel pattern 231A, the second channel pattern 231B, the first tunnel insulating pattern 229A and the second tunnel insulating pattern 229B may be defined by the trench 361. In addition, Fig.31 , Fig.32A and Fig.32B The preliminary stacked structure 210 shown may also be separated into a first stacked pattern 210A and a second stacked pattern 210B. In addition, the first dielectric layer may be separated into a first pattern 221A and a second pattern 221B. As a result, the blocking insulating layer may be separated into a first blocking insulating pattern 220A and a second blocking insulating pattern 220B. The first blocking insulating pattern 220A may include first patterns 221A, 223A2, and 225A of the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second blocking insulating pattern 220B may include second patterns 221B, 223B2, and 225B of the first dielectric layer, the second dielectric layer, and the third dielectric layer.

[0219] The first pillar pattern 235A, the first channel pattern 231A, and the first tunnel insulating pattern 229A may form a first vertical structure 230A. The second pillar pattern 235B, the second channel pattern 231B, and the second tunnel insulating pattern 229B may form a second vertical structure 230B.

[0220] Hereinafter, the plurality of second material layers of the first stack pattern 210A may be referred to as the first group of second material layers 213A, and the plurality of second material layers of the second stack pattern 210B may be referred to as the second group of second material layers 213B. The second material layers 213A in the first group may be separated from the second material layers 213B in the second group by the grooves 361.

[0221] Reference Fig.37B , can be filled with insulating materials Fig.37A As a result, the groove 361 can be Fig.37A The insulating partition walls 245 are formed in the trenches 361 as shown.

[0222] After forming the insulating partition wall 245, a second insulating partition wall 245 may be formed through each of the first stack pattern 210A and the second stack pattern 210B. Figure 4 The slit SI. Fig.37A and Fig.37B The first group of second material layers 213A and the second group of second material layers 213B shown in FIG. Figures 19 to 20B The second material layer described above includes a sacrificial insulating material in the same manner. Each of the first set of second material layers 213A and the second set of second material layers 213B may be replaced with a Fig.35A and Fig.35B A third material layer is described.

[0223] Fig.38 , Fig.39A , Fig.39B , Fig.40 , Fig.41A , Fig.41B and Fig.42 2 is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0224] Fig.38 , Fig.40 and Fig.42 It is a plan view showing the process. Fig.39A and Fig.41A 1 is a cross-sectional view taken along line A2 - A2 ′ of a plan view corresponding thereto for illustrating a process. Fig.39B and Fig.41B 2 is a cross-sectional view taken along the line B2-B2' of the corresponding plan view for illustrating the process. Figures 19 to 35B Descriptions of the same processes described in will be simplified or omitted.

[0225] Fig.38 , Fig.39A and Fig.39B 2 is a diagram illustrating a process of forming a preliminary stack structure 310 penetrated by a plurality of holes 215 and a process of forming a first etch barrier pattern 551A and a second etch barrier pattern 551B.

[0226] Reference Fig.38 , Fig.39A and Fig.39B , which can be found in the above Figures 19 to 20B The preliminary stacking structure 310 is formed on the described lower structure (not shown). The preliminary stacking structure 310 may be penetrated by a plurality of holes 215. Figures 19 to 20B As described, the cross-section of each hole 215 may include a major axis 215_L in the first direction DR1 and a minor axis 215_S in the third direction DR3 .

[0227] The preliminary stacked structure 310 may include a plurality of first material layers 211 and a plurality of second material layers 213' alternately stacked with each other in the fourth direction DR4. The plurality of first material layers 211 may include an insulating material such as a silicon oxide layer. The plurality of second material layers 213' may include the same Fig.35A and Fig.35B The third material layer is the same conductive material as described.

[0228] By using reference Figures 19 to 20B The described process forms holes 215 in preliminary stack structure 310 .

[0229] Subsequently, a first etching barrier pattern 551A and a second etching barrier pattern 551B may be formed to partially block the side of each of the plurality of first material layers 211 and the plurality of second material layers 213' exposed through the hole 215. The first etching barrier pattern 551A and the second etching barrier pattern 551B may include substantially the same material as the plurality of second material layers 213'. The first etching barrier pattern 551A and the second etching barrier pattern 551B may be separated from each other in the first direction DR1 to open a central area 215C of the hole 215. The first etching barrier pattern 551A and the second etching barrier pattern 551B may be formed to expose the inner wall of the hole 215 in the second direction DR2 and the third direction DR3. The first etching barrier pattern 551A and the second etching barrier pattern 551B may be formed using a reference Figures 19 to 20B The process described above can be used to form Figures 19 to 20B Same structure as described.

[0230] Fig.40 , Fig.41A and Fig.41B 217A and 217B, a process of forming a blocking insulating layer 220 ′, a process of forming a first data storage pattern 227A and a second data storage pattern 227B, and a process performed in the hole 215 .

[0231] Reference Fig.40 , Fig.41A and Fig.41B , can be compared with the reference Fig.21 , 22A and Fig. 22B The described process forms the first transverse groove 217A and the second transverse groove 217B on the side of the preliminary stack structure 310 while removing Fig.38 and Fig.39B A first etch barrier pattern 551A and a second etch barrier pattern 551B are shown.

[0232] Subsequently, the side of each of the plurality of second material layers 213' exposed by the hole 215 and the first and second transverse grooves 217A and 217B may be oxidized to form a first dielectric layer 221'. Subsequently, the following steps may be performed as described with reference to Figures 23 to 24B The process for forming the second dielectric layer is described above with reference to Figures 25 to 26B The process of separating the second dielectric layer into the first preliminary pattern and the second preliminary pattern as described above with reference to Fig. 27 and Fig.28 As a result of the described process of oxidizing portions of the first preliminary pattern and portions of the second preliminary pattern, the first dielectric layer 221', the first and second patterns 223A2 and 223B2 of the second dielectric layer, and the first and second patterns 225A and 225B of the third dielectric layer may form a blocking insulating layer 220'.

[0233] Then, refer to the above Fig.29 and Fig.30 The first data storage pattern 227A and the second data storage pattern 227B are formed in the same manner as described above. Figures 31 to 32B In the same manner as described, a tunnel insulating layer 229 , a channel layer 231 , and an insulating pillar 235 may be formed in the hole 215 .

[0234] Fig.42 is a plan view illustrating a process of separating the channel layer 231 into the first channel pattern 231A and the second channel pattern 231B.

[0235] Reference Fig.42 , can be obtained by using the reference above Fig.36A The process described passes through Fig.40 The channel layer 231 and the insulating pillar 235 shown form a groove, and can be used by using the above reference Fig.36B The described process forms insulating partition walls 243 in the trenches. As a result, a vertical structure 230' including insulating partition walls 243, first and second pillar patterns 235A and 235B, first and second channel patterns 231A and 231B, first and second tunnel insulation patterns 229A and 229B may be formed.

[0236] Subsequently, the Figure 4 The described slits S1 penetrate the preliminary stack structure 310. As a result, the preliminary stack structure 310 may be divided as a unit of a gate stack structure. The second material layer 213' of the preliminary stack structure 310 may be used as a gate electrode for controlling the first channel pattern 231A and the second channel pattern 231B.

[0237] Fig.43is a plan view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0238] Fig.43 1 is a plan view showing another embodiment of a process for forming a trench and a process for forming an insulating partition wall. Fig.43 Before the process shown, refer to Figures 38 to 41B Process described.

[0239] Reference Fig.43 , can be obtained by using the reference above Fig.37A The process described passes through Fig.40 The channel layer 231 and the insulating pillar 235 shown form a groove, and can be used by using the above reference Fig.37B The described process forms an insulating partition wall 245 in the trench. As a result, the first pillar pattern 235A, the second pillar pattern 235B, the first channel pattern 231A, the second channel pattern 231B, the first tunnel insulation pattern 229A and the second tunnel insulation pattern 229B may be defined by the insulating partition wall 245. In addition, Figures 40 to 41B The preliminary stack structure 310 shown may be separated into a first stack pattern 310A and a second stack pattern 310B. In addition, the first dielectric layer may be separated into a first pattern 221A' and a second pattern 221B'.

[0240] As described above, the blocking insulating layer may be separated into a first blocking insulating pattern 220A' and a second blocking insulating pattern 220B'. The first blocking insulating pattern 220A' may include first patterns 221A', 223A2, and 225A of the first dielectric layer, the second dielectric layer, and the third dielectric layer. The second blocking insulating pattern 220B' may include second patterns 221B', 223B2, and 225B of the first dielectric layer, the second dielectric layer, and the third dielectric layer. In addition, the first pillar pattern 235A, the first channel pattern 231A, and the first tunnel insulating pattern 229A may form a first vertical structure 230A. The second pillar pattern 235B, the second channel pattern 231B, and the second tunnel insulating pattern 229B may form a second vertical structure 230B. In addition, the plurality of second material layers of the first stack pattern 310A may remain as a plurality of first conductive patterns 213A', and the plurality of second material layers of the second stack pattern 310B may remain as a plurality of second conductive patterns 213B'.

[0241] Fig.44 , Fig.45A , Fig.45B , Fig.46 , Fig.47A , Fig.47B , Fig.48 , Fig.49A and Fig.49B2 is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0242] Fig.44 , Fig.46 and Fig.48 It is a plan view showing the process. Fig.45A , Fig.47A and Fig.49A 1 is a cross-sectional view taken along line A3 - A3 ′ of a plan view corresponding thereto for illustrating a process. Fig.45B , Fig.47B and Fig.49B is a cross-sectional view taken along the line B3-B3' of the corresponding plan view for illustrating the process. Figures 19 to 35B Descriptions of the same processes described in will be simplified or omitted.

[0243] Fig.44 , Fig.45A and Fig.45B 2 is a diagram illustrating a process of forming the first insulating partition wall 233 .

[0244] Reference Fig.44 , Fig.45A and Fig.45B , which can be found by referring to the above Fig.44 , Fig.45A and Fig.45B A plurality of first material layers and a plurality of second material layers are alternately stacked on the lower structure (not shown) to form a preliminary stacked structure. The plurality of first material layers may include insulating materials such as silicon oxide layers. The plurality of second material layers may include the same as those described above. Fig.35A and Fig.35B The third material layer is the same conductive material as described.

[0245] Subsequently, a first insulating partition wall 233 may be formed through the preliminary stack structure. The first insulating partition wall 233 may extend in the first direction DR1 and separate the preliminary stack structure into a first stack pattern 310A and a second stack pattern 310B. The plurality of first material layers of the first stack pattern 310A may remain as a plurality of interlayer insulating patterns 211A. The plurality of second material layers may remain as a plurality of first conductive patterns 213A'. The plurality of first material layers of the second stack pattern 310B may remain as a plurality of interlayer insulating patterns 211B. The plurality of second material layers may remain as a plurality of second conductive patterns 213B'.

[0246] Fig.46 , Fig.47A and Fig.47B 2 is a diagram illustrating a process of forming a plurality of holes 215 and a process of forming a first etch barrier pattern 551A and a second etch barrier pattern 551B.

[0247] Reference Fig.46 , Fig.47A and Fig.47B , can be passed through Fig.44 and Fig.45B A portion of the first insulating partition wall 233 is shown to form a plurality of holes 215. Figures 19 to 20B As described above, the cross section of each hole 215 may include a long axis 215_L in the first direction DR1 and a short axis 215_S in the third direction DR3. Fig.44 and Fig.45B The first insulating partition wall 233 is shown overlapping. Hereinafter, another portion of the first insulating partition wall that does not overlap with the hole 215 and is not penetrated by the hole 215 is denoted by "233P".

[0248] One side of the hole 215 may protrude and extend in the second direction DR2 to pass through a portion of each of the plurality of first interlayer insulating patterns 211A and the plurality of first conductive patterns 213A' of the first stack pattern 310A, and may extend in the fourth direction DR4. The other side of the hole 215 may protrude and extend in the third direction DR3 to pass through a portion of each of the plurality of second interlayer insulating patterns 211B and the plurality of second conductive patterns 213B' of the second stack pattern 310B, and may extend in the fourth direction DR4.

[0249] Subsequently, a first etching barrier pattern 551A and a second etching barrier pattern 551B may be formed. The first etching barrier pattern 551A and the second etching barrier pattern 551B may include substantially the same material as the plurality of first conductive patterns 213A' and the plurality of second conductive patterns 213B'. The first etching barrier pattern 551A and the second etching barrier pattern 551B may be separated in the first direction DR1 to open the central region 215C of the hole 215. The side of the first insulating partition wall 233P may be blocked by the first etching barrier pattern 551A and the second etching barrier pattern 551B. The first etching barrier pattern 551A and the second etching barrier pattern 551B may be used with reference to Figures 19 to 20B The process described above can be used to form Figures 19 to 20B Same structure as described.

[0250] Fig.48 , Fig.49A and Fig.49B FIG. 2 is a diagram showing a process of forming the first and second transverse grooves 217A and 217B, a process of forming the blocking insulating layer 220′, a process of forming the first and second data storage patterns 227A and 227B, and a process of forming the first and second data storage patterns 227A and 227B. Fig.46 A diagram of the process performed in hole 215 is shown.

[0251] Reference Fig.48 , Fig.49A and Fig.49B , can be compared with the reference Fig.21 , Fig.22A and Fig. 22B The described process forms the first transverse groove 217A at the side of the first stack pattern 310A and forms the second transverse groove 217B at the side of the second stack pattern 310B while removing Fig.46 and Fig.47B A first etch barrier pattern 551A and a second etch barrier pattern 551B are shown.

[0252] Subsequently, the first pattern 221A' and the second pattern 221B' of the first dielectric layer may be formed by oxidizing the side of each of the plurality of first conductive patterns 213A' and the plurality of second conductive patterns 213B' exposed through the hole 215 and the first and second transverse grooves 217A and 217B. Subsequently, the method described in reference to Figures 23 to 24B The process for forming the second dielectric layer is described above with reference to Figures 25 to 26B The process of separating the second dielectric layer into the first preliminary pattern and the second preliminary pattern as described above with reference to Figures 23 to 24B The process of oxidizing a portion of the first preliminary pattern and a portion of the second preliminary pattern as described. As a result, a first pattern 223A2 and a second pattern 223B2 of the second dielectric layer and a first pattern 225A and a second pattern 225B of the third dielectric layer may be formed. The first patterns 221A', 223A2 and 225A of the first to third dielectric layers may be disposed in the first transverse groove 217A and form a first blocking insulating pattern 220A'. The second patterns 221B', 223B2 and 225B of the first, second and third dielectric layers may be disposed in the second transverse groove 217B and form a second blocking insulating pattern 220B'.

[0253] Then, refer to the above Fig.29 and Fig.30 The first data storage pattern 227A and the second data storage pattern 227B are formed in the same manner as described above. Figures 31 to 32B In the same manner as described, a tunnel insulating layer 229, a channel layer 231, and an insulating pillar 235 may be formed in the hole 215. The tunnel insulating layer 229, the channel layer 231, and the insulating pillar 235 may form a vertical structure 230".

[0254] Fig.50 , Fig.51 , Fig.52 , Fig.53 , Fig.54 , Fig.55 , Fig.56 and Fig.572 is a diagram illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0255] Fig.50 , Fig.52 , Fig.54 and Fig.56 It is a plan view showing the process. Fig.51 , Fig.53 , Fig.55 and Fig.57 4 is a cross-sectional view taken along the line B4-B4' of the corresponding plan view for illustrating the process. Fig.50 , Fig.52 , Fig.54 and Fig.56 The cross-sectional view taken along the line A4-A4' is shown in FIG. Fig.35A same.

[0256] In execution Figure 50 to Figure 57 Before the process, you can perform the above reference Figures 44 to 49B Process described. Figure 50 to Figure 57 It shows that Fig.48 , Fig.49A and Fig.49B FIG. 2 is a diagram showing a process of separating the channel layer 231 into a first channel pattern and a second channel pattern.

[0257] Reference Fig.50 and Fig.51 , by removing Fig.48 and Fig.49B The first insulating partition wall 233P is shown to form a first recessed portion 371A. The tunnel insulating layer 229 may be exposed through the first recessed portion 371A.

[0258] Reference Fig.52 and Fig.53 , which can be achieved by removing Fig.50 and Fig.51 The first recessed portion 371A shown in the figure exposes a portion of the tunnel insulating layer to extend the first recessed portion. Hereinafter, the extended first recessed portion is referred to as the second recessed portion 371B. The tunnel insulating layer can be separated into the first tunnel insulating pattern 229A and the second tunnel insulating pattern 229B by the second recessed portion 371B. The channel layer 231 can be exposed by the second recessed portion 371B.

[0259] Due to the influence of the etching process of removing a portion of the tunnel insulating layer, a portion of the first pattern 221A' of the first dielectric layer may be etched from the first blocking insulating pattern 220A', and a portion of the second pattern 221B' of the first dielectric layer may be etched from the second blocking insulating pattern 220B'. As a result, the first pattern 223A2 of the second dielectric layer and the second pattern 223B2 of the second dielectric layer may remain protruding from the first blocking insulating pattern 220A' and the second blocking insulating pattern 220B' toward the second recessed portion 371B beyond the first pattern 221A' and the second pattern 221B' of the first dielectric layer.

[0260] Reference Fig.54 and Fig.55 , by removing Fig.52 and Fig.53 The second recessed portion 371B shown exposes a portion of the channel layer, and the second recessed portion may be extended. Hereinafter, the extended second recessed portion is referred to as a third recessed portion 371C. The channel layer may be separated into a first channel pattern 231A and a second channel pattern 231B by the third recessed portion 371C. The insulating pillar 235 may be exposed by the third recessed portion 371C.

[0261] Reference Fig.56 and Fig.57 , can be filled with insulating materials Fig.54 and Fig.55 The third recessed portion 371C is shown to form the second insulating partition wall 247 .

[0262] Fig.58 is a plan view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0263] In execution Fig.58 Before the process shown, the above reference Figures 44 to 49B Process described. Fig.58 It shows that Fig.48 , Fig.49A and Fig.49B FIG. 2 is a diagram of another embodiment in which the channel layer 231 is separated into a first channel pattern and a second channel pattern.

[0264] Reference Fig.58 , a groove can be formed. The groove can be formed from Figures 48 to 49B The center of the insulating pillar 235 is shown extending toward the first insulating partition wall 233P to pass through the channel layer 231. According to an embodiment, a trench may be separated from the first insulating partition wall 233P and formed in the tunnel insulating layer 229. According to another embodiment, the trench may extend in the first direction DR1 to pass through the tunnel insulating layer 229 to expose the first insulating partition wall 233P.

[0265] Subsequently, a second insulating partition wall 249 may be formed by filling the trench with an insulating material. The insulating pillar may be separated into a first pillar pattern 235A and a second pillar pattern 235B by the trench and the second insulating partition wall 249 therein. The channel layer may be separated into a first channel pattern 231A and a second channel pattern 231B.

[0266] Fig.59 is a block diagram illustrating an electronic system 1000 including a semiconductor memory device according to an embodiment of the present disclosure.

[0267] Reference Fig.59 The electronic system 1000 may include a computing system, a medical device, a communication device, a wearable device, or a memory system. The electronic system 1000 may include a host and a storage device 1200 .

[0268] Based on the interface, the host 1100 may store data in the storage device 1200 or may read the stored data from the storage device 1200. The interface may include at least one of a double data rate (DDR) interface, a universal serial bus (USB) interface, a multimedia card (MMC) interface, an embedded MMC (eMMC) interface, a peripheral component interconnect (PCI) interface, a high-speed PCI (PCI-E) interface, an advanced technology attachment (ATA) interface, a serial ATA interface, a parallel ATA interface, a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics interface (IDE), a Firewire interface, a universal flash memory (UFS) interface, and a high-speed non-volatile memory (NVMe) interface.

[0269] The storage device 1200 may include a storage controller 1210 and a semiconductor memory device 1220. According to an embodiment, the storage device 1200 may be a storage medium such as a solid state drive (SSD), a universal serial bus (USB) memory, or the like.

[0270] The memory controller 1210 may store data in the semiconductor memory device 1220 or may read data stored in the semiconductor memory device 1220 in response to a control of the host 1100 .

[0271] The semiconductor memory device 1220 may include a single memory chip or a plurality of memory chips. The semiconductor memory device 1220 may store data or output stored data in response to the control of the memory controller 1210.

[0272] The semiconductor memory device 1220 may be a nonvolatile memory device. The semiconductor memory device 1220 may include a lower interlayer insulating layer, an upper interlayer insulating layer, a channel pattern passing through the lower interlayer insulating layer and the upper interlayer insulating layer, a conductive layer facing the channel pattern between the lower interlayer insulating layer and the upper interlayer insulating layer, and a storage pattern arranged in a transverse groove, the transverse groove being defined between the conductive layer and the channel pattern by the lower interlayer insulating layer and the upper interlayer insulating layer protruding beyond the conductive layer toward the channel pattern. The distance from the conductive layer to the channel pattern may decrease toward the end of the transverse groove.

[0273] According to an embodiment of the present disclosure, the lateral grooves may be separated in the vertical direction by an interlayer insulating layer or an interlayer insulating pattern, and the width of the lateral grooves may decrease toward their ends in a plane. Therefore, in an embodiment, it is possible to prevent or mitigate charges stored in a data storage pattern disposed in the lateral groove from moving to another data storage pattern adjacent thereto in the vertical direction. In addition, in an embodiment, it is possible to prevent or mitigate the reduction of the electric field at the ends of the data storage pattern. Therefore, in an embodiment, the operational reliability of the semiconductor memory device may be improved.

[0274] CROSS-REFERENCE TO RELATED APPLICATIONS

[0275] This application claims the priority of Korean Patent Application No. 10-2023-0096145 filed on July 24, 2023 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: a lower interlayer insulating layer, the lower interlayer insulating layer overlapping the center line, the center line extending in a plane parallel to the lower interlayer insulating layer; an upper interlayer insulating layer, the upper interlayer insulating layer being spaced apart from the lower interlayer insulating layer in a direction intersecting the plane; a first channel pattern and a second channel pattern, the first channel pattern and the second channel pattern extending to pass through the lower interlayer insulating layer and the upper interlayer insulating layer, the first channel pattern being spaced apart from the second channel pattern, and the center line being interposed between the first channel pattern and the second channel pattern; a conductive layer disposed between the lower interlayer insulating layer and the upper interlayer insulating layer, the conductive layer including a first region facing the first channel pattern, a second region facing the second channel pattern, and a third region coupling the first region to the second region; as well as a first data storage pattern formed in a first lateral groove defined by the lower interlayer insulating layer and the upper interlayer insulating layer between the conductive layer and the first channel pattern, the upper interlayer insulating layer and the lower interlayer insulating layer protruding beyond the conductive layer toward the first channel pattern, Wherein, the variable width of the first transverse groove in the plane decreases toward the end of the first transverse groove.

2. The semiconductor memory device according to claim 1 , further comprising a second data storage pattern formed in a second lateral groove, the second lateral groove being defined between the conductive layer and the second channel pattern by the lower interlayer insulating layer and the upper interlayer insulating layer, the upper interlayer insulating layer and the lower interlayer insulating layer protruding beyond the conductive layer toward the second channel pattern, and in, The variable width of the second transverse groove in the plane decreases towards an end of the second transverse groove.

3. The semiconductor memory device according to claim 2, in, The width of the first data storage pattern decreases as the distance of the first data storage pattern from the center line decreases, and Wherein, the width of the second data storage pattern decreases as the distance between the second data storage pattern and the center line decreases.

4. The semiconductor memory device according to claim 2, wherein: The second transverse groove is generally symmetrical to the first transverse groove about the centerline.

5. The semiconductor memory device according to claim 1, wherein: The first transverse groove has a generally semi-elliptical shape.

6. The semiconductor memory device according to claim 1, further comprising: a tunnel insulating layer having a substantially tubular shape and extending to surround an outer wall of the first channel pattern toward the first region of the conductive layer and an outer wall of the second channel pattern toward the second region of the conductive layer; a semiconductor oxide layer overlapping the center line and disposed between an end of the first channel pattern and an end of the second channel pattern; as well as an insulating column located in a central region of the tunnel insulating layer having the substantially tubular shape; as well as A blocking insulating layer extends along a side of each of the first region and the second region of the conductive layer.

7. The semiconductor memory device according to claim 1, further comprising: an insulating partition wall interposed between the first channel pattern and the second channel pattern and overlapping the center line; a pillar pattern disposed between the insulating partition wall and each of the first channel pattern and the second channel pattern; a blocking insulating layer extending along a side portion of each of the first region and the second region of the conductive layer; as well as A tunnel insulating layer extends along an outer wall of each of the first channel pattern and the second channel pattern toward the conductive layer.

8. A semiconductor memory device, the semiconductor memory device comprising: a first lower interlayer insulating pattern and a second lower interlayer insulating pattern, the first lower interlayer insulating pattern and the second lower interlayer insulating pattern being spaced apart from each other and having a center line interposed therebetween, the center line extending in a direction in a plane parallel to each of the first lower interlayer insulating pattern and the second lower interlayer insulating pattern; a first upper interlayer insulating pattern spaced apart from the first lower interlayer insulating pattern in a direction crossing the plane; a second upper interlayer insulating pattern spaced apart from the second lower interlayer insulating pattern in the direction crossing the plane; a first channel pattern and a second channel pattern, the first channel pattern and the second channel pattern extending to pass from between the first lower interlayer insulating pattern and the second lower interlayer insulating pattern to between the first upper interlayer insulating pattern and the second upper interlayer insulating pattern, the first channel pattern and the second channel pattern being spaced apart from each other and the center line being interposed between the first channel pattern and the second channel pattern; a first conductive pattern disposed between the first lower interlayer insulating pattern and the first upper interlayer insulating pattern; a second conductive pattern disposed between the second lower interlayer insulating pattern and the second upper interlayer insulating pattern; as well as a first data storage pattern, the first data storage pattern being formed in a first lateral groove, the first lateral groove being defined between the first conductive pattern and the first channel pattern by the first lower interlayer insulating pattern and the first upper interlayer insulating pattern, the first lower interlayer insulating pattern and the first upper interlayer insulating pattern each protruding beyond the first conductive pattern toward the first channel pattern, Wherein, the variable width of the first transverse groove in the plane decreases toward the end of the first transverse groove.

9. The semiconductor memory device according to claim 8, further comprising: a second data storage pattern formed in a second lateral groove defined between the second conductive pattern and the second channel pattern by the second lower interlayer insulating pattern and the second upper interlayer insulating pattern, the second lower interlayer insulating pattern and the second upper interlayer insulating pattern protruding beyond the second conductive pattern toward the second channel pattern, Wherein, the variable width of the second transverse groove in the plane decreases toward the end of the second transverse groove.

10. The semiconductor memory device according to claim 9, in, The width of the first data storage pattern decreases as the distance of the first data storage pattern from the center line decreases, and Wherein, the width of the second data storage pattern decreases as the distance between the second data storage pattern and the center line decreases.

11. The semiconductor memory device according to claim 9, wherein: The second transverse groove is generally symmetrical to the first transverse groove about the centerline.

12. The semiconductor memory device according to claim 8, wherein: The first transverse groove has a generally semi-elliptical shape.

13. The semiconductor memory device according to claim 8, further comprising: an insulating partition wall interposed between the first channel pattern and the second channel pattern and extending between the first conductive pattern and the second conductive pattern; a first tunnel insulating pattern surrounding an outer wall of the first channel pattern facing the first conductive pattern; a second tunnel insulating pattern surrounding an outer wall of the second channel pattern facing the second conductive pattern; a first blocking insulating pattern extending along an inner wall of the first conductive pattern toward the first channel pattern; a second blocking insulating pattern extending along an inner wall of the second conductive pattern toward the second channel pattern; as well as A pillar pattern is disposed between each of the first and second channel patterns and the insulating partition wall.

14. The semiconductor memory device according to claim 8, further comprising: a first tunnel insulating pattern surrounding an outer wall of the first channel pattern facing the first conductive pattern; a second tunnel insulating pattern surrounding an outer wall of the second channel pattern facing the second conductive pattern; a first blocking insulating pattern extending along an inner wall of the first conductive pattern toward the first channel pattern; a second blocking insulating pattern extending along an inner wall of the second conductive pattern toward the second channel pattern; an insulating column extending from an inner wall of the first channel pattern toward an inner wall of the second channel pattern; as well as An insulating partition wall extends from the insulating pillar to be interposed between ends of the first channel pattern and the second channel pattern and between the first conductive pattern and the second conductive pattern.

15. The semiconductor memory device according to claim 8, further comprising: a first insulating partition wall interposed between the first conductive pattern and the second conductive pattern; second insulating partition walls arranged alternately with the first insulating partition walls in a direction in which the center line extends and including a portion interposed between an end of the first channel pattern and an end of the second channel pattern; a tunnel insulating layer surrounding an outer wall of the first channel pattern facing the first conductive pattern and an outer wall of the second channel pattern facing the second conductive pattern; a blocking insulating layer extending along an inner wall of the first conductive pattern facing the first channel pattern and an inner wall of the second conductive pattern facing the second channel pattern; as well as A pillar pattern is located between each of the first and second channel patterns and the second insulating partition wall.

16. The semiconductor memory device according to claim 15, wherein: The tunnel insulating layer extends between the first insulating partition wall and the second insulating partition wall.

17. The semiconductor memory device according to claim 15, wherein: The blocking insulating layer includes a portion extending between the first insulating partition wall and the second insulating partition wall.

18. A semiconductor memory device, the semiconductor memory device comprising: a first lower interlayer insulating pattern and a second lower interlayer insulating pattern, the first lower interlayer insulating pattern and the second lower interlayer insulating pattern being spaced apart from each other and having a center line interposed therebetween, the center line extending in a direction in a plane parallel to each of the first lower interlayer insulating pattern and the second lower interlayer insulating pattern; a first upper interlayer insulating pattern spaced apart from the first lower interlayer insulating pattern in a direction crossing the plane; a second upper interlayer insulating pattern spaced apart from the second lower interlayer insulating pattern in the direction crossing the plane; a channel layer extending to pass from between the first lower interlayer insulating pattern and the second lower interlayer insulating pattern to between the first upper interlayer insulating pattern and the second upper interlayer insulating pattern; a first conductive pattern disposed between the first lower interlayer insulating pattern and the first upper interlayer insulating pattern; a second conductive pattern disposed between the second lower interlayer insulating pattern and the second upper interlayer insulating pattern; as well as a first data storage pattern, the first data storage pattern being formed in a first lateral groove, the first lateral groove being defined between the first conductive pattern and the channel layer by the first lower interlayer insulating pattern and the first upper interlayer insulating pattern, the first lower interlayer insulating pattern and the first upper interlayer insulating pattern each protruding beyond the first conductive pattern toward the channel layer, Wherein, the variable width of the first transverse groove in the plane decreases toward the end of the first data storage pattern.

19. The semiconductor memory device according to claim 18, further comprising: a second data storage pattern formed in a second lateral groove, the second lateral groove being defined between the second conductive pattern and the channel layer by the second lower interlayer insulating pattern and the second upper interlayer insulating pattern, the second lower interlayer insulating pattern and the second upper interlayer insulating pattern protruding toward the channel layer beyond the second conductive pattern, Wherein, a variable width of the second transverse groove in the plane decreases toward an end of the second data storage pattern.

20. The semiconductor memory device according to claim 19, in, The width of the first data storage pattern decreases as the distance of the first data storage pattern from the center line decreases, and Wherein, the width of the second data storage pattern decreases as the distance between the second data storage pattern and the center line decreases.

21. The semiconductor memory device according to claim 19, wherein The second transverse groove is generally symmetrical to the first transverse groove about the centerline.

22. The semiconductor memory device according to claim 19, wherein: The first transverse groove has a generally semi-elliptical shape.

23. The semiconductor memory device according to claim 19, further comprising: an insulating column, wherein the insulating column is arranged in a central area of ​​the channel layer; an insulating partition wall interposed between the first conductive pattern and the second conductive pattern; a tunnel insulating layer, the tunnel insulating layer surrounding an outer wall of the channel layer; as well as A blocking insulating layer extends along an inner wall of the first conductive pattern facing the channel layer and an inner wall of the second conductive pattern facing the channel layer.

24. The semiconductor memory device according to claim 23, wherein: The channel layer and the tunnel insulating layer extend between the insulating pillar and the insulating partition wall.

25. The semiconductor memory device according to claim 23, wherein: The blocking insulating layer includes a portion extending between the insulating pillar and the insulating partition wall.

26. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a preliminary stacked structure including a plurality of first material layers and a plurality of second material layers alternately stacked on each other; forming a hole through the plurality of first material layers and the plurality of second material layers, the hole including a long axis along a first direction in a plane and a short axis along a second direction intersecting the long axis; forming a first etching barrier pattern extending along a first inner wall of the hole and a second etching barrier pattern extending along a second inner wall of the hole, the first inner wall and the second inner wall being opposite to each other in the first direction in the hole, the first etching barrier pattern and the second etching barrier pattern blocking the plurality of first material layers and the plurality of second material layers; Forming a first lateral groove and a second lateral groove adjacent to each other in the second direction between two first material layers adjacent to each other in the stacking direction among the plurality of first material layers by etching the plurality of second material layers exposed through the third inner wall and the fourth inner wall of the hole facing each other in the second direction; as well as A first data storage pattern is formed in the first transverse groove and a second data storage pattern is formed in the second transverse groove.

27. The method according to claim 26, in, The first etch barrier pattern and the second etch barrier pattern include substantially the same material as the plurality of second material layers, and The first etching barrier pattern and the second etching barrier pattern are removed by etching the materials of the plurality of second material layers when forming the first lateral groove and the second lateral groove.

28. The method according to claim 26, in, The width of the first transverse groove decreases toward each of the first inner wall and the second inner wall of the hole, and Wherein a width of the second transverse groove decreases toward each of the first inner wall and the second inner wall of the hole.

29. The method according to claim 26, further comprising the steps of: before forming the first data storage pattern and the second data storage pattern, forming a blocking insulating layer on a surface of each of the first lateral groove and the second lateral groove; After forming the first data storage pattern and the second data storage pattern, forming a tunnel insulating layer extending along an inner wall of each of the first data storage pattern and the second data storage pattern and along a side of a hole between the first data storage pattern and the second data storage pattern; as well as A channel layer is formed along an inner wall of the tunnel insulating layer.

30. The method of claim 29, wherein: The blocking insulating layer includes a nitride layer, and The nitride layer is separated by the tunnel insulating layer into a first pattern adjacent to the first data storage pattern and a second pattern adjacent to the second data storage pattern.

31. The method according to claim 30, further comprising the steps of: forming slits through the plurality of first material layers and the plurality of second material layers; opening a plurality of horizontal spaces by removing the plurality of second material layers through the slits; forming a semiconductor oxide layer separating the channel layer into a first channel pattern and a second channel pattern by selectively oxidizing a portion of the channel layer through the plurality of horizontal spaces and a region between the first pattern and the second pattern of the nitride layer; as well as A plurality of third material layers are formed in the plurality of horizontal spaces.

32. The method according to claim 29, further comprising the steps of: forming an insulating column in a central region of the hole; as well as forming an insulating partition wall overlapping a center of the insulating column and extending in the first direction to pass through the channel layer, The channel layer is separated into a first channel pattern and a second channel pattern by the insulating partition wall.

33. The method according to claim 29, further comprising the steps of: forming an insulating column in a central region of the hole; as well as forming an insulating partition wall overlapping a center of the insulating column and extending in the first direction to pass through the channel layer and the preliminary stacked structure, wherein the channel layer is separated into a first channel pattern and a second channel pattern by the insulating partition wall, and The preliminary stacked structure is separated into a first stacked pattern and a second stacked pattern by the insulating partition wall.

34. The method according to claim 26, further comprising the steps of: Before forming the hole, forming a first insulating partition wall extending in the first direction and separating the preliminary stacked structure into a first stacked pattern and a second stacked pattern, The hole passes through a portion of the first insulating partition wall, so that the major axis of the hole overlaps with the first insulating partition wall.

35. The method according to claim 34, further comprising the steps of: before forming the first data storage pattern and the second data storage pattern, forming a blocking insulating layer on a surface of each of the first lateral groove and the second lateral groove; After forming the first data storage pattern and the second data storage pattern, forming a tunnel insulating layer extending along an inner wall of each of the first data storage pattern and the second data storage pattern and along the first inner wall and the second inner wall of the hole; forming a channel layer along an inner wall of the tunnel insulating layer; as well as An insulating column is formed in a central region of the hole.

36. The method according to claim 35, further comprising the steps of: After forming the insulating pillar, removing the first insulating partition wall to define a recessed portion; removing a portion of the tunnel insulating layer and a portion of the channel layer through the recessed portion to define an extended recessed portion; as well as filling the extended recessed portion with a second insulating partition wall, wherein the channel layer is separated into a first channel pattern and a second channel pattern by the second insulating partition wall, and The tunnel insulation layer is separated into a first tunnel insulation pattern and a second tunnel insulation pattern by the second insulating partition wall.

37. The method according to claim 35, further comprising the steps of: forming a second insulating partition wall overlapping a center of the insulating column and extending in the first direction to pass through the channel layer, The channel layer is separated into a first channel pattern and a second channel pattern by the insulating partition wall.

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