Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the steps of providing a substrate which comprises a first region and second regions located on the two sides of the first region; a floating gate structure material layer, an initial control gate located on the floating gate structure material layer and a mask structure located on the initial control gate are formed on the substrate, first openings are formed in the initial control gate and the mask structure, and the first openings expose the surface of the floating gate structure material layer on the first region; oxidizing the surface of the initial control gate exposed out of the first opening, and forming a first isolation layer on the surface of the initial control gate; forming a first side wall on the side wall of the first isolation layer and the side wall of the mask structure; and removing the floating gate structure material layer at the bottom of the first opening by taking the first side wall as a mask until the surface of the first region is exposed, and forming a floating gate structure on the second region. The reliability of the semiconductor structure formed by the method is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Floating gate NORD flash memory is widely used in various embedded electronic products such as financial IC cards, automotive electronics, etc., because it helps save chip area and improve storage integration density. As the device size becomes smaller and smaller, the reliability of floating gate NORD flash memory also has some problems.

[0003] Reliability improvement of floating gate NORD flash memory is an ongoing issue that needs to be addressed. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure so as to improve the reliability of a floating gate NORD flash memory device.

[0005] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region located on both sides of the first region; forming a floating gate structure material layer, an initial control gate located on the floating gate structure material layer, and a mask structure located on the initial control gate on the substrate, the initial control gate and the mask structure having a first opening, the first opening exposing the surface of the floating gate structure material layer on the first region; oxidizing the surface of the initial control gate exposed by the first opening, and forming a first isolation layer on the surface of the initial control gate; forming a first sidewall on the sidewall of the first isolation layer and the sidewall of the mask structure; using the first sidewall as a mask to remove the floating gate structure material layer at the bottom of the first opening until the surface of the first region is exposed, and forming a floating gate structure on the second region.

[0006] Optionally, the surface of the initial control gate exposed by the first opening is oxidized, and a process of forming a first isolation layer on the surface of the initial control gate includes: an in-situ water vapor generation oxidation process or a thermal oxidation process.

[0007] Optionally, the material of the initial control gate includes polysilicon.

[0008] Optionally, the mask structure exposes a portion of the top surface of the initial control gate, and the first isolation layer extends from the sidewall surface of the initial control gate to the exposed portion of the top surface of the initial control gate.

[0009] Optionally, the mask structure includes a first mask layer and a second sidewall spacer located on a side wall of the first mask layer, wherein the second sidewall spacer is adjacent to the first region; and the second sidewall spacer exposes a portion of the top surface of the initial control gate.

[0010] Optionally, it also includes: forming an initial dielectric structure located between the floating gate structure material layer and the initial control gate; the first opening is located in the mask structure, the initial control gate and the initial dielectric structure, and the first sidewall is also located on the sidewall surface of the initial dielectric structure exposed by the first opening.

[0011] Optionally, a surface of the first isolation layer protrudes from a surface of the initial dielectric structure.

[0012] Optionally, a method for forming a floating gate structure material layer, an initial dielectric structure, an initial control gate and a mask structure on a substrate includes: forming a floating gate structure material layer, a dielectric structure material layer located on the floating gate structure material layer, and a control gate material layer located on the dielectric structure material layer on the substrate; forming a mask structure on the control gate material layer, the mask structure including a first mask layer and a second sidewall located on a side wall of the first mask layer, the mask structure exposing a surface of the control gate material layer on a first region, the second sidewall being adjacent to the first region; etching the control gate material layer and the dielectric structure material layer using the mask structure as a mask until a portion of the surface of the dielectric structure material layer or the surface of the floating gate structure material layer on the first region is exposed, thereby forming an initial control gate located on the floating gate structure material layer and a mask structure located on the initial control gate, the initial control gate and the mask structure having a first opening therein.

[0013] Optionally, the method for forming the first side wall includes: forming a side wall material layer on the mask structure side wall, the initial control gate side wall, the initial dielectric structure side wall and the surface of the floating gate structure material layer in the first opening; etching back the side wall material layer until the surface of the floating gate structure material layer is exposed, and forming a first side wall on the mask structure side wall, the initial control gate side wall and the initial dielectric structure side wall.

[0014] Optionally, the material of the first sidewall spacer is different from the material of the first isolation layer.

[0015] Optionally, the material of the first sidewall spacer includes silicon nitride; and the material of the first isolation layer includes silicon oxide.

[0016] Optionally, the initial dielectric structure includes at least one dielectric layer.

[0017] Optionally, the dielectric structure includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the second dielectric layer is located between the first dielectric layer and the third dielectric layer; the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the third dielectric layer.

[0018] Optionally, the material of the second dielectric layer is different from that of the first dielectric layer, and the material of the second dielectric layer is different from that of the third dielectric layer; and the material of the first dielectric layer is the same as that of the third dielectric layer.

[0019] Optionally, the material of the second dielectric layer includes silicon nitride, and the material of the first dielectric layer and the material of the third dielectric layer include silicon oxide.

[0020] Optionally, after removing the floating gate structure material layer at the bottom of the first opening using the first sidewall as a mask, it also includes: forming a word line gate structure in the first opening; forming a dielectric structure and a control gate located on the dielectric structure on the floating gate structure in the second region; and forming a third sidewall on the control gate sidewall, the dielectric structure sidewall and the floating gate structure sidewall.

[0021] Optionally, the method for forming a floating gate structure and a control gate on the second region includes: using the first side wall as a mask to remove the floating gate structure material layer at the bottom of the first opening until the surface of the first region is exposed, thereby forming an initial floating gate structure on the substrate; after forming the word line gate structure, removing the initial floating gate structure, the initial dielectric structure and the initial control gate outside the second region, and forming a floating gate structure, a dielectric structure located on the floating gate structure and a control gate located on the dielectric structure on the second region.

[0022] Optionally, the word line gate structure includes: a word line gate dielectric layer located on the surface of the first sidewall, the surface of the first region and the sidewall of the floating gate structure; and a word line gate located in the first opening, wherein the word line gate is located on the surface of the word line gate dielectric layer.

[0023] Optionally, the thickness of the first isolation layer ranges from 60 angstroms to 80 angstroms.

[0024] Optionally, the thickness of the first sidewall spacer ranges from 250 angstroms to 350 angstroms.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] The formation method of the present invention oxidizes the surface of the initial control gate exposed by the first opening, and forms a first isolation layer on the surface of the initial control gate. The top corners of the initial control gate are "rounded" after being oxidized, so that the first isolation layer is not easily pulled and broken at the top corners of the initial control gate. While ensuring the subsequent isolation effect of the first isolation layer on the control gate structure and the word line structure, the first isolation layer has good reliability.

[0027] Furthermore, the surface of the first isolation layer protrudes from the side wall surface of the initial dielectric structure, so that the side wall material layer on the surface of the first isolation layer also protrudes from the side wall surface of the initial dielectric structure. When the side wall material layer at the bottom of the first opening and the top surface of the mask structure is etched back, the back etching process also removes a portion of the side wall material layer on the more protruding surface of the first isolation layer, thereby further reducing the thickness of the formed first side wall, which is beneficial to increasing the coupling area of ​​the subsequent control gate and floating gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a semiconductor structure in one embodiment;

[0029] Figures 2 to 9 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention. DETAILED DESCRIPTION

[0030] As described in the background art, reliability improvement of floating gate NORD flash memory is a problem that needs to be solved continuously.

[0031] Figure 1 Schematic diagram of a semiconductor structure in one embodiment.

[0032] Please refer to Figure 1 The semiconductor structure comprises: a substrate 100, wherein the substrate 100 comprises a first region I and a second region II located on both sides of the first region I; a floating gate structure located on the second region II, wherein the floating gate structure comprises a floating gate dielectric layer 101 and a floating gate layer 102 located on the floating gate dielectric layer 101; a control gate structure located on the floating gate structure, wherein the control gate structure comprises a control gate dielectric layer 103 and a control gate 104 located on the control gate dielectric layer 103; a first mask layer 105 and a first spacer 106 located on the control gate structure; a word line gate structure located on the first region I ... floating gate structure comprises a floating gate dielectric layer 101 and a floating gate layer 102 located on the floating gate dielectric layer 101; a control gate structure located on the floating gate structure, wherein the floating gate structure comprises a floating gate dielectric layer 1 The word line gate structure includes a word line gate dielectric layer 109 and a word line gate 110 on the word line gate dielectric layer 109; a sidewall structure located on the sidewalls of the first sidewall 106 and the sidewalls of the control gate structure, the sidewall structure is also located on the floating gate structure, the sidewall structure includes a second sidewall 107 and a third sidewall 108 on the surface of the second sidewall 107, the word line gate dielectric layer 109 is located on the surface of the sidewall structure, the sidewall surface of the floating gate structure and the surface of the first region I; a fourth sidewall located on the sidewalls of the first mask layer 105, the sidewalls of the control gate structure and the sidewalls of the floating gate structure.

[0033] The formation process of the control gate structure and the floating gate structure is as follows: forming a floating gate structure material layer and a control gate structure material layer on the floating gate structure material layer on the substrate 100; forming a first mask layer 105 and a first sidewall 106 on the control gate structure material layer, wherein the first sidewall 106 is located on the sidewall of the first mask layer 105 adjacent to the first region I, and the first mask layer 105 and the first sidewall 106 expose the surface of the control gate structure material layer on the first region I; etching the control gate structure material layer using the first mask layer 105 and the first sidewall 106 as masks until the surface of the floating gate structure material layer is exposed, thereby forming an initial control gate structure on the substrate 100; etching the control gate structure material layer on the surface of the initial control gate structure sidewall, A sidewall structure is formed on the sidewall surface of the first sidewall 106, and the sidewall structure is located on the floating gate structure material layer; the floating gate structure material layer is etched using the sidewall structure as a mask until the surface of the first region I is exposed, forming an initial floating gate structure and an opening located on the first region I; a word line gate structure is formed on the sidewall surface and the bottom surface of the opening, and the word line gate dielectric layer 109 is located on the surface of the sidewall structure, the sidewall surface of the floating gate structure, and the surface of the first region I; the initial control gate structure and the initial floating gate structure outside the second region II are removed, and a control gate structure and a floating gate structure are formed on the second region II; a fourth sidewall is formed on the sidewall of the first mask layer 105, the sidewall of the control gate structure, and the sidewall of the floating gate structure.

[0034] During the formation of the semiconductor structure, in the process of etching the control gate structure material layer using the first mask layer 105 and the first sidewall 106 as a mask, the first sidewall 106 will also be naturally consumed. Therefore, when the initial control gate structure is formed, the first sidewall 106 will expose a portion of the initial control gate structure surface (e.g. Figure 1 As shown in the middle area A, when the sidewall structure is formed on the sidewall surface of the initial control gate structure and the sidewall surface of the first sidewall 106, the sidewall structure will also extend to the portion of the initial control gate structure surface exposed by the first sidewall 106. In order to obtain a larger coupling area between the subsequent control gate structure and the floating gate structure and improve the coupling efficiency, the thickness range of the sidewall structure is compressed to be very thin. Therefore, when the sidewall structure is deposited on the sidewall surface and the top of the initial control gate structure with a top angle, due to the thin film layer and the long film layer, the sidewall structure is easily pulled and broken at the top angle surface of the initial control gate structure, and the isolation between the subsequent control gate structure and the word line structure cannot be achieved, which affects the performance of the semiconductor structure.

[0035] In order to solve the above problems, the technical solution of the present invention provides a formation method, which oxidizes the surface of the initial control gate exposed by the first opening, and forms a first isolation layer on the surface of the initial control gate. The top corners of the initial control gate are "rounded" after being oxidized, so that the first isolation layer is not easily pulled and broken at the top corners of the initial control gate. While ensuring the subsequent isolation effect of the first isolation layer on the control gate structure and the word line structure, the first isolation layer has good reliability.

[0036] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] Figures 2 to 9 It is a structural schematic diagram of the semiconductor structure forming process in an embodiment of the present invention.

[0038] Please refer to Figure 2 , a substrate 200 is provided, wherein the substrate 200 includes a first region I and a second region II located on both sides of the first region I.

[0039] In this embodiment, the material of the substrate 200 is silicon.

[0040] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0041] Next, a floating gate structure material layer, an initial control gate located on the floating gate structure material layer, and a mask structure located on the initial control gate are formed on the substrate 200, wherein the initial control gate and the mask structure have a first opening, and the first opening exposes the surface of the floating gate structure material layer on the first region I.

[0042] In this embodiment, it also includes: forming an initial dielectric structure located between the floating gate structure material layer and the initial control gate; the first opening is located in the mask structure, the initial control gate and the initial dielectric structure, and the first spacer is also located on the sidewall surface of the initial dielectric structure exposed by the first opening. The formation process of the floating gate structure material layer, the initial control gate, the initial dielectric structure and the mask structure can be referred to Figure 2 and Figure 3 .

[0043] Please continue to refer to Figure 2A floating gate structure material layer, a dielectric structure material layer located on the floating gate structure material layer, and a control gate material layer 206 located on the dielectric structure material layer are formed on the substrate 200; a mask structure is formed on the control gate material layer 206, wherein the mask structure includes a first mask layer 207 and a second sidewall 208 located on a side wall of the first mask layer 207, wherein the mask structure exposes the surface of the control gate material layer 206 on the first region I, and the second sidewall 208 is adjacent to the first region I.

[0044] The floating gate structure material layer includes a floating gate dielectric material layer 201 and a floating gate material layer 202 located on the floating gate dielectric material layer 201 .

[0045] The material of the floating gate dielectric material layer 201 includes silicon oxide or low-K (K is less than 3.9) material; the material of the floating gate material layer 202 includes polysilicon.

[0046] The process for forming the floating gate dielectric material layer 2013 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process; the process for forming the floating gate material layer 202 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0047] The dielectric structural material layer includes at least one dielectric material layer.

[0048] In this embodiment, the dielectric structural material layer includes a first dielectric material layer 203 , a second dielectric material layer 204 and a third dielectric material layer 205 , and the second dielectric material layer 204 is located between the first dielectric material layer 203 and the third dielectric material layer 205 .

[0049] The dielectric constant of the second dielectric material layer 204 is greater than the dielectric constant of the first dielectric material layer 203 , and the dielectric constant of the second dielectric material layer 204 is greater than the dielectric constant of the third dielectric material layer 205 .

[0050] In this embodiment, the material of the second dielectric material layer 204 is different from that of the first dielectric material layer 203 , and the material of the second dielectric material layer 204 is different from that of the third dielectric material layer 205 ; the material of the first dielectric material layer 203 is the same as that of the third dielectric material layer 205 .

[0051] In this embodiment, the material of the second dielectric material layer 204 includes silicon nitride; the material of the first dielectric material layer 203 and the material of the third dielectric material layer 205 include silicon oxide.

[0052] The process for forming the first dielectric material layer 203 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process; the process for forming the second dielectric material layer 204 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process; the process for forming the third dielectric material layer 205 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0053] The control gate material layer 206 is made of polysilicon.

[0054] The process of forming the control gate material layer 206 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0055] The mask structure includes a first mask layer 207 and a second sidewall spacer 208 located on a side wall of the first mask layer 207 , and the second sidewall spacer 208 is adjacent to the first region I.

[0056] The method for forming the mask structure includes: forming a first mask layer 207 on the control gate material layer 206, wherein the first mask layer 207 exposes the surface of the control gate material layer 206 on the first region I; and forming a second sidewall 208 on the sidewall surface of the first mask layer 207 close to the first region I.

[0057] The material of the first mask layer 207 is different from the material of the second sidewall spacer 208 .

[0058] In this embodiment, the material of the first mask layer 207 includes silicon nitride; the material of the second sidewall spacer 208 includes silicon oxide.

[0059] Please refer to Figure 3 , the control gate material layer 206 and the dielectric structure material layer are etched using the mask structure as a mask until a portion of the surface of the dielectric structure material layer on the first region I is exposed, thereby forming an initial dielectric structure located on the floating gate structure material layer, an initial control gate 213 located on the initial dielectric structure, and a mask structure located on the initial control gate 213, wherein the initial dielectric structure, the initial control gate 213, and the mask structure have a first opening 209.

[0060] In this embodiment, the bottom of the first opening 209 is located in the initial dielectric structure. The first opening 209 does not expose the surface of the floating gate structure material layer to avoid damage to the surface of the floating gate structure material layer during the subsequent formation of the first spacer.

[0061] In this embodiment, the dielectric structural material layer includes a first dielectric material layer 203 , a second dielectric material layer 204 and a third dielectric material layer 205 , and the bottom of the first opening 209 is located in any one of the first dielectric material layer 203 , the second dielectric material layer 204 and the third dielectric material layer 205 .

[0062] In other embodiments, the control gate material layer 206 and the dielectric structure material layer are etched using the mask structure as a mask until the surface of the floating gate structure material layer on the first region I is exposed, and the floating gate structure material layer oxidized during the subsequent formation of the first sidewall is removed in a subsequent etching process.

[0063] Figure 3 It is shown that the first opening 209 is located in the first dielectric material layer 203. During the etching of the dielectric structure material layer, the third dielectric material layer 205 is etched to form an initial third dielectric layer 212; the second dielectric material layer 204 is etched to form an initial second dielectric layer 211.

[0064] In this embodiment, the process of etching the control gate material layer 206 and the dielectric structure material layer using the mask structure as a mask includes a dry etching process.

[0065] During the process of etching the control gate material layer 206 and the dielectric structure material layer, the second spacer 208 will also be naturally consumed. In this embodiment, the second spacer 208 exposes a portion of the top surface of the initial control gate 213 .

[0066] Please refer to Figure 4 , oxidizing the surface of the initial control gate 213 exposed by the first opening 209 , and forming a first isolation layer 214 on the surface of the initial control gate 213 .

[0067] The process of oxidizing the surface of the initial control gate 213 exposed by the first opening 209 to form the first isolation layer 214 on the surface of the initial control gate 213 includes: an in-situ steam generation oxidation process or a thermal oxidation process.

[0068] In this embodiment, the material of the first isolation layer 214 includes silicon oxide.

[0069] In this embodiment, the surface of the initial control gate 213 exposed by the first opening 209 is oxidized, and the process of forming the first isolation layer 214 on the surface of the initial control gate 213 includes an in-situ water vapor generation oxidation process. The in-situ water vapor generation oxidation process can form a first isolation layer 214 with a relatively thin thickness and a dense structure, and can ensure the quality of the first isolation layer 214 while reducing the thickness of the first isolation layer 214.

[0070] In this embodiment, the mask structure exposes a portion of the top surface of the initial control gate 213, and the first isolation layer 214 is formed on the surface of the initial control gate 213, so that the first isolation layer 214 extends from the side wall surface of the initial control gate 213 to the exposed portion of the top surface of the initial control gate 213. The first isolation layer 214 is only formed on the surface of the initial control gate 213, so that when the first isolation layer 214 extends from the side wall surface of the initial control gate 213 to the exposed portion of the top surface of the initial control gate 213, the film stress of the first isolation layer 214 is small, and the top corner of the initial control gate 213 is "rounded" after being oxidized, so that the first isolation layer 214 is not easy to be pulled and broken at the top corner position of the initial control gate 213, and the first isolation layer 214 has good reliability while ensuring the subsequent isolation effect of the first isolation layer 214 on the control gate structure and the word line structure.

[0071] In this embodiment, the surface of the first isolation layer 214 protrudes from the surface of the initial dielectric structure.

[0072] In this embodiment, the surface of the first isolation layer 214 protrudes from the side wall surface of the initial third dielectric layer 212 and the side wall surface of the initial second dielectric layer 211 .

[0073] The thickness of the first isolation layer 214 is in a range of 60 angstroms to 80 angstroms.

[0074] Next, a first sidewall is formed on the sidewall of the first isolation layer 214 and the sidewall of the mask structure. The formation process of the first sidewall is shown in FIG. Figure 5 and Figure 6 .

[0075] Please refer to Figure 5 A spacer material layer 215 is formed on the side wall surface of the first isolation layer 214, the side wall surface of the initial third dielectric layer 212, the side wall surface of the initial second dielectric layer 211, the side wall surface of the second spacer 208, the top surface of the mask structure and the surface of the first dielectric material layer 203 at the bottom of the first opening 209.

[0076] The process of forming the spacer material layer 215 includes a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0077] Please refer to Figure 6 , the sidewall material layer 215 is etched back until the surface of the floating gate structure material layer is exposed, and a first sidewall 216 is formed on the sidewall of the mask structure, the sidewall of the initial control gate 213, the sidewall surface of the initial third dielectric layer 212 and the sidewall surface of the initial second dielectric layer 211.

[0078] In this embodiment, the dielectric constant of the material of the first spacer 216 is greater than the dielectric constant of the material of the first isolation layer 214. The dielectric constant of the material of the first spacer 216 is large, and the first spacer 216 has a better electrical isolation effect. The first isolation layer 214 is located between the first spacer 216 and the word line gate structure to avoid the first spacer 216 with a larger dielectric constant directly contacting the word line gate structure, and the first spacer 216 is easily broken down when the word line gate structure is loaded with a voltage, thereby increasing reliability.

[0079] In this embodiment, the surface of the first isolation layer 214 protrudes from the side wall surface of the initial third dielectric layer 212 and the side wall surface of the initial second dielectric layer 211, so that the side wall material layer 215 on the surface of the first isolation layer 214 also protrudes from the side wall surface of the initial third dielectric layer 212 and the side wall surface of the initial second dielectric layer 211. When the side wall material layer 215 at the bottom of the first opening 209 and the top surface of the mask structure is back-etched, the back-etching process also removes a portion of the side wall material layer 215 on the more protruding surface of the first isolation layer 214, thereby further reducing the thickness of the formed first side wall 216, which is beneficial to increasing the coupling area of ​​the subsequent control gate and floating gate structure.

[0080] In this embodiment, the material of the first sidewall spacer 216 is different from the material of the first isolation layer 214 .

[0081] The material of the first sidewall spacer 216 includes silicon nitride or silicon oxynitride.

[0082] In this embodiment, the material of the first spacer 216 includes silicon nitride.

[0083] In other embodiments, the material of the first spacer and the material of the first isolation layer can be the same, and the first spacer and the first isolation layer with different dielectric constants can be formed based on different formation processes or process parameters of the same formation process.

[0084] In this embodiment, the thickness of the first sidewall spacer 216 is in a range of 250 angstroms to 350 angstroms.

[0085] The first sidewall spacer 216 and the first isolation layer 214 are relatively thin, which can meet the requirement of a large coupling area between the subsequent control gate and the floating gate structure in a small-sized structure, thereby improving the coupling efficiency between the control gate and the floating gate structure.

[0086] Next, the floating gate structure material layer at the bottom of the first opening 209 is removed using the first sidewall 216 as a mask until the surface of the first region I is exposed, and a floating gate structure is formed on the second region II. Figures 7 to 9 .

[0087] Please refer to Figure 7 , using the first sidewall 216 as a mask, a portion of the dielectric structure material layer and the floating gate structure material layer at the bottom of the first opening 209 is removed until the surface of the first region I is exposed, thereby forming an initial floating gate structure on the substrate 200 .

[0088] In this embodiment, a portion of the dielectric structure material layer at the bottom of the first opening 209 is removed using the first sidewall spacer 216 as a mask. That is, the first dielectric material layer 203 at the bottom of the first opening 209 is removed using the first sidewall spacer 216 as a mask.

[0089] The first dielectric material layer 203 is etched to form an initial first dielectric layer 217. The initial dielectric structure includes an initial first dielectric layer 217, an initial second dielectric layer 211 and an initial third dielectric layer 212, wherein the initial second dielectric layer 211 is located between the initial first dielectric layer 217 and the initial third dielectric layer 212; the dielectric constant of the initial second dielectric layer 211 is greater than the dielectric constant of the initial first dielectric layer 217, and the dielectric constant of the initial second dielectric layer 211 is greater than the dielectric constant of the initial third dielectric layer 212.

[0090] The initial floating gate structure includes an initial floating gate dielectric layer 218 and an initial floating gate layer 219 located on the initial floating gate dielectric layer 218 .

[0091] Please refer to Figure 8 , a word line gate structure is formed in the first opening 209 .

[0092] The word line gate structure includes: a word line gate dielectric layer 220 located on the side wall surface of the first spacer 216, the surface of the first region I and the side wall surface of the initial floating gate structure; a word line gate 221 located in the first opening 209, and the word line gate 221 is located on the surface of the word line gate dielectric layer 220.

[0093] The material of the word line gate dielectric layer 220 includes silicon oxide or a low-K (K is less than 3.9) material; the material of the word line gate 221 includes polysilicon.

[0094] The method for forming the word line gate structure includes: forming a word line gate dielectric material layer on the side wall surface and top surface of the first opening and the top surface of the mask structure; forming a word line gate material layer on the word line gate dielectric material layer; planarizing the word line gate material layer and the word line gate dielectric material layer until the top surface of the mask structure is exposed, and forming the word line gate structure in the first opening.

[0095] Please refer to Fig. 9A dielectric structure and a control gate 227 located on the dielectric structure are formed on the floating gate structure of the second region II; and a third spacer 228 is formed on the sidewalls of the control gate 227, the dielectric structure and the floating gate structure.

[0096] The method for forming a floating gate structure and a control gate 227 on the second region II includes: after forming a word line gate structure, removing the initial floating gate structure, the initial dielectric structure and the initial control gate 213 outside the second region II, and forming a floating gate structure, a dielectric structure located on the floating gate structure and a control gate 227 located on the dielectric structure on the second region II.

[0097] The floating gate structure includes a floating gate dielectric layer 222 and a floating gate layer 223 located on the floating gate dielectric layer 222 .

[0098] The dielectric structure includes at least one dielectric layer.

[0099] In this embodiment, the dielectric structure includes a first dielectric layer 224, a second dielectric layer 225 and a third dielectric layer 226, and the second dielectric layer 225 is located between the first dielectric layer 224 and the third dielectric layer 226; the dielectric constant of the second dielectric layer 225 is greater than the dielectric constant of the first dielectric layer 224, and the dielectric constant of the second dielectric layer 225 is greater than the dielectric constant of the third dielectric layer 226.

[0100] The material of the second dielectric layer 225 is different from that of the first dielectric layer 224 , and the material of the second dielectric layer 225 is different from that of the third dielectric layer 226 ; the material of the first dielectric layer 224 is the same as that of the third dielectric layer 226 .

[0101] In this embodiment, the material of the second dielectric layer 225 includes silicon nitride, and the material of the first dielectric layer 224 and the material of the third dielectric layer 226 include silicon oxide.

[0102] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and second regions located on both sides of the first region; Forming a floating gate structure material layer, an initial control gate located on the floating gate structure material layer, and a mask structure located on the initial control gate on the substrate, wherein the initial control gate and the mask structure have a first opening therein, and the first opening exposes the surface of the floating gate structure material layer on the first region; Oxidizing the surface of the initial control gate exposed by the first opening to form a first isolation layer on the surface of the initial control gate; forming a first sidewall spacer on a sidewall of the first isolation layer and a sidewall of the mask structure; The floating gate structure material layer at the bottom of the first opening is removed using the first sidewall as a mask until the surface of the first region is exposed, and a floating gate structure is formed on the second region.

2. The method for forming a semiconductor structure according to claim 1, wherein: The surface of the initial control gate exposed by the first opening is oxidized, and the process of forming a first isolation layer on the surface of the initial control gate includes: an in-situ water vapor generation oxidation process or a thermal oxidation process.

3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the initial control gate includes polysilicon.

4. The method for forming a semiconductor structure according to claim 1, wherein: The mask structure exposes a portion of the top surface of the initial control gate, and the first isolation layer extends from the sidewall surface of the initial control gate to the exposed portion of the top surface of the initial control gate.

5. The method for forming a semiconductor structure according to claim 4, wherein: The mask structure includes a first mask layer and a second sidewall spacer located on one side of the first mask layer, wherein the second sidewall spacer is adjacent to the first region; the second sidewall spacer exposes a portion of the top surface of the initial control gate.

6. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: An initial dielectric structure is formed between the floating gate structure material layer and the initial control gate; the first opening is located in the mask structure, the initial control gate and the initial dielectric structure, and the first sidewall is also located on the sidewall surface of the initial dielectric structure exposed by the first opening.

7. The method for forming a semiconductor structure according to claim 6, wherein: A surface of the first isolation layer protrudes from a surface of the initial dielectric structure.

8. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming a floating gate structure material layer, an initial dielectric structure, an initial control gate and a mask structure on a substrate comprises: forming a floating gate structure material layer, a dielectric structure material layer located on the floating gate structure material layer, and a control gate material layer located on the dielectric structure material layer on the substrate; forming a mask structure on the control gate material layer, wherein the mask structure comprises a first mask layer and a second sidewall located on a side wall of the first mask layer, wherein the mask structure exposes a surface of the control gate material layer on a first region, and the second sidewall is adjacent to the first region; etching the control gate material layer and the dielectric structure material layer using the mask structure as a mask until a portion of the surface of the dielectric structure material layer or the surface of the floating gate structure material layer on the first region is exposed, thereby forming an initial control gate located on the floating gate structure material layer and a mask structure located on the initial control gate, wherein the initial control gate and the mask structure have a first opening therein.

9. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the first sidewall spacer includes: forming a sidewall material layer on the mask structure sidewall, the initial control gate sidewall, the initial dielectric structure sidewall and the surface of the floating gate structure material layer in the first opening; etching back the sidewall material layer until the surface of the floating gate structure material layer is exposed, and forming a first sidewall spacer on the mask structure sidewall, the initial control gate sidewall and the initial dielectric structure sidewall.

10. The method for forming a semiconductor structure according to claim 9, wherein: The material of the first sidewall spacer is different from that of the first isolation layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The material of the first sidewall spacer includes silicon nitride; the material of the first isolation layer includes silicon oxide.

12. The method for forming a semiconductor structure according to claim 6, wherein: The initial dielectric structure includes at least one dielectric layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The dielectric structure includes a first dielectric layer, a second dielectric layer and a third dielectric layer, wherein the second dielectric layer is located between the first dielectric layer and the third dielectric layer; the dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer, and the dielectric constant of the second dielectric layer is greater than the dielectric constant of the third dielectric layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The material of the second dielectric layer is different from that of the first dielectric layer, and the material of the second dielectric layer is different from that of the third dielectric layer; the material of the first dielectric layer is the same as that of the third dielectric layer.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the second dielectric layer includes silicon nitride, and the material of the first dielectric layer and the material of the third dielectric layer include silicon oxide.

16. The method for forming a semiconductor structure according to claim 6, wherein: After removing the floating gate structure material layer at the bottom of the first opening using the first sidewall as a mask, the method also includes: forming a word line gate structure in the first opening; forming a dielectric structure and a control gate located on the dielectric structure on the floating gate structure in the second region; and forming a third sidewall on the control gate sidewall, the dielectric structure sidewall and the floating gate structure sidewall.

17. The method for forming a semiconductor structure according to claim 16, wherein: The method for forming a floating gate structure and a control gate on the second region comprises: removing the floating gate structure material layer at the bottom of the first opening by using the first sidewall as a mask until the surface of the first region is exposed, thereby forming an initial floating gate structure on the substrate; after forming the word line gate structure, removing the initial floating gate structure, the initial dielectric structure and the initial control gate outside the second region, thereby forming a floating gate structure, a dielectric structure located on the floating gate structure and a control gate located on the dielectric structure on the second region.

18. The method for forming a semiconductor structure according to claim 16, wherein: The word line gate structure comprises: a word line gate dielectric layer located on the surface of the first spacer sidewall, the surface of the first region and the surface of the floating gate structure sidewall; a word line gate located in the first opening, and the word line gate is located on the surface of the word line gate dielectric layer.

19. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first isolation layer is in a range of 60 angstroms to 80 angstroms.

20. The method for forming a semiconductor structure according to claim 1, wherein: The thickness of the first sidewall spacer ranges from 250 angstroms to 350 angstroms.

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