Semiconductor structure and forming method thereof

Abstract

A semiconductor structure includes a semiconductor-on-insulator (SOI) substrate including a process substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure vertically extending through the top semiconductor layer and the buried insulating layer, and including: a first internal insulating liner laterally surrounding a first portion of the top semiconductor layer in the first device region in a plan view; a first non-insulating trench structure laterally surrounding the first inner insulating liner; and a first outer insulating liner laterally surrounding the first non-insulating trench structure; and a resistive memory array on the first portion of the top semiconductor layer and located entirely within the first device region in plan view. The embodiment of the invention also discloses a method for forming the semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background Art

[0002] Resistive memory devices are susceptible to malfunction due to external noise, such as electromagnetic interference and voltage fluctuations. Operating voltage, manufacturing quality, and the device's operating environment also affect the sensitivity of resistive memory devices to external noise. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate on an insulator, comprising a processing substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure, extending vertically through the top semiconductor layer and the buried insulating layer, and comprising: a first internal insulating pad, laterally surrounding a first portion of the top semiconductor layer located in a first device region in a plan view; a first non-insulating trench structure, laterally surrounding the first internal insulating pad; and a first external insulating pad, laterally surrounding the first non-insulating trench structure; and a resistive memory array, located on the first portion of the top semiconductor layer and completely within the first device region in a plan view.

[0004] According to another aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate on an insulator, comprising a processing substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure, comprising a first non-insulating trench structure laterally surrounding a first portion of the top semiconductor layer located in a first device region in a plan view; a second deep trench isolation structure, comprising a second non-insulating trench structure laterally surrounding the first deep trench isolation structure in a plan view; and a resistive memory array, located on the first portion of the top semiconductor layer and completely within the first device region in a plan view.

[0005] According to another aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, the method comprising: forming at least one moat trench through a top semiconductor layer and a buried insulating layer of a semiconductor-on-insulator substrate, wherein each of the at least one moat trench laterally surrounds a first portion of the top semiconductor layer located in a first device region in a plan view; forming at least one deep trench isolation structure in the at least one moat trench; and forming a resistive memory array on the first portion of the top semiconductor layer, wherein, in a plan view, the resistive memory array is completely formed within the first device region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A is a vertical cross-sectional view of a first configuration of an exemplary structure after forming a shallow trench isolation structure in accordance with an embodiment of the present invention;

[0008] Figure 1B yes Figure 1A A top view of an exemplary structure; vertical plane A-A' is Figure 1A The section plane;

[0009] Figure 2A is a vertical cross-sectional view of a first configuration of an exemplary structure after forming a moat trench according to an embodiment of the present invention;

[0010] Figure 2B yes Figure 2A A top view of an exemplary structure; vertical plane A-A' is Figure 2A The section plane;

[0011] Figure 3A is a vertical cross-sectional view of a first configuration of an exemplary structure after forming a deep trench isolation structure in accordance with an embodiment of the present invention;

[0012] Figure 3B yes Figure 3A A top view of an exemplary structure; vertical plane A-A' is Figure 3A The section plane;

[0013] Figure 4A is a vertical cross-sectional view of a first configuration of an exemplary structure after forming a memory array, peripheral devices, a lower level dielectric material layer, a lower level metal interconnect structure, and a metal moat structure according to an embodiment of the present invention;

[0014] Figure 4B yes Figure 4A A top view of an exemplary structure; vertical plane A-A' is Figure 4A The section plane;

[0015] Figure 4C yes Figure 4A an enlarged vertical cross-sectional view of a portion of a memory array region in;

[0016] Figure 5 is a vertical cross-sectional view of a first configuration of an exemplary structure after forming an upper level dielectric material layer, an upper level metal interconnect structure, and a metal bump structure in accordance with an embodiment of the present invention;

[0017] Figure 6 is a vertical cross-sectional view of a second configuration of an exemplary structure according to an embodiment of the present invention;

[0018] Figure 7 is a vertical cross-sectional view of a third configuration of an exemplary structure according to an embodiment of the present invention;

[0019] Figure 8 is a vertical cross-sectional view of a fourth configuration of an exemplary structure according to an embodiment of the present invention;

[0020] Fig. 9 is a vertical cross-sectional view of a fifth configuration of an exemplary structure according to an embodiment of the present invention;

[0021] Fig.10 is a vertical cross-sectional view of a sixth configuration of an exemplary structure according to an embodiment of the present invention;

[0022] Fig.11 is a vertical cross-sectional view of a seventh configuration of an exemplary structure according to an embodiment of the present invention;

[0023] Fig.12 is a vertical cross-sectional view of an eighth configuration of an exemplary structure according to an embodiment of the present invention;

[0024] Fig.13 is a vertical cross-sectional view of a ninth configuration of an exemplary structure according to an embodiment of the present invention;

[0025] Fig.14 is a vertical cross-sectional view of a tenth configuration of an exemplary structure according to an embodiment of the present invention;

[0026] Fig.15 is a vertical cross-sectional view of an eleventh configuration of an exemplary structure according to an embodiment of the present invention;

[0027] Fig.16 is a flow chart illustrating steps for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. The accompanying drawings are not drawn to scale. Elements with the same reference numerals refer to the same elements and are assumed to have the same material composition and the same thickness range unless otherwise expressly indicated. Unless otherwise expressly stated, embodiments in which multiple instances of any described element are repeated are expressly contemplated. Embodiments in which non-essential elements are omitted are expressly contemplated, even if these embodiments are not expressly disclosed but known in the art.

[0029] Ordinal numbers such as "first", "second", "third" are usually not part of the noun referring to the element, but are merely adjectives. Therefore, in the specification and claims, the same element can be referred to by different ordinal numbers. In addition, whenever there are multiple elements and / or similar elements, these multiple elements and / or similar elements can be numbered in any order. Therefore, for each case in which there are multiple elements, the possibility of numbering the elements with different ordinal numbers is clearly considered. Moreover, for ease of description, spatial relative terms such as "under...", "below...", "lower part", "above...", "upper part" can be used here to easily describe the relationship between an element or component as shown in the figure and another (or other) element or component. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be similarly interpreted accordingly.

[0030] The operation of resistive random access memory (RRAM) devices, particularly where the RRAM devices are used in conjunction with high voltage devices or circuits, raises concerns about crosstalk noise interference. Sensitivity to external noise may compromise the reliability of the operation of the RRAM device. In the present invention, a semiconductor structure is disclosed in which the RRAM device is electrically shielded by a buried insulating layer of a semiconductor substrate on an insulator, at least one deep trench isolation structure, and optionally at least one metal moat structure. Multiple nested deep trench isolation structures and / or multiple metal moat structures may be used. Crosstalk noise originating from the surrounding environment, particularly from high voltage devices and circuits, may be suppressed by various structures of the present invention. The devices of the present invention may be used in memory devices that withstand high levels of electrical noise, such as, but not limited to, memory devices used in the automotive industry.

[0031] refer to Figure 1A and Figure 1B, showing a first configuration of an exemplary structure according to an embodiment of the present invention. The first configuration of the exemplary structure includes a semiconductor on insulator (SOI) substrate 5, which includes, from bottom to top, a handle substrate 2, a buried insulating layer 4, and a top semiconductor layer 10. The handle substrate 2 can have a thickness in the range of 300 microns to 1 mm, although smaller and larger thicknesses can also be used. In one embodiment, the handle substrate 2 can include a semiconductor substrate that includes a single crystalline semiconductor material such as single crystal silicon. The buried insulating layer 4 includes an insulating material such as silicon oxide and can have a thickness in the range of 100nm to 1000nm, although smaller and larger thicknesses can also be used. The top semiconductor layer 10 includes a single crystalline semiconductor material such as single crystal silicon. The thickness of the top semiconductor layer 10 can be in the range of 500nm to 2000nm, although smaller and larger thicknesses can also be used.

[0032] A first pad dielectric layer 11 may be formed above the top surface of the top semiconductor layer 10. The first pad dielectric layer 11 may include, for example, a silicon nitride layer. Other dielectric materials are also within the contemplation of the present disclosure. A photoresist layer (not shown) may be applied above the top surface of the first pad dielectric layer 11 and may be photolithographically patterned to form openings therein. An anisotropic etching process may be implemented to transfer the pattern of the openings through the first pad dielectric layer 11 into the upper portion of the top semiconductor layer 10. Shallow trenches may be formed in the volume from which the material of the top semiconductor layer 10 is removed. The photoresist layer may be removed, for example, by ashing.

[0033] A dielectric filling material, such as undoped silicate glass or doped silicate glass, may be deposited in the shallow trench. A portion of the dielectric filling material covering a horizontal surface including the top surface of the first pad dielectric layer 11 may be removed by performing a planarization process, which may include a chemical mechanical polishing process or a recess etching process. Subsequently, the dielectric filling material may be vertically recessed below a horizontal surface including the top surface of the first pad dielectric layer 11 by performing a selective etching process, which may selectively etch the dielectric filling material relative to the material of the first pad dielectric layer 11. For example, if the dielectric filling material includes silicon oxide, and if the first pad dielectric layer 11 includes silicon nitride, a wet etching process using dilute hydrofluoric acid may be performed to selectively recess the dielectric filling material.

[0034] The remaining portion of the dielectric filling material filling the shallow trench comprises a shallow trench isolation structure (12, 21, 22). The top surface of the shallow trench isolation structure (12, 21, 22) may be formed at or around a level including the top surface of the top semiconductor layer 10. Subsequently, the first pad dielectric layer 11 may be removed selectively relative to the shallow trench isolation structure (12, 21, 22) by performing an additional selective etching process. For example, if the first pad dielectric layer 11 comprises silicon nitride, the additional selective etching process may include a wet etching process using hot phosphoric acid.

[0035] The shallow trench isolation structure (12, 21, 22) includes at least one annular shallow trench filling structure (21, 22) that laterally surrounds a first device region 300 as a corresponding single continuous structure including a corresponding opening therethrough. In one embodiment, each of the at least one annular shallow trench filling structure (21, 22) can be topologically homeomorphic to the torus, i.e., can be continuously deformed without creating any additional opening therethrough or destroying any pre-existing opening in the shape therethrough to the torus. The region of the exemplary structure laterally surrounded by the innermost periphery of the at least one annular shallow trench filling structure (21, 22) constitutes the first device region 300.

[0036] In one embodiment, at least one annular shallow trench filling structure (21, 22) may include an inner annular shallow trench filling structure 21 and an outer annular shallow trench filling structure 22 that laterally surrounds the inner annular shallow trench filling structure 21 and laterally surrounds the inner annular shallow trench filling structure 21. The lateral spacing between the inner top periphery and the outer top periphery of the inner annular shallow trench filling structure 21 can be in the range of 500nm to 5000nm, although smaller and larger lateral spacings can also be used. The lateral spacing between the inner top periphery and the outer top periphery of the outer annular shallow trench filling structure 22 can be in the range of 500nm to 5000nm, although smaller and larger lateral spacings can also be used. An annular gap exists between the outer top periphery of the inner annular shallow trench filling structure 21 and the inner periphery of the outer annular shallow trench filling structure 22. A second device area 400 can be provided outside the outer periphery of the outer annular shallow trench filling structure 22.

[0037] According to one aspect of the present invention, the shallow trench isolation structure (12, 21, 22) may include a shallow trench isolation grid 12 formed in the first device region 300. The shallow trench isolation grid 12 may be formed in an upper region of a first portion of the top semiconductor layer 10 laterally surrounded by at least one annular shallow trench filling structure (21, 22). For example, the shallow trench isolation grid 12 may include an M x N rectangular grid of openings therein. Each of M and N may be an integer greater than 1. For example, each of M and N may be independently between 2 and 2 16 The portion of the top semiconductor layer 10 located within the opening in the shallow trench isolation grid 12 constitutes the active area of ​​the field effect transistor that is subsequently formed. The shallow trench isolation grid 12 can laterally surround the array of active areas of the access transistors, which is a patterned section of the first portion of the top semiconductor layer 10. Therefore, the source region and drain region of the array of access transistors can be subsequently formed within the array of active areas. Additional shallow trench isolation structures (not shown) can be formed in the second device area 400, which can be used to form peripheral devices to control the operation of the memory array that is subsequently formed in the first device area 300.

[0038] refer to Figure 2A and Figure 2B , a second pad dielectric layer 15 may be formed on the top surface of the top semiconductor layer 10. A photoresist layer (not shown) may be applied over the top surface of the second pad dielectric layer 15 and may be patterned photolithographically to form at least one moat-shaped opening therethrough. Each of the at least one moat-shaped opening in the photoresist layer may be formed entirely within an annular region defined by the outer periphery and the inner periphery of the corresponding annular shallow trench filling structure (21, 22). An anisotropic etching process may be performed to transfer the pattern of the at least one moat-shaped opening in the photoresist layer through the second pad dielectric layer 15, the at least one annular shallow trench filling structure (21, 22), the top semiconductor layer 10, and the buried insulating layer 4 to the upper portion of the handle substrate 2. At least one moat trench (17, 18) may be formed in a volume from which the material of the at least one annular shallow trench filling structure (21, 22), the top semiconductor layer 10, the buried insulating layer 4, and the handle substrate 2 comes.

[0039] In one embodiment, each moat trench (17, 18) may be formed through a corresponding annular shallow trench filling structure (21, 22). In one embodiment, at least one moat trench (17, 18) may include an inner moat trench 17 formed through an inner annular shallow trench filling structure 21, and an outer moat trench 18 formed through an outer annular shallow trench filling structure 22. The remaining portion of the inner annular shallow trench filling structure 21 may include a pair of inner annular shallow trench filling structures 21, and the remaining portion of the outer annular shallow trench filling structure 22 may include a pair of outer annular shallow trench filling structures 22. The portion of the top semiconductor layer 10 remaining between the inner moat trench 17 and the outer moat trench 18 may include a single crystal semiconductor moat structure 10M, which is a single crystal semiconductor wall structure extending vertically from the handle substrate 2 to the top surface of the top semiconductor layer 10. As used herein, a moat structure refers to a continuous structure that laterally surrounds a region and is homeomorphic to the annulus, ie, can be continuously deformed without creating any additional openings therethrough or destroying any pre-existing openings therethrough in the shape of the annulus.

[0040] Each of the at least one moat trenches (17, 18) laterally surrounds a first portion of the top semiconductor layer 10 located in the first device region 300 in a plan view such as a top view. Each of the at least one moat trenches (17, 18) may include a corresponding set of straight sidewalls extending vertically from the top surface of the top semiconductor layer 10 to the handle substrate 2. The width of the top of each moat trench (17, 18) may be in the range of 400nm to 4000nm, for example 600nm to 3000nm, although smaller and larger widths may also be used.

[0041] In one embodiment, the handle substrate 2 includes a semiconductor material (such as single crystal silicon), and an electrical dopant (which may be a p-type dopant or an n-type dopant) may be implanted into a surface portion of the handle substrate 2 located below at least one moat trench (17, 18). In this embodiment, at least one doped well (7, 8) may be formed below at least one moat trench (17, 18). For example, an inner annular doped well 7 may be formed below the inner moat trench 17, and an outer annular doped well 8 may be formed below the outer moat trench 18. The atomic concentration of the electrical dopant in each doped well (7, 8) may be between 1.0 x 10 19 / cm 3 Up to 2.0x 10 21 / cm 3 The photoresist layer may then be removed, for example, by ashing.

[0042] refer to Figure 3A and Figure 3B, may be formed in the peripheral portion of at least one of the moat trenches (17, 18) and above the top surface of the second pad dielectric layer 15 (eg Figure 2A and Figure 2B An insulating liner layer is conformally deposited (as shown in ). The insulating liner layer includes an insulating material, such as silicon oxide. The thickness of the insulating liner layer can be in the range of 30nm to 300nm, although smaller and larger thicknesses can also be used. An anisotropic etching process can be performed to remove horizontally extending portions of the insulating liner layer. Each remaining vertically extending portion of the insulating liner layer constitutes an insulating liner (23I, 23O, 24I, 24O).

[0043] In one embodiment, the insulating pads (23I, 23O, 24I, 24O) may include at least one inner insulating pad (23I, 24I) formed on the inner sidewall of the corresponding moat trench (17, 18), and at least one outer insulating pad (23O, 24O) formed on the outer sidewall of the corresponding moat trench (17, 18). In one embodiment, at least one moat trench (17, 18) includes an inner moat trench 17 and an outer moat trench 18, and the insulating pads (23I, 23O, 24I, 24O) may include: a first inner insulating pad 23I formed on the inner sidewall of the inner moat trench 17, a first outer insulating pad 23O formed on the outer sidewall of the inner moat trench 17, a second inner insulating pad 24I formed on the inner sidewall of the outer moat trench 18, and a second outer insulating pad 24O formed on the outer sidewall of the outer moat trench 18. As described above, the ordinal numbers are not part of the noun referring to the insulating pads (23I, 23O, 24I, 24O), therefore, when referring to multiple insulating pads (23I, 23O, 24I, 24O), different groups of ordinal numbers can be used to refer to each insulating pad (23I, 23O, 24I, 24O) individually.

[0044] A non-insulating material may be deposited in the remaining volume of at least one of the moat trenches (17, 18) and above the second pad dielectric layer 15. The non-insulating material may include a conductive material or a semiconductor material. As used herein, "conductive material" refers to a material having a conductivity greater than 1.0 x 10 5 As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0 x 10 -5 S / m. Semiconductor materials refer to materials with electrical conductivity of 1.0x10 -5 S / m to 1.0x 10 5 S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0 x 10 -5S / m to 1.0 S / m, and when properly doped with electrical dopants, can produce a conductivity of 1.0 S / m to 1.0 x 10 7 S / m range. Therefore, whether a semiconductor material is a semiconductor or a conductor depends on the atomic concentration and electrical activity of the electrical dopant therein. If a semiconductor material is conductive, then this semiconductor material is called a heavily doped semiconductor material.

[0045] The non-insulating material deposited in the remaining volume of at least one moat trench (17, 18) and over the second pad dielectric layer 15 may include a semiconductor material such as polysilicon or amorphous silicon, and / or may include at least one metallic material such as a combination of a metal barrier liner material (e.g., TiN, TaN, WN, and / or MoN) and a metal filler material (e.g., a refractory metal). In one embodiment, the non-insulating material may include heavily doped polysilicon, which may then be annealed to activate the electrical dopants to provide a dielectric constant greater than 1.0 x 10 5 Conductivity in S / m.

[0046] A planarization process such as a chemical mechanical polishing process may be performed to remove portions of the non-insulating material from above a horizontal plane including the top surface of the second pad dielectric layer 15. Additionally, a recess etching process may then be performed to vertically recess remaining portions of the non-insulating material from above a horizontal plane including the top surface of the top semiconductor layer 10. Each remaining portion of the non-insulating material that fills a portion of the corresponding moat trench (17, 18) forms a non-insulating moat structure (27, 28), which may be a conductive structure or a semiconductor structure. By performing a selective etching process, the second pad dielectric layer 15 may be selectively removed relative to the material of the top semiconductor layer 10 and the shallow trench isolation structure (21, 22, 12). For example, in the case where the second pad dielectric layer 15 includes silicon nitride, the second pad dielectric layer 15 may be removed using a wet etching process using hot phosphoric acid.

[0047] In one embodiment, the non-insulating moat structure (27, 28) may include an inner non-insulating moat structure 27 formed in the inner moat trench 17, and an outer non-insulating moat structure 28 formed in the outer moat trench 18. Each continuous combination of structural elements filling the corresponding moat trenches (17, 18) constitutes a deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)}. In one embodiment, at least one deep trench isolation structure {(27, 23I, 23O), (28, 24I, 24O)} may include an inner deep trench isolation structure (27, 23I, 23O) formed in the inner moat trench 17, and an outer deep trench isolation structure (28, 24I, 24O) formed in the outer moat trench 18. One of the deep trench isolation structures {(27, 23I, 23O), (28, 24I, 24O)} may be referred to as a first deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)}, and the other of the deep trench isolation structures {(27, 23I, 23O), (28, 24I, 24O)} may be referred to as a second deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)}.

[0048] Typically, at least one deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} may be formed in at least one moat trench (17, 18). The first deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} vertically extends through the top semiconductor layer 10 and the buried insulating layer 4, and includes a first inner insulating liner (23I or 24I) laterally surrounding a first portion of the top semiconductor layer 10 located in the first device region 300 in a plan view; a first non-insulating moat structure (27 or 28) laterally surrounding the first inner insulating liner (23I or 24I), and a first outer insulating liner (23O or 24O) laterally surrounding the first non-insulating moat structure (27 or 28). In one embodiment, the first deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} includes a first non-insulating moat structure (27 or 28) that laterally surrounds a first portion of the top semiconductor layer 10 located in the first device region 300 in a plan view; and the second deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} includes a second non-insulating moat structure (27 or 28) that laterally surrounds the first deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} in a plan view, or is laterally surrounded by the first deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)}.

[0049] According to one aspect of the present invention, each non-insulating trench structure (27, 28) in at least one deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} is used as a structure for signal shielding against external electromagnetic signals. Preferably, each non-insulating trench structure (27, 28) is conductive and provides effective signal shielding through high conductivity. According to one aspect of the present invention, at least one deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} includes a plurality of deep trench isolation structures {(27, 23I, 23O) or (28, 24I, 24O)} to provide sufficient electrical isolation to a memory device subsequently formed in the first device region 300.

[0050] refer to Figure 4A-4C , a semiconductor device, a lower-level dielectric material layer 50, a lower-level metal interconnect structure (62, 64), and a metal trench structure (72, 74, 76) may be formed above the top semiconductor layer 10. In one embodiment, the semiconductor device may include a resistive memory array 302 formed on a first portion of the top semiconductor layer 10 and located entirely within the first device region 300 in a plan view. In addition, the semiconductor device may include a peripheral device 402 formed in the second device region 400.

[0051] In one embodiment, the resistive memory array 302 may include a two-dimensional array of resistive memory devices 30. Each resistive memory device 30 may be a repeating unit that repeats along two different horizontal directions. In one embodiment, the shallow trench isolation grid 12 may include an M x N rectangular grid of openings therein. Each of M and N may be an integer greater than 1. For example, each of M and N may be independently between 2 and 2 16 The resistance memory array 302 may include an M×N rectangular array of resistance memory devices 30. Each resistance memory device 30 may be a repeating unit RU within the resistance memory array 302.

[0052] In one embodiment, each resistance memory device 30 may include an access transistor 310 and a resistance memory cell 360. The access transistor 310 may include a source region 332, a drain region 338, a gate stack including a gate dielectric 352, a gate electrode 354, a gate cap dielectric 358, and a dielectric gate spacer 356. The source region 332 may include a combination of a source extension region and a deep source region. The drain region 338 may include a combination of a drain extension region and a deep drain region. Each resistance memory cell 360 includes a first electrode 364 (which may be a bottom electrode), a resistance memory element 365 including a material providing at least two different resistance states, and a second electrode 366 (which may be a top electrode). The first electrode 364 may include a first inert metal material, such as TiN, TaN, WN, and / or MoN. The second electrode 366 may include a second inert metal material, such as TiN, TaN, WN, and / or MoN.

[0053] The material of each resistive memory element 365 that provides at least two different resistance states is referred to herein as a resistive memory material. In general, the resistive memory material may be any type of resistive memory material known in the art. In one embodiment, the resistive memory material may include a metal oxide material that forms a filament, which is capable of providing higher conductivity when a conductive filament is formed therein (e.g., hafnium oxide, titanium oxide, niobium pentoxide, germanium telluride, silver sulfate, zinc oxide, vanadium oxide, tantalum oxide, zirconium oxide, etc.). In one embodiment, the resistive memory material may include a phase change memory material containing chalcogenide glass (e.g., an alloy of germanium, antimony, and tellurium, and optional additional additives). In one embodiment, the resistive memory material may include a conductive bridge forming material, in which a conductive bridge may be formed or broken (e.g., silver, copper, silver sulfide, mixed ion electronic conductor material (e.g., yttria stabilized zirconium oxide), etc.). In one embodiment, the resistive memory material may include an organic polymer material that can provide at least two different resistance states. In one embodiment, the resistive memory material may include a perovskite-based material that can provide at least two different resistance states. In one embodiment, the resistive memory material may include a two-dimensional material, such as molybdenum disulfide (MoS2), which can provide at least two different resistance states. In one embodiment, the resistive memory material may include an organic-inorganic hybrid resistive memory material that can provide at least two different resistance states. In one embodiment, the resistive memory material may include a rare earth oxide resistive memory material that can provide at least two different resistance states.

[0054] The peripheral devices 402 may include various types of semiconductor devices, and may include field effect transistors, diodes, resistors, capacitors, inductors, etc. The peripheral devices 402 may include word line drivers, bit line drivers, and sense amplifiers for the resistive memory array 302. In addition, the peripheral devices 402 may include input / output drivers, data buffers, and additional circuit components for supporting the operation of the resistive memory array 302.

[0055] Various metal interconnect structures can be formed in the dielectric material layer. Various metal interconnect structures are referred to herein as lower-level metal interconnect structures (62, 64), and the dielectric material layer is referred to herein as lower-level dielectric material layer 50. The lower-level metal interconnect structures (62, 64) include metal via structures 62 and metal line structures 64.

[0056] For example, the metal via structure 62 may include a source contact via structure 62S, a drain contact via structure 62D, a gate contact via structure 62G, a first via level via structure 621, a second via level via structure 622, a third via level via structure 623, a fourth via level via structure 624, a fifth via level via structure 625, a sixth via level via structure 626, a seventh via level via structure 627, etc. In addition, the metal via structure 62 may include a bottom electrode contact via structure 362 contacting a bottom surface of the first electrode 364 (which is a bottom electrode), and a top electrode contact via structure 368 contacting a top surface of the second electrode 366 (which is a top electrode).

[0057] The metal line structure 64 may include a first line-level metal line 641, a second line-level metal line 642, a third line-level metal line 643, a fourth line-level metal line 644, a fifth line-level metal line 645, a sixth line-level metal line which may include a bit line 64B, a seventh line-level metal line 647, an eighth line-level metal line 648, and the like. A subset of the metal line structure 64 may include a source line 64S, which in the example shown may include a subset of the second line-level metal line 642. The lower level metal interconnect structure (62, 64) provides functional electrical connections to and from various components of the resistive memory array 302, and to and from various components of the peripheral device 402. The peripheral devices 402 connected by the lower level metal interconnect structure (62, 64) constitute peripheral circuits configured to operate the resistive memory array 302.

[0058] In summary, an array of access transistors 310 may be formed such that an active region of the array of access transistors 310 is formed within a first portion of the top semiconductor layer 10. A shallow trench isolation grid 12 may be formed within an upper region of the first portion of the top semiconductor layer 10 and may laterally surround the active regions of the access transistors 310 of the resistance memory array 302. Each access transistor 310 may include a drain region 338 electrically connected to a first electrode 364 of a corresponding resistance memory cell 360 within each resistance memory device 30. A peripheral device 402 may be formed in the second device region 400. The peripheral device 402 may be configured to control the operation of the resistance memory devices 30 in the resistance memory array 302. The second device region 400 may be completely outside the first device region 300 and outside the outer periphery of the first deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)}. A first metal interconnect structure (which is a first subset of lower-level metal interconnect structures (62, 64)) formed within a first dielectric material layer (e.g., lower-level dielectric material layer 50) may be formed above the array of access transistors 310 such that the first metal interconnect structure is electrically connected to the array of access transistors 310.

[0059] According to one aspect of the present invention, at least one metal moat structure (72, 74, 76) may be formed in the lower-level dielectric material layer 50. Each metal moat structure (72, 74, 76) vertically extends from a horizontal plane including the top surface of the top semiconductor layer 10 to the uppermost surface of the lower-level dielectric material layer 50. Typically, the uppermost surface of the lower-level dielectric material layer 50 is located above a horizontal plane including the uppermost surface of the resistance memory cell 360. Therefore, each metal moat structure (72, 74, or 76) vertically extends at least from the top surface of the SOI substrate 5 to a horizontal plane covering the uppermost surface of the resistance memory cell 360 within the resistance memory array 302.

[0060] Each metal moat structure (72, 74, 76) may include a vertically alternating sequence of via-level metal wall structures 66 and line-level metal wall structures 68. Each via-level metal wall structure 66 may be formed at the same level as a corresponding subset of the metal via structures 62, and thus, equidistant from a horizontal plane including a top surface of the top semiconductor layer 10 as a corresponding subset of the metal via structures 62. Each line-level metal wall structure 68 may be formed at the same level as a corresponding subset of the metal line structures 64, and thus, equidistant from a horizontal plane including a top surface of the top semiconductor layer 10 as a corresponding subset of the metal line structures 64. Each of the via-level metal wall structures 66 and the line-level metal wall structures 68 may have a corresponding tubular configuration, such that in a plan view, the entirety of the via-level metal wall structures 66 and the line-level metal wall structures 68 are formed outside the area of ​​the first device region 300. In addition, each of the via-level metal wall structures 66 and the line-level metal wall structures 68 may not have any lateral openings therethrough. Thus, each of the via-level metal wall structure 66 and the line-level metal wall structure 68 may be topologically homeomorphic to a torus.

[0061] In one embodiment, the at least one metal moat structure (72, 74, 76) may include a plurality of metal moat structures (72, 74, 76). For example, the at least one metal moat structure (72, 74, 76) may include an inner metal moat structure 72 formed on the top surface of the inner non-insulating moat structure 27, an intermediate metal moat structure 74 formed on the top surface of the single crystalline semiconductor moat structure 10M, and an outer metal moat structure 76 formed on the top surface of the outer non-insulating moat structure 28. In one embodiment, the entire bottom surface of the inner metal moat structure 72 may be in contact with the top surface of the inner non-insulating moat structure 27. In one embodiment, the entire bottom surface of the outer metal moat structure 76 may be in contact with the top surface of the outer non-insulating moat structure 28. In one embodiment, a portion of the top surface of the single crystalline semiconductor moat structure 10M may be converted into a heavily doped single crystalline semiconductor well 13, providing a doping resistance greater than 1.0×10 5 In this embodiment, the bottom surface of the intermediate metal moat structure 74 may contact the top surface of the heavily doped single crystalline semiconductor well 13 which is a part of the top semiconductor layer 10 .

[0062] According to one aspect of the present invention, at least one metal trench structure (72, 74, 76) is used as a structure for signal shielding against external electromagnetic signals at the level of the lower-level metal interconnect structure (62, 64). According to one aspect of the present invention, at least one metal trench structure (72, 74, 76) includes a plurality of metal trench structures (72, 74, 76) to provide enhanced electrical isolation for the resistive memory array 302 located in the first device region 300.

[0063] Typically, the first metal moat structure (72, 74, or 76) is formed to laterally surround the resistive memory array 302. The peripheral device 402 can be formed in the second device region 400, which is completely outside the first device region 300 and outside the outermost periphery of at least one deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)}. The peripheral device 402 is configured to control the operation of the resistive memory device 30 in the resistive memory array 302.

[0064] An array of access transistors 310 may be formed in the first device region 300. A lower level metal interconnect structure (62, 64) embedded in the lower level dielectric material layer 50 may be formed. The resistance memory cells 360 may be formed on a first subset of the lower level metal interconnect structures (62, 64) formed within the first device region 300 below a horizontal plane including a bottom surface of the resistance memory cells 360. In one embodiment, each resistance memory cell 360 includes a first electrode 364, a resistance memory element 365 including a material providing at least two different resistance states, and a second electrode 366. Each access transistor 310 includes a drain region 338 electrically connected to the first electrode 364 of the resistance memory cell 360 through a corresponding subset of the lower level metal interconnect structures (62, 64). The resistance memory array 302 may be formed on a first portion of the top semiconductor layer 10 that is completely within the first device region 300 in a plan view.

[0065] The lower level metal interconnect structure (62, 64) includes a source line 64S and a bit line 64B that are formed in plan view completely within the first device region 300. The source line 64S can be electrically connected to the source regions 332 of the corresponding subset of the access transistors 310 in the resistance memory array 302, and can be located completely within the first device region 300 in plan view. The bit line 64B can be electrically connected to the second electrodes 366 of the corresponding columns of the second electrodes 366 in the resistance memory array 302, and can be located completely within the first device region 300 in plan view.

[0066] The first metal moat structure (72, 74, or 76) may laterally surround the resistance memory array 302 and may vertically extend from the top surface of the SOI substrate 5 to a horizontal plane covering the topmost surface of the resistance memory cells 360 within the resistance memory array 302. In one embodiment, the first metal moat structure (72, 74, or 76) includes a vertically alternating sequence of via-level metal wall structures 66 and line-level metal wall structures 68. The top surface of the first metal moat structure (72, 74, or 76) may be formed in a horizontal plane including the topmost surface of the lower-level dielectric material layer 50.

[0067] In one embodiment, the first metal moat structure may include an inner metal moat structure 72 or an outer metal moat structure 76. In this embodiment, the entire bottom surface of the first metal moat structure (72 or 76) may be in contact with the top surface of the first non-insulating moat structure (27 or 28). In one embodiment, the first metal moat structure may include an intermediate metal moat structure 74 or an outer metal moat structure 76. In this embodiment, the entire bottom surface of the first metal moat structure (including the outer metal moat structure 76) may be in contact with the top surface of a portion of the top semiconductor layer 10 (which may or may not include the heavily doped single crystal semiconductor well 13) located outside the first deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)}.

[0068] In one embodiment, the first deep trench isolation structure may include an outer deep trench isolation structure (28, 24I, 24O), and the first metal moat structure may include an intermediate metal moat structure 74. In this embodiment, the entire bottom surface of the first metal moat structure (including the intermediate metal moat structure 74) contacts the top surface of the portion of the top semiconductor layer 10 located within the first deep trench isolation structure (including the outer deep trench isolation structure (28, 24I, 24O)). In one embodiment, the first deep trench isolation structure may include an inner deep trench isolation structure (27, 23I, 23O), and the first metal moat structure may include an intermediate metal moat structure 74. In this embodiment, the entire bottom surface of the first metal moat structure (including the intermediate metal moat structure 74) contacts the top surface of the portion of the top semiconductor layer 10 located outside the first deep trench isolation structure (including the inner deep trench isolation structure (27, 23I, 23O)).

[0069] In one embodiment, at least one deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} may include a plurality of deep trench isolation structures {(27, 23I, 23O), (28, 24I, 24O)}. For example, multiple deep trench isolation structures {(27, 23I, 23O), (28, 24I, 24O)} may include a first deep trench isolation structure (e.g., an internal deep trench isolation structure (27, 23I, 23O)), which includes a first non-insulating trench structure (e.g., an internal non-insulating trench structure 27) that laterally surrounds a first portion of the top semiconductor layer 10 located in the first device region 300 in a plan view; and may also include a second deep trench isolation structure (e.g., an external deep trench isolation structure (28, 24I, 24O)), which includes a second non-insulating trench structure (e.g., an external non-insulating trench structure 28) that laterally surrounds the first deep trench isolation structure (including the internal deep trench isolation structure (27, 23I, 23O)) in a plan view.

[0070] Typically, the first metal moat structure (72, 74, or 76) laterally surrounds the resistor memory array 302 and extends vertically from the top surface of the SOI substrate 5 to at least a horizontal plane including the topmost surface of the resistor memory cell 360. In one embodiment, the second metal moat structure (72, 74, or 76) laterally surrounds the resistor memory array 302 and extends vertically from the top surface of the SOI substrate 5 to at least a horizontal plane. The second metal moat structure (72, 74, or 76) laterally surrounds the first metal moat structure (72, 74, or 76) or is laterally surrounded by the first metal moat structure (72, 74, or 76). In one embodiment, the third metal moat structure (72, 74, or 76) laterally surrounds the resistor memory array 302 and extends vertically from the top surface of the SOI substrate 5 to at least a horizontal plane. The third metal moat structure (72, 74, or 76) laterally surrounds the first metal moat structure (72, 74, or 76), or is laterally surrounded by the first metal moat structure (72, 74, or 76), and laterally surrounds the second metal moat structure (72, 74, or 76), or is laterally surrounded by the second metal moat structure (72, 74, or 76).

[0071] In an embodiment where a plurality of deep trench isolation structures {(27, 23I, 23O), (28, 24I, 24O)} are provided, the metal moat structure (72, 74, or 76) may contact the top surface of a deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} selected from the first deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} and the second deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)}. Alternatively, the entire bottom surface of the metal moat structure (72, 74, or 76) may contact the top surface of a portion of the top semiconductor layer 10.

[0072] refer to Figure 5 , additional metal interconnect structures and additional dielectric material layers may be formed. The additional metal interconnect structures are referred to as upper-level metal interconnect structures (82, 84), and the additional dielectric material layers are referred to as upper-level dielectric material layers 70. The upper-level metal interconnect structures (82, 84) may include metal via structures 82 and metal line structures 84.

[0073] According to one aspect of the present invention, a subset of the upper level metal interconnect structures (82, 84) extend laterally above the first metal moat structures (72, 74, or 76) and provide a conductive path between the peripheral devices 402 in the second device region 400 and the resistive memory array 302 in the first device region 300. Thus, a lateral electrical connection between the peripheral devices 402 and the resistive memory array 302 may be formed above a horizontal plane including the topmost surface of the metal moat structures (72, 74, 76).

[0074] Subsequently, a metal bump structure 88 may be formed over the upper level metal interconnect structure (82, 84). The metal bump structure 88 may include a micro-bump structure, or a controlled collapse chip connect (C4) bond pad.

[0075] refer to Figure 6 According to the second configuration of the exemplary structure of the embodiment of the present invention, the formation of the intermediate metal trench structure 74 can be omitted. Figure 5 The first configuration of the exemplary structure shown in derives from In this embodiment, the formation of the heavily doped single-crystalline semiconductor well 13 may be omitted.

[0076] refer to Figure 7 According to the third configuration of the exemplary structure of the embodiment of the present invention, the formation of the inner metal trench structure 72 can be omitted. Figure 5 A first configuration of the exemplary structure shown in FIG.

[0077] refer to Figure 8 According to a fourth configuration of the exemplary structure of an embodiment of the present invention, the formation of the outer metal trench structure 76 can be omitted. Figure 5 A first configuration of the exemplary structure shown in FIG.

[0078] refer to Fig. 9 According to a fifth configuration of the exemplary structure of an embodiment of the present invention, the outer metal trench structure 76 can be omitted, and the intermediate metal trench structure 74 can be omitted. Figure 5 The first configuration of the exemplary structure shown in derives from In this embodiment, the formation of the heavily doped single-crystalline semiconductor well 13 may be omitted.

[0079] refer to Fig.10 According to the sixth configuration of the exemplary structure of the embodiment of the present invention, the formation of the inner metal trench structure 72 and the formation of the intermediate metal trench structure 74 can be omitted. Figure 5 The first configuration of the exemplary structure shown in derives from In this embodiment, the formation of the heavily doped single-crystalline semiconductor well 13 may be omitted.

[0080] refer to Fig.11 According to the seventh configuration of the exemplary structure of the embodiment of the present invention, the formation of the inner metal moat structure 72 can be omitted, and the formation of the outer metal moat structure 76 can be omitted. Figure 5 A first configuration of the exemplary structure shown in FIG.

[0081] refer to Fig.12 According to the eighth configuration of the exemplary structure of the embodiment of the present invention, the formation of the inner deep trench isolation structure (27, 23I, 23O) can be omitted. Figure 7 The second configuration of the exemplary structure shown in is derived.

[0082] refer to Fig.13 According to the ninth configuration of the exemplary structure of the embodiment of the present invention, the formation of the outer deep trench isolation structure (28, 24I, 24O) can be omitted. Figure 8 The third configuration of the exemplary structure shown in derives.

[0083] refer to Fig.14 According to the tenth configuration of the exemplary structure of the embodiment of the present invention, the formation of the intermediate metal trench structure 74 can be omitted. Fig.13 The ninth configuration of the exemplary structure shown in derives In this embodiment, the formation of the heavily doped single-crystal semiconductor well 13 may be omitted.

[0084] refer to Fig.15 According to the eleventh configuration of the exemplary structure of the embodiment of the present invention, the formation of the inner metal trench structure 72 can be omitted. Fig.14 The tenth configuration of the exemplary structure shown in derives.

[0085] refer to Fig.16 , which shows a flow chart of steps for forming a semiconductor structure according to an embodiment of the present invention.

[0086] Reference steps 1610 and Figure 1A , Figure 1B , Figure 2A , Figure 2B ,and Figure 7-Figure 15 At least one moat trench (17, 18) can be formed through the top semiconductor layer 10 and the buried insulating layer 4 of the semiconductor-on-insulator (SOI) substrate 5. In a plan view, each of the at least one moat trench (17, 18) laterally surrounds a first portion of the top semiconductor layer 10 located in the first device region 300.

[0087] Refer to step 1620 and Figure 3A , Figure 3B ,and Figure 7-Figure 15At least one deep trench isolation structure {(27, 23I, 23O) or (28, 24I, 24O)} may be formed in at least one moat trench (17, 18).

[0088] Refer to step 1630 and Figure 4A-4C and Figure 5-Figure 15 , a resistance memory array 302 may be formed on a first portion of the top semiconductor layer 10. The resistance memory array 302 is completely formed within the first device region 300 in a plan view.

[0089] Various embodiments of the present invention can be used to provide a semiconductor structure, which includes a resistor memory array 302, which electrically shields electromagnetic noise from the outside through at least one deep trench isolation structure {(27, 23I, 23O), (28, 24I, 24O)} and / or at least one metal moat structure (72, 74, 76). At least one deep trench isolation structure {(27, 23I, 23O), (28, 24I, 24O)} and / or at least one metal moat structure (72, 74, 76), especially in combination, can provide excellent electromagnetic noise shielding from all lateral directions. Therefore, the noise resistance of the resistor memory device 30 in the resistor memory array 302 can be enhanced.

[0090] According to one aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate on an insulator, comprising a processing substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure, extending vertically through the top semiconductor layer and the buried insulating layer, and comprising: a first internal insulating pad, laterally surrounding a first portion of the top semiconductor layer located in a first device region in a plan view; a first non-insulating trench structure, laterally surrounding the first internal insulating pad; and a first external insulating pad, laterally surrounding the first non-insulating trench structure; and a resistive memory array, located on the first portion of the top semiconductor layer and completely within the first device region in a plan view.

[0091] In some embodiments, each resistive memory device within a resistive memory array includes: a resistive memory cell including: a first electrode; a resistive memory element including a material having at least two different resistance states; a second electrode; and an access transistor including a drain region electrically connected to the first electrode of the resistive memory cell.

[0092] In some embodiments, the semiconductor structure further includes a shallow trench isolation grid embedded in an upper region of the first portion of the top semiconductor layer and laterally surrounding an active region of an access transistor of the resistance memory array.

[0093] In some embodiments, the semiconductor structure further includes: a source line electrically connected to source regions of a corresponding subset of access transistors within the resistive memory array and located entirely within the first device region in plan view; and a bit line electrically connected to second electrodes of corresponding columns of second electrodes within the resistive memory array and located entirely within the first device region in plan view.

[0094] In some embodiments, the semiconductor structure further includes: a first metal moat structure laterally surrounding the resistance memory array and vertically extending from a top surface of the SOI substrate to a horizontal plane covering topmost surfaces of the resistance memory cells in the resistance memory array.

[0095] In some embodiments, the first metal moat structure includes a vertically alternating sequence of via-level metal wall structures and line-level metal via structures.

[0096] In some embodiments, the semiconductor structure further includes: a peripheral device for controlling the operation of the resistive memory devices in the resistive memory array and located in a second device region completely outside the first device region and outside the outer periphery of the first deep trench isolation structure; and an upper-level metal interconnect structure extending above the first metal trench structure and providing a conductive path between the peripheral device and the resistive memory array.

[0097] In some embodiments, the entire bottom surface of the first metal moat structure contacts the top surface of the first non-insulating moat structure.

[0098] In some embodiments, an entire bottom surface of the first metal moat structure contacts a top surface of a portion of the top semiconductor layer outside the first deep trench isolation structure.

[0099] In some embodiments, an entire bottom surface of the first metal moat structure contacts a top surface of a portion of the top semiconductor layer within the first deep trench isolation structure.

[0100] In some embodiments, the semiconductor structure further includes: a second metal moat structure laterally surrounding the resistance memory array and extending vertically from the top surface of the SOI substrate to the horizontal plane, wherein the second metal moat structure laterally surrounds the first metal moat structure or is laterally surrounded by the first metal moat structure.

[0101] According to one aspect of an embodiment of the present application, a semiconductor structure is provided, comprising: a semiconductor substrate on an insulator, comprising a processing substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure, comprising a first non-insulating moat structure laterally surrounding a first portion of the top semiconductor layer located in a first device region in a plan view; a second deep trench isolation structure, comprising a second non-insulating moat structure laterally surrounding the first deep trench isolation structure in a plan view; and a resistive memory array located on the first portion of the top semiconductor layer and completely within the first device region in a plan view.

[0102] In some embodiments, the semiconductor structure further includes: a first metal moat structure laterally surrounding the resistance memory array and vertically extending from a top surface of the semiconductor-on-insulator substrate to a horizontal plane covering topmost surfaces of the resistance memory cells in the resistance memory array.

[0103] In some embodiments, the first metal moat structure contacts a top surface of a deep trench isolation structure selected from the first deep trench isolation structure and the second deep trench isolation structure.

[0104] In some embodiments, an entire bottom surface of the first metal moat structure contacts a top surface of a portion of the top semiconductor layer.

[0105] According to another aspect of an embodiment of the present application, a method for forming a semiconductor structure is provided, the method comprising: forming at least one moat trench through a top semiconductor layer and a buried insulating layer of a semiconductor-on-insulator substrate, wherein each of the at least one moat trench laterally surrounds a first portion of the top semiconductor layer located in a first device region in a plan view; forming at least one deep trench isolation structure in the at least one moat trench; and forming a resistive memory array on the first portion of the top semiconductor layer, wherein, in a plan view, the resistive memory array is completely formed within the first device region.

[0106] In some embodiments, forming a resistive memory array includes: forming an access transistor array such that an active region of the access transistor array is formed within a first portion of a top semiconductor layer; forming a first metal interconnect structure embedded in a first dielectric material layer above the access transistor array, wherein the first metal interconnect structure is electrically connected to the access transistor array; and forming resistive memory cells on a subset of the first metal interconnect structure, wherein each resistive memory cell includes: a first electrode; a resistive memory element including a material providing at least two different resistance states; and a second electrode.

[0107] In some embodiments, the method further includes forming a shallow trench isolation grid within an upper region of the first portion of the top semiconductor layer and laterally surrounding an active area array of patterned sections of the first portion of the top semiconductor layer, wherein source and drain regions of the access transistor array are formed within the active area array.

[0108] In some embodiments, the method further includes forming a first metal moat structure laterally surrounding the resistance memory array, wherein the first metal moat structure vertically extends from a top surface of the SOI substrate to a horizontal plane covering topmost surfaces of resistance memory cells in the resistance memory array.

[0109] In some embodiments, the method also includes: forming a peripheral device in a second device region completely outside the first device region and outside the outermost periphery of at least one deep trench isolation structure, wherein the peripheral device is configured to control the operation of the resistive memory device in the resistive memory array; forming a lower-level metal interconnect structure embedded in a lower-level dielectric material layer, wherein the lower-level metal interconnect structure includes a source line and a bit line formed completely within the first device region in a plan view, wherein a top surface of the first metal moat structure is formed in a horizontal plane including the topmost surface of the lower-level dielectric material layer; and forming an upper-level metal interconnect structure embedded in an upper-level dielectric material layer, wherein a subset of the upper-level metal interconnect structure extends laterally above the first metal moat structure and provides a conductive path between the peripheral device and the resistive memory array.

[0110] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Unless otherwise explicitly disclosed herein, each embodiment described using the term "comprising" also inherently discloses that in some embodiments, the term "comprising" can be replaced with "consisting essentially of...", or replaced with the term "consisting of...". Whenever two or more elements are listed in the same paragraph in different paragraphs as an alternative, in some embodiments, the Markush group including two or more element lists can also be implicitly disclosed. Whenever the auxiliary verb "can" is used in the present disclosure to describe the formation of an element or the implementation of a processing step, embodiments in which such elements or such processing steps are not implemented are also explicitly considered, provided that the resulting device or device can provide equivalent results. Therefore, the auxiliary verb "can" applied to the formation of an element or the implementation of a processing step should also be interpreted as "can", or interpreted as "can, or can not", as long as the formation of such elements or such processing steps is omitted to provide the same result or equivalent result, and equivalent results include slightly better results and slightly worse results. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure comprising: A semiconductor-on-insulator substrate comprising a handle substrate, a buried insulating layer, and a top semiconductor layer; A first deep trench isolation structure vertically extends through the top semiconductor layer and the buried insulating layer and includes: a first inner insulating liner laterally surrounding a first portion of the top semiconductor layer in a first device region in a plan view; a first non-insulating moat structure laterally surrounding the first inner insulating liner; and a first outer insulating liner laterally surrounding the first non-insulating moat structure; and a resistive memory array located on the first portion of the top semiconductor layer and completely within the first device region in the plan view.

2. The semiconductor structure according to claim 1, wherein: Each of the resistive memory devices in the resistive memory array comprises: A resistive memory cell comprising: a first electrode; A resistive memory element comprising a material having at least two different resistance states; a second electrode; and An access transistor includes a drain region electrically connected to the first electrode of the resistance memory cell.

3. The semiconductor structure according to claim 2, further comprising: A shallow trench isolation grid is embedded in an upper region of the first portion of the top semiconductor layer and laterally surrounds active regions of the access transistors of the resistive memory array.

4. The semiconductor structure according to claim 2, further comprising: A first metal moat structure laterally surrounds the resistance memory array and vertically extends from a top surface of the semiconductor-on-insulator substrate to a horizontal plane covering the topmost surfaces of the resistance memory cells in the resistance memory array.

5. The semiconductor structure according to claim 4, wherein: The first metal moat structure includes a vertically alternating sequence of via-level metal wall structures and line-level metal wall structures.

6. The semiconductor structure according to claim 4, further comprising: a peripheral device for controlling the operation of the resistive memory devices in the resistive memory array and located in a second device region completely outside the first device region and outside an outer periphery of the first deep trench isolation structure; and An upper level metal interconnect structure extends over the first metal trench structure and provides a conductive path between the peripheral device and the resistive memory array.

7. A semiconductor structure comprising: A semiconductor-on-insulator substrate comprising a handle substrate, a buried insulating layer, and a top semiconductor layer; a first deep trench isolation structure including a first non-insulating moat structure laterally surrounding a first portion of the top semiconductor layer located in a first device region in a plan view; a second deep trench isolation structure, comprising a second non-insulating moat structure laterally surrounding the first deep trench isolation structure in the plan view; as well as A resistive memory array is located on the first portion of the top semiconductor layer and is completely located within the first device region in the plan view.

8. The semiconductor structure according to claim 7, further comprising: A first metal moat structure laterally surrounds the resistance memory array and vertically extends from a top surface of the semiconductor-on-insulator substrate to a horizontal plane covering the topmost surfaces of resistance memory cells in the resistance memory array.

9. A method for forming a semiconductor structure, the method comprising: forming at least one moat trench through a top semiconductor layer and a buried insulating layer of a semiconductor-on-insulator substrate, wherein each of the at least one moat trench laterally surrounds a first portion of the top semiconductor layer located in a first device region in plan view; forming at least one deep trench isolation structure in the at least one moat trench; and A resistive memory array is formed on the first portion of the top semiconductor layer, wherein in the plan view, the resistive memory array is completely formed within the first device region.

10. The method according to claim 9, wherein: Forming the resistive memory array includes: forming an access transistor array such that an active region of the access transistor array is formed within the first portion of the top semiconductor layer; forming a first metal interconnect structure embedded in a first dielectric material layer above the access transistor array, wherein the first metal interconnect structure is electrically connected to the access transistor array; and Resistive memory cells are formed on a subset of the first metal interconnect structures, wherein each of the resistive memory cells comprises: a first electrode; a resistive memory element comprising a material providing at least two different resistance states; and a second electrode.

Images