Semiconductor structure and forming method thereof
By forming a first media layer with a arc surface in the semiconductor structure, and forming a second semiconductor layer with the arc parts on it, the problem of cutting voltage caused by cutting -edge discharge phenomenon is solved, and the height of the semiconductor structure is realized. Skillment voltage.
Patent Information
- Application Number
- CN202410156395.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-20
- Filing Date
- 2024-02-04
- Publication Date
- 2025-01-24
AI Technical Summary
In the process of forming separate gate MOSFETs, sharp angles are often formed in the gate polysilicon, resulting in tip discharge, which in turn causes the breakdown voltage from the gate to the source to drop.
By forming the first groove on the substrate, the first media layer is formed on the bottom and side walls, and then the first half of the conductor layer is formed on the primary media layer, which removes part of the media layer and isolation. The second semiconductor layer is formed on the second semiconductor layer and the second semiconductor layer is formed to make it a curved part to avoid the formation of sharp corners.
Effectively improve the tip discharge phenomenon and maintain the high breakdown voltage of the semiconductor structure.
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Figure CN119364790A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor structure and a forming method thereof, and in particular to a semiconductor structure of a semiconductor layer with an arc portion and a forming method thereof. Background Art
[0002] With the development of technology, semiconductor devices have been widely used in various electronic devices in daily life or high precision. For example, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a medium- and low-voltage high-power component with advantages such as high breakdown voltage and low on-state resistance. It can be used in motor drive, inverter, power management, etc.
[0003] However, in the conventional process of forming a split gate (SGT) metal oxide semiconductor field effect transistor (MOSFET), sharp corners are often formed in the gate polysilicon. The sharp corners may cause leakage due to a tip discharge phenomenon, thereby reducing the gate-to-source breakdown voltage. Summary of the invention
[0004] An embodiment of the present invention proposes a semiconductor structure and a method for forming the same. Through the formation method of the embodiment of the present invention, a first dielectric layer surrounding a first semiconductor layer (e.g., source polysilicon) can have an arc surface that opens upward, so that a second semiconductor layer (e.g., gate polysilicon) subsequently formed thereon has an arc portion and is not prone to forming sharp corners, which can effectively improve the tip discharge phenomenon and thereby maintain a high breakdown voltage of the semiconductor structure.
[0005] Some embodiments of the present invention include a method for forming a semiconductor structure, and the method for forming a semiconductor structure includes the following steps. A first trench is formed in a substrate. A first dielectric layer is formed in the first trench. A first semiconductor layer is formed on the first dielectric layer. A portion of the first dielectric layer is removed to expose a portion of the side surface of the first semiconductor layer. An isolation layer is formed on the first dielectric layer and the first semiconductor layer. A portion of the isolation layer is removed to expose a portion of the surface of the first dielectric layer. A portion of the top of the first dielectric layer is removed through the portion of the surface exposed by the first dielectric layer to form a second trench. The isolation layer is removed. A second dielectric layer is formed on the first semiconductor layer. A second semiconductor layer is formed on the first dielectric layer and the second dielectric layer.
[0006] Some embodiments of the present invention include a semiconductor structure, the semiconductor structure includes a substrate and a first dielectric layer, the substrate has a first trench, and the first dielectric layer is disposed on the bottom of the first trench and extends to a portion of the sidewall of the first trench. The semiconductor structure also includes a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is disposed on the first dielectric layer, and the second semiconductor layer is disposed in the remaining space of the first trench. A portion of the second semiconductor layer is located between the first semiconductor layer and the sidewall of the first trench and has an arc portion. The semiconductor structure further includes a second dielectric layer, and the second dielectric layer is disposed between the first semiconductor layer and the second semiconductor layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] The following will be described in detail with reference to the accompanying drawings. It should be noted that the various characteristic components are not drawn to scale and are only used for illustration. In fact, the size of the components may be enlarged or reduced to clearly show the technical features of the embodiments of the present invention.
[0008] Figures 1 to 7 are partial cross-sectional views illustrating various stages of forming a semiconductor structure according to some embodiments of the present invention.
[0009] Figure 8 FIG. 4 is a partial cross-sectional view of a transistor according to some embodiments of the present invention.
[0010] Reference numerals:
[0011] 1: Transistor
[0012] 100:Semiconductor structure
[0013] 10:Substrate
[0014] 10S: Partial surface
[0015] 10T: Top surface
[0016] 12: First semiconductor layer
[0017] 12S: Part of the side surface
[0018] 12T: Partial surface
[0019] 14: Second semiconductor layer
[0020] 14a: arc part
[0021] 16: Bottom substrate
[0022] 17: Body layer
[0023] 18: Block layer
[0024] 19:Heavily doped area
[0025] 20: First dielectric layer
[0026] 22,24: Temporary dielectric layer
[0027] 26: Barrier layer
[0028] 28: Second dielectric layer
[0029] 29: Dielectric layer
[0030] 30: Insulation layer
[0031] 41,43:Metal layer
[0032] g: Gap
[0033] T1: First groove
[0034] T2: Second groove DETAILED DESCRIPTION
[0035] The following disclosure provides many different embodiments or examples to implement the different features of the present invention. The following disclosure describes specific examples of each component and its arrangement to simplify the description. Of course, these specific examples are not intended to be limiting. For example, if an embodiment of the present invention describes that a first characteristic component is formed on or above a second characteristic component, it means that it may include an embodiment in which the first characteristic component and the second characteristic component are in direct contact, and may also include an embodiment in which other characteristic components are formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact.
[0036] It should be understood that additional operating steps may be implemented before, during or after the method, and in other embodiments of the method, some operating steps may be replaced or omitted.
[0037] In addition, spatially related terms may be used, such as "under", "below", "down", "over", "above", "upper" and similar terms. These spatially related terms are used to facilitate the description of the relationship between one (or some) elements or features and another (or some) elements or features in the drawings. These spatially related terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially related adjectives used therein will also be interpreted according to the orientation after the rotation.
[0038] In the specification, the terms "about", "approximately", and "substantially" generally mean within 20%, within 10%, within 5%, within 3%, within 2%, within 1%, or within 0.5% of a given value or range. The numbers given here are approximate numbers, that is, in the absence of specific descriptions of "about", "approximately", and "substantially", the meanings of "about", "approximately", and "substantially" can still be implied.
[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art in this disclosure. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.
[0040] The different embodiments disclosed below may repeatedly use the same reference symbols and / or marks. These repetitions are for the purpose of simplicity and clarity, and are not intended to limit the specific relationship between the different embodiments and / or structures discussed.
[0041] Figures 1 to 7 1 is a partial cross-sectional view illustrating various stages of forming a semiconductor structure 100 according to some embodiments of the present invention. It should be noted that, for the sake of simplicity, Figures 1 to 7 Some components of the semiconductor structure 100 have been omitted.
[0042] Reference Figure 1 In some embodiments, a first trench T1 is formed in the substrate 10. For example, the substrate 10 may include a bulk semiconductor substrate or a composite substrate formed of different materials, and the substrate 10 may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 10 may include a semiconductor substrate (e.g., a silicon substrate, a silicon germanium substrate, a silicon carbide substrate), an aluminum nitride substrate, a sapphire substrate, a similar material, or a combination thereof. The substrate 10 may also include a semiconductor-on-insulator (SOI) substrate, which is formed by disposing a semiconductor material (e.g., silicon) on an insulating layer.
[0043] In addition, the substrate 10 may include various p-type doped regions and / or n-type doped regions (not shown) formed by, for example, ion implantation and / or diffusion processes. For example, the aforementioned doped regions may be configured to form transistors, photodiodes and / or light-emitting diodes, but the present invention is not limited thereto. The substrate 10 may also include various conductive components (e.g., conductive lines or vias) (not shown). For example, the aforementioned conductive components may be formed of aluminum (Al), copper (Cu), tungsten (W), their respective alloys, other appropriate conductive materials, or combinations thereof.
[0044] A mask layer (not shown) may be disposed above the substrate 10, and then the mask layer is used as an etching mask to perform an etching process to etch the substrate 10 into the first trench T1. For example, the mask layer may include a photoresist, such as a positive photoresist or a negative photoresist. The mask layer may be, for example, a hard mask, and may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbide nitride (SiCN), similar materials, or a combination thereof. The mask layer may be a single layer or a multilayer structure.
[0045] The mask layer may be formed by a deposition process, a photolithography process, other suitable processes or a combination thereof. For example, the deposition process includes spin-on coating, chemical vapor deposition, atomic layer deposition, similar processes or a combination thereof. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask aligning, exposure, post-exposure baking (PEB), developing, rinsing, drying (e.g., hard baking), other suitable processes or a combination thereof.
[0046] The etching process may include a dry etching process, a wet etching process, or a combination thereof. For example, the dry etching process may include reactive ion etching (RIE), inductively-coupled plasma (ICP) etching, neutral beam etching (NBE), electron cyclotron resonance (ERC) etching, similar etching processes, or a combination thereof. For example, the wet etching process may use, for example, hydrofluoric acid (HF), ammonium hydroxide (NH4OH), or any suitable etchant.
[0047] Reference Figure 1 In some embodiments, a first dielectric layer 20 is formed in the first trench T1. In more detail, the first dielectric layer 20 may be formed at the bottom and sidewalls of the first trench T1 and extend outside the first trench T1 (e.g., the top surface of the substrate 10), but the embodiments of the present invention are not limited thereto. For example, the first dielectric layer 20 may include any suitable dielectric material. In some embodiments, the first dielectric layer 20 includes an oxide (e.g., silicon oxide). In addition, the first dielectric layer 20 may be formed by a deposition process (e.g., a chemical vapor deposition process, an atomic layer deposition process, a spin coating process, a similar deposition process, or a combination thereof), but the embodiments of the present invention are not limited thereto.
[0048] Reference Figure 1 In some embodiments, a first semiconductor layer 12 is formed on the first dielectric layer 20. In more detail, the first semiconductor layer 12 may be filled into the first trench T1 and into the space not occupied by the first dielectric layer 20. In the present embodiment, the first semiconductor layer 12 is completely located in the first trench T1. For example, a semiconductor material (e.g., polysilicon) may be formed in the first trench T1 by a deposition process, and then a portion of the semiconductor material may be removed by an etching process so that the height of the first semiconductor layer 12 reaches a predetermined position. Examples of the deposition process and the etching process are described above and will not be repeated here, but the embodiments of the present invention are not limited thereto.
[0049] Reference Figure 2 In some embodiments, a portion of the first dielectric layer 20 is removed to expose a portion of the side surface 12S of the first semiconductor layer 12. In other words, the top surface of the remaining first dielectric layer 20 is lower than the top surface of the first semiconductor layer 12. In some embodiments, a portion of the first dielectric layer 20 is removed by a wet etching process. Figure 2As shown, after a portion of the first dielectric layer 20 is removed, the remaining first dielectric layer 20 may have an inclined top surface, but the embodiment of the present invention is not limited thereto.
[0050] Reference Figure 3 In some embodiments, a temporary dielectric layer 22 is formed on the top surface 10T of the substrate 10 and the partial surface 10S of the substrate 10 accommodating the first trench T1, and a temporary dielectric layer 24 is formed on the top surface and the exposed partial side surface 12S of the first semiconductor layer 12. For example, an oxidation process may be performed on the top surface 10T of the substrate 10 and the partial surface 10S of the substrate 10 accommodating the first trench T1 to form the temporary dielectric layer 22, and an oxidation process may be performed on the top surface and the exposed partial side surface 12S of the first semiconductor layer 12 to form the temporary dielectric layer 24, but the embodiments of the present invention are not limited thereto.
[0051] Next, refer to Figure 3 In some embodiments, an isolation layer 30 is formed on the first dielectric layer 20 and the first semiconductor layer 12. Figure 3 As shown, in the present embodiment, the isolation layer 30 is disposed on the partial surface 10S of the substrate 10 accommodating the first trench T1 and the partial side surface 12S exposed by the first semiconductor layer 12 (i.e., on the temporary dielectric layer 22, the first dielectric layer 20 and the temporary dielectric layer 24), and the isolation layer 30 forms a gap g. The gap g may substantially correspond to a position close to the center of the top of the first dielectric layer 20. In some embodiments, the isolation layer 30 and the first dielectric layer 20 have an etching selectivity. In the present embodiment, the first dielectric layer 20 includes an oxide (e.g., silicon oxide), and the isolation layer 30 includes a nitride (e.g., silicon nitride), but the embodiment of the present invention is not limited thereto.
[0052] Reference Figure 4 In some embodiments, a portion of the insulating layer 30 is removed to expose a portion of the surface 12T of the first dielectric layer 20. Figure 3 and Figure 4 As shown, in this embodiment, when a portion of the isolation layer 30 is removed, the isolation layer 30 at the bottom of the gap g is removed to expose a portion of the surface 12T of the first dielectric layer. Since the isolation layer 30 and the first dielectric layer 20 have etching selectivity, when a portion of the isolation layer 30 is removed, the first dielectric layer 20 is substantially not removed.
[0053] Reference Figure 5In some embodiments, a portion of the top of the first dielectric layer 20 is removed through the exposed partial surface 12T of the first dielectric layer 20 to form a second trench T2. Specifically, a portion of the top of the first dielectric layer 20 can be removed through the gap g to form the second trench T2. Since the isolation layer 30 and the first dielectric layer 20 have etching selectivity, when a portion of the top of the first dielectric layer 20 is removed, the isolation layer 30 will not be substantially removed. For example, the second trench T2 can be formed by a wet etching process. In some embodiments, the second trench T2 is formed by a buffered oxide etch (BOE) process. As Figure 5 As shown, in this embodiment, the second trench T2 has a bottom in the shape of a circular arc.
[0054] Reference Figure 6 In some embodiments, the isolation layer 30 is removed. For example, the isolation layer 30 may be silicon nitride, which may be removed by hot phosphoric acid, but the present invention is not limited thereto. Figure 6 As shown, in some embodiments, after the isolation layer 30 is removed, the temporary dielectric layer 22 and the temporary dielectric layer 24 are also removed.
[0055] Reference Figure 7 In some embodiments, a second dielectric layer 28 is formed on the first semiconductor layer 12. In this embodiment, the second dielectric layer 28 includes an oxide (e.g., silicon oxide). For example, an oxidation process may be performed on the exposed surface of the first semiconductor layer 12 to form the second dielectric layer 28, but the embodiment of the present invention is not limited thereto. Figure 7 As shown, in some embodiments, a barrier layer 26 is formed on the top surface 10T of the substrate 10 and the partial surface 10S of the substrate 10 accommodating the first trench T1. In this embodiment, the barrier layer 26 includes an oxide (e.g., silicon oxide). Similarly, an oxidation process may be performed on the top surface 10T of the substrate 10 and the partial surface 10S of the substrate 10 accommodating the first trench T1 to form the barrier layer 26, but the embodiment of the present invention is not limited thereto.
[0056] Next, refer to Figure 7 In some embodiments, a second semiconductor layer 14 is formed on the first dielectric layer 20 and the second dielectric layer 28 to form the semiconductor structure 100. Specifically, the second semiconductor layer 14 can fill the space in the first trench T1 except the first dielectric layer 20, the second dielectric layer 28 and the barrier layer 26. Figure 7 As shown, in some embodiments, the second semiconductor layer 14 has an arc-shaped portion 14a where it contacts the first dielectric layer 20. The arc-shaped portion 14a is formed because the second semiconductor layer 14 also fills the second trench T2.
[0057] Figure 7 As shown, in some embodiments, the semiconductor structure 100 includes a substrate 10 and a first dielectric layer 20, the substrate 10 has a first trench T1, and the first dielectric layer 20 is disposed on the bottom of the first trench T1 and extends to a portion of the sidewall of the first trench T1. The semiconductor structure 100 also includes a first semiconductor layer 12 and a second semiconductor layer 14, the first semiconductor layer 12 is disposed on the first dielectric layer 20, and the second semiconductor layer 14 is disposed in the remaining space of the first trench T1. A portion of the second semiconductor layer 14 is located between the first semiconductor layer 12 and the sidewall of the first trench T1 and has an arc portion 14a. The semiconductor structure 100 further includes a second dielectric layer 28, and the second dielectric layer 28 is disposed between the first semiconductor layer 12 and the second semiconductor layer 14. In addition, in some embodiments, the semiconductor structure 100 includes a barrier layer 26, and the barrier layer 26 is disposed between the substrate 10 and the second semiconductor layer 14.
[0058] like Figure 7 As shown, in some embodiments, the first dielectric layer 20 surrounding the first semiconductor layer 12 (e.g., source polysilicon) has an arc surface that opens upward, so that the second semiconductor layer 14 (e.g., gate polysilicon) subsequently formed thereon has an arc portion and is not easy to form sharp corners, which can effectively improve the tip discharge phenomenon and maintain a high breakdown voltage of the semiconductor structure.
[0059] Figure 8 FIG. 1 is a partial cross-sectional view of a transistor 1 according to some embodiments of the present invention. For example, the transistor 1 may include Figure 7 All or at least part of the semiconductor structure 100 shown, for example, the first semiconductor layer 12 can be regarded as the source of the transistor 1, and the second semiconductor layer 14 can be regarded as the gate of the transistor 1, but the embodiment of the present invention is not limited to this. Similarly, for simplicity, Figure 8 Some components of the semiconductor structure 100 have been omitted.
[0060] Reference Figure 8 , the substrate 10 may be, for example, an epitaxial layer of the transistor 1, which may be a semiconductor epitaxial layer doped with n-type impurities. In some embodiments, the transistor 1 includes a bottom substrate 16, which is disposed on the bottom of the substrate 10. For example, the bottom substrate 16 may be a semiconductor layer doped with n-type impurities at a higher concentration. The substrate 10 and the bottom substrate 16 may be regarded as the drain of the transistor 1.
[0061] In some embodiments, the transistor 1 also includes a backside metal layer 41, which is disposed on the bottom of the base substrate 16. The metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), similar materials, alloys thereof, or combinations thereof, but the embodiments of the present invention are not limited thereto.
[0062] like Figure 8 As shown, in some embodiments, the transistor 1 further comprises a body layer 17, which is disposed on the substrate 10. In addition, the body layer 17 is substantially adjacent to the second semiconductor layer 14. For example, the body layer 17 can be a semiconductor layer doped with p-type impurities. The body layer 17 can be regarded as a well region of the transistor 1. In addition, in some embodiments, the transistor 1 comprises a block layer 18, which is (at least partially) embedded in the body layer 17. For example, the block layer 18 can be a semiconductor layer doped with p-type impurities at a higher concentration.
[0063] In some embodiments, the transistor 1 also includes a heavily doped region 19 disposed on the body layer. For example, the heavily doped region 19 may be a semiconductor layer doped with n-type impurities at a higher concentration. The heavily doped region 19 may be regarded as a source of the transistor 1 .
[0064] In some embodiments, the transistor 1 further includes a metal layer 43, which is disposed above the heavily doped region 19 and is electrically connected to the bulk layer 18 through a conductive contact 45. In addition, in some embodiments, the transistor 1 includes a dielectric layer 29, which is disposed between the metal layer 43 and the heavily doped region 19. The conductive contact 45 passes through the dielectric layer 29, the barrier layer 26, and the heavily doped region 19 to contact the bulk layer 18.
[0065] The above summarizes the components of multiple embodiments so that the technical personnel in the technical field to which the present invention belongs can better understand the viewpoints of the embodiments of the present invention. The technical personnel in the technical field to which the present invention belongs should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments introduced herein. The technical personnel in the technical field to which the present invention belongs should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and replacements without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope defined by the attached claims. In addition, although the present invention has been disclosed as above with several preferred embodiments, it is not intended to limit the present invention.
[0066] References throughout this specification to features, advantages, or similar language do not imply that all features and advantages that may be realized using the present invention should or may be realized in any single embodiment of the present invention. Conversely, language referring to features and advantages is understood to mean that a particular feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of features and advantages and similar language throughout this specification may, but do not necessarily, represent the same embodiment.
[0067] Furthermore, in one or more embodiments, the described features, advantages, and characteristics of the present invention may be combined in any suitable manner. Based on the description herein, those skilled in the relevant art will appreciate that the present invention may be implemented without one or more of the specific features or advantages of a particular embodiment. In other cases, additional features and advantages may be identified in certain embodiments that may not be present in all embodiments of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that: include: forming a first trench in a substrate; forming a first dielectric layer in the first trench; forming a first semiconductor layer on the first dielectric layer; removing a portion of the first dielectric layer to expose a portion of the side surface of the first semiconductor layer; forming an isolation layer on the first dielectric layer and the first semiconductor layer; removing a portion of the insulating layer to expose a portion of the surface of the first dielectric layer; Removing a portion of the top of the first dielectric layer through the portion of the surface exposed by the first dielectric layer to form a second trench; removing the insulating layer; forming a second dielectric layer on the first semiconductor layer; as well as A second semiconductor layer is formed on the first dielectric layer and the second dielectric layer.
2. The method for forming a semiconductor structure according to claim 1, wherein: The isolation layer is arranged on the partial surface of the substrate accommodating the first groove and the partial side surface of the first semiconductor layer exposed, and the isolation layer forms a gap.
3. The method for forming a semiconductor structure according to claim 2, wherein: When a portion of the isolation layer is removed, the isolation layer at the bottom of the gap is removed to expose the portion of the surface of the first dielectric layer.
4. The method for forming a semiconductor structure according to claim 1, wherein: The isolation layer and the first dielectric layer have etching selectivity.
5. The method for forming a semiconductor structure according to claim 1, wherein: The second groove has a bottom in the shape of a circular arc.
6. The method for forming a semiconductor structure according to claim 1, wherein: The second semiconductor layer has an arc-shaped portion at a location where it contacts the first dielectric layer.
7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the second semiconductor layer, a barrier layer is formed on the top surface of the substrate and a portion of the surface of the substrate accommodating the first trench.
8. The method for forming a semiconductor structure according to claim 1, wherein: The first dielectric layer and the second dielectric layer include oxide, and the isolation layer includes nitride.
9. The method for forming a semiconductor structure according to claim 8, wherein: The second trench is formed by a buffered oxide etching process.
10. A semiconductor structure, characterized in that: include: A substrate having a first groove; a first dielectric layer disposed on the bottom of the first trench and extending onto a portion of the sidewall of the first trench; a first semiconductor layer disposed on the first dielectric layer; A second semiconductor layer is disposed in the remaining space of the first trench, wherein a portion of the second semiconductor layer is located between the first semiconductor layer and the sidewall of the first trench and has an arc-shaped portion; as well as A second dielectric layer is disposed between the first semiconductor layer and the second semiconductor layer.
11. The semiconductor structure according to claim 10, characterized in that Also includes: A barrier layer is disposed between the substrate and the second semiconductor layer.
12. The semiconductor structure according to claim 11, wherein: The first dielectric layer, the second dielectric layer and the barrier layer include oxide.