Preparation method of semiconductor structure and semiconductor structure
By forming a method of forming a quarantine layer and target contact holes in the semiconductor structure, the problem of leakage current in the long -opening groove -type field effect crystal tube in the turning state is solved. Press.
Patent Information
- Application Number
- CN202411487403.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-01-24
AI Technical Summary
The normally open trench junction field effect transistor has a large leakage current in the off state, resulting in increased power consumption and reduced device stability and reliability.
Effective isolation between conductive structures is achieved by forming mesa structures spaced apart along the first direction on the substrate, forming first isolation layers and second isolation layers respectively, and removing part of the isolation material layer to form target contact holes.
Significantly reduces leakage current, increases device voltage resistance, and improves performance and reliability in the off state.
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Figure CN119364793A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art
[0002] In semiconductor power devices, leakage current is a critical parameter. Leakage current refers to the small current that still exists when the device is turned off. This current may cause multiple negative effects.
[0003] The effect of leakage current is particularly significant for normally-on trench junction field effect transistors. Normally-on trench junction field effect transistor devices usually require a negative voltage to be applied to the gate to turn off. The negative voltage can effectively turn off the device, preventing the main current from flowing from the source to the drain, thereby achieving the off function of the switch. However, in this off state, even if the device itself is not turned on, a certain amount of leakage current will still be generated.
[0004] Therefore, how to reduce the leakage current of the device becomes an urgent problem to be solved. Summary of the invention
[0005] Based on this, an embodiment of the present application provides a method for preparing a semiconductor structure and a semiconductor structure.
[0006] According to some embodiments, the present application provides a method for preparing a semiconductor structure, the method for preparing a semiconductor structure comprising:
[0007] Providing a substrate, and forming mesa structures arranged at intervals along a first direction on the substrate, wherein the first direction is a direction parallel to the substrate, and isolation grooves are provided between adjacent mesa structures;
[0008] forming a first isolation material layer, wherein the first isolation material layer is located in the isolation trench and covers the top surface of the mesa structure;
[0009] removing a portion of the first isolation material layer to form an initial isolation material layer;
[0010] forming a second isolation material layer on the top surface of the initial isolation material layer;
[0011] A portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure are removed to form a target contact hole, and the remaining initial isolation material layer constitutes a first isolation layer, and the remaining second isolation material layer constitutes a second isolation layer.
[0012] In the method for preparing the semiconductor structure of the above embodiment, a first isolation material layer is first formed to form an initial isolation material layer, and then a second isolation material layer is formed on the top surface of the initial isolation material layer, and a portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure are removed to form a first isolation layer and a second isolation layer, and a target contact hole is formed. In this way, by forming the first isolation layer and the second isolation layer separately to form the target contact hole, the process window is large, and isolation between conductive structures can be effectively formed, which greatly reduces leakage current and improves device withstand voltage.
[0013] In some embodiments, the first isolation material layer has a first preset thickness on the top surface of the mesa structure; the initial isolation material layer has at least a second preset thickness on the top surface of the mesa structure; and / or the second isolation material layer has a third preset thickness.
[0014] In some embodiments, the first predetermined thickness ranges from 15 kÅ to 17 kÅ; the second predetermined thickness ranges from 3 kÅ to 5 kÅ; and / or the third predetermined thickness ranges from 1 kÅ to 3 kÅ.
[0015] In some embodiments, the initial isolation material layer includes a first part and a second part; removing a portion of the first isolation material layer to form an initial isolation material layer includes: removing a portion of the first isolation material layer to form an initial groove, the remaining first isolation material layer located on the side wall of the initial groove constitutes the first part, and the remaining first isolation material layer located at the bottom of the initial groove constitutes the second part; wherein the first part has a first preset thickness and the second part has a second preset thickness.
[0016] In some embodiments, a portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure are removed to form a target contact hole, including: removing a second portion of the portion of the initial isolation material layer, and removing a portion of the second isolation material layer located on the top surface of the mesa structure to form the target contact hole.
[0017] In some embodiments, a portion of the second portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure are removed simultaneously based on a one-time etching process to form a target contact hole.
[0018] In some embodiments, a substrate is provided, and mesa structures arranged at intervals along a first direction are formed on the substrate, including:
[0019] Providing a substrate and forming an epitaxial layer on the substrate;
[0020] forming buried layers spaced apart along a first direction in the epitaxial layer, wherein the top surface of the buried layers is flush with the top surface of the epitaxial layer;
[0021] forming a first doped layer, wherein the first doped layer is located on the exposed top surface of the epitaxial layer and between adjacent buried layers;
[0022] forming a gate, the gate being located on both sides of the first doped layer and on the top surface of the buried layer;
[0023] forming a first contact layer, wherein the contact layer is located between the gates and on the exposed top surface of the buried layer;
[0024] forming a second doping layer, wherein the second doping layer is located on a top surface of the first doping layer and on a top surface of the gate;
[0025] A second contact layer is formed on the top surface of the second doped layer.
[0026] In some embodiments, the target contact hole exposes at least a portion of a top surface of the second contact layer.
[0027] According to some embodiments, the present application also provides a semiconductor structure, which includes a substrate and mesa structures, target contact holes, a first isolation layer and a second isolation layer located on the substrate and arranged at intervals along a first direction; the first direction is a direction parallel to the substrate, and there are isolation grooves between adjacent mesa structures; the target contact hole is located on the top surface of the mesa structure; the first isolation layer is at least located in the isolation groove and between adjacent target contact holes; the second isolation layer is located on the top surface of the first isolation layer.
[0028] In the semiconductor structure of the above embodiment, the first isolation layer is at least located in the isolation trench and between adjacent target contact holes; the second isolation layer is located on the top surface of the first isolation layer, and the target contact hole is located on the top surface of the mesa structure. In this way, the first isolation layer and the second isolation layer are formed separately to form the target contact hole, and the process window is large, which can effectively form isolation between conductive structures, greatly reduce leakage current, and improve device withstand voltage.
[0029] In some embodiments, the semiconductor structure also includes an epitaxial layer, which is located on the substrate; the mesa structure includes a buried layer, a first doped layer, a gate, a first contact layer, a second doped layer and a second contact layer arranged at intervals along a first direction; the buried layer is located in the epitaxial layer, and the top surface of the buried layer is flush with the top surface of the epitaxial layer; the first doped layer is located on the exposed top surface of the epitaxial layer and between adjacent buried layers; the gate is located on both sides of the first doped layer and on the top surface of the buried layer; the first contact layer is located between the gates and on the exposed top surface of the buried layer; the second doped layer is located on the top surface of the first doped layer and on the top surface of the gate; the second contact layer is located on the top surface of the second doped layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided in one embodiment of the present application;
[0031] Figure 2 A schematic cross-sectional view of a structure obtained in step S10 and step S30 in a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0032] Figure 3 A schematic cross-sectional view of a structure obtained in step 50 of a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0033] Figure 4 A schematic cross-sectional view of a structure obtained in step 70 of a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0034] Figure 5 A schematic cross-sectional view of a structure obtained in step 90 of a method for preparing a semiconductor structure provided in one embodiment of the present application;
[0035] Figure 6 The curve of the leakage current of the device varies with the normal distribution number. The curve in region A is a curve of the leakage current of the structure obtained by the preparation method of a half structure provided in an embodiment of the present application varies with the normal distribution number; the curve in region B is a curve of the leakage current of the device in the related art varies with the normal distribution number.
[0036] Explanation of the accompanying drawings: 10, substrate; 11, epitaxial layer; 20, mesa structure; 21, buried layer; 22, first doped layer; 23, gate; 24, first contact layer; 25, second doped layer; 26, second contact layer; 30, isolation trench; 31, initial groove; 41, first isolation material layer; 42, initial isolation material layer; 421, first part; 422, second part; 43, second isolation material layer; 44, first isolation layer; 45, second isolation layer; 50, target contact hole. DETAILED DESCRIPTION
[0037] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.
[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.
[0039] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.
[0040] In addition, in order to clearly indicate the multiple layers and regions in the drawings, the thickness of each layer and each region in the drawings are enlarged to clearly illustrate the relative positions between the layers and the distribution of each region. When a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, the expression includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between. And, it is understood that when a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, it generally refers to the side located directly above the other part.
[0041] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.
[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0043] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.
[0044] The effect of leakage current is particularly significant for normally-on trench junction field effect transistors. Normally-on trench junction field effect transistor devices usually require a negative voltage to be applied to the gate to turn off. The negative voltage can effectively turn off the device, preventing the main current from flowing from the source to the drain, thereby achieving the off function of the switch. However, in this off state, even if the device itself is not turned on, a certain amount of leakage current will still be generated.
[0045] When a load is connected to the device, the leakage current generated in the off state may become more significant. If the leakage current is too large, it will directly lead to several problems. First, the leakage current will cause additional power consumption of the device when it is turned off. Although the device is not turned on at this time, there will still be power loss through the leakage current, affecting the energy efficiency of the overall system. Especially in high-frequency or high-power applications, the power consumption caused by leakage current may significantly affect the thermal management and stability of the device, causing performance degradation or damage. Secondly, the increase in leakage current may affect the stability and reliability of the device. Excessive leakage current will not only cause the device temperature to rise, but may also cause overheating and aging, accelerating the failure of the device.
[0046] Therefore, when designing and applying normally-open trench junction field-effect transistors, special attention must be paid to the control of leakage current. By optimizing the device structure, improving material selection, and precisely adjusting the manufacturing process, the leakage current can be effectively reduced, thereby improving the performance and reliability of the power device in the off state. This is of vital importance to improving the overall efficiency and longevity of the power management system. In traditional processes, for such devices, an isolation layer is deposited and then the contact holes are opened by etching. This process has limitations, the process window is small, and the leakage current of the formed semiconductor structure is large.
[0047] Based on this, in order to solve the above problems, an embodiment of the present application provides a method for preparing a semiconductor structure and a semiconductor structure.
[0048] See also Figure 1 The present application provides a method for preparing a semiconductor structure, which includes the following steps.
[0049] Step S10, providing a substrate, and forming mesa structures arranged at intervals along a first direction on the substrate, wherein the first direction is a direction parallel to the substrate, and isolation grooves are provided between adjacent mesa structures;
[0050] Step S30, forming a first isolation material layer, wherein the first isolation material layer is located in the isolation trench and covers the top surface of the mesa structure;
[0051] Step S50, removing part of the first isolation material layer to form an initial isolation material layer;
[0052] Step S70, forming a second isolation material layer on the top surface of the initial isolation material layer;
[0053] Step S90, removing part of the initial isolation material layer and part of the second isolation material layer located on the top surface of the mesa structure to form a target contact hole, the remaining initial isolation material layer constitutes a first isolation layer, and the remaining second isolation material layer constitutes a second isolation layer.
[0054] In the method for preparing the semiconductor structure of the above embodiment, a first isolation material layer is first formed to form an initial isolation material layer, and then a second isolation material layer is formed on the top surface of the initial isolation material layer, and a portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure are removed to form a first isolation layer and a second isolation layer, and a target contact hole is formed. In this way, by forming the first isolation layer and the second isolation layer separately to form the target contact hole, the process window is large, and isolation between conductive structures can be effectively formed, which greatly reduces leakage current and improves device withstand voltage.
[0055] In some embodiments, the first isolation material layer has a first preset thickness on the top surface of the mesa structure; the initial isolation material layer has at least a second preset thickness on the top surface of the mesa structure; and / or the second isolation material layer has a third preset thickness.
[0056] In some embodiments, the first predetermined thickness ranges from 15 kÅ to 17 kÅ; the second predetermined thickness ranges from 3 kÅ to 5 kÅ; and / or the third predetermined thickness ranges from 1 kÅ to 3 kÅ.
[0057] In some embodiments, step S10, providing a substrate, and forming mesa structures arranged at intervals along a first direction on the substrate, includes:
[0058] Step S11, providing a substrate, and forming an epitaxial layer on the substrate;
[0059] Step S12, forming buried layers arranged at intervals along a first direction in the epitaxial layer, wherein the top surface of the buried layers is flush with the top surface of the epitaxial layer;
[0060] Step S13, forming a first doped layer, wherein the first doped layer is located on the exposed top surface of the epitaxial layer and between adjacent buried layers;
[0061] Step S14, forming a gate, the gate being located on both sides of the first doped layer and on the top surface of the buried layer;
[0062] Step S15, forming a first contact layer, wherein the contact layer is located between the gates and on the exposed top surface of the buried layer;
[0063] Step S16, forming a second doping layer, wherein the second doping layer is located on a top surface of the first doping layer and on a top surface of the gate;
[0064] Step S17, forming a second contact layer on the top surface of the second doped layer.
[0065] In some embodiments, the target contact hole exposes at least a portion of a top surface of the second contact layer.
[0066] In some embodiments, the initial isolation material layer includes a first portion and a second portion; step S50, removing a portion of the first isolation material layer to form the initial isolation material layer, includes:
[0067] Step S51, remove part of the first isolation material layer to form an initial groove, the remaining first isolation material layer located on the side wall of the initial groove constitutes a first part, and the remaining first isolation material layer located at the bottom of the initial groove constitutes a second part; wherein the first part has a first preset thickness, and the second part has a second preset thickness.
[0068] In some embodiments, step S90, removing a portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure to form a target contact hole, includes:
[0069] Step S91 , removing a portion of the second portion of the initial isolation material layer, and removing a portion of the second isolation material layer located on the top surface of the mesa structure to form a target contact hole.
[0070] In some embodiments, a portion of the second portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure are removed simultaneously based on a one-time etching process to form a target contact hole.
[0071] In the above embodiments of the present disclosure, unless otherwise specified herein, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.
[0072] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiment, Figures 2 to 6 The method is described in detail.
[0073] like Figure 2 As shown, in step S10 , a substrate 10 is provided, and mesa structures 20 arranged at intervals along a first direction are formed on the substrate 10 . The first direction is a direction parallel to the substrate 10 , and isolation trenches 30 are provided between adjacent mesa structures 20 .
[0074] In some embodiments, step S10 , providing a substrate 10 , and forming mesa structures 20 arranged at intervals along a first direction on the substrate 10 , includes the following steps S11 to S17 .
[0075] Step S11, providing a substrate 10, and forming an epitaxial layer 11 on the substrate 10;
[0076] As an example, in the embodiment of the present disclosure, the substrate 10 may be made of a semiconductor material, an insulating material, a conductor material, or any combination of their material types. The substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10, or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 may be a layered substrate 10 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI), or a silicon germanium on an insulator. A person skilled in the art may select the type of substrate 10 according to the type of transistor formed on the substrate 10, so the type of substrate 10 should not limit the scope of protection of the present disclosure.
[0077] Step S12, forming buried layers 21 arranged at intervals along a first direction in the epitaxial layer 11, wherein the top surface of the buried layers 21 is flush with the top surface of the epitaxial layer 11;
[0078] For example, in step S12, the buried layer 21 can be formed by removing part of the epitaxial layer 11 and then depositing the buried layer 21. For example, the buried layer 21 can also be formed by doping a specified area of the epitaxial layer 11 so that the buried layer 21 has a preset doping type. In a specific embodiment, the buried layer 21 is a P-type doped layer.
[0079] Step S13, forming a first doped layer 22, wherein the first doped layer 22 is located on the exposed top surface of the epitaxial layer 11 and between adjacent buried layers 21;
[0080] For example, the bottom surface of the first doped layer 22 is flush with the top surface of the buried layer 21, and the sidewall of the first doped layer 22 is flush with the sidewall of the buried layer 21. It can be understood that those skilled in the art can determine the doping type and doping concentration of the first doped layer 22 according to the required device type. In a specific embodiment, the first doping is an N-type doping layer.
[0081] Step S14, forming a gate 23, wherein the gate 23 is located on both sides of the first doping layer 22 and on the top surface of the buried layer 21;
[0082] By way of example, the top surface of the gate 23 is flush with the top surface of the first doping layer 22. An isolation trench 30 is provided between the opposite gates 23 in adjacent mesa structures 20.
[0083] Illustratively, the material of the gate 23 is selected from titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten, tungsten nitride, titanium nitride, titanium nitride silicon, or a combination thereof.
[0084] Step S15, forming a first contact layer 24, the contact layer is located between the gates 23 and on the exposed top surface of the buried layer 21;
[0085] By way of example, a top surface of the first contact layer 24 is lower than a top surface of the doping layer, and the first contact layer 24 is located at the bottom of the isolation trench 30 .
[0086] By way of example, the first contact layer 24 is made of silicon oxide.
[0087] Step S16, forming a second doping layer 25, wherein the second doping layer 25 is located on the top surface of the first doping layer 22 and on the top surface of the gate 23;
[0088] For example, the sidewall of the second doping layer 25 is flush with the outer sidewall of the gate 23 covered by it. It can be understood that those skilled in the art can also determine the doping type and doping concentration of the second doping layer 25 according to the required device type. In a specific embodiment, the second doping layer is an N-type doping layer.
[0089] Step S17 , forming a second contact layer 26 on the top surface of the second doping layer 25 .
[0090] For example, the second contact layer 26 may be made of the same material as the first contact layer 24. At this time, step S15 and step S17 may be completed based on a one-time deposition process to form the first contact layer 24 and the second contact layer 26 at the same time.
[0091] like Figure 2 As shown, in step S30 , a first isolation material layer 41 is formed. The first isolation material layer 41 is located in the isolation trench 30 and covers the top surface of the mesa structure 20 .
[0092] In some embodiments, a portion of the first isolation material layer 41 located on the top surface of the mesa structure 20 has a first predetermined thickness.
[0093] In some embodiments, the first preset thickness ranges from 15 kÅ to 17 kÅ. For example, the first preset thickness ranges from 15 kÅ, 16 kÅ, or 17 kÅ, etc.
[0094] like Figure 2 and 3 As shown, step S50, a portion of the first isolation material layer 41 is removed to form an initial isolation material layer 42. In step S50, an etching process or a planarization process (chemical mechanical polishing, CMP) may be used to remove a portion of the first isolation material layer 41.
[0095] In some embodiments, the portion of the initial isolation material layer 42 located on the top surface of the mesa structure 20 has at least a second predetermined thickness;
[0096] In some embodiments, the second preset thickness ranges from 3 kÅ to 5 kÅ; for example, the second preset thickness ranges from 3 kÅ, 4 kÅ, or 5 kÅ, etc.
[0097] In some embodiments, the initial isolation material layer 42 includes a first portion 421 and a second portion 422. Step S50, removing a portion of the first isolation material layer 41 to form the initial isolation material layer 42, includes:
[0098] Step S51, remove part of the first isolation material layer 41 to form an initial groove 31, the remaining first isolation material layer 41 located on the side wall of the initial groove 31 constitutes a first part 421, and the remaining first isolation material layer 41 located at the bottom of the initial groove 31 constitutes a second part 422; wherein the first part 421 has a first preset thickness, and the second part 422 has a second preset thickness.
[0099] like Figure 4 As shown, in step S70 , a second isolation material layer 43 is formed on the top surface of the initial isolation material layer 42 .
[0100] In some embodiments, the second isolation material layer 43 has a third preset thickness. In some embodiments, the third preset thickness ranges from 1 kÅ to 3 kÅ. For example, the third preset thickness ranges from 1 kÅ, 2 kÅ, or 3 kÅ.
[0101] For example, the second isolation material layer 43 may be formed on the top surface of the initial isolation material layer 42 by chemical vapor deposition or physical vapor deposition (PVD) and other processes. The chemical vapor deposition process may include one or more of atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). For example, the second isolation material layer 43 may be formed by plasma enhanced chemical vapor deposition, which is formed by ionizing the film layer by glow discharge in a deposition chamber and then chemically reacting on the film layer to deposit the second isolation material layer 43. The plasma enhanced chemical vapor deposition method can enhance the activity of chemical vapor reaction substances through plasma activation, increase the surface reaction rate, and significantly reduce the deposition temperature through high energy ions.
[0102] In some embodiments, the initial isolation material layer 42 and the second isolation material layer 43 may be made of the same material. For example, the material of the initial isolation material layer 42 and the second isolation material layer 43 may be selected from silicon oxide, silicon nitride, silicon oxynitride or a combination thereof.
[0103] like Figure 4 and Figure 5 As shown, in step S90, part of the initial isolation material layer 42 and part of the second isolation material layer 43 located on the top surface of the mesa structure 20 are removed to form a target contact hole 50, and the remaining initial isolation material layer 42 constitutes a first isolation layer 44, and the remaining second isolation material layer 43 constitutes a second isolation layer 45.
[0104] In some embodiments, the target contact hole 50 exposes at least a portion of the top surface of the second contact layer 26 .
[0105] In some embodiments, step S90 may also include the step of coating a photoresist material layer on the surface of the second isolation material layer 43. The photoresist material layer is subjected to a series of steps such as exposure and development to form a patterned photoresist layer. The patterned photoresist layer has an opening pattern of the position and shape of the target contact hole 50. The photoresist may be a positive photoresist or a negative photoresist, and the development method may be a positive development or a negative development.
[0106] In some embodiments, step S90, removing a portion of the initial isolation material layer 42 and a portion of the second isolation material layer 43 located on the top surface of the mesa structure 20 to form the target contact hole 50, includes:
[0107] Step S91 , removing a portion of the second portion 422 of the initial isolation material layer 42 , and removing a portion of the second isolation material layer 43 located on the top surface of the mesa structure 20 , to form a target contact hole 50 .
[0108] In some embodiments, the second portion 422 of the initial isolation material layer 42 and the portion of the second isolation material layer 43 on the top surface of the mesa structure 20 are removed simultaneously based on a one-time etching process to form a target contact hole 50 .
[0109] For example, in step S90 , an etching process may be used to simultaneously etch the initial isolation material layer 42 and the second isolation material layer 43 using a patterned photoresist layer as a mask to form the target contact hole 50 .
[0110] It should be added that the "one-time etching process" mentioned in some embodiments of the present disclosure can be understood as: etching based on the pattern of the same mask plate at the same time to form multiple patterns in one etching process; it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.
[0111] Figure 6 The leakage current curves under different normal distribution numbers are shown. Figure 6 As shown in the curve of area B in the figure, the leakage current in the conventional process is relatively large. The applicant has shown through experiments that Figure 6 As shown in the curve of the A region, when the method for preparing the semiconductor structure in the above embodiment is adopted, the first isolation material layer 41 is first formed to form the initial isolation material layer 42, and then the second isolation material layer 43 is formed on the top surface of the initial isolation material layer 42, and a portion of the initial isolation material layer 42 and a portion of the second isolation material layer 43 located on the top surface of the mesa structure 20 are removed to form the first isolation layer 44 and the second isolation layer 45, and to form the target contact hole 50. In this way, by forming the first isolation layer 44 and the second isolation layer 45 respectively to form the target contact hole 50, the process window is large, and isolation between the conductive structures can be effectively formed, which greatly reduces the leakage current and improves the withstand voltage of the device.
[0112] See also Figure 5According to some embodiments, the present application also provides a semiconductor structure, which includes a substrate 10 and a mesa structure 20, a target contact hole 50, a first isolation layer 44 and a second isolation layer 45 arranged at intervals along a first direction on the substrate 10; the first direction is a direction parallel to the substrate 10, and there is an isolation groove 30 between adjacent mesa structures 20; the target contact hole 50 is located on the top surface of the mesa structure 20; the first isolation layer 44 is at least located in the isolation groove 30 and is located between adjacent target contact holes 50; the second isolation layer 45 is located on the top surface of the first isolation layer 44.
[0113] In the semiconductor structure of the above embodiment, the first isolation layer 44 is at least located in the isolation trench 30 and between adjacent target contact holes 50; the second isolation layer 45 is located on the top surface of the first isolation layer 44, and the target contact hole 50 is located on the top surface of the mesa structure 20. In this way, the first isolation layer 44 and the second isolation layer 45 are formed separately to form the target contact hole 50, and the process window is large, which can effectively form isolation between conductive structures, greatly reduce leakage current, and improve device withstand voltage.
[0114] In some embodiments, the semiconductor structure also includes an epitaxial layer 11, which is located on the substrate 10; the mesa structure 20 includes a buried layer 21, a first doped layer 22, a gate 23, a first contact layer 24, a second doped layer 25 and a second contact layer 26 arranged at intervals along a first direction; the buried layer 21 is located in the epitaxial layer 11, and the top surface of the buried layer 21 is flush with the top surface of the epitaxial layer 11; the first doped layer 22 is located on the exposed top surface of the epitaxial layer 11 and is located between adjacent buried layers 21; the gate 23 is located on both sides of the first doped layer 22 and on the top surface of the buried layer 21; the first contact layer 24 is located between the gates 23 and on the exposed top surface of the buried layer 21; the second doped layer 25 is located on the top surface of the first doped layer 22 and on the top surface of the gate 23; the second contact layer 26 is located on the top surface of the second doped layer 25.
[0115] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0116] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, and forming mesa structures arranged at intervals along a first direction on the substrate, wherein the first direction is a direction parallel to the substrate, and isolation grooves are provided between adjacent mesa structures; forming a first isolation material layer, wherein the first isolation material layer is located in the isolation trench and covers the top surface of the mesa structure; removing a portion of the first isolation material layer to form an initial isolation material layer; forming a second isolation material layer on the top surface of the initial isolation material layer; A portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure are removed to form a target contact hole, and the remaining initial isolation material layer constitutes a first isolation layer, and the remaining second isolation material layer constitutes a second isolation layer.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The portion of the first isolation material layer located on the top surface of the mesa structure has a first preset thickness; The portion of the initial isolation material layer located on the top surface of the mesa structure has at least a second preset thickness; and / or The second isolation material layer has a third preset thickness.
3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The first preset thickness ranges from 15 kÅ to 17 kÅ; The second predetermined thickness is in the range of 3 kÅ-5 kÅ; and / or The third preset thickness ranges from 1 kÅ to 3 kÅ.
4. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that: The initial isolation material layer includes a first portion and a second portion; The removing part of the first isolation material layer to form an initial isolation material layer comprises: A portion of the first isolation material layer is removed to form an initial groove, and the remaining portion of the first isolation material layer located on the sidewall of the initial groove constitutes the first portion, and the remaining portion of the first isolation material layer located at the bottom of the initial groove constitutes the second portion; wherein the first portion has a first preset thickness, and the second portion has a second preset thickness.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The removing of a portion of the initial isolation material layer and a portion of the second isolation material layer located on the top surface of the mesa structure to form a target contact hole comprises: A portion of the second portion of the initial isolation material layer is removed, and a portion of the second isolation material layer located on the top surface of the mesa structure is removed to form the target contact hole.
6. The method for preparing a semiconductor structure according to claim 5, characterized in that: Based on a one-time etching process, a portion of the second portion of the initial isolation material layer is removed simultaneously, and a portion of the second isolation material layer located on the top surface of the mesa structure is removed to form the target contact hole.
7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The method of providing a substrate and forming mesa structures arranged at intervals along a first direction on the substrate comprises: Providing a substrate, and forming an epitaxial layer on the substrate; forming buried layers arranged at intervals along a first direction in the epitaxial layer, wherein the top surface of the buried layers is flush with the top surface of the epitaxial layer; forming a first doped layer, wherein the first doped layer is located on the exposed top surface of the epitaxial layer and between adjacent buried layers; forming a gate, wherein the gate is located on both sides of the first doped layer and on the top surface of the buried layer; forming a first contact layer, wherein the contact layer is located between the gates and on the exposed top surface of the buried layer; forming a second doping layer, wherein the second doping layer is located on a top surface of the first doping layer and on a top surface of the gate; A second contact layer is formed on a top surface of the second doped layer.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The target contact hole at least exposes a portion of the top surface of the second contact layer.
9. A semiconductor structure, characterized in that: include: A substrate, and mesa structures arranged on the substrate at intervals along a first direction, wherein the first direction is a direction parallel to the substrate, and isolation grooves are provided between adjacent mesa structures; a target contact hole, located on the top surface of the mesa structure; A first isolation layer, at least located in the isolation trench and between adjacent target contact holes; The second isolation layer is located on the top surface of the first isolation layer.
10. The semiconductor structure according to claim 9, characterized in that: It also includes an epitaxial layer located on the substrate; the mesa structure includes: A buried layer arranged at intervals along a first direction, wherein the buried layer is located in the epitaxial layer, and a top surface of the buried layer is flush with a top surface of the epitaxial layer; A first doped layer, located on the exposed top surface of the epitaxial layer and between adjacent buried layers; a gate, located on both sides of the first doped layer and on a top surface of the buried layer; A first contact layer, located between the gates and on the exposed top surface of the buried layer; A second doping layer, located on a top surface of the first doping layer and on a top surface of the gate; The second contact layer is located on the top surface of the second doping layer.