SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with split gate for improving gate oxide reliability and preparation method thereof

Abstract

The invention discloses a SiC MOSFET device with a split gate for improving gate oxide reliability and a preparation method thereof, and relates to the technical field of semiconductors. In a reverse blocking working mode, the second P + region and the first N + region form a PN junction, a strong electric field can be shielded, the withstand voltage of the device is increased, and a gate-oxide electric field is reduced. And meanwhile, the P + region in the region below the P-body can reduce the risk that the corner of the P-body region is broken down, so that the gate oxide is protected, and the reliability of the device is improved. The N + conductive region, namely the second N + region, is arranged around the channel, so that the on-resistance of a current path can be reduced. By adopting the split gate mode, the overlapping area of the gate and the N-voltage-withstanding area can be reduced, so that the purpose of reducing the gate capacitance is achieved, the switching performance of the device can be improved to a certain extent, and the switching loss is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC MOSFET device with a split gate for improving gate oxygen reliability and a preparation method thereof. Background Art

[0002] As a third-generation semiconductor material, SiC material has the characteristics of wide bandgap and high breakdown field strength, which makes SiC devices more withstand voltage than Si material devices of the same power level, but its gate oxide is also more susceptible to breakdown. Since the bandgap width of SiC is three times that of Si, for the same threshold voltage, the gate oxide thickness of SiC MOSFET devices is thinner than that of SiMOSFET, so the gate oxide layer of SiC MOSFET has to withstand higher electric field strength, resulting in reduced gate oxide reliability.

[0003] Gate oxide reliability is mainly manifested by gate-source reliability and gate-drain reliability. The method to improve gate-source reliability is to perform NO annealing after the gate oxide layer is formed to reduce the interface state density. NO annealing can reduce the interface state density by more than one order of magnitude compared to before annealing. Gate-drain reliability is mainly reflected in the reverse blocking performance of the device. In the blocking state of the SiC MOSFET structure device, the P-body and the N-epitaxial layer form a space charge region to withstand the reverse voltage. The maximum electric field is concentrated at the top of the JFET region, that is, below the gate oxide. The smaller the width of the JFET region, the more obvious the pinch-off effect, the smaller the electric field strength of the gate oxide layer, and the better the reliability of the device; however, the smaller the width of the JFET region, the greater the on-resistance, which affects the on-performance of the device. Therefore, developing a SiC MOSFET structure that can both improve gate oxide reliability and reduce on-resistance is a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of the above problems, the present invention provides a SiC MOSFET device with a split gate and a preparation method thereof, which can effectively shield strong electric fields, enhance device withstand voltage, and improve gate oxide reliability without affecting on-resistance.

[0005] The technical solution of the present invention is: A method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability comprises the following steps: Step 1: epitaxially grow an N-epitaxial layer on an N+ substrate layer, and sequentially implant into the N-epitaxial layer to form a P-body region, a first N+ region, and a first P+ region; Step 2: Form a second P+ region connected to the P-body region on the top of the N-epitaxial layer by multiple Al ion implantations; Step 3, forming a second N+ region by multiple N ion implantation on the top of the second P+ region; Step 4, growing a gate oxide layer on top of the N-epitaxial layer by dry oxygen thermal oxidation method and depositing a Poly layer on the gate oxide layer; Step 5, depositing an isolation dielectric layer covering the Poly layer on the N-epitaxial layer, isolating the gate electrode and the source electrode metal; Step 6: sputter a layer of Ni metal on the first N+ region and the first P+ region as a source ohmic contact metal layer to form an ohmic contact with the first N+ region and the first P+ region; Step seven: forming a front electrode metal layer on the isolation dielectric layer and the ohmic contact alloy layer by Al metal sputtering to serve as a source electrode lead.

[0006] Specifically, the concentration range of the P-body region in step 1 is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um.

[0007] Specifically, in step 1, SiO2 is used as a mask to implant N ions into the P-body region multiple times to form the first N+ region with a concentration range of 1E18cm -2 -1E19cm -2 The injection depth is 0.4-0.8um, and RCA cleaning is performed after the injection is completed.

[0008] Specifically, in step 1, the concentration range of the first P+ region is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um.

[0009] Specifically, in step 2, the concentration range of the second P+ region is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 1-1.7um.

[0010] Specifically, in step 3, the concentration range of the second N+ region is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.2-0.4um.

[0011] Specifically, the gate oxide layer in step 4 is grown to a thickness of 40-60 nm.

[0012] Specifically, the thickness of the Poly layer in step 4 is 800 nm.

[0013] A SiC MOSFET device with a split gate for improving gate oxide reliability, comprising an N+ substrate layer, an N-epitaxial layer, a gate oxide layer, a Poly layer, an isolation dielectric layer and a front electrode metal layer arranged in sequence from bottom to top; The N-epitaxial layer is provided with: A pair of P-body regions are provided, each extending downward from the top surface of the N-epitaxial layer; A first N+ region, extending downward from the top surface of the P-body region, and having a spacing with the side surface and the bottom surface of the P-body region 3; A first P+ region extending downward from the top surface of the P-body region and connected to a side portion of the first N+ region; A second P+ region extends downward along the inner side of the P-body region to below the P-body region and wraps the inner corner of the P-body region; a second N+ region extending downward from a top of the second P+ region and connected to the P-body region; The bottom surface of the gate oxide layer is connected to the first N+ region, the P-body region and the second N+ region respectively; the Poly layer is arranged on the top surface of the gate oxide layer; An ohmic contact alloy layer is provided on the top surface of the first N+ region and the first P+ region; the ohmic contact alloy layer (11) is separated from the gate oxide layer and the Poly layer by an isolation dielectric layer.

[0014] Specifically, the bottom of the isolation dielectric layer is connected to the N-epitaxial layer, the first N+ region and the Poly layer.

[0015] The ohmic contact alloy layer is respectively located on the left and right sides of the isolation dielectric layer, and the side surfaces thereof are in contact with the isolation dielectric layer.

[0016] In the reverse blocking working mode of the present invention, the second P+ region forms a PN junction with the first N+ region, which can shield the strong electric field, increase the withstand voltage of the device, and reduce the gate oxide electric field. At the same time, the P+ region in the area below the P-body can reduce the risk of the corner of the P-body region being broken down, thereby protecting the gate oxide and improving the reliability of the device. An N+ conductive region, i.e., the second N+ region, is set around the channel to reduce the on-resistance of the current path. By adopting the form of a split gate, the overlapping area of ​​the gate and the N- withstand voltage region can be reduced, thereby achieving the purpose of reducing the gate capacitance, which can improve the switching performance of the device to a certain extent and reduce the switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the structure for preparing an N-epitaxial layer; Figure 2 It is a schematic diagram of the structure of the preparation of the P-body region; Figure 3 is a schematic diagram of the structure for preparing the first N+ region; Figure 4 is a schematic diagram of the structure for preparing the first P+ region; Figure 5 is a schematic diagram of the structure for preparing the second P+ region; Figure 6 is a schematic diagram of the structure for preparing the second N+ region; Figure 7 is a schematic diagram of the structure for preparing a gate oxide layer; Figure 8 It is a schematic diagram of the structure of preparing the Poly layer; Fig. 9 is a schematic diagram of the structure for preparing an isolation dielectric layer; Fig.10 It is a schematic diagram of the structure for preparing an ohmic contact alloy layer; Fig.11 It is a schematic diagram of the structure for preparing the front electrode metal layer; In the figure, 1 is the N+ substrate layer, 2 is the N- epitaxial layer, 3 is the P-body region, 4 is the first N+ region, 5 is the first P+ region, 6 is the second P+ region, 7 is the second N+ region, 8 is the gate oxide layer, 9 is the Poly layer, 10 is the isolation dielectric layer, 11 is the ohmic contact alloy layer, and 12 is the front electrode metal layer. DETAILED DESCRIPTION

[0018] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0019] The present invention is described below with reference to Figures 1-11; A method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability comprises the following steps: Step 1: epitaxially grow an N-epitaxial layer 2 on an N+ substrate layer 1, and sequentially implant into the N-epitaxial layer 2 to form a P-body region 3, a first N+ region 4, and a first P+ region 5; Specifically, Figure 1-2 As shown, an N-epitaxial layer 2 is formed by epitaxial growth on the N+ substrate layer 1, and a P-body region 3 is formed on the top of the N-epitaxial layer 2 by ion implantation, with a concentration range of 1E 17 cm -2 -1E 18 cm -2, the injection depth is 0.8-1.5um, such as Figure 2 As shown; like Figure 3 As shown, SiO2 is used as a mask to implant N ions into the P-body region 3 multiple times to form the first N+ region 4, with a concentration range of 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um, and RCA cleaning is performed after the injection is completed; like Figure 4 As shown, SiO2 is used as a mask, and Al ions are implanted multiple times in the P-body region 3 to form the first P+ region 5, with a concentration range of 1E 18 cm -2 -1E 19 cm -2 The injection depth is 0.4-0.8um, and the mask is removed after the injection is completed; Step 2, such as Figure 5 As shown, Al ions are implanted multiple times on the top of the N-epitaxial layer 2 to form a second P+ region 6 connected to the P-body region 3, with a concentration range of 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 1-1.7um; Step three, such as Figure 6 As shown, a second N+ region 7 is formed by multiple N ion implantations on the top of the second P+ region 6, with a concentration range of 1E 18 cm -2 -1E 19 cm -2 , the implantation depth is 0.2-0.4um; then a thin layer of graphite is deposited on the surface of the device as protection, and annealed at a high temperature of 1650℃-1690℃ for 15min to activate the implanted ions; Step 4: Figure 7 As shown, a gate oxide layer 8 is grown on the top of the N-epitaxial layer 2 by using a dry oxygen thermal oxidation method and a Poly layer 9 is deposited on the gate oxide layer 8; Specifically, the gate oxide layer 8 is grown to a thickness of 40-60 nm and is annealed in a NO atmosphere at a temperature of 1250° C. for 1 hour to improve the compactness of the gate oxide layer and reduce defects.

[0020] like Figure 8 As shown, a Poly layer 9 is deposited on the gate oxide layer 8 by LPCVD method, with a thickness of 800nm, as a gate electrode lead; Step 5: Fig. 9As shown, an isolation dielectric layer 10 covering the Poly layer 9 is deposited on the N-epitaxial layer 2 to isolate the gate electrode and the source electrode metal; Step 6: Fig.10 As shown, a layer of Ni metal is sputtered on the first N+ region 4 and the first P+ region 5 as the source ohmic contact metal layer 11, and then annealed at 1000°C for 5 minutes for alloying treatment to form an ohmic contact with the first N+ region 4 and the first P+ region 5; Step 7: Fig.11 As shown, a front electrode metal layer 12 is formed on the isolation dielectric layer 10 and the ohmic contact alloy layer 11 by Al metal sputtering to serve as a source electrode lead.

[0021] In this case, the P-body region 3, the first N+ region 4, the first P+ region 5, the second P+ region 6 and the second N+ region 7 are all at the same potential, which can not only improve the reliability of the gate oxide, but also enhance the voltage resistance and short-circuit tolerance of the device.

[0022] At the same time, the injection depth of the second P+ region 6 is greater than the injection depth of the P-body region 3 to protect the corner of the P-body region. The injection depth of the second N+ region 7 is 0.3-0.4 times the injection depth of the second P+ region 6, which can protect the gate oxide, improve the gate oxide reliability, and reduce the on-resistance of the device.

[0023] A SiC MOSFET device with a split gate for improving gate oxide reliability, comprising, from bottom to top, an N+ substrate layer 1, an N-epitaxial layer 2, a gate oxide layer 8, a Poly layer 9, an isolation dielectric layer 10 and a front electrode metal layer 12; The N-epitaxial layer 2 is provided with: A pair of P-body regions 3 are provided, each extending downward from the top surface of the N-epitaxial layer 2; A first N+ region 4 extends downward from the top surface of the P-body region 3 and is spaced apart from the side surface and the bottom surface of the P-body region 3; A first P+ region 5 extends downward from the top surface of the P-body region 3 and is connected to the side of the first N+ region 4; a gap is provided between the bottom surface of the first P+ region 5 and the bottom surface of the P-body region 3; A second P+ region 6 extends downward along the inner side of the P-body region 3 to below the P-body region 3 and wraps the inner corner of the P-body region 3; a second N+ region 7 extending downward from the top of the second P+ region 6 and connected to the P-body region 3; The bottom surface of the gate oxide layer 8 is connected to the first N+ region 4, the P-body region 3 and the second N+ region 7 respectively; the Poly layer 9 is arranged on the top surface of the gate oxide layer 8; Specifically, the gate oxide layer 8 is configured in the form of two split gates, located above the P-body 3, the first N+ region 4 and the second N+ region 7, and the bottom is in contact with the N-epitaxial layer 2; An ohmic contact alloy layer 11 is disposed on the top surfaces of the first N+ region 4 and the first P+ region 5 ; the ohmic contact alloy layer 11 is separated from the gate oxide layer 8 and the Poly layer 9 by an isolation dielectric layer 10 .

[0024] The bottom surface of the ohmic contact alloy layer 11 is connected to the first N+ region 4 and the first P+ region 5 .

[0025] The bottom of the isolation dielectric layer 10 is connected to the N-epitaxial layer 2 , the first N+ region 4 and the Poly layer 9 .

[0026] The ohmic contact alloy layer 11 is located on the left and right sides of the isolation dielectric layer 10 , respectively, and the side surfaces thereof are in contact with the isolation dielectric layer 10 .

[0027] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case may be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case should be based on the protection scope of the claims.

Claims

1. A method for preparing a SiC MOSFET device with a split gate to improve gate oxide reliability, characterized in that: The following steps are involved: Step 1: epitaxially growing an N-epitaxial layer (2) on an N+ substrate layer (1), and sequentially implanting into the N-epitaxial layer (2) to form a P-body region (3), a first N+ region (4), and a first P+ region (5); Step 2: Forming a second P+ region (6) connected to the P-body region (3) on the top of the N-epitaxial layer (2) by multiple Al ion implantation; Step 3, forming a second N+ region (7) by multiple N ion implantation on the top of the second P+ region (6); Step 4: growing a gate oxide layer (8) on the top of the N-epitaxial layer (2) by dry oxygen thermal oxidation and depositing a Poly layer (9) on the gate oxide layer (8); Step 5, depositing an isolation dielectric layer (10) covering the Poly layer (9) on the N-epitaxial layer (2) to isolate the gate electrode and the source electrode metal; Step six, sputtering a layer of Ni metal on the first N+ region (4) and the first P+ region (5) as a source ohmic contact metal layer (11) to form an ohmic contact with the first N+ region (4) and the first P+ region (5); Step seven: forming a front electrode metal layer (12) on the isolation dielectric layer (10) and the ohmic contact alloy layer (11) by means of Al metal sputtering, as a source electrode lead.

2. A method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability according to claim 1, characterized in that: The concentration range of the P-body region (3) in step 1 is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um.

3. The method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability according to claim 1, characterized in that: In step 1, SiO2 is used as a mask to implant N ions multiple times into the P-body region (3) to form the first N+ region (4) with a concentration range of 1E18cm -2 -1E19cm -2 The injection depth is 0.4-0.8um, and RCA cleaning is performed after the injection is completed.

4. The method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability according to claim 1, characterized in that: The concentration range of the first P+ region (5) in step 1 is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um.

5. The method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability according to claim 1, characterized in that: The concentration range of the second P+ region (6) in step 2 is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 1-1.7um.

6. The method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability according to claim 1, characterized in that: The concentration range of the second N+ region (7) in step 3 is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.2-0.4um.

7. The method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability according to claim 1, characterized in that: The gate oxide layer (8) in step 4 is grown to a thickness of 40-60 nm.

8. The method for preparing a SiC MOSFET device with a split gate and improved gate oxide reliability according to claim 1, characterized in that: The thickness of the Poly layer (9) in step 4 is 800 nm.

9. A SiC MOSFET device with a split gate and improved gate oxygen reliability, prepared by the method for preparing a SiC MOSFET device with a split gate and improved gate oxygen reliability according to claim 1, characterized in that: It comprises, from bottom to top, an N+ substrate layer (1), an N- epitaxial layer (2), a gate oxide layer (8), a Poly layer (9), an isolation dielectric layer (10) and a front electrode metal layer (12); The N-epitaxial layer (2) is provided with: A pair of P-body regions (3) are provided, each extending downward from the top surface of the N-epitaxial layer (2); A first N+ region (4), extending downward from the top surface of the P-body region (3), and having a spacing from the side surface and the bottom surface of the P-body region 3; a first P+ region (5), extending downward from the top surface of the P-body region (3) and connected to the side of the first N+ region (4); A second P+ region (6) extends downward along the inner side of the P-body region (3) to below the P-body region (3) and wraps around the inner corner of the P-body region (3); a second N+ region (7), extending downward from the top of the second P+ region (6) and connected to the P-body region (3); The bottom surface of the gate oxide layer (8) is respectively connected to the first N+ region (4), the P-body region (3) and the second N+ region (7); the Poly layer (9) is arranged on the top surface of the gate oxide layer (8); An ohmic contact alloy layer (11) is provided on the top surfaces of the first N+ region (4) and the first P+ region (5); the ohmic contact alloy layer (11) is separated from the gate oxide layer (8) and the Poly layer (9) by an isolation dielectric layer (10).

10. A SiC MOSFET device with split gate and improved gate oxide reliability according to claim 9, characterized in that: The bottom of the isolation dielectric layer (10) is connected to the N-epitaxial layer (2), the first N+ region (4) and the Poly layer (9); The ohmic contact alloy layer (11) is respectively located on the left and right sides of the isolation dielectric layer (10), and the side surfaces are in contact with the isolation dielectric layer (10).

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