Semiconductor structure

Abstract

A semiconductor structure includes a first nitride semiconductor layer disposed on a substrate and a second nitride semiconductor layer disposed on the first nitride semiconductor layer, wherein a carrier channel is formed at an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. The semiconductor structure further includes a gate structure, a source region, and a drain region. The gate structure is arranged on the second nitride semiconductor layer and comprises a first metal layer which forms Schottky contact with the second nitride semiconductor layer, a gate oxide layer arranged on the first metal layer, a second metal layer arranged on the gate oxide layer, a field plate arranged on the second metal layer and a gate electrode arranged on the field plate. The source region and the drain region are disposed on opposite sides of the gate structure.

Description

Technical Field

[0001] The invention relates to a semiconductor structure of a high electron mobility transistor, and in particular to a semiconductor structure of a high electron mobility transistor having stacked Schottky metal layers and a gate insulating layer. Background Art

[0002] Field effect transistors are the basic components of integrated circuits under semiconductor manufacturing technology. Currently, field effect transistors (FET) are generally based on the structure of metal-oxide-semiconductor (MOS). Metal-oxide-semiconductor field effect transistors (MOSFET) have their own characteristics that cannot be ignored, but field effect transistors based on gallium nitride (GaN) have also been proposed, and it is expected that they will gradually replace metal-oxide-semiconductor field effect transistors.

[0003] Today, several years after the GaN technology was proposed and developed, specific transistor structures have been proposed and are still being actively developed. For example, the GaN high electron mobility transistor can use the energy band characteristics between AlGaN and GaN at their junctions to produce a phenomenon called "two-dimensional electron gas" to provide a good channel layer. The two-dimensional electron gas has high conductivity, and the high bandgap characteristics of GaN can increase the breakdown voltage of the transistor.

[0004] With the needs of applications, depletion-type high electron mobility transistors have also been proposed one after another. Common structures include general depletion-type high electron mobility transistors in which the gate metal layer and AlGaN are in Schottky contact, and metal-insulator-semiconductor (MIS) high electron mobility transistors with a metal layer, an insulating layer, and a semiconductor stack between the gate metal layer and AlGaN. In terms of performance, the metal-insulator-semiconductor high electron mobility transistor has a lower leakage current than the general depletion-type high electron mobility transistor, but the general depletion-type high electron mobility transistor has a lower temperature coefficient threshold voltage than the metal-insulator-semiconductor high electron mobility transistor. Therefore, the performance of the depletion-type high electron mobility transistor still has a lot of room for improvement. Summary of the invention

[0005] The present invention proposes a semiconductor structure of a depletion-type high electron mobility transistor, which greatly reduces the leakage current of a general depletion-type high electron mobility transistor by forming a gate oxide layer on a first metal layer in Schottky contact with a nitride semiconductor layer. In addition, since the first metal layer is in Schottky contact with the nitride semiconductor layer, it is not easy for the first metal layer to capture electrons, thereby reducing the temperature coefficient of the threshold voltage of the semiconductor structure. The present invention further proposes a semiconductor structure of a depletion-type high electron mobility transistor, in which a tunneling insulating layer is formed between the first metal layer and the nitride semiconductor layer to exclude the electrons captured by the first metal layer, so as to further reduce the temperature coefficient of the threshold voltage of the semiconductor structure. In other words, the semiconductor structure of the depletion-type high electron mobility transistor proposed by the present invention can simultaneously retain the advantages of a general depletion-type high electron mobility transistor and a metal-insulating layer-semiconductor high electron mobility transistor.

[0006] In view of this, the present invention proposes a semiconductor structure, including a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a gate structure, a source region and a drain region. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer, wherein a carrier channel is formed on an interface between the first nitride semiconductor layer and the second nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer. The gate structure includes a first metal layer, a gate oxide layer, a second metal layer and a third metal layer. The first metal layer forms a Schottky contact with the second nitride semiconductor layer, and the gate oxide layer is disposed on the first metal layer. The second metal layer is disposed on the gate oxide layer. The field plate is disposed on the second metal layer. The third metal layer is disposed on the field plate and forms a gate electrode. The source region and the drain region are disposed on the second nitride semiconductor layer and located at two opposite sides of the gate structure, wherein the carrier channel extends between the source region and the drain region.

[0007] According to an embodiment of the present invention, the gate oxide layer forms a first capacitor, the interface between the first metal layer and the second nitride semiconductor layer forms a second capacitor, and the second nitride semiconductor layer forms a third capacitor. The first capacitor, the second capacitor, and the third capacitor are sequentially connected in series between the gate electrode and the carrier channel.

[0008] According to an embodiment of the present invention, the gate oxide layer is formed at a temperature not greater than 400 degrees Celsius.

[0009] According to an embodiment of the present invention, the semiconductor structure further comprises an insulating layer. The insulating layer is disposed on the second nitride semiconductor layer, wherein the first metal layer passes through the insulating layer to form the Schottky contact with the second nitride semiconductor layer.

[0010] According to an embodiment of the present invention, the insulating layer is composed of nitride.

[0011] According to one embodiment of the present invention, the source region and the drain region further include a fourth metal layer, a fifth metal layer, a sixth metal layer and a seventh metal layer. The fourth metal layer is disposed on the insulating layer and forms an ohmic contact with the second nitride semiconductor layer through the insulating layer. The fifth metal layer is disposed on the fourth metal layer and contacts the fourth metal layer to form a source electrode. The sixth metal layer is disposed on the insulating layer and forms another ohmic contact with the second nitride semiconductor layer through the insulating layer. The seventh metal layer is disposed on the sixth metal layer and contacts the sixth metal layer to form a drain electrode.

[0012] According to an embodiment of the present invention, the semiconductor structure further includes a tunneling insulating layer disposed between the second metal layer and the second nitride semiconductor.

[0013] According to an embodiment of the present invention, the material of the tunnel insulating layer includes one of aluminum oxide, silicon nitride, silicon dioxide, hafnium silicon oxide and hafnium oxide.

[0014] According to an embodiment of the present invention, the thickness of the tunneling insulating layer is less than 5 nanometers.

[0015] According to an embodiment of the present invention, the gate oxide layer forms a first capacitor, the first metal layer and the tunneling insulating layer form a fourth capacitor, and the second nitride semiconductor layer forms a third capacitor. The first capacitor, the fourth capacitor, and the third capacitor are sequentially connected in series between the gate electrode and the carrier channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A cross-sectional view showing a semiconductor structure according to an embodiment of the present invention;

[0017] Figure 2 Display according to the present invention Figure 1 Schematic diagram of a gate structure of a semiconductor structure;

[0018] Figure 3 A cross-sectional view showing a semiconductor structure according to another embodiment of the present invention; and

[0019] Figure 4 Display according to the present invention Figure 1 Schematic diagram of the gate structure of a semiconductor structure.

[0020] 100,300:Semiconductor structure

[0021] 110:Substrate

[0022] 120: first nitride semiconductor layer

[0023] 130: Second nitride semiconductor layer

[0024] 140: Insulation layer

[0025] 150: Gate structure

[0026] 151: First metal layer

[0027] 152: Gate oxide layer

[0028] 153: Second metal layer

[0029] 154: Field board

[0030] 155: The third metal layer

[0031] 156: tunneling insulating layer

[0032] 160: Source region

[0033] 161: Fourth metal layer

[0034] 162: Fifth metal layer

[0035] 170: Drain region

[0036] 171: Sixth metal layer

[0037] 172: Seventh metal layer

[0038] 180: Second insulation layer

[0039] 120A: Carrier channel

[0040] G: Gate electrode

[0041] S: Source electrode

[0042] D: Drain electrode

[0043] C1: First capacitor

[0044] C2: Second capacitor

[0045] C3: The third capacitor

[0046] C4: The fourth capacitor DETAILED DESCRIPTION

[0047] The following descriptions are examples of the present disclosure, and are intended to illustrate the general principles of the present disclosure, and should not be considered as limitations of the present disclosure, the scope of which shall be determined by the scope of the claims.

[0048] It is noteworthy that the content disclosed below can provide multiple embodiments or examples for practicing the different features of the present disclosure. The special component examples and arrangements described below are only used to simply and concisely explain the spirit of the present disclosure, and are not used to limit the scope of the present disclosure. In addition, the following description may reuse the same component symbols or words in multiple examples. However, the purpose of reuse is only to provide a simplified and clear description, and is not used to limit the relationship between multiple embodiments and / or configurations discussed below. In addition, the description of a feature described in the following description being connected to, coupled to, and / or formed on another feature, etc., can actually include multiple different embodiments, including that the multiple features are in direct contact, or that other additional features are formed between the multiple features, etc., so that the multiple features are not in direct contact.

[0049] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the device of the diagram is turned upside down, the element described on the "lower" side will become the element on the "upper" side.

[0050] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present disclosure.

[0051] Some embodiments of the present disclosure may be combined with the following Figure 1 It is also understood that the drawings of the embodiments of the present disclosure are also considered as part of the description of the embodiments of the present disclosure. It should be understood that the drawings of the embodiments of the present disclosure are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present disclosure. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present disclosure.

[0052] Here, the terms "about", "approximately" and "generally" generally mean within 20% of a given value or range, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The numbers given here are approximate numbers, that is, in the absence of specific description of "about", "approximately" or "generally", the meanings of "about", "approximately" or "generally" can still be implied.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present disclosure, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present disclosure.

[0054] The following is a detailed description of the component substrate, semiconductor device and semiconductor device manufacturing method of some embodiments of the present disclosure. It should be understood that the following description provides many different embodiments or examples for implementing different modes of some embodiments of the present disclosure. The specific components and arrangements described below are only for simple and clear description of some embodiments of the present disclosure. Of course, these are only used for example and not for limitation of the present disclosure. In addition, repeated numbers or marks may be used in different embodiments. These repetitions are only for simple and clear description of some embodiments of the present disclosure, and do not represent any correlation between the different embodiments and / or structures discussed. Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it includes the situation where the first material layer is in direct contact with the second material layer. Alternatively, there may be a situation where there are one or more other material layers in between, in which case the first material layer and the second material layer may not be in direct contact.

[0055] In some embodiments of the present disclosure, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only for the convenience of explanation and do not mean that the device described therein needs to be manufactured or operated in a specific orientation. Terms related to bonding and connection, such as "connection" and "interconnection", etc., unless otherwise defined, may refer to direct contact between two structures, or may also refer to non-direct contact between two structures, wherein other structures are disposed between the two structures. Moreover, such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed.

[0056] Embodiments of the present invention disclose embodiments of semiconductor devices, and the above embodiments may be included in an integrated circuit (IC) such as a microprocessor, a memory device and / or other devices. The above IC may also include various passive and active microelectronic devices, such as thin-film resistors, other types of capacitors such as metal-insulator-metal capacitors (MIMCAP), inductors, diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS transistors, bipolar junction transistors (BJTs), laterally diffused MOS transistors, high-power MOS transistors or other types of transistors. Those skilled in the art of the present invention will appreciate that the semiconductor device may also be used in an IC including other types of semiconductor devices.

[0057] Figure 1 A cross-sectional view of a semiconductor structure according to an embodiment of the present invention is shown. Figure 1 As shown, the semiconductor structure 100 includes a substrate 110. In some embodiments, the substrate 110 may be a bulk semiconductor substrate or a composite substrate formed of different materials, and the substrate 110 may be doped (e.g., using P-type or N-type dopants) or undoped. In some embodiments, the substrate 110 may include a semiconductor substrate, a glass substrate, or a ceramic substrate, such as a silicon substrate, a silicon germanium substrate, a silicon carbide, an aluminum nitride substrate, a sapphire substrate, a combination of the foregoing, or a similar material, but the embodiments of the present invention are not limited thereto. In some embodiments, the substrate 110 may include a semiconductor-on-insulator (SOI) substrate, which is formed by disposing a semiconductor material on an insulating layer.

[0058] like Figure 1 As shown, the semiconductor structure 100 also includes a first nitride semiconductor layer 120 and a second nitride semiconductor layer 130 formed on the first nitride semiconductor layer 120. According to one embodiment of the present invention, the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130 are material layers with different energy band gaps, and the band gap of the second nitride semiconductor layer 130 is higher than the band gap of the first nitride semiconductor layer 120.

[0059] According to some embodiments of the present invention, the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130 are composed of compounds formed by elements in Group III-V of the periodic table. However, the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130 are different from each other in composition. According to some embodiments of the present invention, the first nitride semiconductor layer 120 includes a GaN layer, and the second nitride semiconductor layer 130 includes Al x Ga 1-x GaN layer, where 0 < x ≤ 1. The first nitride semiconductor layer 120 is in direct contact with the second nitride semiconductor layer 130. Since the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130 have different band gaps, a heterojunction is formed at the interface between the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130.

[0060] The first nitride semiconductor layer 120 can be grown epitaxially by metal-organic chemical vapor deposition (MOCVD) using a gallium-containing precursor and a nitrogen-containing precursor. The gallium-containing precursor may include trimethylgallium (TMG), triethylgallium (TEG), or other suitable chemicals; the nitrogen-containing precursor includes ammonia (NH3), tertiarybutylamine (TBAm), phenyl hydrazine, or other suitable chemicals. However, the embodiments of the present invention are not limited thereto.

[0061] As Figure 1As shown, the second nitride semiconductor layer 130 is epitaxially grown on the first nitride semiconductor layer 120. The second nitride semiconductor layer 130 can be formed by a deposition process, such as metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods or a combination of the foregoing. For example, the second nitride semiconductor layer 130 can be epitaxially grown by metal organic vapor deposition (MOCVD) using an aluminum-containing precursor, a gallium-containing precursor, and a nitrogen-containing precursor. The aluminum-containing precursor includes trimethylaluminum (TMA), triethylaluminum (TEA), or other suitable chemicals; the gallium-containing precursor includes trimethylgallium (TMG), triethylgallium (TEG) or other suitable chemicals; the nitrogen-containing precursor includes ammonia (NH3), tert-butylamine (TBAm), phenyl hydrazine (phenyl hydrazine) or other suitable chemicals. However, the embodiments of the present invention are not limited thereto.

[0062] The band gap discontinuity and the piezo-electric effect between the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130 generate a carrier channel 120A having highly mobile conduction electrons near the interface between the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130. The carrier channel 120A is called a two-dimensional electron gas (2-DEG), which forms a carrier channel at the interface between the first nitride semiconductor layer 120 and the second nitride semiconductor layer 130.

[0063] According to some embodiments of the present invention, the semiconductor structure 100 may include a buffer layer ( Figure 1 The buffer layer is disposed between the substrate 110 and the first nitride semiconductor layer 120. The buffer layer is used to reduce the gap between the substrate 110 and the nitride semiconductor layer to be formed later (in the Figure 1 In the embodiment of the present invention, the buffer layer refers to the strain generated by the first nitride semiconductor layer 120. The buffer layer may be, for example, a combination of an AlN core layer and an AlGaN transition layer. The buffer layer may reduce defects caused by lattice misalignment between the substrate 110 and the nitride semiconductor layer formed later.

[0064] According to some embodiments of the present invention, Figure 1 As shown, the semiconductor structure 100 further includes an insulating layer 140, wherein the insulating layer 140 is disposed on the second nitride semiconductor layer 130. According to some embodiments of the present invention, the insulating layer 140 includes an insulating material containing nitrogen, such as silicon nitride.

[0065] According to some embodiments of the present invention, the semiconductor structure 100 further includes a gate structure 150, a source region 160, and a drain region 170, wherein the gate structure 150, the source region 160, and the drain region 170 are all formed on the insulating layer 140, and the source region 160 and the drain region 170 are respectively located on two different sides of the gate structure 150. Figure 1 As shown, the carrier channel 120A extends between the source region 160 and the drain region 170 , and the gate structure 150 controls whether the carrier channel 120A is turned on.

[0066] like Figure 1 As shown, the gate structure 150 includes a first metal layer 151, a gate oxide layer 152, a second metal layer 153, a field plate 154 and a third metal layer 155. The first metal layer 151 is formed on the insulating layer 140 and passes through the insulating layer 140 to form a Schottky contact with the second nitride semiconductor layer 130.

[0067] The gate oxide layer 152 is disposed on the first metal layer 151. According to one embodiment of the present invention, since the gate oxide layer 152 is formed on the first metal layer 151, the gate oxide layer 152 is formed in a low temperature process. According to some embodiments of the present invention, the gate oxide layer 152 is formed below 400 degrees Celsius. According to some embodiments of the present invention, the gate oxide layer is formed at about 350 degrees Celsius. According to some embodiments of the present invention, the gate oxide layer 152 is formed using plasma enhanced chemical vapor deposition (PECVD).

[0068] The second metal layer 153 is disposed on the gate oxide layer 152 and in contact with the gate oxide layer 152. The field plate 154 is disposed on the second metal layer 153 and in contact with the second metal layer 153, wherein the field plate 154 is used to reconstruct the electric field strength distribution of the channel. The third metal layer 155 is disposed on the field plate 154 and in contact with the field plate 154 to form a gate electrode G. According to some embodiments of the present invention, the second metal layer 153 is a general metal material as a gate metal, and the third metal layer 155 is an external metal gate.

[0069] According to some embodiments of the present invention, the material of the third metal layer 155 may include a conductive material, such as a metal, a metal silicide, other suitable materials, or a combination of the foregoing materials. The metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), a combination of the foregoing, an alloy of the foregoing, or a multilayer of the foregoing. However, the embodiments of the present invention are not limited thereto. The third metal layer 155 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), coating, sputtering, or other suitable techniques.

[0070] According to some embodiments of the present invention, Figure 1 As shown, the semiconductor structure 100 further includes a source region 160 and a drain region 170 . The source region 160 and the drain region 170 are disposed on the insulating layer 140 and located on opposite sides of the gate structure 150 . The carrier channel 120A extends between the source region 160 and the drain region 170 .

[0071] like Figure 1 As shown, the source region 160 includes a fourth metal layer 161 and a fifth metal layer 162. The fourth metal layer 161 is disposed on the insulating layer 140 and passes through the insulating layer 140 to form an ohmic contact with the second nitride semiconductor layer 130. The fifth metal layer 162 is disposed on the fourth metal layer 161, and the fourth metal layer 161 and the fifth metal layer 162 are in contact with each other, wherein the fifth metal layer 162 is used to form a source electrode S.

[0072] The drain region 170 includes a sixth metal layer 171 and a seventh metal layer 172. The sixth metal layer 171 is disposed on the insulating layer 140 and passes through the insulating layer 140 to form an ohmic contact with the second nitride semiconductor layer 130. The seventh metal layer 172 is disposed on the sixth metal layer 171 and contacts the sixth metal layer 171 and the seventh metal layer 172, wherein the seventh metal layer 172 is used to form a drain electrode D.

[0073] According to some embodiments of the present invention, the material of the fifth metal layer 162 and the seventh metal layer 172 may include a conductive material, such as a metal, a metal silicide, other suitable materials or a combination of the foregoing materials. The metal may include gold (Au), nickel (Ni), platinum (Pt), palladium (Pd), iridium (Ir), titanium (Ti), chromium (Cr), tungsten (W), aluminum (Al), copper (Cu), a combination of the foregoing, an alloy of the foregoing or a multilayer of the foregoing. However, the embodiments of the present invention are not limited thereto. The fifth metal layer 162 and the seventh metal layer 172 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), coating, sputtering or other suitable techniques.

[0074] like Figure 1 As shown, the semiconductor structure 100 further includes a second insulating layer 180. The second insulating layer 180 is used to electrically isolate the gate structure 150, the source region 160 and the drain region 170 from each other.

[0075] According to some embodiments of the present invention, since the first metal layer 151 and the second nitride semiconductor layer 130 form a Schottky contact, the first metal layer 151 is not easy to capture electrons, so that the semiconductor structure 100 has a smaller temperature coefficient of threshold voltage. In addition, since the semiconductor structure 100 further includes a gate oxide layer 152, it is helpful to reduce the leakage current of the Schottky contact between the first metal layer 151 and the second nitride semiconductor layer 130.

[0076] Figure 2 Display according to the present invention Figure 1 Schematic diagram of the gate structure of a semiconductor structure. Figure 2 As shown, the gate oxide layer 152 forms a first capacitor C1, the interface between the first metal layer 151 and the second nitride semiconductor layer 130 forms a second capacitor C2, the second nitride semiconductor layer 130 forms a third capacitor C3, and the first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected in series between the gate electrode G and the carrier channel 120A in sequence. When the gate electrode G receives a control voltage, the control voltage is divided by the capacitance of the first capacitor C1, the second capacitor C2 and the third capacitor C3, and a corresponding voltage is generated in the first metal layer 151, thereby controlling whether to conduct or not conduct the carrier channel 120A.

[0077] Figure 3 A cross-sectional view of a semiconductor structure according to another embodiment of the present invention is shown. Figure 3 The semiconductor structure 300 and Figure 1Compared to the semiconductor structure 100, the gate structure 150 further includes a tunneling insulating layer 156. The tunneling insulating layer 156 is disposed between the first metal layer 151 and the second nitride semiconductor layer 130 to discharge electrons trapped by the first metal layer 151, thereby reducing electrical drift. According to some embodiments of the present invention, the tunneling insulating layer 156 can reduce the temperature coefficient of the threshold voltage of the semiconductor structure 300.

[0078] According to some embodiments of the present invention, the thickness of the tunneling insulating layer 156 is not greater than 5 nanometers. According to some embodiments of the present invention, the thickness of the tunneling insulating layer 156 is between 1 nanometer and 3 nanometers. However, the embodiments of the present invention are not limited thereto. According to some embodiments of the present invention, the material of the tunneling insulating layer 156 may include a metal oxide, wherein the metal oxide may include one of aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxide (SiO2), hafnium silicon oxide (HfSiO2) and hafnium oxide (HfO2). However, the embodiments of the present invention are not limited thereto.

[0079] According to some embodiments of the present invention, since the tunneling insulating layer 156 helps to remove the electrons captured by the first metal layer 151, it helps to stabilize the electrical characteristics of the semiconductor structure 300 and further reduce the temperature coefficient of the threshold voltage of the semiconductor structure 300. In addition, since the semiconductor structure 300 also includes the gate oxide layer 152, the high leakage disadvantage of the Schottky contact between the first metal layer 151 and the second nitride semiconductor layer 130 can be significantly improved.

[0080] Figure 4 Display according to the present invention Figure 1 Schematic diagram of the gate structure of a semiconductor structure. Figure 4 As shown, the gate oxide layer 152 forms a first capacitor C1, the first metal layer 151 and the tunneling insulating layer 156 form a fourth capacitor C4, the second nitride semiconductor layer 130 forms a third capacitor C3, and the first capacitor C1, the fourth capacitor C4 and the third capacitor C3 are sequentially connected in series between the first metal layer 151 and the carrier channel 120A. When the gate electrode G receives a control voltage, the control voltage is divided by the capacitance of the first capacitor C1, the fourth capacitor C4 and the third capacitor C3, and a corresponding voltage is generated in the first metal layer 151, thereby controlling whether to conduct or not conduct the carrier channel 120A.

[0081] The present invention proposes a semiconductor structure of a depletion-type high electron mobility transistor, which greatly reduces the leakage current of a general depletion-type high electron mobility transistor by forming a gate oxide layer on a first metal layer in Schottky contact with a nitride semiconductor layer. In addition, since the first metal layer is in Schottky contact with the nitride semiconductor layer, it is not easy for the first metal layer to capture electrons, thereby reducing the temperature coefficient of the threshold voltage of the semiconductor structure. The present invention further proposes a semiconductor structure of a depletion-type high electron mobility transistor, in which a tunneling insulating layer is formed between the first metal layer and the nitride semiconductor layer to exclude the electrons captured by the first metal layer, so as to further reduce the temperature coefficient of the threshold voltage of the semiconductor structure. In other words, the semiconductor structure of the depletion-type high electron mobility transistor proposed by the present invention can simultaneously retain the advantages of a general depletion-type high electron mobility transistor and a metal-insulating layer-semiconductor high electron mobility transistor.

[0082] Although the embodiments and advantages of the present disclosure have been disclosed as above, it should be understood that any person skilled in the art may make changes, substitutions and modifications without departing from the spirit and scope of the present disclosure. In addition, the scope of protection of the present disclosure is not limited to the processes, machines, manufactures, material compositions, devices, methods and steps in the specific embodiments described in the specification. Any person skilled in the art can understand the current or future developed processes, machines, manufactures, material compositions, devices, methods and steps from the disclosure of some embodiments of the present disclosure. As long as the same functions can be implemented in the embodiments described herein or the same results can be obtained, they can be used according to some embodiments of the present disclosure. Therefore, the scope of protection of the present disclosure includes the above-mentioned processes, machines, manufactures, material compositions, devices, methods and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present disclosure also includes the combination of each claim scope and the embodiment.

Claims

1. A semiconductor structure, characterized in that: include: a substrate; a first nitride semiconductor layer, disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer, wherein a carrier channel is formed on an interface between the first nitride semiconductor layer and the second nitride semiconductor layer; A gate structure is disposed on the second nitride semiconductor layer, wherein the gate structure comprises: a first metal layer, forming a Schottky contact with the second nitride semiconductor layer; a gate oxide layer, disposed on the first metal layer; a second metal layer disposed on the gate oxide layer; a field plate disposed on the second metal layer; and a third metal layer, disposed on the field plate and forming a gate electrode; and A source region and a drain region are disposed on the second nitride semiconductor layer and located at opposite sides of the gate structure, wherein the carrier channel extends between the source region and the drain region.

2. The semiconductor structure according to claim 1, wherein: The gate oxide layer forms a first capacitor, the interface between the first metal layer and the second nitride semiconductor layer forms a second capacitor, and the second nitride semiconductor layer forms a third capacitor, wherein the first capacitor, the second capacitor and the third capacitor are connected in series in sequence between the gate electrode and the carrier channel.

3. The semiconductor structure according to claim 1, wherein: The gate oxide layer is formed at a temperature not greater than 400 degrees Celsius.

4. The semiconductor structure according to claim 1, wherein: Also includes: An insulating layer is disposed on the second nitride semiconductor layer, wherein the first metal layer passes through the insulating layer to form the Schottky contact with the second nitride semiconductor layer.

5. The semiconductor structure according to claim 4, characterized in that The insulating layer is composed of nitride.

6. The semiconductor structure according to claim 4, wherein: The source region and the drain region further include: a fourth metal layer, disposed on the insulating layer, and passing through the insulating layer to form an ohmic contact with the second nitride semiconductor layer; a fifth metal layer, disposed on the fourth metal layer and in contact with the fourth metal layer, for forming a source electrode; a sixth metal layer, disposed on the insulating layer and passing through the insulating layer to form another ohmic contact with the second nitride semiconductor layer; and A seventh metal layer is disposed on the sixth metal layer and in contact with the sixth metal layer to form a drain electrode.

7. The semiconductor structure according to claim 4, wherein: Also includes: A tunneling insulating layer is disposed between the second metal layer and the second nitride semiconductor.

8. The semiconductor structure according to claim 7, wherein: The material of the tunnel insulating layer includes one of aluminum oxide, silicon nitride, silicon dioxide, hafnium silicon oxide and hafnium oxide.

9. The semiconductor structure according to claim 7, wherein: The thickness of the tunneling insulating layer is less than 5 nanometers.

10. The semiconductor structure according to claim 7, wherein: The gate oxide layer forms a first capacitor, the first metal layer and the tunneling insulating layer form a fourth capacitor, and the second nitride semiconductor layer forms a third capacitor, wherein the first capacitor, the fourth capacitor and the third capacitor are sequentially connected in series between the gate electrode and the carrier channel.

Images