Semiconductor structure and forming method thereof
Through the introduction of the blocking layer during the formation of the semiconductor structure to protect the integrity of the ditch layer, the existing semiconductor structure shows the problem of lack of short channel effects and electrical performance on a smaller process node. Structural performance.
Patent Information
- Application Number
- CN202310904371.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-21
- Publication Date
- 2025-01-24
Smart Images
Figure CN119364805A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistor size is getting smaller and smaller, and Fin-type field-effect transistor (FinFET) came into being. However, to maintain the original driving current performance, this structure is no longer suitable for smaller nodes. So the all-around gate transistor (Gate-All-Around, GAAFET) appeared. Its control of short channel effects and superior electrical performance make it replace FinFET and become the mainstream at smaller process nodes.
[0003] GAAFET is a four-sided ring gate structure that can better suppress the short channel effect and achieve better electrical performance.
[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the invention
[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the performance of the semiconductor structure.
[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a channel structure layer suspended on the substrate, the channel structure layer comprising one or more channel layers spaced from bottom to top; a gate structure spanning the channel structure layer, the gate structure filling between the channel layer and the substrate and between adjacent channel layers, and the gate structure surrounding the channel layer; wherein the portion of the gate structure located between the substrate and the channel layer or between adjacent channel layers serves as a first portion; the portion of the gate structure spanning the channel structure layer serves as a second portion; a gate sidewall located on the sidewall of the second portion; a barrier layer located between the bottom of the gate sidewall and the channel layer; and a source-drain doping layer located in the channel structure layer on both sides of the gate structure and in contact with the end of the channel structure layer.
[0007] Optionally, the barrier layer is a single-layer structure; the material of the barrier layer includes silicon carbide, silicon carbide boride or silicon carbide phosphide.
[0008] Optionally, the blocking layer includes a plurality of sub-blocking layers stacked in sequence, and materials of adjacent sub-blocking layers have an etching selectivity ratio; the material of the sub-blocking layer includes silicon oxide, silicon nitride or silicon oxynitride.
[0009] Optionally, the barrier layer has a thickness of 5 nm to 20 nm.
[0010] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a substrate, one or more channel stacks stacked in sequence on the substrate, and a barrier layer on the top of the channel stack, each of the channel stacks comprising a sacrificial layer and a channel layer on the sacrificial layer; forming a dummy gate structure spanning the channel stack and the barrier layer on the substrate, the dummy gate structure covering a portion of the top of the barrier layer and a portion of the side walls of the barrier layer and the channel stack; forming source-drain doping layers in the channel stack on both sides of the dummy gate structure; after forming the source-drain doping layers, removing the dummy gate structure and the barrier layer at the bottom of the dummy gate structure to form a gate opening, the gate opening exposing the top and side walls of the channel stack; removing the sacrificial layer to form a through groove, the through groove being connected to the gate opening; filling the gate opening and the through groove with a gate structure, the gate structure surrounding the channel layer.
[0011] Optionally, the step of removing the dummy gate structure and the blocking layer at the bottom of the dummy gate structure includes: defining the etching stop position with the top of the blocking layer, removing part of the dummy gate structure, and forming an initial gate opening; removing the remaining dummy gate structure and the blocking layer exposed by the initial gate opening, and forming the gate opening, and the removal rate of the dummy gate structure is greater than the removal rate of the blocking layer.
[0012] Optionally, an etching process is used to remove the dummy gate structure and the barrier layer at the bottom of the dummy gate structure; in the step of removing part of the dummy gate structure by defining the etching stop position with the top of the barrier layer, the etching rate of the dummy gate structure is a first rate; in the step of removing the remaining dummy gate structure and the barrier layer exposed by the initial gate opening, the etching rate of the dummy gate structure is a second rate, and the second rate is less than the first rate.
[0013] Optionally, the process of defining the etching stop position by the top of the barrier layer and removing part of the dummy gate structure includes: an anisotropic dry etching process.
[0014] Optionally, the process of removing the remaining dummy gate structure and the barrier layer exposed by the initial gate opening includes: an anisotropic dry etching process.
[0015] Optionally, the barrier layer is a single-layer structure.
[0016] Optionally, the material of the barrier layer includes silicon carbide, silicon carbide boride or silicon carbide phosphide.
[0017] Optionally, the barrier layer includes a plurality of sub-barrier layers stacked in sequence, and materials of adjacent sub-barrier layers have an etching selectivity ratio.
[0018] Optionally, the material of the sub-blocking layer includes silicon oxide, silicon nitride or silicon oxynitride.
[0019] Optionally, the step of providing a base includes: forming a substrate and one or more channel material stacks located on the substrate, each of the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer; forming a blocking material layer on the channel material stack; patterning the blocking material layer and the channel material stack, the remaining blocking material layer is used as the blocking layer, the remaining channel material layer is used as the channel layer, and the remaining sacrificial material layer is used as the sacrificial layer.
[0020] Optionally, the process of forming the barrier material layer includes an epitaxial process or a deposition process.
[0021] Optionally, in the step of providing a substrate, the barrier layer has a thickness of 5 nm to 20 nm.
[0022] Optionally, the method for forming the semiconductor structure further includes: performing a heat treatment in an inert gas atmosphere after forming the through groove and before filling the gate opening and the through groove with a gate structure.
[0023] Optionally, the step of performing heat treatment in an inert gas atmosphere includes: performing heat treatment in a deuterium and inert gas atmosphere.
[0024] Optionally, the process parameters of the heat treatment include: a total flow rate of deuterium and inert gas of 2 slm to 20 slm, a process temperature of 400° C. to 700° C., and a process time of 1 minute to 30 minutes.
[0025] Optionally, the method for forming the semiconductor structure also includes: after forming the dummy gate structure and before forming the source-drain doping layer, forming a gate sidewall on the sidewall of the dummy gate structure, wherein the gate sidewall covers a portion of the top of the blocking layer; in the step of forming the source-drain doping layer, the source-drain doping layer is in contact with the sidewall of the blocking layer.
[0026] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0027] The semiconductor structure provided by the embodiment of the present invention also includes the barrier layer, which is located between the bottom of the gate side wall and the channel layer. Since the barrier layer is also located on the top of the channel stack during the formation of the semiconductor structure, the barrier layer can define the etching stop position on the top of the channel stack in the step of removing the dummy gate structure and the barrier layer at the bottom of the dummy gate structure, and can correspondingly protect the channel layer at the top of the channel stack, thereby reducing the probability of damage to the channel layer at the top of the channel stack caused by the process of removing the dummy gate structure, thereby ensuring the integrity of the channel layer and optimizing the performance of the semiconductor structure.
[0028] In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the step of providing a substrate, a barrier layer is also formed on the top of the channel stack. The barrier layer can define the etching stop position on the top of the channel stack in the step of removing the dummy gate structure and the barrier layer at the bottom of the dummy gate structure, and can accordingly protect the channel layer at the top of the channel stack, thereby reducing the probability of damage to the channel layer at the top of the channel stack caused by the process of removing the dummy gate structure, thereby ensuring the integrity of the channel layer and optimizing the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figures 1 to 6 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;
[0030] Figure 7 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;
[0031] Figures 8 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0032] As can be seen from the background technology, the performance of the current semiconductor structure needs to be improved. Now, in combination with a method for forming a semiconductor structure, the reasons why the performance of the semiconductor structure needs to be improved are analyzed. Figures 1 to 6 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.
[0033] refer to Figure 1 , providing a base, including a substrate 50 and one or more sequentially stacked channel stacks 60 located on the substrate 50 , each of the channel stacks 60 including a sacrificial layer 61 and a channel layer 62 located on the sacrificial layer 61 .
[0034] refer to Figure 2 A dummy gate structure 51 is formed on the substrate 50 and spans the channel stack 60 . The dummy gate structure 51 covers a portion of the top and a portion of the sidewall of the channel stack 60 .
[0035] refer to Figure 3 , a source-drain doped layer 52 is formed in the channel stack 60 on both sides of the dummy gate structure 51 .
[0036] refer to Figure 4 After forming the source-drain doping layer 52 , the dummy gate structure 51 is removed to form a gate opening 53 to expose the channel stack 60 .
[0037] refer to Figure 5 , removing the sacrificial layer 61 exposed by the gate opening 53 to form a through groove 54 , wherein the through groove 54 is connected to the gate opening 53 .
[0038] refer to Figure 6 , a gate structure 55 is filled in the gate opening 53 and the through groove 54 , and the gate structure 55 surrounds the channel layer 62 .
[0039] The dummy gate structure 51 covers part of the top and part of the sidewall of the channel stack 60; in the step of removing the dummy gate structure 51 to form the gate opening 53, since the depth of the dummy gate structure 51 covering part of the sidewall of the channel stack 60 is deep, the dummy gate structure 51 located on the top of the channel stack 60 is removed earlier, resulting in the top of the channel stack 60 being exposed to the etching environment for a longer time, and in the step of removing the dummy gate structure 51, over etching is usually performed. Both of the above aspects are likely to cause damage to the top surface of the channel layer 62 at the top of the channel stack 60 (such as Figure 4 The performance of the semiconductor structure is degraded.
[0040] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, wherein the barrier layer is also provided and located between the bottom of the gate side wall and the channel layer. Since the barrier layer is also located on the top of the channel stack during the formation of the semiconductor structure, the barrier layer can play a role in defining the etching stop position on the top of the channel stack in the step of removing the dummy gate structure and the barrier layer at the bottom of the dummy gate structure, and can correspondingly protect the channel layer at the top of the channel stack, thereby reducing the probability of damage to the channel layer at the top of the channel stack caused by the process of removing the dummy gate structure, thereby ensuring the integrity of the channel layer and optimizing the performance of the semiconductor structure.
[0041] In order to solve the technical problem, an embodiment of the present invention also provides a method for forming a semiconductor structure. In the step of providing a substrate, a barrier layer is also formed on the top of the channel stack. The barrier layer can define the etching stop position on the top of the channel stack in the step of removing the dummy gate structure and the barrier layer at the bottom of the dummy gate structure, and can accordingly protect the channel layer at the top of the channel stack, thereby reducing the probability of damage to the channel layer at the top of the channel stack caused by the process of removing the dummy gate structure, thereby ensuring the integrity of the channel layer and optimizing the performance of the semiconductor structure.
[0042] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 7 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.
[0043] like Figure 7 As shown, in this embodiment, the semiconductor structure includes: a substrate 100; a channel structure layer 170, suspended on the substrate 100, the channel structure layer 170 includes one or more channel layers 20 arranged in sequence from bottom to top; a gate structure 190, spanning the channel structure layer 170, the gate structure 190 is filled between the channel layer 20 and the substrate 100 and between adjacent channel layers 20, and the gate structure 190 surrounds the channel layer 20; wherein the gate structure 190 is located The portion between the substrate 100 and the channel layer 20, or between adjacent channel layers 20, serves as the first portion 191; the portion of the gate structure 190 spanning the channel structure layer 170 serves as the second portion 192; the gate sidewall 125 is located on the sidewall of the second portion 192; the barrier layer 115 is located between the bottom of the gate sidewall 125 and the channel layer 20; the source-drain doping layer 210 is located in the channel structure layer 170 on both sides of the gate structure 190 and in contact with the end of the channel structure layer 170.
[0044] The substrate 100 is used to provide a process platform for forming a semiconductor structure.
[0045] In this embodiment, the semiconductor structure is a gate all around (GAA) transistor as an example for description. In other embodiments, the semiconductor structure may also be a forksheet transistor or a complementary field effect transistor (CFET).
[0046] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium arsenide, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0047] In this embodiment, the semiconductor structure further includes a well region (not shown), which is located in the substrate 100, and the doping type of the well region is different from the doping type of the source-drain doping layer 210. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.
[0048] In this embodiment, the semiconductor structure further includes: an isolation layer (not shown), which is located in the substrate 100 between adjacent device regions and exposes the channel structure layer 170. The isolation layer is used to achieve isolation between adjacent devices.
[0049] In this embodiment, the isolation layer is a shallow trench isolation structure. The material of the isolation layer may include one or more of silicon oxide, silicon oxynitride and silicon nitride.
[0050] In this embodiment, the channel structure layer 170 includes a plurality of channel layers 20 as an example for description, and the plurality of channel layers 20 are stacked and arranged on the substrate 100 in a direction perpendicular to the surface of the substrate 100. In other embodiments, based on actual process requirements, the number of the channel layer can also be one.
[0051] Specifically, the channel layer 20 is used to form a conductive channel of a MOS transistor.
[0052] In this embodiment, an NMOS transistor is formed, and the material of the channel layer 20 is the same as that of the substrate 100, both of which are silicon. In other embodiments, when a PMOS transistor is formed, in order to improve the performance of the PMOS transistor, a silicon germanium channel technology may be used, that is, the material of the channel layer is silicon germanium.
[0053] In other embodiments, based on actual process requirements, other materials may be selected for the channel layer.
[0054] When the device is working, the gate structure 190 is used to control the opening and closing of the conductive channel. Specifically, in this embodiment, the gate structure 190 is formed on the isolation layer.
[0055] In this embodiment, the portion of the gate structure 190 located between the substrate 100 and the channel layer 20 or between adjacent channel layers 20 is the first portion 191 ; the portion of the gate structure 190 spanning the channel structure layer 170 is the second portion 192 .
[0056] In this embodiment, the gate structure 190 is a metal gate structure, and the gate structure 190 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove and the gate opening.
[0057] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.
[0058] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.
[0059] The work function layer is used to adjust the work function of the gate structure 190, and then adjust the threshold voltage of the field effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.
[0060] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 to an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.
[0061] The gate spacer 125 is located on the sidewall of the second portion 192 and is used to protect the sidewall of the gate structure 190 .
[0062] In this embodiment, the material of the gate spacer 125 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric or ultra-low-k dielectric material, and the gate spacer 125 is a single-layer or stacked structure. As an example, the gate spacer 125 is a single-layer structure, and the material of the gate spacer 125 is silicon nitride.
[0063] The semiconductor structure is also provided with the barrier layer 115, which is located between the bottom of the gate sidewall 125 and the channel layer 20. Since the barrier layer 115 is also located on the top of the channel stack during the formation of the semiconductor structure, the barrier layer 115 can define the etching stop position on the top of the channel stack in the step of removing the dummy gate structure and the barrier layer 115 at the bottom of the dummy gate structure, and can accordingly protect the channel layer 20 at the top of the channel stack, thereby reducing the probability of damage to the channel layer 20 at the top of the channel stack caused by the process of removing the dummy gate structure, thereby ensuring the integrity of the channel layer 20 and optimizing the performance of the semiconductor structure.
[0064] In this embodiment, the semiconductor structure further includes: an inner sidewall 180 , which is located between the first portion 191 and the source-drain doped layer 210 along the extension direction of the channel layer 20 .
[0065] In this embodiment, the inner sidewall 180 is used to achieve isolation between the source-drain doped layer 210 and the gate structure 190 , and also increases the distance between the source-drain doped layer 210 and the gate structure 190 , which is beneficial to reducing the parasitic capacitance between the source-drain doped layer 210 and the gate structure 190 .
[0066] In this embodiment, the material of the inner sidewall 180 is an insulating material to achieve isolation between the source-drain doped layer 210 and the gate structure 190, thereby reducing the parasitic capacitance between the source-drain doped layer 210 and the gate structure 190. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.
[0067] The barrier layer 115 is made of a material having etching selectivity with the channel layer 20 and the dummy gate structure, thereby ensuring that the barrier layer 115 can play a role in defining an etching stop position on the top of the channel stack 110 during the step of removing the dummy gate structure.
[0068] In this embodiment, the barrier layer 115 may be a single-layer structure or a multi-layer structure.
[0069] In this embodiment, the barrier layer 115 is described as a single-layer structure, which is helpful to simplify the formation process and structure of the barrier layer 115. In this embodiment, the material of the barrier layer 115 includes silicon carbide, silicon carbide or silicon carbide. The material of the barrier layer 115 has a large hardness, which is helpful to improve the etching resistance of the barrier layer 115, thereby improving the barrier effect of the barrier layer 115 in the step of removing the dummy gate structure.
[0070] Moreover, in this embodiment, the source-drain doping layer 210 contacts the side wall of the blocking layer 115. In this embodiment, the material of the blocking layer 115 contains carbon elements. The blocking layer 115 can block the lateral diffusion of doped ions in the source-drain doping layer 210 along the channel length direction.
[0071] In other embodiments, the barrier layer may also be a stacked structure, wherein the barrier layer includes a plurality of sub-barrier layers stacked in sequence, and materials of adjacent sub-barrier layers have an etching selectivity ratio.
[0072] The barrier layer includes multiple sub-barrier layers, and there is an etching selectivity ratio between the materials of adjacent sub-barrier layers, so that in two adjacent sub-barrier layers, the lower sub-barrier layer can also be used as an etching barrier layer for the upper sub-barrier layer, thereby further improving the etching barrier capability of the barrier layer.
[0073] As an example, the material of the sub-blocking layer includes silicon oxide, silicon nitride or silicon oxynitride, and the materials of adjacent sub-blocking layers are different, so that the materials of adjacent sub-blocking layers can have an etching selectivity ratio.
[0074] It should be noted that the thickness of the barrier layer 115 should not be too small or too large. If the thickness of the barrier layer 115 is too small, the barrier layer 115 is easily removed prematurely in the step of removing the dummy gate structure, which may result in the barrier layer 115 not being effective in defining the etching stop position on the top of the channel stack; if the thickness of the barrier layer 115 is too large, it may increase the difficulty of removing the barrier layer 115 at the bottom of the dummy gate structure, and may also cause waste of materials and work time. For this reason, in this embodiment, the thickness of the barrier layer 115 is 5nm to 20nm.
[0075] As an example, when the barrier layer includes three sub-barrier layers stacked in sequence, that is, the barrier layer includes a first sub-barrier layer, a second sub-barrier layer located on the first sub-barrier layer, and a third sub-barrier layer located on the second sub-barrier layer. The thickness of the first sub-barrier layer is 1.5nm to 2nm, the thickness of the second sub-barrier layer is 2.5nm to 3nm, and the thickness of the third sub-barrier layer is 1.5nm to 2nm.
[0076] The source-drain doped layer 210 is used as a source or a drain of the MOS transistor. When the MOS transistor is working, the source-drain doped layer 210 is used to provide a carrier source.
[0077] In this embodiment, the material of the source-drain doping layer 210 includes a stress layer doped with ions. When the all-around gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doping ions in the source-drain doping layer 210 are P-type ions; when the all-around gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doping ions in the source-drain doping layer 210 are N-type ions.
[0078] In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 220 located at the side of the gate structure 190 and covering the source-drain doped layer 210 .
[0079] The interlayer dielectric layer 220 is used to cover the source-drain doped layer 210, and is also used to achieve electrical isolation between adjacent devices. The material of the interlayer dielectric layer 220 includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer 220 is silicon nitride.
[0080] Specifically, in this embodiment, the interlayer dielectric layer 220 is formed on the isolation layer and covers the source-drain doped layer 210 .
[0081] The semiconductor structure may be formed by the method for forming a semiconductor structure provided by an embodiment of the present invention, or may be formed by other methods.
[0082] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 8 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.
[0083] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.
[0084] refer to Figure 8 , providing a substrate, the substrate comprising a substrate 100, one or more channel stacks 110 stacked in sequence on the substrate 100, and a barrier layer 115 located on top of the channel stack 110, each of the channel stacks 110 comprising a sacrificial layer 10 and a channel layer 20 located on the sacrificial layer 10.
[0085] The substrate 100 is used to provide a process platform for subsequent process steps. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example for description. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field effect transistor (CFET).
[0086] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium arsenide, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.
[0087] In this embodiment, the channel stack 110 provides a process basis for subsequently forming the channel layer 20 with suspended spacing.
[0088] In this embodiment, the number of the channel stacks 110 is multiple as an example for description, and the stacking direction of the multiple channel stacks on the substrate 100 is perpendicular to the surface of the substrate 100. More specifically, in this embodiment, the number of the channel stacks 110 is three. In other embodiments, the number of the channel stacks may also be two, four, etc. In other embodiments, based on actual process requirements, the number of the channel stacks may also be only one.
[0089] Specifically, the channel layer 20 is used to form a conductive channel of the MOS transistor, and the sacrificial layer 10 is used to support the channel layer 20, thereby providing a process basis for the subsequent realization of the spaced suspended arrangement of the channel layer 20. The sacrificial layer 10 is also used to occupy a spatial position for the subsequent formation of a gate structure.
[0090] In this embodiment, the formation of an NMOS transistor is taken as an example for explanation. The material of the channel layer 20 is the same as that of the substrate 100 , both of which are silicon; and the material of the sacrificial layer 10 is silicon germanium.
[0091] In the subsequent process of removing the sacrificial layer 10, the etching selectivity of silicon germanium and silicon is relatively high. Therefore, by setting the material of the sacrificial layer 10 to silicon germanium and the material of the channel layer 20 to silicon, the effect of the removal process of the sacrificial layer 10 on the channel layer 20 can be effectively reduced, thereby improving the quality of the channel layer 20, which is beneficial to improving device performance.
[0092] In other embodiments, when forming a PMOS transistor, in order to improve the performance of the PMOS transistor, a silicon germanium channel technology may be used, that is, the material of the channel layer is silicon germanium, and the material of the sacrificial layer is silicon.
[0093] In other embodiments, based on actual process requirements, other materials may be selected for the channel layer and the sacrificial layer.
[0094] It should be noted that, in this embodiment, a well region (not shown) is also formed in the substrate 100 and the channel layer 20, and the doping type of the well region is different from the channel conductivity type of the MOS transistor. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.
[0095] Subsequent steps also include: forming a dummy gate structure across the channel stack 110 and the barrier layer 115 on the substrate 100, and forming source and drain doping layers in the channel stack on both sides of the dummy gate structure; after forming the source and drain doping layers, removing the dummy gate structure to form a gate opening.
[0096] Among them, the barrier layer 115 can play the role of defining the etching stop position on the top of the channel stack 110 in the step of removing the dummy gate structure and the barrier layer at the bottom of the dummy gate structure, and can accordingly protect the channel layer 20 at the top of the channel stack 110, thereby reducing the probability of damage to the channel layer 20 at the top of the channel stack 110 caused by the process of removing the dummy gate structure, thereby ensuring the integrity of the channel layer 20 and optimizing the performance of the semiconductor structure.
[0097] The barrier layer 115 is made of a material having etching selectivity with the channel layer 20 and the subsequent dummy gate structure, thereby ensuring that the barrier layer 115 can play a role in defining an etching stop position on the top of the channel stack 110 in the subsequent step of removing the dummy gate structure.
[0098] In this embodiment, the barrier layer 115 may be a single-layer structure or a multi-layer structure.
[0099] In this embodiment, the barrier layer 115 is described as a single-layer structure, which is helpful to simplify the process of forming the barrier layer 115. In this embodiment, the material of the barrier layer 115 includes silicon carbide, silicon carbide or silicon carbide. The material of the barrier layer 115 has a large hardness, which is helpful to improve the etching resistance of the barrier layer 115, thereby improving the barrier effect of the barrier layer 115 in the subsequent step of removing the dummy gate structure.
[0100] Moreover, in this embodiment, the method for forming the semiconductor structure also includes: after forming the dummy gate structure and before forming the source-drain doping layer, forming a gate sidewall on the sidewall of the dummy gate structure, and the gate sidewall covers a portion of the top of the blocking layer; in the step of forming the source-drain doping layer, the source-drain doping layer is in contact with the sidewall of the blocking layer 115. In this embodiment, the material of the blocking layer 115 contains carbon elements, and the blocking layer 115 can block the lateral diffusion of doped ions in the source-drain doping layer along the length direction of the channel.
[0101] In other embodiments, the barrier layer may also be a stacked structure, wherein the barrier layer includes a plurality of sub-barrier layers stacked in sequence, and materials of adjacent sub-barrier layers have an etching selectivity ratio.
[0102] The barrier layer includes multiple sub-barrier layers, and there is an etching selectivity ratio between the materials of adjacent sub-barrier layers, so that in two adjacent sub-barrier layers, the lower sub-barrier layer can also be used as an etching barrier layer for the upper sub-barrier layer, thereby further improving the etching barrier capability of the barrier layer.
[0103] As an example, the material of the sub-blocking layer includes silicon oxide, silicon nitride or silicon oxynitride, and the materials of adjacent sub-blocking layers are different, so that the materials of adjacent sub-blocking layers can have an etching selectivity ratio.
[0104] It should be noted that the thickness of the barrier layer 115 should not be too small or too large. If the thickness of the barrier layer 115 is too small, the barrier layer 115 is easily removed prematurely in the subsequent step of removing the dummy gate structure, which may result in the barrier layer 115 not being effective in defining the etching stop position on the top of the channel stack 110; if the thickness of the barrier layer 115 is too large, it may increase the difficulty of removing the barrier layer 115 at the bottom of the dummy gate structure, and may also cause waste of materials and work time. For this reason, in this embodiment, the thickness of the barrier layer 115 is 5nm to 20nm.
[0105] As an example, when the barrier layer includes three sub-barrier layers stacked in sequence, that is, the barrier layer includes a first sub-barrier layer, a second sub-barrier layer located on the first sub-barrier layer, and a third sub-barrier layer located on the second sub-barrier layer. The thickness of the first sub-barrier layer is 1.5nm to 2nm, the thickness of the second sub-barrier layer is 2.5nm to 3nm, and the thickness of the third sub-barrier layer is 1.5nm to 2nm.
[0106] As an example, the step of providing a base includes: forming a substrate 100 and one or more channel material stacks (not shown) located on the substrate 100, each of the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer; forming a blocking material layer (not shown) on the channel material stack; patterning the blocking material layer and the channel material stack, the remaining blocking material layer is used as the blocking layer 115, the remaining channel material layer is used as the channel layer 20, and the remaining sacrificial material layer is used as the sacrificial layer 10.
[0107] In this embodiment, the process of forming the barrier material layer includes an epitaxial process or a deposition process.
[0108] In a specific embodiment, in the step of patterning the barrier material layer and the channel material stack, a partial thickness of the substrate 100 may also be patterned so that the substrate 100 in the adjacent device area is surrounded by a groove (not shown). The groove is used to define the isolation area between adjacent devices so as to provide a spatial position for forming an isolation layer in the groove.
[0109] Correspondingly, in this embodiment, the step of providing a substrate may further include: forming an isolation layer (not shown) in the trench, wherein the isolation layer exposes the channel stack 110 .
[0110] The isolation layer is used to isolate adjacent devices. In this embodiment, the isolation layer is a shallow trench isolation structure. The material of the isolation layer may include one or more of silicon oxide, silicon oxynitride and silicon nitride.
[0111] refer to Fig. 9 A dummy gate structure 120 is formed on the substrate 100 and spans the channel stack 110 and the barrier layer 115 . The dummy gate structure 120 covers a portion of the top of the barrier layer 115 and a portion of the sidewalls of the barrier layer 115 and the channel stack 110 .
[0112] The dummy gate structure 120 is used to pre-occupy a space position for the subsequent formation of a gate structure. Specifically, in this embodiment, the dummy gate structure 120 is formed on the isolation layer and across the channel stack 110 , and covers part of the top and part of the sidewall of the channel stack 110 .
[0113] In this embodiment, the dummy gate structure 120 includes a dummy gate oxide layer 121 and a dummy gate layer 122 located on the dummy gate oxide layer 121. In this embodiment, the material of the dummy gate oxide layer 121 includes one or more of silicon oxide and silicon oxynitride. In this embodiment, the material of the dummy gate layer 122 includes polysilicon or amorphous silicon.
[0114] In a specific implementation, a dummy gate mask layer 135 is further formed on the top of the dummy gate layer 122. The dummy gate mask layer 135 is used as an etching mask for patterning the dummy gate material layer to form the dummy gate structure 120.
[0115] As an example, the material of the dummy gate mask layer 135 is silicon nitride.
[0116] In this embodiment, after forming the dummy gate structure 120, the method for forming a semiconductor structure further includes: forming a gate spacer 125 on the sidewall of the dummy gate structure 120. In this embodiment, the gate spacer 125 also covers a portion of the top of the barrier layer 115.
[0117] The gate sidewall 125 is used together with the dummy gate layer 122 and the dummy gate mask layer 135 as an etching mask for the subsequent formation of source and drain grooves to define the formation position of the source and drain doping layers. The gate sidewall 125 is also used to protect the dummy gate layer 122 and the sidewalls of the subsequent gate structure.
[0118] The material of the gate spacer 125 is an insulating dielectric material. In this embodiment, the material of the gate spacer 125 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric or ultra-low-k dielectric material, and the gate spacer 125 is a single-layer or stacked structure. As an example, the gate spacer 125 is a single-layer structure, and the material of the gate spacer 125 is silicon nitride.
[0119] refer to Fig.10 , a source-drain doped layer 210 is formed in the channel stack 110 on both sides of the dummy gate structure 120 .
[0120] When the device is working, the source-drain doped layer 210 is used as a source or a drain to provide a carrier source.
[0121] In this embodiment, the source-drain doping layer 210 includes a stress layer doped with ions. When the all-around gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doping ions in the source-drain doping layer 210 are P-type ions; when the all-around gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiGe, and the doping ions in the source-drain doping layer 210 are N-type ions.
[0122] Specifically, the step of forming the source-drain doped layer 210 includes: removing the barrier layer 115 and the channel stack 110 on both sides of the dummy gate structure 120 to form source-drain grooves (not shown); and forming the source-drain doped layer 210 in the source-drain grooves.
[0123] The source-drain grooves are used to provide spatial locations for the subsequent formation of source-drain doping layers.
[0124] As an example, the step of forming the source-drain groove includes: using an anisotropic dry etching process to etch the barrier layer 115 and the channel stack 110 exposed by the dummy gate structure 120 to form the source-drain groove. The anisotropic dry etching process has anisotropic etching characteristics, which is conducive to improving the profile controllability of forming the source-drain groove, and the dry etching process has high etching accuracy and fast etching rate, and the dry etching process is easy to achieve a high etching selectivity, which is conducive to reducing the probability of damage to other film layer structures in the process of forming the source-drain groove.
[0125] As an example, the step of forming the source-drain doped layer 210 in the source-drain groove includes: using an epitaxial process to form a stress layer, and in-situ self-doping ions during the process of forming the stress layer, and the stress layer doped with ions is used as the source-drain doped layer 210.
[0126] Specifically, based on the substrate 100 and the channel layer 20 exposed by the source-drain grooves, epitaxial growth is performed to form the source-drain doped layer 210 .
[0127] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 210 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SIC, and the doped ions in the source and drain doping layer 210 are N-type ions.
[0128] In this embodiment, the source-drain doping layer 210 is in contact with the sidewall of the barrier layer 115 .
[0129] In this embodiment, the method for forming a semiconductor structure also includes: after forming the source and drain grooves and before forming the source and drain doping layer 210, laterally etching the portion of the sacrificial layer 10 exposed on the sidewalls of the source and drain grooves in a direction parallel to the substrate 100 and perpendicular to the extension direction of the dummy gate structure 120 to form an inner groove (not shown), the inner groove being surrounded by the adjacent channel layer 20 and the remaining sacrificial layer 10, or the inner groove being surrounded by the substrate 100, the channel layer 20 adjacent to the substrate 100 and the remaining sacrificial layer 10; forming an inner sidewall 180 in the inner groove.
[0130] Specifically, the inner groove provides a space for forming the inner side wall.
[0131] In this embodiment, the process of laterally etching the part of the sacrificial layer 10 exposed by the sidewalls of the source and drain grooves includes an isotropic etching process. The isotropic etching process has the characteristics of isotropic etching, and is easy to achieve a large etching selectivity, so that the part of the sacrificial layer 10 exposed along the sidewalls of the source and drain grooves can be laterally etched, which is conducive to reducing the difficulty of etching the sacrificial layer 10 and reducing the probability of damage to other film structures.
[0132] Subsequently, a gate structure is formed at the position of the dummy gate structure 120 and the sacrificial layer 10. The inner sidewall 180 is used to achieve isolation between the source-drain doped layer and the gate structure, and also increases the distance between the source-drain doped layer 210 and the gate structure, which is beneficial to reducing the parasitic capacitance between the source-drain doped layer and the gate structure.
[0133] In this embodiment, the material of the inner sidewall 180 is an insulating material to achieve isolation between the source and drain doping layers and the gate structure. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.
[0134] refer to Fig.11 After forming the source-drain doping layer 210 , the dummy gate structure 120 and the barrier layer 115 at the bottom of the dummy gate structure 120 are removed to form a gate opening 160 , wherein the gate opening 160 exposes the top and sidewalls of the channel stack 110 .
[0135] The gate opening 160 is used to provide a space for the subsequent formation of a gate structure. The gate opening 160 exposes the top and sidewalls of the channel stack 110 and is also used to facilitate the subsequent removal of the sacrificial layer 10 in the channel stack 110 .
[0136] In the present embodiment, in the step of providing a substrate, a barrier layer 115 is further formed on the top of the channel stack 110. The barrier layer 115 can define the etching stop position on the top of the channel stack 110 in the step of removing the dummy gate structure 120 and the barrier layer 115 at the bottom of the dummy gate structure 120, and can accordingly protect the channel layer at the top of the channel stack 110, thereby reducing the probability of damage to the channel layer 20 at the top of the channel stack 110 caused by the process of removing the dummy gate structure 120, thereby ensuring the integrity of the channel layer 20 and optimizing the performance of the semiconductor structure.
[0137] In this embodiment, an etching process is used to remove the dummy gate structure 120 and the blocking layer 115 at the bottom of the dummy gate structure 120 .
[0138] In this embodiment, the step of removing the dummy gate structure 120 and the blocking layer 115 at the bottom of the dummy gate structure 120 includes: defining the etching stop position with the top of the blocking layer 115, removing part of the dummy gate structure 120, and forming an initial gate opening (not shown); removing the remaining dummy gate structure 120 and the blocking layer 115 exposed by the initial gate opening, forming the gate opening 160, and the removal rate of the dummy gate structure 120 is greater than the removal rate of the blocking layer 115.
[0139] In the process of removing part of the dummy gate structure 120, there is a high etching selectivity ratio between the dummy gate structure 120 and the barrier layer 115, so that the etching stop position can be defined by the top of the barrier layer 115, and part of the dummy gate structure 120 is removed to form the initial gate opening.
[0140] Furthermore, in the step of removing the remaining dummy gate structure 120 and the barrier layer exposed by the initial gate opening, the removal rate of the dummy gate structure 120 is greater than the removal rate of the barrier layer 115, thereby ensuring that the barrier layer 115 can play a sufficient etching barrier role.
[0141] It should also be noted that, in the present embodiment, in the step of removing part of the dummy gate structure 120 by defining the etching stop position at the top of the barrier layer 115, the etching rate of the dummy gate structure 120 is a first rate; in the step of removing the remaining dummy gate structure 120 and the barrier layer 115 exposed by the initial gate opening, the etching rate of the dummy gate structure 120 is a second rate, and the second rate is less than the first rate. That is, when it is detected that the barrier layer 115 is etched, the etching rate is adjusted to further reduce the probability of damaging the channel layer 20 located at the top of the channel stack 110.
[0142] In this embodiment, the process of removing part of the dummy gate structure 120 by defining the etching stop position with the top of the barrier layer 115 includes: an anisotropic dry etching process. The anisotropic dry etching process has anisotropic etching characteristics and is easy to achieve a higher etching selectivity.
[0143] In this embodiment, the process of removing the remaining dummy gate structure 120 and the barrier layer 115 exposed by the initial gate opening includes: an anisotropic dry etching process. The anisotropic dry etching process is easy to adjust the etching rate and etching selectivity by adjusting the etching recipe (for example, etching gas type and ratio, etc.).
[0144] In this embodiment, the method for forming a semiconductor structure further includes: after forming the source-drain doping layer 210 , forming an interlayer dielectric layer 220 on the substrate 100 on the side of the dummy gate structure 120 , the interlayer dielectric layer 220 covering the source-drain doping layer 210 and exposing the top of the dummy gate structure 111 .
[0145] Accordingly, in this embodiment, in the step of removing the dummy gate structure 120 and the barrier layer 115 located at the bottom of the dummy gate structure 120 , a gate opening is formed in the interlayer dielectric layer 220 .
[0146] The interlayer dielectric layer 220 is used to cover the source-drain doped layer 210, and plays a role in protecting the source-drain doped layer 210 when the gate opening is subsequently formed. The interlayer dielectric layer 220 is also used to achieve electrical isolation between adjacent devices. The material of the interlayer dielectric layer 220 includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer 220 is silicon nitride.
[0147] Specifically, in this embodiment, the interlayer dielectric layer 220 is formed on the isolation layer and covers the source-drain doped layer 210 .
[0148] refer to Fig.12 , the sacrificial layer 10 is removed to form a through groove 165 , wherein the through groove 165 is connected to the gate opening 160 .
[0149] The gate opening 160 and the through-slot 165 are used to provide a space for forming a gate structure.
[0150] After removing the sacrificial layer 10, one or more channel layers 20 are suspended and arranged at intervals, so that the subsequent gate structure can surround the channel layer 20. Among them, one or more channel layers 20 that are suspended and arranged at intervals in sequence are used to form a channel structure layer 170.
[0151] In this embodiment, the method for forming the semiconductor structure further includes: performing a heat treatment in an inert gas atmosphere after forming the through-groove 165 and before filling the gate structure in the gate opening 160 and the through-groove 165 .
[0152] In this embodiment, heat treatment is performed in an inert gas atmosphere to repair the interface state between the gate opening 160 and the surface of the through groove 165, so as to provide good interface quality for the subsequent formation of the gate structure and optimize the performance of the semiconductor structure.
[0153] In this embodiment, the step of performing heat treatment in an inert gas atmosphere includes: performing heat treatment in a deuterium and inert gas atmosphere.
[0154] Deuterium or inert gas combines more stably with the interface dangling bonds, thereby inhibiting the formation of unstable chemical bonds with hydrogen, and then passivating the interface state. Then, by performing a second heat treatment in a deuterium and inert gas atmosphere, the surface interface state of the gate opening 160 and the through groove 165 can be repaired.
[0155] Specifically, in this embodiment, deuterium and an inert gas are introduced into the reaction chamber to perform heat treatment.
[0156] It should be noted that the gas flow rate of the heat treatment should not be too small or too large. If the gas flow rate of the heat treatment is too small, the efficiency of the interface repair is easily reduced; if the gas flow rate of the heat treatment is too large, the probability of uneven interface repair is easily increased. For this reason, in this embodiment, in the step of heat treatment, the total flow rate of deuterium and inert gas is 2slm (standard litre per minute, a flow rate of 1L / min under standard conditions) to 20slm.
[0157] It should also be noted that the process temperature of the heat treatment should not be too low or too high. If the process temperature of the heat treatment is too low, the efficiency of interface repair and lattice damage repair will be reduced; if the process temperature of the heat treatment is too high, the probability of diffusion of doped ions in the semiconductor structure will be increased. For this reason, in this embodiment, the process temperature of the heat treatment is 400°C to 700°C.
[0158] It should also be noted that the heat treatment process time should not be too short or too long. If the heat treatment process time is too short, it is easy to cause insufficient repair of interface states and lattice damage; if the heat treatment process time is too long, it is easy to increase the probability of diffusion of doped ions in the semiconductor structure and it is also easy to waste working hours. For this reason, the heat treatment process time is 1 minute to 30 minutes.
[0159] refer to Fig.13 , a gate structure 190 is filled in the gate opening 160 and the through groove 165 , and the gate structure 190 surrounds the channel layer 20 .
[0160] When the device is operating, the gate structure 190 is used to control the opening and closing of the conductive channel.
[0161] In this embodiment, the portion of the gate structure 190 located between the substrate 100 and the channel layer 20 or between adjacent channel layers 20 is the first portion 191 ; the portion of the gate structure 190 spanning the channel structure layer 170 is the second portion 192 .
[0162] In this embodiment, the gate structure 190 is a metal gate structure, and the gate structure 190 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove and the gate opening.
[0163] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.
[0164] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.
[0165] The work function layer is used to adjust the work function of the gate structure 190, and then adjust the threshold voltage of the field effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.
[0166] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 to an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.
[0167] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.
Claims
1. A semiconductor structure, characterized in that: include: substrate; A channel structure layer is suspended on the substrate, and the channel structure layer includes one or more channel layers sequentially arranged from bottom to top; A gate structure spanning the channel structure layer, the gate structure is filled between the channel layer and the substrate and between adjacent channel layers, and the gate structure surrounds the channel layer; wherein the portion of the gate structure located between the substrate and the channel layer or between adjacent channel layers is used as the first portion; the portion of the gate structure spanning the channel structure layer is used as the second portion; A gate sidewall spacer, located on a sidewall of the second portion; A barrier layer, located between the bottom of the gate sidewall and the channel layer; The source-drain doping layer is located in the channel structure layer at both sides of the gate structure and is in contact with the end of the channel structure layer.
2. The semiconductor structure according to claim 1, wherein: The barrier layer is a single-layer structure; the material of the barrier layer includes silicon carbide, silicon carbide boride or silicon carbide phosphide.
3. The semiconductor structure according to claim 1, wherein: The blocking layer includes a plurality of sub-blocking layers stacked in sequence, and materials of adjacent sub-blocking layers have an etching selectivity ratio; the material of the sub-blocking layers includes silicon oxide, silicon nitride or silicon oxynitride.
4. The semiconductor structure according to claim 1, wherein: The thickness of the barrier layer is 5 nm to 20 nm.
5. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a substrate, one or more sequentially stacked channel stacks located on the substrate, and a barrier layer located on top of the channel stacks, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure across the channel stack and the barrier layer on the substrate, wherein the dummy gate structure covers a portion of the top of the barrier layer and a portion of the sidewalls of the barrier layer and the channel stack; forming source-drain doping layers in the channel stacks on both sides of the dummy gate structure; After forming the source-drain doping layer, removing the dummy gate structure and the barrier layer at the bottom of the dummy gate structure to form a gate opening, wherein the gate opening exposes the top and sidewalls of the channel stack; Removing the sacrificial layer to form a through groove, wherein the through groove is connected to the gate opening; A gate structure is filled in the gate opening and the through groove, and the gate structure surrounds the channel layer.
6. The method for forming a semiconductor structure according to claim 5, wherein: The step of removing the dummy gate structure and the barrier layer at the bottom of the dummy gate structure includes: defining the etching stop position with the top of the barrier layer, removing part of the dummy gate structure, and forming an initial gate opening; removing the remaining dummy gate structure and the barrier layer exposed by the initial gate opening, and forming the gate opening, and the removal rate of the dummy gate structure is greater than the removal rate of the barrier layer.
7. The method for forming a semiconductor structure according to claim 6, wherein: Using an etching process to remove the dummy gate structure and the blocking layer at the bottom of the dummy gate structure; In the step of defining the etching stop position by the top of the barrier layer and removing part of the dummy gate structure, the etching rate of the dummy gate structure is a first rate; In the step of removing the remaining dummy gate structure and the barrier layer exposed by the initial gate opening, the etching rate of the dummy gate structure is a second rate, which is smaller than the first rate.
8. The method for forming a semiconductor structure according to claim 6, wherein: The process of defining the etching stop position with the top of the barrier layer and removing part of the dummy gate structure includes: an anisotropic dry etching process.
9. The method for forming a semiconductor structure according to claim 6, wherein: The process of removing the remaining dummy gate structure and the barrier layer exposed by the initial gate opening includes: an anisotropic dry etching process.
10. The method for forming a semiconductor structure according to claim 5, wherein: The barrier layer is a single-layer structure.
11. The method for forming a semiconductor structure according to claim 10, wherein: The material of the barrier layer includes silicon carbide, silicon carbide boride or silicon carbide phosphide.
12. The method for forming a semiconductor structure according to claim 5, wherein: The barrier layer includes a plurality of sub-barrier layers stacked in sequence, and materials of adjacent sub-barrier layers have an etching selectivity ratio.
13. The method for forming a semiconductor structure according to claim 12, wherein: The material of the sub-blocking layer includes silicon oxide, silicon nitride or silicon oxynitride.
14. The method for forming a semiconductor structure according to claim 5, wherein: The step of providing a substrate includes: forming a substrate and one or more channel material stacks located on the substrate, each of the channel material stacks including a sacrificial material layer and a channel material layer located on the sacrificial material layer; A barrier material layer is formed on the channel material stack; the barrier material layer and the channel material stack are patterned, the remaining barrier material layer is used as the barrier layer, the remaining channel material layer is used as the channel layer, and the remaining sacrificial material layer is used as the sacrificial layer.
15. The method for forming a semiconductor structure according to claim 14, wherein: The process of forming the barrier material layer includes an epitaxial process or a deposition process.
16. The method for forming a semiconductor structure according to claim 5, wherein: In the step of providing a substrate, the barrier layer has a thickness of 5 nm to 20 nm.
17. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming a semiconductor structure further comprises: performing a heat treatment in an inert gas atmosphere after forming the through-groove and before filling the gate opening and the through-groove with a gate structure.
18. The method for forming a semiconductor structure according to claim 17, wherein: The step of performing heat treatment in an inert gas atmosphere includes: performing heat treatment in a deuterium and inert gas atmosphere.
19. The method for forming a semiconductor structure according to claim 18, wherein: The process parameters of the heat treatment include: a total flow rate of deuterium and inert gas of 2 slm to 20 slm, a process temperature of 400° C. to 700° C., and a process time of 1 minute to 30 minutes.
20. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the semiconductor structure also includes: after forming the dummy gate structure and before forming the source-drain doping layer, forming a gate sidewall on the sidewall of the dummy gate structure, wherein the gate sidewall covers a portion of the top of the barrier layer; in the step of forming the source-drain doping layer, the source-drain doping layer is in contact with the sidewall of the barrier layer.