Vertical MOS channel diode device and preparation method and integration application thereof

Abstract

The invention relates to a vertical MOS channel diode device and a preparation method and integrated application thereof, and belongs to the technical field of semiconductor devices, and an epitaxial structure sequentially comprises a substrate, an n-GaN drift layer, a p-GaN layer and an n +-GaN source layer from bottom to top; a groove is etched on the n < + >-GaN source electrode layer, and the groove extends into the n <->-GaN drift layer to form a groove of an MOS (Metal Oxide Semiconductor) region; dielectric layers are deposited on the surface of the MOS groove area and the surface of the n +-GaN source electrode layer, holes are etched in the dielectric layers on the surface of the n +-GaN source electrode layer on the two sides of the MOS groove area, and anode metal is sputtered on the holes and the dielectric layers. By integrating the source electrodes and the grid electrodes of the MOSFET devices prepared by the same batch of process, a unipolar two-terminal device with a high breakdown voltage level is realized, and a reverse recovery working mode with the high breakdown voltage level and low power consumption is realized.

Description

Technical Field

[0001] The invention relates to a vertical MOS channel diode device and a preparation method and integrated application thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] Power semiconductor devices are the core of power electronic systems and are widely used in many fields such as consumer electronics, rail transportation, photovoltaic power generation and industrial control. They undertake many functions such as frequency conversion, rectification, voltage conversion, power amplification and power management. Compared with the first-generation semiconductor silicon (Si), the third-generation semiconductor gallium nitride (GaN) has attracted much attention due to its advantages such as larger bandgap width, higher critical breakdown field strength and faster saturation drift speed. Therefore, GaN-based power transistors can break through the development bottleneck of traditional Si-based power transistors and further meet the needs of the next generation of power electronic systems.

[0003] Thanks to the high-mobility two-dimensional electron gas (2DEG) at the AlGaN / GaN interface, horizontal power devices based on the AlGaN / GaN heterostructure have achieved excellent performance, and GaN-based lateral high electron mobility transistors (HEMTs) on Si substrates with an operating voltage of 650V have been successfully commercialized. However, for applications in high-voltage and high-current scenarios, the vertical configuration is still the best choice. For horizontal power transistors, if higher voltage levels are to be achieved, a larger source-drain spacing is required, which will increase the size of the chip and lead to higher product costs. At the same time, the parasitic elements and pins of horizontal power transistors are proportional to the distance from the gate to the drain. The realization of high-voltage devices by increasing the source-drain spacing will increase parasitic effects and degrade the switching speed of the device.

[0004] Compared with GaN horizontal power transistors, GaN vertical power transistors can achieve higher breakdown voltage by increasing the thickness of the drift region without increasing the chip package size. The source and drain of GaN vertical power transistors are located on both sides of the wafer, which helps to achieve uniform current distribution and higher current levels. At present, vertical GaN power transistors mainly include trench MOSFETs (T-MOSFETs), current hole vertical electron transistors (CAVETs), junction FETs (JFETs) and fin power field effect transistors (FinFETs). Compared with other major vertical GaN power transistors, T-MOSFETs have a threshold voltage of 3-5 volts, which can avoid the device from being mistakenly turned on due to noise of the input signal while ensuring that the device realizes the normally off mode. It has a relatively simple manufacturing process, so it has been widely studied.

[0005] As another important branch in the field of power devices, Schottky barrier diodes (SBDs) are an important component of power electronic systems, playing important roles such as rectification and voltage resistance. SBDs have low forward voltage drop and fast switching speed, which makes them widely used in high-efficiency power conversion and high-frequency applications, such as switching power supplies, inverters, and electric vehicles.

[0006] However, the above-mentioned T-MOSFET power devices and Schottky diode devices have certain problems in circuit applications. For Schottky diodes, under reverse bias, the strong electric field concentration at the Schottky contact interface will cause the Schottky barrier to decrease, so Schottky diodes usually exhibit lower reverse breakdown voltage and larger reverse leakage current. If you want to realize a Schottky diode device that can be used in high-voltage scenarios, you need to weaken the peak electric field at the Schottky anode through structural design and experimental optimization, such as field plates and ion implantation. However, this will bring more complex and strict preparation conditions, which is not conducive to promoting the industrialization process of the device.

[0007] For GaN power transistors, their application scenarios usually require a reverse freewheeling path. Traditional T-MOSFETs can achieve three-quadrant freewheeling capability by integrating SBD and embedded body diode, avoiding the additional power loss, package volume, parasitic effects and circuit ringing caused by the external anti-parallel freewheeling diode. However, if the drain bias is too large and the embedded diode is turned on, the bipolar current of the diode will cause the reverse recovery performance to deteriorate and the switching loss of the device to increase. Therefore, a low-power freewheeling path can be achieved by integrating SBD devices on a MOSFET monolithic chip. However, the breakdown voltage level of the integrated SBD device is usually lower than that of the MOSFET, which will make the breakdown voltage of the MOSFET device meaningless through process optimization. Summary of the invention

[0008] In view of the deficiencies of the prior art, the present invention provides a unipolar MOS channel diode device and proposes its integrated application. Replacing the body pn junction with the MOS channel diode as a freewheeling diode can effectively reduce the switching loss of the device during reverse freewheeling. Replacing the SBD device with a MOS channel diode device as a freewheeling diode can avoid the problem of a decrease in the breakdown voltage level. The present application provides a MOS channel diode and a preparation method thereof, and provides a solution for integrating it with a MOSFET, so as to realize a diode device and an integrated device with a higher breakdown voltage level and better current conduction capability without adding additional process steps.

[0009] The technical solution of the present invention is as follows:

[0010] A vertical MOS channel diode device, the epitaxial structure includes a substrate, a n --GaN drift layer, p-GaN layer and n + -GaN source layer; the n + -Etch a trench on the GaN source layer, extending to the n - -GaN drift layer, forming a trench in the MOS region; in the MOS trench region and n + - A dielectric layer is deposited on the surface of the GaN source layer, and n + A hole is etched into the dielectric layer on the surface of the GaN source layer, and an anode metal is deposited at the hole and on the dielectric layer.

[0011] Preferably, the substrate material is Si, sapphire, GaN, SiC, diamond, the dielectric layer is SiO2, Al2O3, SiN or HfO2, and the anode metal is Cr / Au or Al or Ni.

[0012] Preferably, n - The thickness of the -GaN drift layer is 3um-8um, preferably 7um, and the doping concentration is unintentional doping; the thickness of the p-GaN layer is 300nm-700nm, preferably 400nm, and the doping concentration of Mg is 5×10 18 cm -3 -2×10 19 cm -3 , preferably 2×10 19 cm -3 ;n + -GaN source layer is a double-layer structure, with the Si doping concentration of the bottom layer being 5×10 18 cm -3 The 200nm GaN layer and the upper Si doping concentration are 1×10 19 cm -3 20nm GaN layer; the thickness of the dielectric layer is 50-150nm.

[0013] Preferably, the diode device has a body electrode, the dielectric layer is etched to open a hole to the p-GaN layer, metal Pb is provided in the hole, and the p-GaN layer is connected to the anode metal through the metal Pb.

[0014] A method for preparing a vertical MOS trench diode device comprises the following steps:

[0015] (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer;

[0016] (b) Perform trench etching on the epitaxial structure until n --GaN drift layer upper part; trench etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer;

[0017] (c) removing the surface mask and performing post annealing (PIA) to increase the hole activation rate inside the p-GaN; using ALD to deposit a layer of SiO2 film as a SiO2 dielectric layer at the bottom and sidewall of the trench in the MOS region;

[0018] (d) Use photoresist as a mask to cut n on both sides of the MOS region trench. + -Etching the dielectric layer on the surface of the GaN source layer to open holes, and the etching depth is ≥ the thickness of the dielectric layer;

[0019] (e) Sputter Cr / Au metal in the range where the openings of the two dielectric layers are opposite to each other, first sputter Cr and then sputter Au, to form a diode anode, and make a cathode under the substrate.

[0020] Preferably, in step (d), when no body electrode is formed, the etching depth is 100 nm to 200 nm; when a body electrode is formed, the etching is performed to the p-GaN layer.

[0021] Preferably, in step (e), the thickness of the Cr metal layer is 50 nm, and the thickness of the Au metal layer is 150 nm; when making the body electrode, the body electrode Pb is evaporated at the opening of the dielectric layer, and the body electrode contacts the p-GaN layer to form an ohmic contact; then, Cr / Au metal is evaporated in the relative range of the two dielectric layer openings to form the anode of the diode.

[0022] A vertical MOS channel diode device and MOSFET monolithic integrated device, comprising, from bottom to top, a substrate, a n - -GaN drift layer, p-GaN layer and n + -GaN source layer; wherein, from left to right, a gate groove and a source groove are arranged in sequence, and the gate groove and the source groove are both made of n + -GaN source layer is etched to n - -GaN drift layer; a dielectric layer is deposited on the bottom and sidewalls of the gate groove, and a gate metal is sputtered on the dielectric layer; a dielectric layer is deposited on the bottom and sidewalls of the source groove, and a source metal is sputtered on the dielectric layer.

[0023] Preferably, the gate metal is Cr / Au double-layer metal or Al or Ni, and the source metal is Cr / Au or Al or Ni.

[0024] Preferably, the thickness of the dielectric layer at the gate groove is greater than the thickness of the dielectric layer at the source groove.

[0025] Preferably, the integrated device is provided with a body electrode, and holes are etched in the dielectric layer on both sides of the groove represented by the gate groove / source groove, and the hole is etched to the p-GaN layer, and metal Pb is provided in the hole, that is, the p-GaN layer is connected to the anode metal through the metal Pb.

[0026] A method for preparing a vertical MOS trench diode device and a MOSFET monolithic integrated device, wherein the gate metal and the source metal are made of the same material and the thickness of the dielectric layer at the gate groove is equal to the thickness of the dielectric layer at the source groove, comprises the following steps:

[0027] (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer;

[0028] (b) Etching two or more trenches on the epitaxial structure, including gate trenches and source trenches, until n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer;

[0029] (c) removing the surface mask and performing post annealing (PIA) to increase the hole activation rate inside the p-GaN; using ALD to deposit a 50-150nm thick SiO2 film as a SiO2 dielectric layer on the bottom and sidewall of the gate groove and the source groove, and the dielectric layer material is preferably SiO2, Al2O3, SiN or HfO2;

[0030] (d) using a photoresist as a mask, etching holes in the dielectric layer on both sides of the trench, wherein the etching depth is ≥ the thickness of the dielectric layer, preferably 100 nm to 200 nm;

[0031] (e) Use electron beam to evaporate gate metal in the gate groove and source metal in the source groove to form the gate source of the MOSFET device and the anode of the diode device, and make the drain under the substrate. The source of the MOSFET device and the anode of the diode device are the same electrode and are in a short-circuited state. The source gate is integrated onto the same metal electrode to act as the anode, and the drain is connected to the cathode through the substrate. The forward conduction path of the device is the side wall of the trench, achieving a higher breakdown voltage level and third quadrant freewheeling capability.

[0032] Preferably, in step (b), the etching depth is 1-1.5 um.

[0033] A method for preparing a vertical MOS trench diode device and a MOSFET monolithic integrated device, wherein the thickness of the dielectric layer at the gate groove is equal to the thickness of the dielectric layer at the source groove, and the gate metal and the source metal materials are different, comprising the following steps:

[0034] (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer;

[0035] (b) Etching two or more trenches on the epitaxial structure, including gate trenches and source trenches, until n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer;

[0036] (c) removing the surface mask and performing post annealing (PIA) to increase the hole activation rate inside the p-GaN; using ALD to deposit a 50-150nm thick SiO2 film as a SiO2 dielectric layer on the bottom and sidewall of the gate groove and the source groove, and the dielectric layer material is preferably SiO2, Al2O3, SiN or HfO2;

[0037] (d) using photoresist as a mask and sputtering gate metal at the gate groove;

[0038] (e) removing the photoresist mask in step (d), and using a new photoresist mask to etch holes in the dielectric layer on both sides of the groove, wherein the etching depth is ≥ the thickness of the dielectric layer, preferably 100 nm to 200 nm;

[0039] (f) Sputter source metal in the source groove to form the gate source of the MOSFET device and the anode of the diode device, and make the drain under the substrate. The source of the MOSFET device and the anode of the diode device are the same electrode and are in a short-circuited state. The source gate is integrated onto the same metal electrode to act as the anode, and the drain is connected to the cathode through the substrate. The forward conduction path of the device is the side wall of the trench, achieving a higher breakdown voltage level and third quadrant freewheeling capability.

[0040] A method for preparing a vertical MOS trench diode device and a MOSFET monolithic integrated device, when the thickness of the dielectric layer at the gate groove is greater than the thickness of the dielectric layer at the source groove, comprises the following steps:

[0041] (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer;

[0042] (b) Etching the gate groove on the epitaxial structure until the gate groove is n - -GaN drift layer upper part, etching depth>n +-The sum of the thickness of the GaN source layer and the p-GaN layer;

[0043] (c) removing the surface mask and performing post-annealing treatment; using ALD to deposit a 50-150nm thick SiO2 film as a dielectric layer on the gate groove;

[0044] (d) Use photoresist as a mask to sputter metal at the gate groove; remove the photoresist mask, use a new photoresist as a mask to open a hole on the right side of the gate groove, and the etching depth is ≥ the thickness of the dielectric layer; then etch the source groove to n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer;

[0045] (e) removing the surface mask, and using ALD to deposit a SiO2 film having a thickness smaller than that of the dielectric layer at the gate groove as the dielectric layer at the source groove;

[0046] (f) using RIE etching and using photoresist as a mask to etch holes in the dielectric layer on both sides of the trench in the MOS region; the etching depth is ≥ the thickness of the dielectric layer;

[0047] (g) Sputtering metal to form the gate source of the MOSFET device and the anode of the diode device, wherein the source of the MOSFET and the anode of the MOS channel diode are the same electrode; and making a drain under the substrate.

[0048] A method for preparing a vertical MOS channel diode device and a MOSFET monolithic integrated device, wherein when the integrated device is provided with a body electrode, the method comprises the following steps:

[0049] (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer;

[0050] (b) Using SiO2 as a hard mask on the epitaxial structure, ICP (Cl2 / BCl3 / Ar) etching is performed to the n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer;

[0051] (c) removing the SiO2 hard mask on the surface and performing post annealing (PIA) to increase the hole activation rate inside the p-GaN; using ALD to deposit a layer of SiO2 film on the bottom and sidewall of the trench as a SiO2 dielectric layer;

[0052] (d) using RIE etching, using photoresist as a mask to etch holes in the dielectric layer on both sides of the trench, and etching to the p-GaN layer;

[0053] (e) Using electron beam evaporation, a body electrode is evaporated at the opening of the dielectric layer to form an ohmic contact with the p-GaN layer; then, a gate metal is evaporated in the gate groove and a source metal is evaporated in the source groove to form the gate source of the MOSFET device and the anode of the diode device, wherein the source of the MOSFET and the anode of the MOS channel diode are the same electrode.

[0054] The diode of the present application is not a Schottky diode, and all metals are not involved in forming Schottky contacts with semiconductors. The present application can realize a unipolar diode device with a higher breakdown level under relatively simple process. The process of forward conduction of the diode is as follows: the anode voltage of the diode gradually increases, and the electrons in the drift region can cross the potential barrier at the sidewall of the groove and enter the highly doped GaN layer to achieve conduction. The material of the transistor of the present invention is not limited to GaN, and can also be wide bandgap semiconductor materials such as SiC, GaO, AlN, and AlGaN.

[0055] The present application can realize the preparation of a unipolar (only electrons participate in the conduction of the device) diode device with fewer process steps, and has good on-resistance and turn-on voltage, and has excellent breakdown voltage. Therefore, when the device is reverse recovered, the switching speed is faster than when the body pn junction is turned on, and the switching loss is lower.

[0056] The MOS trench diode and MOSFET monolithic integrated device proposed in this application can achieve good third quadrant freewheeling characteristics without sacrificing the breakdown voltage of the integrated device, and can reduce the overall packaging difficulty and parasitic parameters caused by interconnection lines, making the system more stable and reliable.

[0057] The beneficial effects of the present invention are:

[0058] The present invention realizes a two-terminal device with a high breakdown voltage level by integrating the source and gate of MOSFET devices prepared by the same batch of processes. Since the conducting channel of the device is an electronic channel on the MOS side wall, the device is a unipolar device, which can effectively reduce the switching loss of the device.

[0059] The monolithic integration solution proposed in this application can effectively solve the problem of the breakdown voltage level being reduced due to the integrated Schottky diode device. In addition, since there are differences in the energy bands when the first three quadrants of the MOSFET structure are turned on, there are also differences in the turn-on voltages of the first three quadrants of the MOSFET structure. The MOS channel diode and MOSFET integrated device proposed in this application can simultaneously meet the higher threshold voltage of the first quadrant and the lower turn-on voltage of the third quadrant. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] Figure 1 Schematic diagram of the structure of the vertical GaN MOS channel diode of Example 1;

[0061] Figure 2 This is a schematic diagram of the structure of a vertical GaN MOS channel diode and MOSFET monolithic integrated device in Example 1;

[0062] Figure 3 This is a process flow chart of a vertical GaN MOS trench diode according to Example 2;

[0063] Figure 4 This is a process flow chart of a vertical GaN MOS channel diode and MOSFET monolithic integrated device according to Example 2;

[0064] Figure 5 is a forward characteristic curve of a vertical GaN MOS channel diode in Example 1;

[0065] Figure 6a This is a forward output curve diagram of the vertical GaN MOS channel diode and MOSFET monolithic integrated device of Example 2;

[0066] Figure 6b The transfer curve diagram of the vertical GaN MOS channel diode and MOSFET monolithic integrated device in Example 2;

[0067] Figure 7 The breakdown voltage diagram of the vertical GaN MOS channel diode and MOSFET monolithic integrated device and discrete device in Example 2;

[0068] Figure 8 This is a schematic diagram of the structure of a vertical GaN MOS channel diode and MOSFET monolithic integrated device according to Example 4;

[0069] Fig. 9 This is a process flow chart of a vertical GaN MOS channel diode and MOSFET monolithic integrated device according to Example 4;

[0070] Fig.10 This is a schematic diagram of the structure of a vertical GaN MOS channel diode and MOSFET monolithic integrated device according to Example 5;

[0071] Fig.11 This is a process flow chart of a vertical GaN MOS channel diode and MOSFET monolithic integrated device according to Example 5;

[0072] Fig.12 Schematic diagram of the structure of a vertical GaN MOS channel diode with p-GaN grounding according to Example 6;

[0073] Fig.13 FIG. 6 is a process flow chart of a vertical GaN MOS trench diode with p-GaN grounding according to Example 6;

[0074] Fig.14 The schematic diagram of the structure of a vertical GaN MOS channel diode and a MOSFET monolithic integrated device with p-GaN grounding according to Example 7;

[0075] Fig.15 This is a process flow chart of a vertical GaN MOS channel diode and MOSFET monolithic integrated device with p-GaN grounding according to Example 7. DETAILED DESCRIPTION

[0076] The present invention will be further described below by way of embodiments in conjunction with the accompanying drawings, but is not limited thereto.

[0077] Embodiment 1:

[0078] like Figure 1 As shown, a vertical MOS channel diode device, the epitaxial structure includes a substrate, n - -GaN drift layer, p-GaN layer and n + -GaN source layer; the n + -Etch a trench on the GaN source layer, extending to the n - -GaN drift layer, forming a trench in the MOS region; in the MOS trench region and n + - A dielectric layer is deposited on the surface of the GaN source layer, and n + -A hole is etched in the dielectric layer on the surface of the GaN source layer, and an anode metal is deposited at the hole and on the dielectric layer. The substrate material is Si, the dielectric layer is SiO2, and the anode metal is a double-layer metal Cr / Au.

[0079] The n - -GaN drift layer thickness is 7um, and doping concentration is unintentional doping.

[0080] The p-GaN layer has a thickness of 400 nm and a Mg doping concentration of 1×10 19 cm -3 .

[0081] The + -GaN source layer is a double-layer structure, with the Si doping concentration of the bottom layer being 5×10 18 cm -3 The 200nmGaN layer and the upper Si doping concentration are 1×10 19 cm -3 20nm GaN layer.

[0082] The SiO2 dielectric layer used is 100nm.

[0083] like Figure 3 As shown, the method for preparing the diode device described in Example 1 is:

[0084] (a) NPN epitaxial structure is grown by MOCVD, and 7um n - -GaN drift layer, 400nm p-GaN layer and 220nm n + -GaN source layer.

[0085] (b) Using SiO2 as a hard mask on the epitaxial structure, ICP (Cl2 / BCl3 / Ar) etching is performed to the n - -The upper part of the GaN drift layer has an etching depth of 1um.

[0086] (c) Remove the SiO2 hard mask on the surface and perform post-annealing (PIA) at 850°C in a nitrogen environment for 20 minutes to increase the hole activation rate inside the p-GaN. A 100nm thick SiO2 film is deposited on the bottom and sidewall of the MOS region trench using ALD as a SiO2 dielectric layer.

[0087] (d) RIE etching is used to etch the n-type MOS grooves on both sides of the grooves using photoresist as a mask. + - The dielectric layer on the surface of the GaN source layer is etched to open holes with an etching depth of 100 nm.

[0088] (e) Sputter 50 / 150nm of Cr / Au metal in the range where the two dielectric layer openings are opposite to each other, first sputter Cr and then sputter Au, to form a diode anode, and make a cathode under the substrate.

[0089] Embodiment 2:

[0090] like Figure 2 As shown, a vertical MOS channel diode and MOSFET monolithic integrated device includes, from bottom to top, a substrate, n - -GaN drift layer, p-GaN layer and n + -GaN source layer; wherein, from left to right, a gate groove and a source groove are arranged in sequence, and the gate groove and the source groove are both made of n + -GaN source layer is etched to n - -GaN drift layer; a dielectric layer is deposited on the bottom and sidewalls of the gate groove, and a gate metal is sputtered on the dielectric layer; a dielectric layer is deposited on the bottom and sidewalls of the source groove, and a source metal is sputtered on the dielectric layer. The epitaxial structure parameters are consistent with those of Example 1.

[0091] like Figure 4 As shown, the method for preparing the integrated device described in Example 2 is:

[0092] (a) NPN epitaxial structure is grown by MOCVD, and 7um n - -GaN drift layer, 400nm p-GaN layer and 220nm n + -GaN source layer.

[0093] (b) Using SiO2 as a hard mask, two trenches are etched by ICP (Cl2 / BCl3 / Ar) on the epitaxial structure, including the gate trench and the source trench, until the n - -The upper part of the GaN drift layer has an etching depth of 1um.

[0094] (c) Remove the SiO2 hard mask on the surface and perform post-annealing (PIA) at 850°C in a nitrogen environment for 20 minutes to increase the hole activation rate inside the p-GaN. A 100nm thick SiO2 film is deposited on the bottom and sidewall of the trench as a SiO2 dielectric layer using ALD.

[0095] (d) RIE etching is used to etch holes in the dielectric layer on both sides of the trench using photoresist as a mask, as shown in the figure, on the left side of the gate trench, between the gate trench and the source trench, and on the right side of the source trench; the etching depth is 100nm.

[0096] (e) Sputter 50 / 150nm of Cr / Au metal to form the gate source of the MOSFET device and the anode of the diode device, where the source of the MOSFET and the anode of the MOS channel diode are the same electrode; and make a drain under the substrate.

[0097] Depend on Figure 5 It can be seen that the third quadrant freewheeling start voltage of the MOS channel diode and MOSFET monolithic integrated device is 2.7V. Figure 6a and 6b It can be seen that the monolithic integrated device has good forward conduction characteristics, with a forward threshold voltage of 4.3V and a forward resistance of 9.43mΩ·cm 2 .Depend on Figure 7 It can be seen that the breakdown voltage of the monolithic integrated device is almost the same as that of the independent MOSFET device, which shows that the integrated MOS trench diode does not reduce the breakdown voltage level of the device. In addition, by comparing the breakdown voltage with the monolithic integrated MOSFET-SBD device (Comparative Example 1), it can be seen that the integrated MOS trench diode device can improve the problem of the breakdown voltage level reduction caused by the integrated Schottky diode.

[0098] Comparative Example 1

[0099] C. Liu, RA Khadar and E. Matioli, "Vertical GaN-on-Si MOSFETs with Monolithically Integrated Freewheeling Schottky Barrier Diodes," IEEE ElectronDevice Lett., vol.39, no.7, pp.1034-1037, Jul.2018, doi:10.1109 / LED.2018.2841959.

[0100] Example 3

[0101] A vertical MOS channel diode device has the same structure as that of the first embodiment, except that the dielectric layer of the device is 100nm Al2O3 and the substrate material is sapphire.

[0102] Example 4

[0103] A vertical MOS channel diode and MOSFET integrated device, the structure is as follows Figure 8 As shown, the difference from Example 2 is that the gate metal is Ni and the source metal is Al.

[0104] like Fig. 9 As shown, the method for preparing the integrated device described in Example 4 is:

[0105] (a) NPN epitaxial structure is grown by MOCVD, and 7um n - -GaN drift layer, 400nm p-GaN layer and 220nm n + -GaN source layer.

[0106] (b) Using SiO2 as a hard mask, two trenches were etched by ICP (Cl2 / BCl3 / Ar) on the epitaxial structure until n - -The upper part of the GaN drift layer has an etching depth of 1um.

[0107] (c) Remove the SiO2 hard mask on the surface and perform post-annealing (PIA) at 850°C in a nitrogen environment for 20 minutes to increase the hole activation rate inside the p-GaN. A 100nm thick SiO2 film is deposited on the bottom and sidewall of the MOS region trench using ALD as a SiO2 dielectric layer.

[0108] (d) Using photoresist as a mask, sputter 200nm Ni metal at the gate groove.

[0109] (e) removing the photoresist mask in step (d), and using a new photoresist mask to etch holes in the dielectric layer on both sides of the trench, such as Fig. 9 (e) shows the left side of the gate groove, between the gate groove and the source groove, and the right side of the source groove; the etching depth is 100nm.

[0110] (f) Sputter 200nm Al metal to form the gate source of the MOSFET device and the anode of the diode device, where the source of the MOSFET and the anode of the MOS channel diode are the same electrode; and make a drain under the substrate.

[0111] Example 5

[0112] A vertical MOS channel diode and MOSFET integrated device, the structure is as follows Fig.10 As shown, the difference from Example 2 is that the thickness of the SiO2 dielectric layer at the source groove is 50 nm, and the thickness of the SiO2 dielectric layer at the gate groove is 100 nm.

[0113] like Fig.11 As shown, the method for preparing the integrated device described in Example 5 is:

[0114] (a) NPN epitaxial structure is grown by MOCVD, and 7um n - -GaN drift layer, 400nm p-GaN layer and 220nm n + -GaN source layer.

[0115] (b) Using SiO2 as a hard mask on the epitaxial structure, ICP (Cl2 / BCl3 / Ar) etching is performed to the n - -The upper part of the GaN drift layer has an etching depth of 1um.

[0116] (c) Remove the SiO2 hard mask on the surface and perform post-annealing (PIA) at 850°C in a nitrogen environment for 20 minutes to increase the hole activation rate inside the p-GaN. A 100nm thick SiO2 film is deposited on the bottom and sidewall of the MOS region trench using ALD as a SiO2 dielectric layer.

[0117] (d) Use photoresist as a mask and sputter 200nm Ni metal at the gate groove. Remove the photoresist mask and use a new photoresist as a mask to open a hole on the right side of the gate groove with an etching depth of 100nm. Then perform ICP (Cl2 / BCl3 / Ar) etching on the source groove until the n - -The upper part of the GaN drift layer has an etching depth of 1um.

[0118] (e) Remove the surface SiO2 hard mask and use ALD to deposit a 50nm thick SiO2 film on the bottom and sidewall of the source groove as the SiO2 source groove dielectric layer.

[0119] (f) RIE etching is used to etch holes in the dielectric layer on both sides of the MOS region trench using photoresist as a mask. The etching depth is 200 nm.

[0120] (g) Sputter 50 / 150nm of Cr / Au metal to form the gate source of the MOSFET device and the anode of the diode device, where the source of the MOSFET and the anode of the MOS channel diode are the same electrode; and make a drain under the substrate.

[0121] Example 6

[0122] A vertical MOS trench diode device, such as Fig.12 As shown, the difference from Example 1 is that the device has a body electrode, and the dielectric layer is etched to open holes in the p-GaN layer, that is, the p-GaN layer is connected to the anode metal through a metal, and the metal used here is Pb.

[0123] The device is prepared differently from Example 1. Fig.13 As shown, the differences mainly focus on the steps (d) and (e) in Example 1, which are as follows:

[0124] (a) NPN epitaxial structure is grown by MOCVD, and 7um n - -GaN drift layer, 400nm p-GaN layer and 220nm n + -GaN source layer.

[0125] (b) Using SiO2 as a hard mask on the epitaxial structure, ICP (Cl2 / BCl3 / Ar) etching is performed to the n - -The upper part of the GaN drift layer has an etching depth of 1um.

[0126] (c) Remove the SiO2 hard mask on the surface and perform post-annealing (PIA) at 850°C in a nitrogen environment for 20 minutes to increase the hole activation rate inside the p-GaN. A 100nm thick SiO2 film is deposited on the bottom and sidewall of the MOS region trench using ALD as a SiO2 dielectric layer.

[0127] (d) RIE etching is performed by using photoresist as a mask to etch holes in the dielectric layer on both sides of the trench in the MOS region. The etching depth is 320 nm, and the p-GaN layer is etched.

[0128] (e) Using electron beam evaporation, the body electrode Pb is evaporated at the opening of the dielectric layer, and the body electrode contacts the p-GaN layer to form an ohmic contact; then, Cr / Au metal is evaporated in the range where the two dielectric layer openings are opposite to each other to form the anode of the diode.

[0129] Example 7

[0130] A vertical MOS channel diode and MOSFET monolithic integrated device, the unit structure is the same as that of embodiment 5, the device has a body electrode, such as Fig.14 As shown, from bottom to top, the substrate, n - -GaN drift layer, p-GaN layer and n + -GaN source layer; wherein, from left to right, a gate groove and a source groove are arranged in sequence, and the gate groove and the source groove are both made of n + -GaN source layer is etched to n - -GaN drift layer; a dielectric layer is deposited at the bottom and sidewalls of the gate groove, and a gate metal is sputtered on the dielectric layer; a dielectric layer is deposited at the bottom and sidewalls of the source groove, and a source metal is sputtered on the dielectric layer. Holes are etched in the dielectric layer on both sides of the groove until the p-GaN layer is etched, and metal Pb is provided in the hole, that is, the p-GaN layer is connected to the anode metal through metal, and the metal used here is Pb.

[0131] Process steps such as Fig.15 As shown:

[0132] (a) NPN epitaxial structure is grown by MOCVD, and 7um n - -GaN drift layer, 400nm p-GaN layer and 220nm n + -GaN source layer.

[0133] (b) Using SiO2 as a hard mask on the epitaxial structure, ICP (Cl2 / BCl3 / Ar) etching is performed to the n - -The upper part of the GaN drift layer has an etching depth of 1um.

[0134] (c) Remove the SiO2 hard mask on the surface and perform post-annealing (PIA) at 850°C in a nitrogen environment for 20 minutes to increase the hole activation rate inside the p-GaN. A 100nm thick SiO2 film is deposited on the bottom and sidewall of the trench as a SiO2 dielectric layer using ALD.

[0135] (d) RIE etching is performed using a photoresist as a mask to etch holes in the dielectric layer. The etching depth is 320 nm and the p-GaN layer is etched.

[0136] (e) Using electron beam evaporation, a body electrode is evaporated at the opening of the dielectric layer to form an ohmic contact between the body electrode and the p-GaN layer; then, metal is evaporated to form the gate source of the MOSFET device and the anode of the diode device, wherein the source of the MOSFET and the anode of the MOS channel diode are the same electrode.

[0137] Example 8

[0138] A vertical MOS channel diode device, the structure of which is as described in Example 1, except that the dielectric layer of the device is 50nm SiN. - The thickness of the -GaN drift layer is 3um, and the doping concentration is unintentional; the thickness of the p-GaN layer is 300nm, and the doping concentration of Mg is 5×10 18 cm -3 .

[0139] Example 9

[0140] A vertical MOS channel diode device, the structure of which is as described in Example 1, except that the dielectric layer of the device is 150nm HfO2. - The thickness of the -GaN drift layer is 8um, and the doping concentration is unintentional; the thickness of the p-GaN layer is 700nm, and the doping concentration of Mg is 2×10 19 cm -3 .

Claims

1. A vertical MOS channel diode device, characterized in that: The epitaxial structure includes substrate, n - -GaN drift layer, p-GaN layer and n + -GaN source layer; the n + -Etch a trench on the GaN source layer, extending to the n - -GaN drift layer, forming a trench in the MOS region; in the MOS trench region and n + - A dielectric layer is deposited on the surface of the GaN source layer, and n + A hole is etched into the dielectric layer on the surface of the GaN source layer, and an anode metal is deposited at the hole and on the dielectric layer.

2. The vertical MOS channel diode device according to claim 1, characterized in that: Includes one of the following options: Ⅰ. The substrate material is Si, sapphire, GaN, SiC, diamond, the dielectric layer is SiO2, Al2O3, SiN or HfO2, and the anode metal is Cr / Au double-layer metal or Al or Ni; II.n - The thickness of the -GaN drift layer is 3um-8um, and the doping concentration is unintentional; the thickness of the p-GaN layer is 300nm-700nm, and the doping concentration of Mg is 5×10 18 cm -3 -2×10 19 cm -3 ;n + -GaN source layer is a double-layer structure, with the Si doping concentration of the bottom layer being 5×10 18 cm -3 The 200nm GaN layer and the upper Si doping concentration are 1×10 19 cm -3 20nm GaN layer; the thickness of the dielectric layer is 50-150nm.

3. The vertical MOS channel diode device according to claim 2, characterized in that: n - The thickness of the -GaN drift layer is 7um, and the doping concentration is unintentional; the thickness of the p-GaN layer is 400nm, and the doping concentration of Mg is 2×10 19 cm -3 .

4. The vertical MOS channel diode device according to claim 1, characterized in that: The device has a body electrode, a dielectric layer is etched to open a hole to the p-GaN layer, a metal Pb is arranged in the hole, and the p-GaN layer is connected to the anode metal through the metal Pb.

5. A method for preparing the vertical MOS trench diode device according to claim 1, characterized in that: The steps include: (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer; (b) Groove etching is performed on the epitaxial structure until n - - Upper part of GaN drift layer; Trench etching depth > n + -The sum of the thickness of the GaN source layer and the p-GaN layer; (c) removing the surface mask, performing post-annealing treatment, and depositing a layer of SiO2 film as a dielectric layer on the bottom and sidewall of the MOS region trench; (d) Use photoresist as a mask to cut n on both sides of the MOS region trench. + -Etching the dielectric layer on the surface of the GaN source layer to open holes, and the etching depth is ≥ the thickness of the dielectric layer; (e) Sputtering metal in the range where the two dielectric layer openings are opposite to each other to form a diode anode, and making a cathode under the substrate.

6. The method for preparing a vertical MOS channel diode according to claim 5, characterized in that: In step (d), when the body electrode is not formed, the etching depth is 100 nm to 200 nm; when the body electrode is formed, the etching is performed to the p-GaN layer.

7. The method for preparing a vertical MOS channel diode according to claim 5, characterized in that: In step (e), 50 / 150nm of Cr / Au double-layer metal is sputtered, the Cr metal layer is 50nm thick, and the Au metal layer is 150nm thick; when making the body electrode, the body electrode Pb is evaporated at the opening of the dielectric layer, and the body electrode contacts the p-GaN layer to form an ohmic contact; then, the Cr / Au double-layer metal is evaporated in the range relative to the openings of the two dielectric layers to form the anode of the diode.

8. An integrated device using the vertical MOS channel diode and MOSFET monolithically integrated as claimed in claim 1, characterized in that: From bottom to top, wrap the substrate, n - -GaN drift layer, p-GaN layer and n + -GaN source layer; wherein, from left to right, a gate groove and a source groove are arranged in sequence, and the gate groove and the source groove are both made of n + -GaN source layer is etched to n - -GaN drift layer; a dielectric layer is deposited on the bottom and sidewalls of the gate groove, and a gate metal is sputtered on the dielectric layer; a dielectric layer is deposited on the bottom and sidewalls of the source groove, and a source metal is sputtered on the dielectric layer.

9. The vertical MOS channel diode device and MOSFET monolithic integrated device according to claim 8, characterized in that: Includes one of the following options: Ⅰ. The gate metal is Cr / Au double-layer metal or Al or Ni, and the source metal is Cr / Au double-layer metal or Al or Ni; Ⅱ. The thickness of the dielectric layer in the gate trench is greater than that in the source trench; III. The integrated device is provided with a body electrode, holes are etched in the dielectric layer on both sides of the groove, and the hole is etched to the p-GaN layer. Metal Pb is provided in the hole, and the p-GaN layer is connected to the anode metal through the metal Pb.

10. A method for preparing the vertical MOS channel diode and MOSFET monolithic integrated device according to claim 9, characterized in that: Includes one of the following options: Ⅰ. When the thickness of the dielectric layer at the gate groove is equal to the thickness of the dielectric layer at the source groove, and the gate metal and the source metal are made of the same material, the following steps are included: (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer; (b) Etching two or more trenches on the epitaxial structure, including gate trenches and source trenches, until n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer; (c), removing the surface mask and performing post-annealing treatment; using ALD to deposit a 50-150nm thick SiO2 film as a SiO2 dielectric layer on the bottom and sidewall of the gate groove and the source groove, and the dielectric layer material is selected from SiO2, Al2O3, SiN or HfO2; (d) Using photoresist as a mask, the dielectric layer is etched to open holes on both sides of the trench, and the etching depth is ≥ the thickness of the dielectric layer; (e) forming a gate metal in the gate groove, forming a source metal in the source groove, and forming a drain under the substrate; II. When the thickness of the dielectric layer at the gate groove is equal to the thickness of the dielectric layer at the source groove, and the gate metal and the source metal are different in material, the steps are as follows: (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer; (b) Etching two or more trenches on the epitaxial structure, including gate trenches and source trenches, until n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer; (c) removing the surface mask and performing post-annealing treatment; using ALD to deposit a 50-150nm thick SiO2 film as a dielectric layer on the bottom and sidewall of the gate groove and the source groove; (d) using photoresist as a mask and sputtering gate metal at the gate groove; (e) removing the photoresist mask in step (d), and using a new photoresist mask to etch holes in the dielectric layer on both sides of the groove, wherein the etching depth is ≥ the thickness of the dielectric layer; (f) sputtering source metal to make a drain under the substrate, and the drain is connected to the cathode through the substrate; III. When the thickness of the dielectric layer in the gate trench is greater than the thickness of the dielectric layer in the source trench, the method comprises the following steps: (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer; (b) Etching the gate groove on the epitaxial structure until the gate groove is n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer; (c), removing the surface mask and performing post-annealing treatment; A layer of SiO2 film is deposited as a dielectric layer in the gate groove by ALD; (d) using photoresist as a mask and sputtering metal at the gate groove; Remove the photoresist mask, use a new photoresist as a mask to open a hole on the right side of the gate groove, and the etching depth is ≥ the thickness of the dielectric layer; Then the source trench is etched to n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer; (e) removing the surface mask, and using ALD to deposit a SiO2 film having a thickness smaller than that of the dielectric layer at the gate groove as the dielectric layer at the source groove; (f) using RIE etching and using photoresist as a mask to etch holes in the dielectric layer on both sides of the trench in the MOS area; Etching depth ≥ thickness of dielectric layer; (g) sputtering metal to form the gate source of the MOSFET device and the anode of the diode device, wherein the source of the MOSFET and the anode of the MOS channel diode are the same electrode; forming a drain electrode below the substrate; IV. When the integrated device has a body electrode, the steps include: (a) Growing NPN epitaxial structure by MOCVD, epitaxially growing n - -GaN drift layer, p-GaN layer and n + -GaN source layer; (b) Use SiO2 as a hard mask to perform trench etching on the epitaxial structure until the n - -GaN drift layer upper part, etching depth>n + -The sum of the thickness of the GaN source layer and the p-GaN layer; (c), removing the surface SiO2 hard mask and performing post-annealing treatment; using ALD to deposit a layer of SiO2 film as a SiO2 dielectric layer on the bottom and sidewall of the trench; (d) using RIE etching, using photoresist as a mask to etch holes in the dielectric layer on both sides of the trench, and etching to the p-GaN layer; (e) using electron beam evaporation to deposit a body electrode at the opening of the dielectric layer, so that the body electrode forms an ohmic contact with the p-GaN layer; Then, gate metal is evaporated in the gate groove, and source metal is evaporated in the source groove to form the gate source of the MOSFET device and the anode of the diode device, wherein the source of the MOSFET and the anode of the MOS channel diode are the same electrode.

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