Manufacturing method of semiconductor structure

Abstract

The invention discloses a method for manufacturing a semiconductor structure, which comprises the following steps of: providing a substrate which is provided with a dielectric layer and a gate trench formed in the dielectric layer; and performing a physical vapor deposition process on the substrate in a PVD chamber equipped with an automatic capacitance tuner, depositing a metal layer on a top surface of the dielectric layer and an inner surface of the gate trench. The physical vapor deposition process includes: (i) adjusting an automatic capacitance tuner to provide a positive radio frequency (RF) bias to a substrate in a PVD chamber for a first period of time; (ii) The auto-capacitance tuner is then adjusted to provide a negative RF bias to the substrate in the PVD chamber for a second period of time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure. Background Art

[0002] High-k dielectric layers and metal gate electrodes have been introduced into complementary metal oxide semiconductor (CMOS) logic technology and integrated into semiconductor processes using gate-first and gate-last schemes.

[0003] The gate-last process can solve the problem of high-temperature processing of metal materials. In the gate-last process, a dummy polysilicon gate is first formed and is not removed until the interlayer dielectric layer (ILD) is deposited. In a subsequent stage, the dummy polysilicon gate can be replaced with a metal gate. The metal gate is then polished to the desired gate height.

[0004] As gate length and device spacing decrease, it is difficult for transistors to achieve low gate resistance because voids are created in the metal gate electrode after depositing the metal layer to fill the high-aspect-ratio trench. In particular, the work function metal layer of the NMOS transistor is more susceptible to problems such as overhang, too thin sidewall deposition thickness, and bottom hump profile due to uneven deposition. Summary of the invention

[0005] The main purpose of the present invention is to provide an improved method for manufacturing a semiconductor structure to solve the deficiencies or shortcomings of the prior art.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A method for manufacturing a semiconductor structure comprises: providing a substrate having a dielectric layer and a gate trench formed in the dielectric layer; and performing a physical vapor deposition process on the substrate in a physical vapor deposition (PVD) chamber equipped with an automatic capacitance tuner to conformally deposit a metal layer on a top surface of the dielectric layer and an inner surface of the gate trench, wherein the physical vapor deposition process comprises: (i) adjusting the automatic capacitance tuner to provide a positive radio frequency (RF) bias to the substrate in the PVD chamber during a first time period; and (ii) subsequently adjusting the automatic capacitance tuner to provide a negative RF bias to the substrate in the PVD chamber during a second time period.

[0008] According to an embodiment of the present invention, the dielectric layer includes a silicon oxide layer.

[0009] According to an embodiment of the present invention, the method further includes: forming a contact etch stop layer between the dielectric layer and the substrate.

[0010] According to an embodiment of the present invention, the method further includes: forming a spacer layer between the metal layer and the contact etching stop layer.

[0011] According to an embodiment of the present invention, the semiconductor structure is a metal gate of an NMOS transistor.

[0012] According to an embodiment of the present invention, the metal layer is an NMOS work function layer.

[0013] According to an embodiment of the present invention, the metal layer includes TiAl.

[0014] According to an embodiment of the present invention, the method further includes: depositing a barrier layer on the metal layer in the gate trench.

[0015] According to an embodiment of the present invention, the barrier layer includes TiN.

[0016] According to an embodiment of the present invention, the method further includes: depositing an adhesion layer on the barrier layer in the gate trench.

[0017] According to an embodiment of the present invention, the adhesion layer includes Ti.

[0018] According to an embodiment of the present invention, the method further includes: depositing a low resistance conductive layer on the adhesion layer in the gate trench, wherein the metal layer, the barrier layer, the adhesion layer and the low resistance conductive layer completely fill the gate trench.

[0019] According to an embodiment of the present invention, the low-resistance conductive layer includes Al.

[0020] According to an embodiment of the present invention, the positive RF bias voltage is +85V, and the first time period is 10 seconds to 30 seconds.

[0021] According to an embodiment of the present invention, the negative RF bias voltage is 0V to -250V, and the second time period is 10 to 30 seconds.

[0022] According to an embodiment of the present invention, the thickness of the metal layer is 80 to 120 angstroms. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figures 1 to 4 A schematic diagram of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0024] Figure 5 Schematic diagram of a PVD chamber equipped with an automatic capacitance tuner.

[0025] Main component symbols

[0026] 1PVD Room

[0027] 2 Housing

[0028] 3. Substrate support base

[0029] 4 Target

[0030] 5 Automatic Capacitor Tuner

[0031] 100 Substrate

[0032] 102 Trench insulation structure

[0033] 104 Doping region

[0034] 106 Doping region

[0035] 110 Spacer

[0036] 120 Contact Etch Stop Layer

[0037] 210 Interlayer dielectric layer

[0038] 310 Gate dielectric layer

[0039] 320 Metal Layer

[0040] 330 Barrier layer

[0041] 340 Adhesive layer

[0042] 350 Low resistance conductive layer

[0043] AA Active Area

[0044] H Depth

[0045] MG Metal Gate

[0046] NR NMOS transistor area

[0047] T Gate Trench

[0048] w Width DETAILED DESCRIPTION

[0049] In the following, the details will be described with reference to the accompanying drawings, which also constitute part of the detailed description of the specification and are illustrated in a specific way that the embodiment can be implemented. The following embodiments have been described in sufficient detail to enable a person skilled in the art to implement them.

[0050] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be considered as limiting, but rather, the embodiments included therein will be defined by the appended claims.

[0051] See also Figures 1 to 4 , which is a schematic diagram of a method for manufacturing a semiconductor structure according to an embodiment of the present invention. According to an embodiment of the present invention, the semiconductor structure may be a metal gate of an NMOS transistor. Figure 1 As shown, a substrate 100 is provided, for example, a silicon substrate. An NMOS transistor region NR is included on the substrate 100. A trench insulating structure 102 is formed in the substrate 100 in the NMOS transistor region NR to electrically insulate the active region AA. Doped regions 104 and 106 may be formed in the substrate 100 in the active region AA. For example, the doped regions 104 and 106 may be N-type doped regions, which may serve as the source and drain of the NMOS transistor.

[0052] According to an embodiment of the present invention, after forming an interlayer dielectric layer 210 on the substrate 100 using a gate-last process, the dummy polysilicon gate (not shown) is removed to form a gate trench T. The width w of the gate trench T is equal to the distance between two opposite inner surfaces of the spacer layer 110. According to an embodiment of the present invention, for example, the width w may be between 200 and 300 angstroms, but is not limited thereto. According to an embodiment of the present invention, for example, the depth H of the gate trench T may be between 400 and 500 angstroms, but is not limited thereto. According to an embodiment of the present invention, for example, the aspect ratio (H / w) of the gate trench T may be between 1.5 and 2.

[0053] According to an embodiment of the present invention, for example, the interlayer dielectric layer 210 may include silicon oxide or a low dielectric constant material layer, but is not limited thereto. According to an embodiment of the present invention, for example, the spacer layer 110 may include silicon oxide or silicon oxynitride, etc. According to an embodiment of the present invention, a contact etch stop layer 120, for example, a silicon nitride layer, may be formed between the spacer layer 110 and the interlayer dielectric layer 210.

[0054] According to an embodiment of the present invention, a gate dielectric layer 310 may be formed at the bottom of the gate trench T. According to an embodiment of the present invention, the gate dielectric layer 310 may include a silicon oxide layer or a high dielectric constant material layer, such as hafnium oxide, but is not limited thereto.

[0055] Then, if Figure 2As shown, a physical vapor deposition process is performed on the substrate 100 in a physical vapor deposition (PVD) chamber equipped with an auto capacitance tuner (ACT), and a metal layer 320 is conformally deposited on the top surface 210a of the interlayer dielectric layer 210 and the inner surface of the gate trench T. According to an embodiment of the present invention, the metal layer 320 is an NMOS work function layer. According to an embodiment of the present invention, for example, the metal layer 320 may include TiAl. According to an embodiment of the present invention, the thickness of the metal layer 320 is 80-120 angstroms, for example, 100 angstroms.

[0056] Figure 5 A PVD chamber equipped with an automatic capacitance tuner is illustrated. The PVD chamber 1 includes a grounded shell (shield) 2, in which at least a substrate support base (substrate support) 3, a target (target) 4, and an automatic capacitance tuner 5 connected to the substrate support base 3 are configured. The automatic capacitance tuner 5 adjusts the capacitance (and impedance) from the substrate support base electrode to the ground. In some embodiments, the current on the automatic capacitance tuner 5 can be measured to determine the ion energy at the substrate 100, and if necessary, the position or set point of the automatic capacitance tuner 5 can be adjusted in response to the measured current to maintain the ion energy at the substrate 100 at a desired level. Alternatively, the bias voltage on the substrate 100 can be measured and used to determine whether the actual ion energy needs to be increased or decreased (and the automatic capacitance tuner 5 is adjusted) to maintain the ion energy at the substrate 100 at a desired level.

[0057] According to an embodiment of the present invention, for example, the physical vapor deposition process includes: (i) adjusting the automatic capacitance tuner 5 to provide a positive radio frequency (RF) bias to the substrate 100 in the PVD chamber 1 in a first time period; (ii) subsequently adjusting the automatic capacitance tuner 5 to provide a negative RF bias to the substrate 100 in the PVD chamber 1 in a second time period. According to an embodiment of the present invention, the positive RF bias is +85V, and the first time period is 10 seconds to 30 seconds. According to an embodiment of the present invention, the negative RF bias is 0V to -250V, and the second time period is 10 to 30 seconds. According to an embodiment of the present invention, the above steps (i) and (ii) can be repeated.

[0058] like Figure 3As shown, then, a barrier layer 330 is deposited on the metal layer 320 in the gate trench T. According to an embodiment of the present invention, for example, the barrier layer may include TiN, but is not limited thereto. According to an embodiment of the present invention, then, an adhesive layer 340 is deposited on the barrier layer 330 in the gate trench T. According to an embodiment of the present invention, for example, the adhesive layer may include Ti, but is not limited thereto. According to an embodiment of the present invention, then, a low-resistance conductive layer 350 is deposited on the adhesive layer 340 in the gate trench T, wherein the metal layer 320, the barrier layer 330, the adhesive layer 340 and the low-resistance conductive layer 350 completely fill the gate trench T. According to an embodiment of the present invention, for example, the low-resistance conductive layer 350 may include Al, but is not limited thereto.

[0059] like Figure 4 As shown, a chemical mechanical polishing (CMP) process is then performed to remove the metal layer 320 , the barrier layer 330 , the adhesive layer 340 and the low resistance conductive layer 350 on the top surface 210 a of the interlayer dielectric layer 210 , thereby forming a metal gate MG.

[0060] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate having a dielectric layer and a gate trench formed in the dielectric layer; as well as Performing a physical vapor deposition process on a substrate in a physical vapor deposition chamber equipped with an automatic capacitance tuner to conformally deposit a metal layer on a top surface of the dielectric layer and an inner surface of the gate trench, wherein the physical vapor deposition process comprises: (i) adjusting the automatic capacitance tuner to provide a positive radio frequency bias to the substrate in the physical vapor deposition chamber during a first time period; (ii) subsequently adjusting the automatic capacitance tuner to provide a negative radio frequency bias to the substrate in the physical vapor deposition chamber for a second time period.

2. The method according to claim 1, characterized in that: The dielectric layer includes a silicon oxide layer.

3. The method according to claim 1, characterized in that: Also includes: A contact etch stop layer is formed between the dielectric layer and the substrate.

4. The method according to claim 3, characterized in that: Also includes: A spacer layer is formed between the metal layer and the contact etch stop layer.

5. The method according to claim 1, characterized in that: The semiconductor structure is a metal gate of an NMOS transistor.

6. The method according to claim 5, characterized in that: The metal layer is an NMOS work function layer.

7. The manufacturing method according to claim 1, characterized in that: The metal layer includes TiAl.

8. The manufacturing method according to claim 1, characterized in that: Also includes: A barrier layer is deposited on the metal layer within the gate trench.

9. The manufacturing method according to claim 8, characterized in that: The barrier layer includes TiN.

10. The manufacturing method according to claim 8, characterized in that: Also includes: An adhesion layer is deposited on the barrier layer within the gate trench.

11. The manufacturing method according to claim 10, characterized in that: The adhesion layer includes Ti.

12. The manufacturing method according to claim 10, characterized in that: Also includes: A low resistance conductive layer is deposited on the adhesion layer in the gate trench, wherein the metal layer, the barrier layer, the adhesion layer and the low resistance conductive layer completely fill the gate trench.

13. The manufacturing method according to claim 12, characterized in that: The low resistance conductive layer includes Al.

14. The manufacturing method according to claim 1, characterized in that: The positive RF bias voltage is +85V, and the first time period is 10 seconds to 30 seconds.

15. The manufacturing method according to claim 14, characterized in that: The negative RF bias voltage is 0V to -250V, and the second time period is 10 to 30 seconds.

16. The manufacturing method according to claim 1, characterized in that: The thickness of the metal layer is 80 to 120 angstroms.

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