Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, the semiconductor structure comprises a substrate, and the substrate comprises a partition region and an active region; the fin part is located on the substrate of the active region; the isolation layer is located on the substrate and comprises a first isolation layer and a second isolation layer; wherein the first isolation layers are located on the substrate of the partition region and the active region, the first isolation layers of the active region cover the side walls of the fin parts, and the first isolation layers of the partition region are separately arranged at intervals in the arrangement direction of the fin parts; the second isolation layers are located on the substrate of the partition area, the second isolation layers are located between the adjacent first isolation layers, and the tops of the second isolation layers are flush with the tops of the first isolation layers of the active area. According to the invention, the stress effect of the process of removing the fin part on the residual fin part is reduced, and when the second isolation layer is formed, part of the first isolation layer is still arranged on the substrate of the isolation region, so that the stress effect of the formation of the second isolation layer on the fin part of the active region adjacent to the isolation region is reduced, and the probability of the fin part bending problem is reduced.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits develop in the direction of smaller size, higher circuit precision and higher circuit complexity.

[0003] In order to better adapt to the requirement of device size reduction, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as Fin Field Effect Transistor (FinFET). Among them, in Fin Field Effect Transistor, the gate surrounds the fin-shaped channel on three sides. Compared with planar transistors, the gate of Fin Field Effect Transistor has stronger control over the channel and can better suppress the short channel effect.

[0004] In the semiconductor field, a fin cut process is usually used to remove unnecessary fins according to process requirements. However, the performance of the fin field effect transistor formed after the fin cut process still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate comprising an isolation region and an active region; a fin, located on the substrate of the active region; an isolation layer, located on the substrate, the isolation layer comprising a first isolation layer and a second isolation layer; wherein the first isolation layer is located on the substrate of the isolation region and the active region, the first isolation layer of the active region covers the side walls of the fin, and the first isolation layer of the isolation region is spaced and discretely arranged along the arrangement direction of the fin; the second isolation layer is located on the substrate of the isolation region, the second isolation layer is located between adjacent first isolation layers, and the top of the second isolation layer is flush with the top of the first isolation layer of the active region.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an isolation region and an active region, fins being formed on the substrate of the isolation region and the active region; forming a first isolation layer on the substrate on the side of the fin, the first isolation layer covering the side walls of the fin; removing a portion of the thickness of the fin and the first isolation layer of the isolation region, forming a first groove in the isolation region, the first groove being surrounded by the remaining fin and the first isolation layer, and the first isolation layer of the active region; removing the fin at the bottom of the first groove, forming a second groove connected to the first groove, the second groove exposing the top of the substrate of the isolation region; forming a second isolation layer in the first groove and the second groove, the second isolation layer covering the side walls of the first groove, the second isolation layer and the first isolation layer constituting an isolation layer.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present invention, the isolation layer includes a first isolation layer and a second isolation layer, the first isolation layer is located on the substrate of the partition area and the active area, the first isolation layer of the active area covers the side wall of the fin, and the first isolation layer of the partition area is arranged separately along the arrangement direction of the fin; the second isolation layer is located on the substrate of the partition area, the second isolation layer is located between adjacent first isolation layers, and the top of the second isolation layer is flush with the top of the first isolation layer of the active area; the isolation layer is formed step by step by the first isolation layer and the second isolation layer, usually first on the substrate on the side of the fin A first isolation layer is formed on the substrate, the first isolation layer covers the side walls of the fin, and then the fin and the first isolation layer of the partition area are partially removed to form a first groove in the partition area; after the first groove is formed, the fin at the bottom of the first groove is first removed to form a second groove connected to the first groove, and then a second isolation layer is formed in the first groove and the second groove, so that the second isolation layer in the isolation area is located between adjacent first isolation layers. Since the side walls of the fin are covered with the first isolation layer, the stress of the process of removing the fin on the remaining fin is reduced, thereby reducing the probability of the fin bending problem occurring in the fin, and correspondingly improving the quality of the fin; moreover, when forming the second isolation layer, there is still a partial thickness of the first isolation layer on the substrate of the partition area, that is, the thickness of the formed second isolation layer is relatively small, thereby reducing the stress of the formation of the second isolation layer on the fin of the active area adjacent to the partition area, thereby also reducing the probability of the fin bending problem occurring in the fin, and correspondingly improving the quality of the fin, thereby improving the performance of the semiconductor structure.

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a first isolation layer is first formed on the substrate on the side of the fin, the first isolation layer covers the side wall of the fin, and then a partial thickness of the fin and the first isolation layer in the isolation area are removed to form a first groove in the isolation area; after the first groove is formed, the fin at the bottom of the first groove is first removed to form a second groove connected to the first groove, and then a second isolation layer is formed in the first groove and the second groove, the second isolation layer covers the side wall of the first groove, so that the second isolation layer in the isolation area is located between adjacent first isolation layers, and the second isolation layer and the first isolation layer constitute an isolation layer. It can be seen that the isolation layer is formed step by step by the first isolation layer and the second isolation layer in sequence. In the process of forming the first groove, since the side wall of the fin is covered with the first isolation layer, the stress of the process of removing the fin on the remaining fin is reduced, thereby reducing the probability of the fin bending problem occurring in the fin, and correspondingly improving the quality of the fin; moreover, when forming the second isolation layer, there is still a partial thickness of the first isolation layer on the substrate in the partition area, that is, the thickness of the formed second isolation layer is relatively small, thereby reducing the stress effect of the formation of the second isolation layer on the fin of the active area adjacent to the partition area, thereby reducing the probability of the fin bending problem occurring in the fin, and correspondingly improving the quality of the fin, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figure 6 It is a structural schematic diagram of a semiconductor structure of the present invention;

[0013] Figure 7 is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention;

[0014] Figures 8 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0015] At present, the performance of semiconductor structures still needs to be improved. Now, combined with a method for forming a semiconductor structure, the reasons why the performance of semiconductor structures needs to be improved are analyzed.

[0016] Figures 1 to 5 The present invention is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure: wherein, Figure 4 yes Figure 3 A partial enlarged view of area A.

[0017] refer to Figure 1A substrate 10 is provided, wherein the substrate 10 includes a partition region I' and an active region II', and fins 11 are formed on the substrate 10 in the partition region I' and the active region II'.

[0018] refer to Figure 2 , the fin 11 of the partition area I' is removed, and a first groove 12 is formed in the partition area I'.

[0019] refer to Figure 3 After removing the fins 11 of the partition region I′, the substrate 10 and the remaining fins 11 are wet stripped.

[0020] refer to Figure 5 After wet processing, an isolation layer 13 is formed in the first groove 12 and on the substrate 10 at the side of the fin 11 of the active area II', and the isolation layer 13 also covers the side wall of the fin 11 of the active area II'.

[0021] like Figure 4 As shown, research has found that as the process nodes continue to shrink, the aspect ratio of the height of the fin 11 and the space between adjacent fins 11 continues to increase. Since the capillary force between the chemical solution used in the wet processing process and the fins 11 changes, the chemical solution is difficult to be completely removed, so that the chemical solution remaining due to the capillary force has a stress effect on the fins 11, which makes it easy for the fins 11 to bend or even the adjacent fins 11 to fuse.

[0022] On the other hand, since the fins 11 in the isolation area I' are removed, the semiconductor structure has a dense area of ​​the fins 11 and a sparse area of ​​the fins 11, so that in the process of forming the isolation layer 13 in the first groove 12 and on the substrate 10 at the side of the fins 11 in the active area II', stress is easily generated on the fins 11, which also leads to the problem of bending of the fins 11 and even fusion of adjacent fins 11 (such as Figure 4 shown).

[0023] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate, the substrate including a partition area and an active area; a fin, located on the substrate of the active area; an isolation layer, located on the substrate, the isolation layer including a first isolation layer and a second isolation layer; wherein, the first isolation layer is located on the substrate of the partition area and the active area, the first isolation layer of the active area covers the side wall of the fin, and the first isolation layer of the partition area is spaced and discretely arranged along the arrangement direction of the fin; the second isolation layer is located on the substrate of the partition area, the second isolation layer is located between adjacent first isolation layers, and the top of the second isolation layer is flush with the top of the first isolation layer of the active area.

[0024] In the semiconductor structure provided by the embodiment of the present invention, the isolation layer includes a first isolation layer and a second isolation layer, the first isolation layer is located on the substrate of the partition area and the active area, the first isolation layer of the active area covers the side wall of the fin, and the first isolation layer of the partition area is arranged separately along the arrangement direction of the fin; the second isolation layer is located on the substrate of the partition area, the second isolation layer is located between adjacent first isolation layers, and the top of the second isolation layer is flush with the top of the first isolation layer of the active area; the isolation layer is formed step by step by the first isolation layer and the second isolation layer, usually first on the substrate on the side of the fin A first isolation layer is formed on the substrate, the first isolation layer covers the side walls of the fin, and then the fin and the first isolation layer of the partition area are partially removed to form a first groove in the partition area; after the first groove is formed, the fin at the bottom of the first groove is first removed to form a second groove connected to the first groove, and then a second isolation layer is formed in the first groove and the second groove, so that the second isolation layer in the isolation area is located between adjacent first isolation layers. Since the side walls of the fin are covered with the first isolation layer, the stress of the process of removing the fin on the remaining fin is reduced, thereby reducing the probability of the fin bending problem occurring in the fin, and correspondingly improving the quality of the fin; moreover, when forming the second isolation layer, there is still a partial thickness of the first isolation layer on the substrate of the partition area, that is, the thickness of the formed second isolation layer is relatively small, thereby reducing the stress of the formation of the second isolation layer on the fin of the active area adjacent to the partition area, thereby also reducing the probability of the fin bending problem occurring in the fin, and correspondingly improving the quality of the fin, thereby improving the performance of the semiconductor structure.

[0025] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] refer to Figure 6 , Figure 6It is a structural schematic diagram of a semiconductor structure of the present invention;

[0027] In this embodiment, the semiconductor structure includes: a substrate 110, wherein the substrate 110 includes a partition region i and an active region ii; a fin 120, located on the substrate 110 in the active region ii; an isolation layer 145, located on the substrate 110, wherein the isolation layer 145 includes a first isolation layer 140 and a second isolation layer 141; wherein the first isolation layer 140 is located on the substrate 110 in the partition region i and the active region ii, the first isolation layer 140 in the active region ii covers the side wall of the fin 130, and the first isolation layer 140 in the partition region i is arranged separately and at intervals along the arrangement direction of the fin 120; the second isolation layer 141 is located on the substrate 110 in the partition region i, the second isolation layer 141 is located between adjacent first isolation layers 140, and the top of the second isolation layer 141 is flush with the top of the first isolation layer 140 in the active region ii.

[0028] The substrate 110 is used to provide an operating basis for a semiconductor structure forming process.

[0029] In this embodiment, the substrate 110 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0030] In this embodiment, the substrate 110 is used to form a fin field effect transistor (FinFET).

[0031] The isolation region i is used to achieve isolation between the active regions ii, and is also used to provide a process platform for forming the second isolation layer 141 .

[0032] The active area ii is used to provide a process platform for forming various semiconductor devices.

[0033] In this embodiment, the top of the substrate 110 in the isolation region i is lower than the top of the substrate 110 in the active region ii.

[0034] During the formation of the semiconductor structure, a partial thickness of the initial substrate (not shown) is usually etched first to form a substrate 110 and a fin 120 protruding from the surface of the substrate 110, and then the fin 120 of the partition area i is removed. The top of the substrate 110 in the partition area i is lower than the top of the substrate 110 in the active area ii, which is beneficial in ensuring that the fin 120 in the partition area i can be removed cleanly during the removal of the fin 120 in the partition area i, thereby improving the problem of the performance of the semiconductor structure being affected by the residual fin 120 in the partition area i.

[0035] It should be noted that the vertical distance l between the bottom of the substrate 110 of the partition area i and the top of the substrate 110 of the active area ii should not be too large or too small. If the vertical distance l between the bottom of the substrate 110 of the partition area i and the top of the substrate 110 of the active area ii is too large, it is easy for the substrate 110 of the partition area i to be difficult to meet the process requirements. If the vertical distance l between the bottom of the substrate 110 of the partition area i and the top of the substrate 110 of the active area ii is too small, it is easy to increase the probability of the fin 120 of the partition area i remaining. Therefore, in this embodiment, the vertical distance l between the bottom of the substrate 110 of the partition area i and the top of the substrate 110 of the active area ii is 50 angstroms to 350 angstroms.

[0036] The fin 120 provides a process basis for forming an active fin, which is used to provide a conductive channel when the semiconductor device is working.

[0037] The material of the fin 120 includes one or more of silicon, silicon germanium, germanium and III-V semiconductor materials. The material of the fin 120 is determined according to the channel conductivity type and performance requirements of the transistor.

[0038] As an example, the material of the fin 120 is single crystal silicon, and the material of the fin 120 and the substrate 110 is the same.

[0039] The isolation layer 145 is used to isolate each semiconductor device to prevent leakage current from occurring between the devices.

[0040] Typically, a first isolation layer 140 is first formed on the substrate 110 at the side of the fin 120, the first isolation layer 140 covers the sidewall of the fin 120, and then a portion of the thickness of the fin 120 and the first isolation layer 140 in the partition area i is removed to form a first groove (not shown in the figure); after the first groove is formed, the fin 120 at the bottom of the first groove is first removed to form a second groove connected to the first groove (not shown in the figure), and then a second isolation layer 141 is formed in the first groove and the second groove, so that the first isolation layer 140 in the isolation area i is arranged separately along the arrangement direction of the fin 120, and the second isolation layer 141 of the isolation area i is located between adjacent first isolation layers 140, The side walls of the fin 120 are covered with a first isolation layer 140, which reduces the stress of the process of removing the fin 120 on the remaining fin 120, thereby reducing the probability of the fin 120 bending problem occurring in the fin 120, and correspondingly improving the quality of the fin 120; moreover, when forming the second isolation layer 141, a partial thickness of the first isolation layer 140 is still present on the substrate 110 of the partition area i, that is, the thickness of the formed second isolation layer 141 is relatively small, thereby reducing the stress of the formation of the second isolation layer 141 on the fin 120 of the active area ii adjacent to the partition area i, thereby also reducing the probability of the fin 120 bending problem occurring in the fin 120, and correspondingly improving the quality of the fin 120, thereby improving the performance of the semiconductor structure.

[0041] It should be noted that, in the partition region i, along the direction perpendicular to the sidewall of the fin 120, the top surface width d of the second isolation layer 141 between adjacent first isolation layers 140 should not be too small or too large. If the top surface width d of the second isolation layer 141 is too small, the corresponding opening size of the second groove is also too small, which is easy to increase the process difficulty of forming the second isolation layer 141 in the second groove; if the width d of the second isolation layer 141 is too large, the corresponding opening size of the second groove is also too large, which is easy to increase the probability of the first isolation layer 140 being damaged during the formation of the second groove, and correspondingly, the probability of the fin 120 in the active region ii being damaged is easily increased. Therefore, in this embodiment, in the partition region i, along the direction perpendicular to the sidewall of the fin 120, the top surface width d of the second isolation layer 141 between adjacent first isolation layers 140 is 10 nanometers to 17 nanometers.

[0042] In the present embodiment, the first isolation layer 140 of the active area ii covers the side wall of the fin 120, which means that the first isolation layer 140 of the active area ii covers part of the side wall of the fin 120. In other words, the top of the first isolation layer 140 of the active area ii is lower than the top of the fin 120, and the isolation layer 145 exposes a partial height of the fin 120 in the active area ii.

[0043] The isolation layer 145 exposes a portion of the height of the fin 120 in the active region ii to serve as an effective fin.

[0044] The material of the isolation layer 145 is an insulating material. As an example, the material of the isolation layer 145 is silicon oxide. Silicon oxide has good insulation properties, and the stress generated by silicon oxide is also small, which is conducive to improving process reliability. In other embodiments, the material of the isolation layer can also be a suitable insulating material such as silicon oxynitride.

[0045] In this embodiment, the first isolation layer 140 and the second isolation layer 141 are made of the same material.

[0046] By making the first isolation layer 140 and the second isolation layer 141 made of the same material, the adhesion between the first isolation layer 140 and the second isolation layer 141 is improved, which is beneficial to improving the reliability of the isolation layer 145 .

[0047] Secondly, during the formation of the semiconductor structure, the isolation layer 145 initially covers the entire side wall of the fin 120, and by removing a portion of the thickness of the isolation layer 145, a portion of the height of the fin 120 is exposed, so that the materials of the first isolation layer 140 and the second isolation layer 141 are the same, which is also beneficial for improving the consistency of the removal rate when removing a portion of the thickness of the first isolation layer 140 and a portion of the thickness of the second isolation layer 141, thereby improving the consistency of the top surface height of the isolation layer 145 in the semiconductor structure.

[0048] In other embodiments, different materials may be selected for the first isolation layer and the second isolation layer according to process requirements.

[0049] refer to Figure 7 , Figure 7 It is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention.

[0050] The similarities between this embodiment and the aforementioned embodiment are not repeated here. The difference between this embodiment and the aforementioned embodiment is that: the top of the first isolation layer 240 of the partition area i" is lower than the top of the first isolation layer 240 of the active area ii"; the second isolation layer 241 also covers the top of the first isolation layer 240 of the partition area i", and the sidewalls of the first isolation layer 240 of the active area ii".

[0051] In this embodiment, the second isolation layer 241 covers the entire sidewall of the fin 220 .

[0052] The second isolation layer 241 also covers the top of the first isolation layer 240 of the isolation area i" and the side walls of the first isolation layer 240 of the active area ii", that is, the top of the second isolation layer 241 is flush with the top of the first isolation layer 240 of the active area ii", so that the first isolation layer 240 and the second isolation layer 241 of the same thickness can be removed subsequently to expose the fin 220 of a partial height in the active area ii".

[0053] It should be noted that, usually, the first groove (not shown) is formed first, and then the fin 220 at the bottom of the first groove (not shown) is removed to form a second groove (not shown) connected to the first groove, and then a second isolation layer 241 is formed in the first groove and the second groove. That is to say, along the normal direction of the top surface of the substrate 210, the distance h from the top of the first isolation layer 240 in the partition area i" to the top of the fin 220 in the active area ii" is the depth of the first groove. Therefore, along the normal direction of the top surface of the substrate 210, the thickness h of the second isolation layer 242 covering the top of the first isolation layer 240 should not be too large or too small. If the distance h from the top of the first isolation layer 240 of the partition area i" to the top of the fin 220 of the active area ii" is too large, it means that the depth of the first groove is too large, which may result in poor effect in reducing the stress of the process of removing the fin 220 on the remaining fin 220 during the formation of the first groove, and correspondingly poor effect in reducing the probability of the fin 220 bending problem occurring in the fin 220. If the distance h from the top of the first isolation layer 240 of the partition area i" to the top of the fin 220 of the active area ii" is too small, it means that the depth of the first groove is too small, which may increase the difficulty of the process of removing the fin 220 at the bottom of the first groove. Therefore, in the present embodiment, along the normal direction of the top surface of the substrate 210, the distance h from the top of the first isolation layer 240 of the partition area i" to the top of the fin 220 of the active area ii" is 40% to 60% of the height of the fin 220 of the active area ii".

[0054] In this embodiment, the semiconductor structure further includes a fin mask layer (not shown) located on the top of the fin 220 .

[0055] The fin mask layer is used as an etching mask when forming the fin 220. In this embodiment, the material of the fin mask layer is silicon nitride.

[0056] Correspondingly, as an example, the top of the first isolation layer 240 of the active region ii" is flush with the top of the fin mask layer, and the top of the second isolation layer 241 of the isolation region i" is flush with the top of the fin mask layer.

[0057] For a detailed description of the semiconductor, reference may be made to the related description of the aforementioned embodiment, which will not be repeated here.

[0058] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 8 to 15 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0059] refer to Figure 8 , providing a substrate 510, wherein the substrate 510 includes a partition region I and an active region II, and a fin 520 is formed on the substrate 510 of the partition region I and the active region II.

[0060] The substrate 510 is used to provide a process platform for subsequent process steps.

[0061] In this embodiment, the substrate 510 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0062] In this embodiment, the substrate 510 is used to form a fin field effect transistor.

[0063] The isolation region I is used to achieve isolation between the active regions II, and is also used to provide a process platform for subsequently forming a first groove and a second isolation layer.

[0064] The active region II is used to provide a process platform for forming various semiconductor devices in subsequent process steps.

[0065] The fin 520 in the active area II provides a process basis for the subsequent formation of an effective fin, which is used to provide a conductive channel when the semiconductor device is working; the fin 520 in the isolation area i is a pseudo fin. By forming the pseudo fin in the isolation area I, it is beneficial to improve the uniformity of the graphic density of the fin 520 on the substrate 510, thereby improving the size accuracy and morphology accuracy of the fin 520.

[0066] The material of the fin 520 includes one or more of silicon, silicon germanium, germanium and III-V semiconductor materials. The material of the fin 520 is determined according to the channel conductivity type and performance requirements of the transistor.

[0067] As an example, the material of the fin 520 is single crystal silicon, and the material of the fin 520 and the substrate 510 is the same.

[0068] In this embodiment, a fin hard mask structure 530 is further formed on the top of the fin 520 .

[0069] The fin hard mask structure 530 is used as an etching mask for forming the fin 520 .

[0070] It should be noted that when the first isolation layer is subsequently planarized, the fin hard mask structure 530 can be used to define a stop position for the planarization process and protect the top of the fin 520 .

[0071] Specifically, the fin hard mask structure 530 includes a first fin hard mask layer 531 , a second fin hard mask layer 532 , and a third fin hard mask layer 533 stacked sequentially from bottom to top.

[0072] In a specific embodiment, the material of the first fin mask layer 531 is silicon oxide, the material of the second fin hard mask layer 532 is silicon nitride, and the material of the third fin hard mask layer 533 is silicon oxide.

[0073] refer to Fig. 9 , a first isolation layer 540 is formed on the substrate 510 at the side of the fin 520 , and the first isolation layer 540 covers the sidewall of the fin 520 .

[0074] The first isolation layer 540 is used to provide a process basis for subsequently forming an isolation layer.

[0075] The first isolation layer 540 is made of insulating material, such as silicon oxide, silicon oxynitride, etc.

[0076] Specifically, the step of forming a first isolation layer 540 on the substrate 510 on the side of the fin 520 includes: forming a first isolation material layer (not shown) on the substrate 510 exposed by the fin 520, the top of the first isolation material layer being higher than the top of the fin hard mask structure 530; planarizing the first isolation material layer, removing the first isolation material layer above the top of the fin hard mask structure 530, and the remaining first isolation material layer serving as the first isolation layer 540.

[0077] More specifically, the fin hard mask structure 530 includes a first fin hard mask layer 531, a second fin hard mask layer 532 and a third fin hard mask layer 533 stacked in sequence from bottom to top, and the material of the second fin hard mask layer 532 is silicon nitride. Therefore, in the planarization step, the top of the second fin hard mask layer 532 is used as the stopping position, and the first isolation material layer above the top of the second fin hard mask layer 532 is removed, and the remaining first isolation material layer serves as the first isolation layer 540.

[0078] Accordingly, the third fin hard mask layer 533 is removed during the planarization process.

[0079] It should be noted that after forming the first isolation layer 540, the remaining thickness of the fin hard mask structure 530 (that is, the first fin hard mask layer 531 and the second fin hard mask layer 532) is retained. The remaining thickness of the fin hard mask structure 530 can protect the top of the fin 520 of the active area II in the process of subsequently removing the fin 520 at the bottom of the first groove and forming a second groove connected to the first groove, thereby reducing the probability of damage to the fin 520 of the active area II. In other embodiments, the remaining thickness of the fin hard mask structure 530 can also be removed after forming the first isolation layer.

[0080] refer to Fig.10 In this embodiment, after forming the first isolation layer 540 and before forming the first groove, it also includes: forming a patterned mask structure 550 on the fin 520 and the first isolation layer 540 of the active area II, the mask structure 550 having a mask opening 555, and the mask opening 555 is located in the isolation area I.

[0081] The mask structure 550 having the mask opening 555 is used as an etching mask for subsequent patterning of the first isolation layer 540 . Moreover, the mask structure 550 is also used as an etching mask for subsequent removal of the fin 520 at the bottom of the first groove.

[0082] Specifically, the mask structure 550 includes a first mask layer 551 , a second mask layer 552 and a third mask layer 553 which are sequentially stacked from bottom to top.

[0083] More specifically, the material of the first mask layer 551 includes spin-on carbon (SOC), which is formed by a spin coating process with low process cost; the material of the second mask layer 552 includes a silicon-containing anti-reflective coating (Si-ARC) material to improve exposure uniformity and pattern transfer accuracy; the material of the third mask layer 553 includes a photoresist (PR).

[0084] refer to Fig.11 , remove a portion of the thickness of the fin 520 and the first isolation layer 540 of the partition area I, and form a first groove 560 in the partition area I, wherein the first groove 560 is surrounded by the remaining fin 520 and the first isolation layer 540, and the first isolation layer 540 of the active area II.

[0085] A first groove 560 is formed in the partition area I to provide space for the subsequent formation of a second isolation layer.

[0086] During the process of forming the first groove 560, since the side wall of the fin 520 is covered with the first isolation layer 540, the stress of the process of removing the fin 520 on the remaining fin 520 is reduced, thereby reducing the probability of the fin 520 bending problem, and correspondingly improving the quality of the fin 520.

[0087] It should be noted that, along the normal direction of the top surface of the substrate 510, the depth H of the first groove 560 should not be too large or too small. If the depth H of the first groove 560 is too large, it is easy to reduce the effect of the stress of the process of removing the fin 520 on the remaining fin 520 during the formation of the first groove 560, and correspondingly reduce the probability of the fin 520 bending problem. The effect is not good. If the depth H of the first groove 560 is too small, it is easy to increase the difficulty of the subsequent process of removing the fin 520 at the bottom of the first groove 560. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 510, the depth H of the first groove 560 is 40% to 60% of the height of the fin 520 of the active area II.

[0088] Here, the depth H of the first groove 560 refers to the distance from the bottom of the first groove 560 to the top of the fin 520 of the active region ii" along the normal direction of the top surface of the substrate 510.

[0089] In this embodiment, in the step of forming the first groove 560 , a portion of the thickness of the fin 520 and the first isolation layer 540 in the isolation region I at the bottom of the mask opening 555 is removed along the mask opening 555 .

[0090] Specifically, along the mask opening 555, the fin 520 and the first isolation layer 540 of the isolation region I are partially removed at the bottom of the mask opening 555, and in the process of forming the first groove 560, the third mask layer 553 and the second mask layer 552 of the isolation region I are removed.

[0091] In this embodiment, after the first groove 560 is formed, the remaining mask structure 550 is retained.

[0092] The remaining mask structure 550 protects the fin 520 in the active area II during the subsequent modification of the fin 520 in the isolation area I.

[0093] As an example, in the process of forming the first groove 560, the second mask layer 552 and the third mask layer 553 are removed, so the first mask layer 551 is retained. The first mask layer 551 protects the fin 520 of the active area II in the subsequent process of modifying the fin of the isolation area I.

[0094] In other embodiments, the remaining mask structure may be removed after the first groove is formed.

[0095] refer to Fig.12 In this embodiment, after forming the first isolation layer 540 and before forming the second groove, the formation method further includes: modifying the fin 520 of the partition area I to improve the removal selectivity between the modified fin 520 and the unmodified substrate 510.

[0096] The fin 520 of the isolation area I is modified to improve the removal selectivity ratio between the modified fin 520 and the unmodified substrate 510, which facilitates the definition of the stop position for subsequent removal of the fin 520 at the bottom of the first groove 560, and helps to reduce the probability of damage to the substrate 510 during the subsequent removal of the fin 520 at the bottom of the first groove 560.

[0097] Specifically, the method of modifying the fin portion 520 of the partition region I includes: performing ion implantation on the fin portion 520 of the partition region I.

[0098] The ion implantation process can achieve a local processing effect, thereby achieving the purpose of changing the characteristics of the fin 520 of the isolation region I, and at the same time, it is beneficial to reduce the impact on other film layers (such as the substrate 510).

[0099] In this embodiment, the parameters of the ion implantation process include: the implanted ions are B ions or As ions, the implantation energy is 1 KeV to 600 KeV, the implantation dose is 1×10 12 ions / cm 2 Up to 2×10 18 ions / cm 2 .

[0100] After the ion implantation process is performed on the fin 520 at the bottom of the first groove 560 , the etching rate of the fin 520 doped with ions is increased, and the influence on the isolation performance of the first isolation layer 540 is relatively small.

[0101] As an example, B ions or As ions are doped into the fin 520 to modify the single crystal silicon of the fin 520 material, so that the modified fin 520 has a higher etching rate, thereby improving the removal selectivity between the modified fin 520 and the unmodified substrate 510.

[0102] It should be noted that the injection energy of the ion implantation process should not be too large or too small. If the injection energy is too large, the process is difficult to control (for example, it is easy to cause the thickness of the substrate 510 doped with ions to be too large), and it is easy to make the thickness of the substrate 510 of the remaining isolation area I too small to meet the process requirements after removing the fin 520 at the bottom of the first groove 560, thereby affecting the performance of the semiconductor structure; if the injection energy is too small, the reaction time of the ion implantation is too long, the efficiency of the process is reduced, and it is easy to affect the height of the fin 520 of the isolation area I doped with ions, which is easy to increase the difficulty of removing the fin 520 of the isolation area I, thereby easily causing the fin 520 of the isolation area I to remain, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the injection energy is 1KeV to 600KeV.

[0103] It should also be noted that the implantation dose of the ion implantation process should not be too large or too small. If the implantation dose is too large, the probability of the first isolation layer 540 being damaged is likely to increase; if the implantation dose is too small, it is likely to result in poor effect in improving the removal selectivity between the modified fin 520 and the unmodified substrate 510. Therefore, in this embodiment, the implantation dose is 1×10 12 ions / cm 2 Up to 2×10 18 ions / cm 2 .

[0104] In this embodiment, after the first groove 560 is formed, the fin 520 of the partition area I is modified.

[0105] After forming the first groove 560, the fin 520 of the partition area I is modified, that is, only the remaining fin 520 at the bottom of the first groove 560 is modified, which reduces the height of the fin 520 that needs to be modified, is beneficial to control the process, and also makes it easy to reduce the injection energy and injection dose of the ion injection process, thereby helping to improve process efficiency and save process costs.

[0106] In this embodiment, in the step of performing ion implantation on the fin 520 of the partition region I, ion implantation is also performed on a partial thickness of the substrate 510 of the partition region I, so that a partial thickness of the substrate 510 of the partition region I is subsequently removed.

[0107] In this embodiment, during the process of modifying the fin portion 520 in the isolation region I, the remaining mask structure 550 in the active region II protects the fin portion 520 in the active region II.

[0108] The remaining mask structure 550 of the active area II protects the fin 520 of the active area II. During the process of modifying the fin 520 of the isolation area I, the probability of the fin 520 of the active area II being affected by the modification treatment is reduced, which is correspondingly beneficial to reducing the probability of damage to the fin 520 of the active area II during the subsequent process of forming the second groove.

[0109] refer to Fig.13 , the fin 520 at the bottom of the first groove 560 is removed to form a second groove 570 connected to the first groove 560, and the second groove 570 exposes the top of the substrate 510 of the isolation area I.

[0110] The second groove 570 provides a space for subsequently forming a second isolation layer.

[0111] Specifically, the fin 520 at the bottom of the first groove 560 is removed by a wet etching process to form a second groove 570 connected to the first groove 560 .

[0112] The cost of the wet etching process is relatively low, the operation steps are simple, and it is easy to achieve a large etching selectivity ratio.

[0113] More specifically, in the wet etching process, the etching selectivity ratio of the fin 520 to the first isolation layer 540 is greater than 8.

[0114] The etching selectivity ratio between the fin 520 and the first isolation layer 540 is greater than 8, which is beneficial to reducing the probability of damage to the first isolation layer 540 and correspondingly improving the morphology accuracy and dimensional accuracy of the second groove 570 .

[0115] In this embodiment, the process parameters of the wet etching process include: the etching solution includes a mixed solution of hydrofluoric acid, nitric acid and acetic acid, and the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the mixed solution of hydrofluoric acid, nitric acid and acetic acid is 1:1:2 to 1:2:6, the process temperature is 30 degrees Celsius to 60 degrees Celsius, and the process time is 100 seconds to 240 seconds.

[0116] The mixed solution of hydrofluoric acid, nitric acid and acetic acid is an HNA solution. The HNA solution can easily achieve a higher etching selectivity ratio between the etched object (i.e., the fin 520 of the partition area I) and the first isolation layer 540 of the partition area I, thereby reducing the difficulty of removing the fin 520 of the partition area I, and correspondingly reducing the difficulty of forming the second groove 570.

[0117] As an example, the fin 520 is doped with B ions or As ions to modify the single crystal silicon of the fin 520 material; the fin 520 at the bottom of the first groove 560 is removed using HNA solution to facilitate a higher etching selectivity between the single crystal silicon and the first isolation layer 540.

[0118] Specifically, in the mixed solution of hydrofluoric acid, nitric acid and acetic acid used in the wet etching process, the volume ratio of hydrofluoric acid to nitric acid is 1:1 to 1:2, and the volume ratio of hydrofluoric acid to acetic acid is 1:2 to 1:6. By setting the volume ratio of hydrofluoric acid, nitric acid and acetic acid in the above range, it is ensured that the HNA solution can significantly improve the etching selectivity between the fin 520 and the first isolation layer 540 of the partition region I.

[0119] The process temperature of the wet etching process should not be too high or too low. If the process temperature is too high, the probability of other film layers (e.g., the first isolation layer 540) being damaged is likely to increase. If the process temperature is too low, the fin 520 in the partition area I is likely to remain, which is likely to affect the quality of forming the second groove 570, thereby affecting the quality of the subsequent formation of the second isolation layer in the second groove 570. Therefore, in this embodiment, the process temperature is 30 degrees Celsius to 60 degrees Celsius.

[0120] The process time of the wet etching process should not be too long or too short. If the wet etching process time is too long, it is easy to increase the probability of other film layers (for example, the first isolation layer 540) being damaged. If the process time of the wet etching process is too short, it is easy to cause the fin 520 of the partition area I to remain, which is easy to affect the quality of forming the second groove 570, thereby affecting the quality of the subsequent formation of the second isolation layer in the second groove 570. Therefore, in this embodiment, the process time is 100 seconds to 260 seconds.

[0121] It should be noted that the opening size D of the second groove 570 should not be too small or too large. If the opening size D of the second groove 570 is too small, it is easy to increase the difficulty of the subsequent process of forming the second isolation layer in the second groove 570; if the opening size D of the second groove 570 is too large, it is easy to increase the probability of the first isolation layer 540 being damaged, and correspondingly, it is easy to increase the probability of damage to the fin 520 in the active area II. Therefore, in this embodiment, along the direction perpendicular to the side wall of the fin 520, the opening size D of the second groove 570 is 10 nanometers to 17 nanometers.

[0122] In this embodiment, in the step of forming the second groove 570 , a portion of the thickness of the substrate 510 in the isolation region I is also removed.

[0123] In the step of forming the second groove 570, a partial thickness of the substrate 510 of the partition area I is also removed to ensure that the fin 520 of the partition area I can be completely removed, thereby improving the problem of the performance of the semiconductor structure being affected by the residual fin 520 of the partition area I.

[0124] It should be noted that the thickness L of the substrate 510 removed from the partition area I along the normal direction of the top surface of the substrate 510 should not be too large or too small. If the thickness L of the substrate 510 removed from the partition area I is too large, it is easy for the remaining substrate 510 of the partition area I to fail to meet the process requirements; if the thickness L of the substrate 510 removed from the partition area I is too small, it is easy to cause the effect of completely removing the fin 520 of the partition area I to be poor. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 510, the thickness L of the substrate 510 removed from the partition area I is 50 angstroms to 350 angstroms.

[0125] In this embodiment, during the modification of the fin 520 in the partition area I, the fin 520 in the active area II is protected by the remaining mask structure 550 in the active area II. Accordingly, after the fin 520 in the partition area I is modified and before the second groove 570 is formed, the remaining mask structure 550 is removed.

[0126] Specifically, the process of removing the remaining mask structure 550 includes an ashing process.

[0127] It should be noted that the remaining mask structure 550 is removed first, and then the fin 520 at the bottom of the first groove 560 is removed, so that in the process of removing the remaining mask structure 550, the fin 520 can protect the substrate 510, which is beneficial to reduce the probability of damage to the substrate 510. Moreover, after removing the mask structure 550, the fin 520 at the bottom of the first groove 560 is removed, which is beneficial to reduce the probability of the mask structure 550 having an adverse effect on the formation of the second groove 570 in the process of removing the fin 520 at the bottom of the first groove 560. For example, it is beneficial to prevent the probability of defects caused by introducing the mask structure 550 when forming the second groove 570.

[0128] refer to Fig.14 A second isolation layer 541 is formed in the first groove 560 and the second groove 570 . The second isolation layer 541 covers the sidewall of the first groove 560 . The second isolation layer 541 and the first isolation layer 540 constitute an isolation layer 545 .

[0129] First, a first isolation layer 540 is formed on the substrate on the side of the fin 520, and the first isolation layer 540 covers the side wall of the fin 520. Then, a partial thickness of the fin 520 and the first isolation layer 540 in the isolation area I are removed to form a first groove 560 in the isolation area I. After the first groove 560 is formed, the fin 520 at the bottom of the first groove 560 is removed to form a second groove 570 connected to the first groove 560. Then, a second isolation layer 541 is formed in the first groove 560 and the second groove 570. The second isolation layer 541 covers the side wall of the first groove 560, so that the second isolation layer 541 in the isolation area I is located between adjacent first isolation layers 540, and the second isolation layer 541 and the first isolation layer 540 constitute an isolation layer 545. It can be seen that the isolation layer 545 is formed step by step by the first isolation layer 540 and the second isolation layer 541 in sequence. In the process of forming the first groove 560, since the side wall of the fin 520 is covered with the first isolation layer 540, the stress of the process of removing the fin 520 on the remaining fin 520 is reduced, thereby reducing the probability of the fin 520 bending problem occurring in the fin 520, and correspondingly improving the quality of the fin 520; moreover, when forming the second isolation layer 541, there is still a partial thickness of the first isolation layer 540 on the substrate 510 of the partition area I, that is, the thickness of the formed second isolation layer 541 is relatively small, thereby reducing the stress of the formation of the second isolation layer 541 on the fin 520 of the active area II adjacent to the partition area I, thereby reducing the probability of the fin 520 bending problem occurring in the fin 520, and correspondingly improving the quality of the fin 520, thereby improving the performance of the semiconductor structure.

[0130] The isolation layer 545 is used to isolate each semiconductor device to prevent leakage current from occurring between the devices.

[0131] The material of the isolation layer 545 is an insulating material. As an example, the material of the isolation layer 545 is silicon oxide. Silicon oxide has good insulation properties, and the stress generated by silicon oxide is also small, which is conducive to improving process reliability. In other embodiments, the material of the isolation layer can also be an applicable insulating material such as silicon oxynitride.

[0132] In this embodiment, the first isolation layer 540 and the second isolation layer 541 are made of the same material.

[0133] By making the first isolation layer 540 and the second isolation layer 541 made of the same material, the adhesion between the first isolation layer 540 and the second isolation layer 541 is improved, which is beneficial to improving the reliability of the isolation layer 545 .

[0134] Secondly, making the materials of the first isolation layer 540 and the second isolation layer 541 the same is also beneficial to improving the consistency of the removal rates of the first isolation layer 540 and the second isolation layer 541 in the subsequent process of removing a portion of the thickness of the isolation layer 545 to expose a portion of the height of the fin 520 in the active area II, thereby improving the consistency of the top surface height of the isolation layer 545 in the semiconductor structure.

[0135] In other embodiments, different materials may be selected for the first isolation layer and the second isolation layer according to process requirements.

[0136] In this embodiment, the step of forming the second isolation layer 541 includes: filling a second isolation material layer (not shown) in the second groove 570 and the first groove 560, the second isolation material layer also covering the fin 520 outside the first groove 560 and the top of the first isolation layer 540; planarizing the second isolation material layer to form a second isolation layer 541 whose top surface is flush with the first isolation layer 540.

[0137] First, a second isolation material layer is filled in the second groove 570 and the first groove 560, and the second isolation material layer also covers the fin 520 outside the first groove 560 and the top of the first isolation layer 540. Then, the second isolation material layer is planarized to form a second isolation layer 541 whose top surface is flush with the first isolation layer 540, which is beneficial to reducing the difficulty of forming the second isolation layer 541. In addition, by planarizing the second isolation material layer to form a second isolation layer 541 whose top surface is flush with the first isolation layer 540, it is beneficial to improve the flatness of the top surface of the second isolation layer 541 formed, thereby improving the performance of the semiconductor structure.

[0138] Specifically, multiple filling operations are performed until the second isolation material layer is filled in the second groove 570, and the steps of the filling operation include: filling the second groove 570 with an initial second isolation material layer (not shown); after filling the initial second isolation material layer, removing the initial second isolation material layer near the opening position of the second groove 570 to expose the opening of the second groove 570; wherein, after completing the multiple filling operations, the initial second isolation material layer in the second groove 570 serves as the second isolation material layer.

[0139] After the initial second isolation material layer is filled in the second groove 570, the initial second isolation material layer near the opening position of the second groove 570 is removed to expose the opening of the second groove 570. In other words, alternating the steps of filling the initial second isolation material layer and removing the initial second isolation material layer near the opening position of the second groove 570 is beneficial to avoid the opening of the second groove 570 from closing prematurely, and correspondingly helps to improve the quality of the second isolation layer 541 formed in the second groove 570, thereby helping to improve the quality of the isolation layer 545, and further improving the performance of the semiconductor structure.

[0140] It should be noted that the number of filling operations should not be too few or too many. If the number of filling operations is too few, it is easy to prevent the opening of the second groove 570 from closing too early, and accordingly it is easy to improve the quality of the second isolation layer 541 formed in the second groove 570. If the number of filling operations is too many, it is easy to reduce the process efficiency and cause a waste of process capacity. Therefore, in this embodiment, the number of filling operations is 15 to 30 times.

[0141] In this embodiment, the process of forming the second isolation layer includes a flowable chemical vapor deposition process.

[0142] The flowable chemical vapor deposition process has good filling capability and is suitable for filling spaces with high aspect ratios. It is beneficial to reduce the probability of defects such as voids in the second isolation layer 541 formed in the second groove 570, and correspondingly improves the quality of the isolation layer 545, thereby improving the performance of the semiconductor structure.

[0143] refer to Fig.15 In this embodiment, the formation method further includes: removing a portion of the thickness of the isolation layer 545 to expose a portion of the height of the fin 520 in the active region II.

[0144] The fin 520 that exposes a portion of the height in the active region II is used as an effective fin. The effective fin is used to provide a conductive channel when the semiconductor device is working.

[0145] As an example, a portion of the isolation layer 545 is removed by etching back. For example, the etching back process may include a dry etching process.

[0146] In this embodiment, after forming the isolation layer 545 and before removing a portion of the thickness of the isolation layer 545 , the process further includes: removing the first fin hard mask layer 531 and the second fin hard mask layer 532 .

[0147] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a partition region and an active region; A fin portion, located on the substrate of the active region; An isolation layer is located on the substrate, and the isolation layer includes a first isolation layer and a second isolation layer; wherein, The first isolation layer is located on the substrate of the partition area and the active area, the first isolation layer of the active area covers the sidewall of the fin, and the first isolation layer of the partition area is spaced apart and arranged along the arrangement direction of the fin; The second isolation layer is located on the substrate of the partition area, the second isolation layer is located between adjacent first isolation layers, and the top of the second isolation layer is flush with the top of the first isolation layer of the active area.

2. The semiconductor structure according to claim 1, wherein: The substrate top of the isolation region is lower than the substrate top of the active region.

3. The semiconductor structure according to claim 2, wherein: A vertical distance between a substrate bottom of the isolation region and a substrate top of the active region is 50 angstroms to 350 angstroms.

4. The semiconductor structure according to claim 1, wherein: In the partition region, along a direction perpendicular to the sidewall of the fin portion, a top surface width of the second isolation layer between adjacent first isolation layers is 10 nanometers to 17 nanometers.

5. The semiconductor structure according to claim 1, wherein: The top of the first isolation layer in the partition area is lower than the top of the first isolation layer in the active area; The second isolation layer also covers the top of the first isolation layer in the isolation region and the sidewall of the first isolation layer in the active region.

6. The semiconductor structure according to claim 5, characterized in that Along the normal direction of the top surface of the substrate, the distance from the top of the first isolation layer in the partition area to the top of the fin in the active area is 40% to 60% of the height of the fin in the active area.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a partition area and an active area, wherein fins are formed on the substrate of the partition area and the active area; forming a first isolation layer on the substrate at the side of the fin, wherein the first isolation layer covers the sidewall of the fin; Removing a portion of the thickness of the fin and the first isolation layer in the isolation area to form a first groove in the isolation area, wherein the first groove is surrounded by the remaining fin and the first isolation layer, and the first isolation layer in the active area; Removing the fin at the bottom of the first groove to form a second groove connected to the first groove, wherein the second groove exposes the top of the substrate of the partition area; A second isolation layer is formed in the first groove and the second groove, the second isolation layer covers the sidewall of the first groove, and the second isolation layer and the first isolation layer constitute an isolation layer.

8. The method for forming a semiconductor structure according to claim 7, wherein: After forming the first isolation layer and before forming the second groove, the forming method further includes: modifying the fin portion of the partition region to improve a removal selectivity ratio between the modified fin portion and the unmodified substrate.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method of modifying the fin portion of the partition region includes: performing ion implantation on the fin portion of the partition region.

10. The method for forming a semiconductor structure according to claim 9, wherein: The parameters of the ion implantation process include: the implanted ions are B ions or As ions, the implantation energy is 1 KeV to 600 KeV, the implantation dose is 1×10 12 ions / cm 2 Up to 2×10 18 ions / cm 2 .

11. The method for forming a semiconductor structure according to claim 8, wherein: After forming the first groove, the fin portion of the partition region is modified.

12. The method for forming a semiconductor structure according to claim 11, wherein: After forming the first isolation layer and before forming the first groove, the method further includes: forming a patterned mask structure on the fin portion of the active area and the first isolation layer, wherein the mask structure has a mask opening, and the mask opening is located in the partition area; In the step of forming the first groove, the fin portion and the first isolation layer of the isolation region having a partial thickness at the bottom of the mask opening are removed along the mask opening; In the process of modifying the fin portion of the partition area, the fin portion of the active area is protected by the remaining mask structure of the active area; After forming the second groove and before forming the second isolation layer, the method further includes: removing the remaining mask structure.

13. The method for forming a semiconductor structure according to claim 7, wherein: Using a wet etching process to remove the fin at the bottom of the first groove to form a second groove connected to the first groove; Wherein, in the wet etching process, an etching selectivity ratio between the fin and the first isolation layer is greater than 8.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process parameters of the wet etching process include: the etching solution includes a mixed solution of hydrofluoric acid, nitric acid and acetic acid, in which the volume ratio of hydrofluoric acid, nitric acid and acetic acid is 1:1:2 to 1:2:6, the process temperature is 30 degrees Celsius to 60 degrees Celsius, and the process time is 100 seconds to 240 seconds.

15. The method for forming a semiconductor structure according to claim 7, wherein: In the step of forming the second groove, a partial thickness of the substrate in the partition region is also removed.

16. The method for forming a semiconductor structure according to claim 7, wherein: The process of forming the second isolation layer includes a flow chemical vapor deposition process.

17. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the second isolation layer comprises: Filling a second isolation material layer in the second groove and the first groove, wherein the second isolation material layer also covers the fin portion outside the first groove and the top of the first isolation layer; The second isolation material layer is planarized to form a second isolation layer whose top surface is flush with the first isolation layer.

18. The method for forming a semiconductor structure according to claim 17, wherein: Performing multiple filling operations until the second groove is filled with a second isolation material layer, the filling operation comprising: filling an initial second isolation material layer in the second groove; After filling the initial second isolation material layer, removing the initial second isolation material layer near the opening of the second groove to expose the opening of the second groove; After completing the filling operation multiple times, the initial second isolation material layer in the second groove serves as the second isolation material layer.

19. The method for forming a semiconductor structure according to claim 18, wherein: The filling operation is performed 15 to 30 times.

20. The method for forming a semiconductor structure according to claim 7, wherein: The forming method further includes: removing a portion of the thickness of the isolation layer to expose a portion of the height of the fin in the active area.

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