Preparation method of photovoltaic cell and photovoltaic cell

By using a mask push layer containing nitrogen elements in the preparation process of TBC photovoltaic cells, the problems of mask layer residue and phosphorus atom diffusion are solved, achieving more efficient cell preparation and performance improvement.

CN119364890APending Publication Date: 2025-01-24TRINA SOLAR CO LTD
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Patent Information

Application Number
CN202411234758.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-09-04
Publication Date
2025-01-24

AI Technical Summary

Technical Problem

In the preparation process of existing TBC photovoltaic cells, the mask layer is prone to remain during the etching process, affecting the battery efficiency, and the BSG layer cannot completely block the phosphorus atoms during phosphorus diffusion, destroying Ppoly's passivation.

Method used

Adopt a mask -containing mask promotion layer instead of the traditional BSG layer, and through high temperature promotion, the first transmitted amorphous silicon layer is transformed into a polycrystalline silicon layer with doped elements, and the blocking effect of the mask propulsion layer is used during phosphorus diffusion. Essence

Benefits of technology

It effectively avoids mask layer residue, improves battery efficiency, and protects the Ppoly passivation layer by blocking the diffusion of phosphorus atoms, further improving battery performance.

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Abstract

The invention provides a preparation method of a photovoltaic cell and the photovoltaic cell. The preparation method comprises the following steps that a substrate is provided, the substrate is provided with a substrate front face and a substrate back face which are opposite, and the substrate front face is closer to the light-facing face of the photovoltaic cell than the substrate back face; preparing a first tunneling layer and a first intrinsic amorphous silicon layer on the back surface of the substrate to obtain a first battery middleware; after a mask propulsion layer is deposited on one side of the back face of the substrate of the first battery middleware, a second battery middleware is obtained, the mask propulsion layer contains nitrogen elements and first doping elements at the same time, and the mask propulsion layer is suitable for enabling the first intrinsic amorphous silicon layer to be converted into a first doped polycrystalline silicon layer with the first doping elements after high-temperature propulsion; and preparing a second doped region on one side of the back surface of the substrate to obtain the photovoltaic cell, the second doped region comprising a second doping element different from the first doping element. According to the invention, the mask residue problem can be optimized and improved, and the battery efficiency is improved.
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Description

Technical Field

[0001] The present application mainly relates to the field of photovoltaic technology, and in particular to a method for preparing a photovoltaic cell and a photovoltaic cell. Background Art

[0002] BC (Back Contact) cells are back-contact cells. BC cell technology places the PN junction and metal contact on the back of the cell, so that there is no electrode blocking the front of the cell. The cell absorbs more sunlight, thereby improving the conversion efficiency and enabling the photovoltaic cell to generate more electricity. In the field, TBC cells, which are formed by superposition of BC technology and Topcon (tunneling oxide passivation contact cell technology), have received widespread attention in recent years.

[0003] At present, the preparation process of TBC batteries is basically to carry out boron diffusion and phosphorus diffusion in two steps on the back of the battery, and to prepare the corresponding positions of different doping areas by grooving, so as to finally form doping areas with different doping elements. However, this method usually has some disadvantages. Since BSG with uneven thickness is produced as a mask layer during the preparation of the doping area, when the grooved area is etched after grooving, BSG residue is prone to appear in the grooved area at the edge of the silicon wafer, and it cannot be completely etched, affecting the efficiency of the battery. In addition, when phosphorus diffuses, the BSG on the surface of Ppoly may not be able to completely block the phosphorus atoms. The phosphorus atoms will enter the Ppoly area and destroy the passivation of Ppoly, thereby affecting the efficiency of the battery. Summary of the invention

[0004] The technical problem to be solved by the present application is to provide a method for preparing a photovoltaic cell and a photovoltaic cell, which can optimize and improve the mask residue problem and improve the cell efficiency.

[0005] To solve the above technical problems, the present application provides a method for preparing a photovoltaic cell, comprising the following steps: providing a substrate, the substrate having a relative substrate front side and a substrate back side, the substrate front side being closer to the light-facing surface of the photovoltaic cell than the substrate back side; obtaining a first cell intermediate component after preparing a first tunneling layer and a first intrinsic amorphous silicon layer on the back side of the substrate; obtaining a second cell intermediate component after depositing a mask advancement layer on the back side of the substrate of the first cell intermediate component, wherein the mask advancement layer has both nitrogen and a first doping element, and the mask advancement layer is suitable for converting the first intrinsic amorphous silicon layer into a first doped polycrystalline silicon layer having the first doping element after high-temperature advancement; and preparing a second doping region on the back side of the substrate to obtain the photovoltaic cell, wherein the second doping region includes a second doping element different from the first doping element.

[0006] Optionally, it also includes obtaining a third battery middle component having a first doped region after high-temperature pushing the first intrinsic amorphous silicon layer through the mask pushing layer on the second battery middle component, wherein the first doped region contains the first doping element; and preparing the second doped region on the back side of the substrate of the third battery middle component.

[0007] Optionally, the step of preparing a second doped region on the back side of the substrate of the third battery intermediate component includes: performing a first laser grooving on the back side of the substrate of the third battery intermediate component at a corresponding position of the second doped region to obtain a fourth battery intermediate component; preparing a second tunneling layer and a second intrinsic amorphous silicon layer on the back side of the substrate of the fourth battery intermediate component to obtain a fifth battery intermediate component; and diffusing the second doping element on the second intrinsic amorphous silicon layer to obtain a sixth battery intermediate component.

[0008] Optionally, the method further includes performing a second laser grooving on the sixth battery intermediate component to form an isolation region between the first doping region and the second doping region, thereby obtaining a seventh battery intermediate component.

[0009] Optionally, the method further includes etching the back side of the substrate and texturing the front side of the substrate after performing the second laser grooving.

[0010] Optionally, the method further includes preparing a double-sided passivation layer and / or a double-sided anti-reflection layer for the seventh battery intermediate component.

[0011] Optionally, the passivation layer includes aluminum oxide, and the anti-reflection layer includes silicon nitride.

[0012] Optionally, the method further includes performing the high temperature advancement while preparing the second doping region, so as to transform the first intrinsic amorphous silicon layer into a first doped polysilicon layer having a first doping element.

[0013] Optionally, the first doping element includes a Group III element, and the second doping element includes phosphorus.

[0014] Optionally, the mask push-up layer is deposited by PECVD, and the following preparation conditions are controlled when depositing the mask push-up layer: pressure of 1000-2000mTorr, and / or silane amount of 1000-3000sccm, and / or ammonia amount of 10000-20000sccm, and / or diborane amount of 100-2000sccm.

[0015] Optionally, the method further includes removing the mask push-in layer by a cleaning solution after preparing the second doping region.

[0016] Optionally, the cleaning solution is a mixture of HF and deionized water in a volume ratio of (0.02-0.06):(10-100).

[0017] Another aspect of the present application further provides a photovoltaic cell, which is prepared according to the preparation method of any embodiment of the present application.

[0018] Another aspect of the present application also proposes a photovoltaic cell, which includes: a substrate, the substrate having a relative substrate front side and a substrate back side, the substrate front side is closer to the light-facing surface of the photovoltaic cell than the substrate back side; a first doping region and a second doping region, which are both located on the back side of the substrate, wherein the first doping region includes a first doping element, and the second doping region includes a second doping element different from the first doping element; the first doping region is obtained by high-temperature driving of a first intrinsic amorphous silicon layer adjacent to the mask driving layer through a mask driving layer.

[0019] Optionally, the mask advancing layer is removed by a cleaning solution after the second doping region is formed during the preparation process of the photovoltaic cell.

[0020] Optionally, the cleaning solution comprises a mixture of HF and deionized water in a volume ratio of (0.02-0.06):(10-100).

[0021] Compared with the prior art, the present application has the following advantages: the present application adopts a mask advancement layer to replace the BSG layer in the traditional technology, which overcomes the phenomenon that the BSG layer remains in the etching area at the edge of the silicon wafer during this process, and provides a wider window for the wet process. In addition, compared with the BSG layer, the mask advancement layer containing nitrogen elements can better block the diffusion of phosphorus atoms during the phosphorus diffusion process, preventing phosphorus atoms from entering the Ppoly area, thereby improving battery efficiency. In some preferred embodiments, the advancement step of the mask advancement layer can be combined with the high-temperature advancement step of the phosphorus doping area, so that the entire process has only one high-temperature process, reducing process risks, reducing production defects, and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of the present application. They are included and constitute a part of the present application. The accompanying drawings illustrate embodiments of the present application and together with the present specification serve to explain the principles of the present application. In the accompanying drawings:

[0023] Figure 1 It is a schematic diagram of a process for preparing a photovoltaic cell according to an embodiment of the present application;

[0024] Figure 2 is a schematic structural diagram of a photovoltaic cell according to an embodiment of the present application;

[0025] Figure 3 to Figure 8 This application is Figure 2 A diagram of an intermediate process of preparing a photovoltaic cell in the illustrated embodiment; and

[0026] Fig. 9 Schematic diagram of the residue on the edge of the BSG layer in the traditional preparation method. DETAILED DESCRIPTION

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some examples or embodiments of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.

[0028] As shown in this application and claims, unless the context clearly indicates an exception, the words "a", "an", "an" and / or "the" do not refer to the singular and may also include the plural. Generally speaking, the terms "include" and "comprise" only indicate the inclusion of the steps and elements that have been clearly identified, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0029] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present application. At the same time, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant field may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the authorization specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, so that once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0030] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0031] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0032] In addition, it should be noted that the use of words such as "first" and "second" to define components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above words have no special meaning and cannot be understood as limiting the scope of protection of this application. In addition, although the terms used in this application are selected from well-known and commonly used terms, some terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term.

[0033] It should be understood that when a component is referred to as being "on another component," "connected to another component," "coupled to another component," or "contacting another component," it may be directly on, connected to, coupled to, or contacting the other component, or there may be intervening components. In contrast, when a component is referred to as being "directly on another component," "directly connected to," "directly coupled to," or "directly contacting" another component, there are no intervening components. Similarly, when a first component is referred to as being "electrically in contact with" or "electrically coupled to" a second component, there is an electrical path between the first component and the second component that allows current to flow. The electrical path may include capacitors, coupled inductors, and / or other components that allow current to flow, even without direct contact between conductive components.

[0034] This application refers to Figure 1 A method 10 for preparing a photovoltaic cell (hereinafter referred to as "method 10") is proposed, which can optimize and improve the mask residue problem and improve the cell efficiency. Figure 1 Flowcharts are used to illustrate the operations performed by the system according to the embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed precisely in order. Instead, various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more operations may be removed from these processes.

[0035] according to Figure 1 , method 10 includes the following steps. Step S1 is to provide a substrate, the substrate having a relative substrate front side and a substrate back side, the substrate front side is closer to the light-facing surface of the photovoltaic cell than the substrate back side. Step S2 is to obtain a first cell intermediate after preparing a first tunneling layer and a first intrinsic amorphous silicon layer on the back side of the substrate. Step S3 is to obtain a second cell intermediate after depositing a mask advancement layer on the back side of the substrate of the first cell intermediate, wherein the mask advancement layer has both nitrogen and a first doping element, and the mask advancement layer is suitable for converting the first intrinsic amorphous silicon layer into a first doped polycrystalline silicon layer having a first doping element after high-temperature advancement. Step S4 is to prepare a second doping region on the back side of the substrate to obtain a photovoltaic cell, wherein the second doping region includes a second doping element that is different from the first doping element. In the present application, preferably, the first doping element includes a Group III element, and the second doping element includes a phosphorus element. On the other hand, in the above step S3, it is preferred to deposit the mask push-up layer by PECVD, and control the following preparation conditions when depositing the mask push-up layer: pressure of 1000-2000mTorr, and / or silane amount of 1000-3000sccm, and / or ammonia amount of 10000-20000sccm, and / or diborane amount of 100-2000sccm.

[0036] Further preferably, after the above step S3, the method further includes performing high temperature advancement on the first intrinsic amorphous silicon layer through the mask advancement layer of the second battery intermediate component to obtain a third battery intermediate component having a first doping region, wherein the first doping region contains a first doping element; and preparing the second doping region on the back side of the substrate of the third battery intermediate component. However, the present application is not limited thereto. In some embodiments of the present application, the subsequent preparation steps may be performed after the preparation of the mask advancement layer is completed, and a high temperature advancement may be used to complete the crystallization process of the first doped polysilicon layer in the first doping region while the second doping region is subsequently prepared.

[0037] Specifically, if the process of first annealing the mask push layer at high temperature is adopted, the step of preparing the second doping region on the back side of the substrate of the third battery intermediate component further includes: performing a first laser groove on the back side of the substrate of the third battery intermediate component at the corresponding position of the second doping region to obtain a fourth battery intermediate component; preparing a second tunneling layer and a second intrinsic amorphous silicon layer on the back side of the substrate of the fourth battery intermediate component to obtain a fifth battery intermediate component; and diffusing the second doping element on the second intrinsic amorphous silicon layer to obtain a sixth battery intermediate component. On this basis, the sixth battery intermediate component can also be further laser grooved for a second time to form an isolation region between the first doping region and the second doping region, thereby obtaining a seventh battery intermediate component.

[0038] On the other hand, preferably, after the second laser grooving is performed as described above, the back side of the substrate can be etched and the front side of the substrate can be textured. As a preferred embodiment, the mask advancement layer can be removed by cleaning after the preparation of the second doping region is completed. Specifically, a mixture of HF and deionized water with a volume ratio of (0.02-0.06): (10-100) can be used to remove the mask advancement layer. Since the step of removing this layer is relatively late in the entire manufacturing process, it can not only reflect the material property advantages of the mask advancement layer itself, but also can be used as a promotion barrier layer for the second doping element when preparing the second doping region, thereby effectively protecting the first doping region prepared first. This benefit will be further explained later.

[0039] On this basis, in some embodiments of the present application, on the basis of the seventh battery intermediate member, a double-sided passivation layer and / or a double-sided anti-reflection layer can also be prepared. Preferably, the passivation layer includes aluminum oxide, and the anti-reflection layer includes silicon nitride.

[0040] Another aspect of the present application provides a photovoltaic cell, which is prepared according to the method for preparing a photovoltaic cell of any embodiment of the present application.

[0041] Figure 2A photovoltaic cell 20 proposed in another aspect of the present application is shown, and the photovoltaic cell 20 includes a substrate 200, a first doping region 21, and a second doping region 22. Specifically, the substrate 200 has a substrate front side 201 and a substrate back side 202 opposite to each other, and the substrate front side 201 is closer to the light-facing side of the photovoltaic cell than the substrate back side 202.

[0042] according to Figure 2 The first doping region 21 and the second doping region 22 are both located on the back side 202 of the substrate, and the first doping region 21 includes a first doping element, and the second doping region 22 includes a second doping element different from the first doping element. Figure 2 As shown, the first doped region 21 includes a first tunneling layer 211 and a first doped polysilicon layer 212 (P-type); the second doped region 22 includes a second tunneling layer 221 and a second polysilicon layer 222 (N-type). The back side 202 of the substrate of the photovoltaic cell also has a first electrode 251 and a second electrode 252, which are respectively connected to the p-type polysilicon layer 212 in the first doped region 21 and the n-type polysilicon layer 222 in the second doped region 22. In the present embodiment, the photovoltaic cell 20 also has a passivation layer 23 and an anti-reflection layer 24 on both sides of the cell. Specifically, the material of the passivation layer 23 may be aluminum oxide, and the material of the anti-reflection layer 24 may be a single layer of silicon nitride or a multilayer film containing silicon nitride. In the present embodiment, the first doped region 21 is obtained by high-temperature advancement of the first intrinsic amorphous silicon layer adjacent to the mask advancement layer by the mask advancement layer. Exemplarily, Figure 2 The photovoltaic cell 20 shown may be made of Figure 1 The photovoltaic cell 20 is prepared by the method 10 shown. For the photovoltaic cell 20, the mask advancing layer is preferably removed by a cleaning solution during the preparation of the photovoltaic cell 20. The cleaning solution is preferably a mixture of HF and deionized water in a volume ratio of (0.02-0.06): (10-100).

[0043] In order to more clearly illustrate the above method 10, photovoltaic cell 20 and preferred variants thereof, the following reference is made to Figure 2 to Figure 8 Taking the photovoltaic cell 20 prepared by the method 10 as an example, the intermediate process of preparing the photovoltaic cell 20 is described in detail.

[0044] First refer to Figure 3, polishing is performed on the N-type doped bare silicon wafer to obtain a substrate 200, which has a substrate front side 201 and a substrate back side 202. Further, a first tunneling layer 221 (for example, SiO2) and a first intrinsic amorphous silicon layer 312 are deposited on the substrate 200 by LPCVD. Exemplarily, the thickness of the first tunneling layer can be controlled to be 1nm to 2nm, and the thickness of the first intrinsic amorphous silicon layer can be controlled to be 100nm to 400nm. The growth temperature of the first tunneling layer is preferably controlled to be 580℃ to 620℃, and the growth time is controlled to be 10min to 50min. The deposition temperature of the first intrinsic amorphous silicon layer 312 is controlled to be 550℃ to 590℃, and the deposition time is controlled to be 20min to 200min.

[0045] On this basis, refer to Figure 3 On the basis of the first tunneling layer 221 and the first intrinsic amorphous silicon layer 312, a first battery intermediate is obtained, and on this basis, a mask advancement layer 313 is preferably prepared by PECVD. In this embodiment, the mask advancement layer 313 is preferably implemented as silicon nitride containing the III-group element boron. Further preferably, the process conditions when preparing the mask advancement layer 313 in this embodiment can be controlled to be a pressure of 1000-2000 mTorr, and / or a silane amount of 1000-3000 sccm, and / or an ammonia amount of 10000-20000 sccm, and / or a diborane amount of 100-2000 sccm.

[0046] On this basis, for example, after completing Figure 3 After the relevant steps shown in the figure, the second battery intermediate member is obtained. The boron impurity atoms in the mask advancement layer 313 can be activated in a high temperature furnace at 800-1000°C, so that the boron element is advanced into the first intrinsic amorphous silicon layer 312 adjacent thereto, thereby obtaining the second battery intermediate member as shown in the figure. Figure 4 The third battery middleware shown, at this time according to Figure 4 The third battery intermediate component already has a first doping region 21 , that is, the first tunneling layer 211 and the first doped polysilicon layer 212 included in the first doping region 21 have been prepared.

[0047] On this basis, further reference Figure 5 , for example Figure 4 The third battery intermediate member having the first doping region 21 shown in the figure is subjected to a laser grooving step on the back side 202 of the substrate to obtain a Figure 5The fourth battery middleware shown. Preferably, the process conditions of laser grooving can be set to: wavelength of 500nm~600nm; square spot, overlap rate of 80%; 500kHz, 10w~50w power. On this basis, exemplarily, considering that the depth of the grooving is difficult to control under some conditions, the grooved area (that is, the area corresponding to the second doping area 22) can be further etched at this time to expose the back side 202 of the substrate of the second doping area 22. Preferably, the etching conditions can be controlled to etch with a mixed solution of KOH solution and deionized water in a volume ratio of (1-2): (5-20), wherein the concentration of the KOH solution is 45-55wt%, the etching and cleaning temperature is 50℃~80℃, and the cleaning time is 200s~400s.

[0048] Further, see Figure 6 , in such Figure 5 On the basis of the fourth battery intermediate shown, the second tunneling layer 221 (for example, a SiO2 tunneling layer) and the second intrinsic amorphous silicon layer 322 are preferably deposited on the back side 202 of the substrate by LPCVD. Exemplarily, the thickness of the second tunneling layer is about 1nm to 2nm, and the thickness of the second intrinsic amorphous silicon layer 322 is about 100nm to 400nm. The growth temperature of the second tunneling layer is preferably controlled to 580℃ to 620℃, and the growth time is controlled to 10min to 50min. The deposition temperature of the second intrinsic amorphous silicon layer 322 is preferably controlled to 550℃-590℃, and the deposition time is 20min to 200min. After completing the above preparation, the following is obtained. Figure 6 The fifth battery intermediate piece is shown.

[0049] On this basis, refer to Figure 7 , for example, Figure 6 The fifth battery intermediate member shown is placed in a diffusion furnace and phosphorus is diffused at a temperature of 780°C to 900°C. The diffusion time is preferably 10min to 60min, thereby obtaining a sixth battery intermediate member. Figure 3 and Figure 4 An implementation of the present application is described, that is, in Figure 3 The high temperature driving is directly performed on the second battery intermediate member shown in the figure to drive the boron impurity atoms in the activation mask driving layer 313 into the first intrinsic amorphous silicon layer 312 adjacent thereto. However, the present application is not limited thereto. In other embodiments, the high temperature driving may not be performed. Figure 4 The relevant preparation steps shown in the figure do not perform high temperature advancement on the boron element alone, but directly perform subsequent preparation steps after forming the mask advancement layer 313 until reaching the state as shown in the figure. Figure 7In the state shown, during the phosphorus diffusion process, the boron element in the mask push-on layer 313 will simultaneously enter the first amorphous silicon layer 212 under high temperature driving to obtain the first doped polysilicon layer 212 doped with boron element.

[0050] Furthermore, Figures 7 and 8 The process shows that the sixth battery middle piece is laser grooved for the second time to form an isolation region 26 between the first doping region 21 and the second doping region 22 to obtain the seventh battery middle piece; and further etching is performed on the back side 202 of the substrate and texturing is performed on the front side 201 of the substrate so that the battery morphology is as follows: Figure 8 As shown. Preferably, the preparation conditions for the second laser grooving can be as follows: wavelength of 500nm~600nm; square spot, overlap rate of 70-80%; laser frequency of 400kHz~600kHz, power of 10w~50w. Further: This embodiment preferably uses a mixture of KOH solution and deionized water in a volume ratio of (2-8): (10-20) to clean the grooved area (i.e., the location of the isolation area 26) and to texture the front side 201 of the substrate at the same time. The preferred concentration of the KOH solution is 45-55wt%, the etching temperature is 50-80℃, and the etching time is 120s~300s. On this basis, a cleaning solution is used to remove the mask push layer 313 using a mixture of HF and deionized water in a volume ratio of (0.02-0.06): (10-100). Exemplarily, the cleaning solution may also be used to simultaneously remove the phosphosilicate glass layer formed on the back side 202 of the substrate during the phosphorus diffusion process, and the preferred cleaning time is 10s to 200s.

[0051] Finally, combine Figure 8 And return the reference Figure 2 , an ALD machine can be further used to form a double-sided passivation layer 23 (for example, aluminum oxide), and the thickness of the passivation layer 23 is preferably 4nm to 5nm. Then, a double-sided anti-reflection layer 24 (for example, silicon nitride) is prepared by PECVD, and the thickness of the anti-reflection layer 24 is preferably 70nm to 90nm. On this basis, screen printing is performed on one side of the back side 202 of the substrate to form a first electrode 251 and a second electrode 252.

[0052] In order to better understand the technical effects of this application, Fig. 9A photovoltaic cell 40 made by conventional preparation means is shown, which has a substrate 400 and two doped regions on the back of the cell, the two doped regions respectively including a tunneling layer 411, a tunneling layer 421 and a doped polysilicon layer 412 and a doped polysilicon layer 422 with different doping elements. If conventional preparation means are used, since the mask push layer of the present application is not used, then referring to the above preparation process, when the grooved area (that is, the position corresponding to the doped area prepared later) is etched after the first laser groove, etching residue 43 is likely to appear in the grooved area at the edge of the silicon wafer, and it cannot be completely etched, affecting the efficiency of the cell. This is because the conventional preparation means uses BSG to provide doping impurities, which has the characteristics of being thin in the middle and thick at the edge during the formation process, so it cannot be completely removed by laser groove and solution etching (excessive removal depth will also affect the overall structure of the battery, such as having adverse consequences such as thinning the substrate). In addition, due to the use of the BSG layer, when preparing the doping area corresponding to another doping element, that is, phosphorus diffusion, the BSG on the P poly surface may not be able to completely block the phosphorus atoms. The phosphorus atoms will enter the Ppoly area, destroy the passivation of Ppoly, and affect the battery efficiency.

[0053] In contrast, the above-mentioned technical solution of the present application prepares the mask advancement layer 313 after preparing the functional layers related to the first doping region 21. Preferably, the mask advancement layer 313 uses silicon nitride containing boron elements. During deposition, a uniform and flat deposition of the entire surface can be achieved based on the material properties. Therefore, the difficulties caused by the unfavorable morphology of high sides and low middle when using BSG in the traditional method for the subsequent preparation process are solved. At the same time, as a phosphorus element barrier layer during subsequent phosphorus diffusion, the battery preparation method and battery efficiency are optimized.

[0054] Specifically, the mask advancement layer 313 deposited in the present application can be a dielectric material containing nitrogen such as silicon nitride or silicon oxynitride, and contains group III elements (for example, one or more of boron, gallium, and indium). The mask advancement layer 313 is very uniform and does not react with alkali. After the first laser grooving and etching, there will be no residual phenomenon in the etched area at the edge of the silicon wafer, which reserves a wider window for the wet process. Further, the blocking effect of the mask advancement layer 313 in the phosphorus diffusion step is better than BSG. When phosphorus diffusion is performed, phosphorus atoms will not enter the Ppoly region, thereby improving the battery efficiency. In addition, in a preferred embodiment of the present application, high-temperature advancement can be performed directly after the mask advancement layer 313 is deposited, but when high-temperature phosphorus diffusion is performed later, the group III elements in the mask advancement layer 313 are simultaneously advanced into the first intrinsic amorphous silicon layer 312 adjacent thereto, so as to realize the preparation of the first doped polysilicon layer 212 doped with boron, and finally form the first doped region 21, i.e., the Ppoly region. In such an embodiment, the entire process has only one high-temperature process, that is, one-step high-temperature advancement, which reduces process risks, reduces production defects, and reduces production costs.

[0055] The basic concepts have been described above. Obviously, for those skilled in the art, the above application disclosure is only an example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0056] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0057] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more application embodiments, in the above description of the embodiments of this application, multiple features are sometimes merged into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0058] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, the numerical parameters should take into account the specified significant digits and adopt the general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0059] Although the present application has been described with reference to the current specific embodiments, ordinary technicians in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions may be made without departing from the spirit of the present application. Therefore, as long as the changes and modifications to the above embodiments are within the essential spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A method for preparing a photovoltaic cell, characterized in that: The steps include: Providing a substrate, wherein the substrate has a front side of the substrate and a back side of the substrate opposite to each other, wherein the front side of the substrate is closer to the light-facing side of the photovoltaic cell than the back side of the substrate; After preparing a first tunneling layer and a first intrinsic amorphous silicon layer on the back side of the substrate, a first battery intermediate component is obtained; A second battery intermediate component is obtained after depositing a mask advancement layer on the back side of the substrate of the first battery intermediate component, wherein the mask advancement layer has both nitrogen and a first doping element, and the mask advancement layer is suitable for converting the first intrinsic amorphous silicon layer into a first doped polysilicon layer having the first doping element after high-temperature advancement; and A second doping region is prepared on the back side of the substrate to obtain the photovoltaic cell, wherein the second doping region includes a second doping element different from the first doping element.

2. The preparation method according to claim 1, characterized in that The method further includes performing high-temperature advancement on the first intrinsic amorphous silicon layer through the mask advancement layer on the second battery intermediate component to obtain a third battery intermediate component having a first doping region, wherein the first doping region contains the first doping element; as well as The second doping region is prepared on the back side of the substrate of the third battery intermediate component.

3. The preparation method according to claim 2, characterized in that: The step of preparing a second doping region on the back side of the substrate of the third battery intermediate component comprises: Performing a first laser groove on a back side of the substrate of the third battery intermediate component at a position corresponding to the second doping region to obtain a fourth battery intermediate component; After preparing a second tunneling layer and a second intrinsic amorphous silicon layer on the back side of the substrate of the fourth cell intermediate component, a fifth cell intermediate component is obtained; and The second intrinsic amorphous silicon layer is diffused with the second doping element to obtain a sixth battery intermediate member.

4. The preparation method according to claim 3, characterized in that: The method also includes performing a second laser grooving on the sixth battery intermediate member to form an isolation region between the first doping region and the second doping region, thereby obtaining a seventh battery intermediate member.

5. The preparation method according to claim 4, characterized in that: The method further includes etching the back side of the substrate and texturing the front side of the substrate after the second laser grooving.

6. The preparation method according to claim 4, characterized in that: The method also includes preparing a double-sided passivation layer and / or a double-sided anti-reflection layer for the seventh battery intermediate component.

7. The preparation method according to claim 6, characterized in that: The passivation layer includes aluminum oxide, and the anti-reflection layer includes silicon nitride.

8. The preparation method according to claim 1, characterized in that: The method also includes performing the high temperature advancement while preparing the second doping region, so as to transform the first intrinsic amorphous silicon layer into a first doped polysilicon layer having a first doping element.

9. The preparation method according to any one of claims 1 to 8, characterized in that: The first doping element includes a Group III element, and the second doping element includes phosphorus.

10. The preparation method according to any one of claims 1 to 8, characterized in that: It also includes depositing the mask advancement layer by PECVD, and controlling the following preparation conditions when depositing the mask advancement layer: pressure of 1000-2000mTorr, and / or silane amount of 1000-3000sccm, and / or ammonia amount of 10000-20000sccm, and / or diborane amount of 100-2000sccm.

11. The preparation method according to any one of claims 1 to 8, characterized in that: The method also includes removing the mask push-in layer by a cleaning solution after preparing the second doping region.

12. The preparation method according to claim 11, characterized in that: The cleaning solution is a mixed solution of HF and deionized water in a volume ratio of (0.02-0.06):(10-100).

13. A photovoltaic cell, characterized in that: The photovoltaic cell is prepared according to the preparation method according to any one of claims 1 to 12.

14. A photovoltaic cell, characterized in that: The photovoltaic cell comprises: A substrate, wherein the substrate has a front side of the substrate and a back side of the substrate opposite to each other, wherein the front side of the substrate is closer to the light-facing side of the photovoltaic cell than the back side of the substrate; The first doping region and the second doping region are both located on the back side of the substrate, wherein: The first doping region includes a first doping element, and the second doping region includes a second doping element different from the first doping element; The first doped region is obtained by performing high-temperature driving of a first intrinsic amorphous silicon layer adjacent to the mask driving layer using a mask driving layer.

15. The photovoltaic cell according to claim 14, characterized in that The mask push-up layer is removed by a cleaning solution after the second doping region is formed during the preparation process of the photovoltaic cell.

16. The photovoltaic cell according to claim 15, characterized in that The cleaning solution comprises a mixed solution of HF and deionized water in a volume ratio of (0.02-0.06):(10-100).