Photovoltaic cell piece preparation method, photovoltaic cell piece and photovoltaic module

Abstract

The invention relates to a photovoltaic cell piece preparation method, a photovoltaic cell piece and a photovoltaic module, and the preparation method comprises the steps: providing a silicon substrate which is provided with a first sunken part which is sunken towards the interior of the silicon substrate; forming a tunneling layer at least in the first sunken part, and enabling the tunneling layer to further form a second sunken part which is sunken towards the interior of the first sunken part; at least forming a doped dielectric layer in the second sunken part, and enabling the doped dielectric layer to further form a third sunken part which is sunken towards the interior of the second sunken part; and forming a metal electrode in metallization contact with the doped dielectric layer in the third sunken part. According to the photovoltaic cell piece and the preparation method, the photoelectric conversion efficiency of the photovoltaic cell piece can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic cells, and in particular to a method for preparing a photovoltaic cell, a photovoltaic cell and a photovoltaic module. Background Art

[0002] The photoelectric conversion efficiency of photovoltaic cells in the prior art is low. Summary of the invention

[0003] In view of this, the present application provides a method for preparing a photovoltaic cell, a photovoltaic cell and a photovoltaic module to improve the photoelectric conversion efficiency of the photovoltaic cell.

[0004] In a first aspect, the present application provides a method for preparing a photovoltaic cell, the method comprising: providing a silicon substrate, wherein the silicon substrate is provided with a first recessed portion recessed into the silicon substrate; forming a tunneling layer at least in the first recessed portion, and the tunneling layer is also formed with a second recessed portion recessed into the first recessed portion; forming a doped medium layer at least in the second recessed portion, and the doped medium layer is also formed with a third recessed portion recessed into the second recessed portion; and forming a metal electrode in the third recessed portion that is in metallization contact with the doped medium layer.

[0005] Compared with the prior art, in the preparation method of the present application, since the tunneling layer and the doped medium layer are sequentially formed in the first recessed portion of the silicon substrate, and the second recessed portion and the third recessed portion are correspondingly formed in sequence. In the process of preparing the metal electrode (the metal electrode corresponding to the third recessed portion), the third recessed portion can be used as a guide structure, that is, the third recessed portion can guide the raw material for forming the metal electrode to move into the third recessed portion, so that the raw material for forming the metal electrode is distributed in the depth direction of the third recessed portion, so that the area of ​​the contact surface between the formed metal electrode and the doped medium layer is relatively large, so that the contact resistance between the metal electrode and the doped medium layer is relatively small, that is, the conductivity between the metal electrode and the doped medium layer is strong.

[0006] Compared with the prior art, in the preparation method of the present application, the third recess can also serve as a shaping structure, that is, the third recess can play a good shaping role on the raw materials used to form the metal electrode. It can also be said that the size of the metal electrode that can be formed can be limited by the third recess. The metal electrode is not easy to cover more doped medium layers. The area in the doped medium layer that can be illuminated by light is relatively large. More light enters the silicon substrate through the doped medium layer, and the number of photogenerated electrons and photogenerated holes that can be generated by the silicon substrate is relatively large.

[0007] Therefore, the photovoltaic cell prepared by the preparation method of the embodiment of the present application has a higher photoelectric conversion efficiency.

[0008] Furthermore, compared with the prior art, the preparation method of the present application makes the position accuracy of the formed bottom metal electrode relatively high, that is, the probability that the formed bottom metal electrode as a whole is within the predetermined range is high. In the subsequent process of forming a battery string, the contact area between the bottom metal electrode and the welding strip is relatively large, and the contact resistance between the bottom metal electrode and the welding strip is relatively low, thereby making the output power of the finally formed photovoltaic module relatively high.

[0009] Optionally, before providing a silicon substrate having a first recessed portion, the preparation method further includes: using a laser to remove a local structure of the silicon substrate to form the first recessed portion; or, forming a patterned mask layer on the silicon substrate, wherein the patterned mask layer is provided with a window, and using an acid or alkaline solution to remove the local structure of the portion of the silicon substrate exposed by the window to form the first recessed portion.

[0010] Optionally, the method of removing a local structure of the silicon substrate to form the first recessed portion includes: removing a portion of the silicon substrate having a depth D 1 A local structure of 1 μm to 20 μm; and / or, removing a width dimension W from the silicon substrate 1 It is a local structure of 10μm to 200μm.

[0011] Optionally, the thickness H of the tunneling layer is controlled 1 The thickness of the doped dielectric layer H 2 The sum is less than the depth dimension D of the first recessed portion 1 ; Control the thickness of the tunneling layer H 1 The thickness of the doped dielectric layer H 2 The sum of the two times is less than the width dimension W of the first recessed portion. 1 .

[0012] Optionally, after forming the doped medium layer and before forming the metal electrode, the preparation method further includes: forming a first passivation layer containing hydrogen elements at least in the third recessed portion, and forming a fourth recessed portion recessed into the third recessed portion in the first passivation layer; annealing treatment.

[0013] In a second aspect, the present application provides a photovoltaic cell, which can be prepared by the preparation method described above, and the photovoltaic cell includes a silicon substrate, a tunneling layer, a doped conductive layer and a metal electrode. The silicon substrate is provided with a first recessed portion recessed toward the silicon substrate; at least part of the structure of the tunneling layer is located in the first recessed portion, and the tunneling layer is provided with a second recessed portion recessed toward the first recessed portion; at least part of the structure of the doped conductive layer is at least located in the second recessed portion, and the doped conductive layer is provided with a third recessed portion recessed toward the second recessed portion and also recessed toward the first recessed portion; at least part of the structure of a portion of the metal electrodes is located in the third recessed portion, and a portion of the metal electrodes are in metallization contact with the doped conductive layer.

[0014] Optionally, the first recessed portion has a set depth dimension D 1 , depth dimension D 1 The first recessed portion has a width W of 1 μm to 20 μm. 1 , width dimension W 1 Meet 10μm~200μm.

[0015] Optionally, the metal electrode disposed in the third recessed portion has a set height dimension D 5 , height dimension D 5 5 μm to 30 μm; and / or the metal electrode disposed in the third recess has a set width dimension W 5 , width dimension W 5 Meet 10μm~50μm.

[0016] Optionally, the doped conductive layer includes a first part and a second part, the first part is located in the second recessed portion, the first part is in metallization contact with the corresponding metal electrode, and the second part is located outside the second recessed portion, and the second part is not in metallization contact with the metal electrode; the size of the first part in the thickness direction of the photovoltaic cell is larger than the size of the second part in the thickness direction of the photovoltaic cell.

[0017] In a third aspect, the present application provides a photovoltaic module, which includes a plurality of photovoltaic cells electrically connected to form a battery string as described above. The photovoltaic module of the present application also includes the technical effects of the photovoltaic cells described above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0019] Figure 1 is a schematic structural diagram of a silicon substrate in a specific embodiment;

[0020] Figure 2 is a schematic structural diagram of a silicon substrate and a tunneling layer in a specific embodiment;

[0021] Figure 3 is a schematic structural diagram of a silicon substrate, a tunneling layer and a doped dielectric layer in a specific embodiment;

[0022] Figure 4It is a schematic structural diagram of a silicon substrate, a tunneling layer, a doped dielectric layer, a first passivation layer and a bottom metal electrode in a specific embodiment;

[0023] Figure 5 is a schematic structural diagram of a silicon substrate in a specific embodiment, wherein the silicon substrate is not provided with a first recessed portion;

[0024] Figure 6 is a schematic structural diagram of a silicon substrate and a patterned mask layer, wherein the silicon substrate is not provided with a first recessed portion;

[0025] Figure 7 It is a schematic diagram of the structure of a silicon substrate and a patterned mask layer, wherein the silicon substrate is provided with a first recessed portion;

[0026] Figure 8 is a schematic structural diagram of a silicon substrate, a tunneling layer, a doped dielectric layer and a first passivation layer in a specific embodiment;

[0027] Fig. 9 A schematic diagram of the structure of a silicon substrate, a tunneling layer, a doped dielectric layer and a patterned first passivation layer in a specific embodiment;

[0028] Fig.10 This is a schematic diagram of the structure of a photovoltaic cell provided in this application in a specific embodiment.

[0029] Reference numerals:

[0030] 1-Silicon substrate;

[0031] 1a-first recessed portion;

[0032] 2- tunneling layer;

[0033] 2a-second recessed portion;

[0034] 3- doped dielectric layer;

[0035] 3a-third recessed portion;

[0036] 30-doped conductive layer;

[0037] 301-Part I;

[0038] 302-Part II;

[0039] 4- first passivation layer;

[0040] 4a- fourth recessed portion;

[0041] 5- bottom metal electrode;

[0042] 51-crystal part;

[0043] 6- diffusion layer;

[0044] 7- second passivation layer;

[0045] 71-aluminum oxide passivation layer;

[0046] 72-silicon nitride passivation layer;

[0047] 8-top metal electrode;

[0048] 9-patterned mask layer;

[0049] 9a-Window. DETAILED DESCRIPTION

[0050] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0051] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0052] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0053] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0054] In the figures of this document, direction X is perpendicular to direction Y, and direction Y is the direction from the bottom to the top of the photovoltaic cell, and the top of the photovoltaic cell is the part directly illuminated by sunlight. The dotted lines in the figures of this document are structural section lines to show the local structure.

[0055] In a first aspect, an embodiment of the present application provides a method for preparing a photovoltaic cell sheet, and the preparation method includes the following contents.

[0056] Provide as Figure 1 The silicon substrate 1 shown in the figure is provided with a first recessed portion 1 a recessed into the silicon substrate 1 .

[0057] Among them, Figure 1As shown, the first recess 1a can be arranged at the bottom of the silicon substrate 1, so that the tunnel passivation structure and metal electrode corresponding to the first recess 1a to be formed subsequently are located at the bottom of the silicon substrate 1, thereby forming a tunnel passivated contact photovoltaic cell (Tunnel Oxide Passivated Contact, TOPCon).

[0058] In other embodiments (not shown in the figures), the first recessed portion may also be disposed on the top of the silicon substrate so that the tunneling passivation structure and metal electrode corresponding to the first recessed portion to be formed subsequently are located on the top of the silicon substrate, thereby forming a tunneling passivation contact photovoltaic cell.

[0059] In other embodiments (not shown in the figures), recessed portions may be provided at the bottom and the top of the silicon substrate, so that a tunneling passivation structure and a metal electrode corresponding to the top recessed portion to be formed subsequently may be located at the top of the silicon substrate, and a tunneling passivation structure and a metal electrode corresponding to the bottom recessed portion to be formed subsequently may be located at the bottom of the silicon substrate, thereby forming a tunneling passivation contact photovoltaic cell.

[0060] In addition, the silicon substrate 1 may be an N-type substrate, and at least one N-type element (element of the fifth main group in the periodic table of chemical elements) may be doped in the silicon substrate 1, such as phosphorus, arsenic, antimony and other N-type elements. In other embodiments, the silicon substrate 1 may also be a P-type substrate, and at least one P-type element (element of the third main group in the periodic table of chemical elements) may be doped in the silicon substrate 1, such as boron, aluminum, gallium and other P-type elements.

[0061] After obtaining the silicon substrate 1 having the first recessed portion 1a, at least a Figure 2 The tunnel layer 2 shown in the figure further has a second recessed portion 2a recessed into the first recessed portion 1a.

[0062] The tunneling layer 2 may include at least one of silicon oxide, silicon nitride and silicon oxynitride, the thickness of the tunneling layer 2 is nanometer-level, and the photogenerated carriers (such as electrons) generated by the silicon substrate 1 may pass through the tunneling layer 2 by means of the tunneling effect.

[0063] In addition, the preparation process of the tunnel layer 2 may include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD).

[0064] After forming the tunnel layer 2, at least in the second recessed portion 2a, a Figure 3 The doped medium layer 3 is shown, and the doped medium layer 3 is further formed with a third recessed portion 3a recessed into the second recessed portion 2a.

[0065] The doped medium layer 3 may include at least one of polycrystalline silicon, amorphous silicon and microcrystalline silicon.

[0066] In addition, the doped medium layer 3 may be doped with at least one N-type element described above, or the doped medium layer 3 may be doped with at least one P-type element described above.

[0067] Furthermore, the method for forming the doped dielectric layer 3 includes: first forming an intrinsic layer containing at least one of polycrystalline silicon, amorphous silicon and microcrystalline silicon, wherein the intrinsic layer is not doped with impurities. The preparation process for forming the doped dielectric layer 3 may specifically include low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition or normal pressure chemical vapor deposition. Then, the impurities are diffused into the intrinsic layer using a diffusion process to form the doped dielectric layer 3. Alternatively, the method for forming the doped dielectric layer 3 includes: directly using plasma enhanced chemical vapor deposition to form the doped dielectric layer 3 containing doped impurities.

[0068] In addition, before the doped dielectric layer 3 is annealed, the crystallization rate of the doped dielectric layer 3 is relatively low, and even if the doped dielectric layer 3 is doped with impurities for conductivity, the conductivity of the doped dielectric layer 3 is relatively weak. After the doped dielectric layer 3 is annealed, the crystallization rate of the doped dielectric layer 3 is high, that is, the doped dielectric layer 3 mainly includes polysilicon and conductive impurities, and accordingly, the conductivity of the doped dielectric layer 3 is high, and the doped dielectric layer 3 can also be regarded as a doped conductive layer.

[0069] After forming the doped dielectric layer 3, a Figure 4The metal electrode shown is in metallization contact with the doped dielectric layer 3. Since the description is based on the example of "the third recessed portion 3a at the bottom of the silicon substrate 1", the metal electrode formed in the third recessed portion 3a can also be referred to as the bottom metal electrode 5, and the bottom metal electrode 5 can be used to electrically connect to an external circuit. Correspondingly, a top metal electrode (not shown in the figure) can be provided above the top of the silicon substrate 1 (not shown in the figure), and the bottom metal electrode 5 and the top metal electrode have opposite electrical polarities.

[0070] In other embodiments (not shown in the figures), all metal electrodes can be arranged on the bottom side of the silicon substrate, and the impurity type doped in the doped medium layer corresponding to a part of the metal electrodes is different from the impurity type doped in the doped medium layer corresponding to another part of the metal electrodes. Therefore, the prepared photovoltaic cell can be a back contact cell (Back Contact) with a tunneling passivation contact structure.

[0071] The subsequent content of this article mainly describes the preparation method of an embodiment of the present application using "a first recessed portion 1a located at the bottom of the silicon substrate 1, the silicon substrate 1 is an N-type substrate, the doped medium layer 3 is doped with at least one N-type element, a bottom metal electrode 5 is formed at the bottom of the silicon substrate 1 and a top metal electrode is formed above the silicon substrate 1" as an example.

[0072] The preparation method of the prior art mainly forms a metal electrode on a doped dielectric layer without a recessed portion. The preparation method of the prior art has the following disadvantages:

[0073] The portion of the formed metal electrode that can enter the doped dielectric layer has a smaller length dimension along the thickness direction of the photovoltaic cell. In other words, the area of ​​the contact surface between the formed metal electrode and the doped dielectric layer extending along the thickness direction of the photovoltaic cell is smaller, which makes the contact resistance between the metal electrode and the doped dielectric layer larger, that is, the conductivity between the metal electrode and the doped dielectric layer is weaker.

[0074] The shaping effect of the formed metal electrode is relatively poor, so that the dimensional accuracy of the formed metal electrode in the direction perpendicular to the thickness direction of the photovoltaic cell is low, and the formed metal electrode is easy to cover more doped medium layers in the direction perpendicular to the thickness direction of the photovoltaic cell. The area in the doped medium layer that can be irradiated by light is relatively small, and less light enters the silicon substrate through the doped medium layer, and the number of photogenerated electrons and photogenerated holes that can be generated by the silicon substrate is relatively small.

[0075] Therefore, the photovoltaic cell prepared by the preparation method of the prior art has a low photoelectric conversion efficiency.

[0076] Furthermore, since the shaping effect of the metal electrode prepared by the preparation method of the prior art is relatively poor, the position accuracy of the formed metal electrode is also relatively low, so that the local part of the formed metal electrode may deviate from the predetermined range. In the subsequent process of forming a battery string, the contact area between the metal electrode and the welding strip is relatively small, and there are even non-contact parts between the metal electrode and the welding strip, which makes the contact resistance between the metal electrode and the welding strip relatively large, which can easily lead to a relatively low output power of the final photovoltaic module.

[0077] Compared with the prior art, in the preparation method of the embodiment of the present application, the tunneling layer 2 and the doped medium layer 3 are sequentially formed in the first recessed portion 1a of the silicon substrate 1, and the second recessed portion 2a and the third recessed portion 3a are sequentially formed accordingly.

[0078] Compared with the prior art, in the process of preparing the bottom metal electrode 5, the third recessed portion 3a can be used as a guiding structure, that is, the third recessed portion 3a can guide the raw material for forming the bottom metal electrode 5 to move into the third recessed portion 3a, so that the raw material for forming the bottom metal electrode 5 is distributed in the depth direction (direction Y) of the third recessed portion 3a, so that the area of ​​the contact surface extending along the direction Y between the formed bottom metal electrode 5 and the doped medium layer 3 is relatively large, so that the contact resistance between the bottom metal electrode 5 and the doped medium layer 3 is relatively small, that is, the conductivity between the bottom metal electrode 5 and the doped medium layer 3 is strong.

[0079] Compared with the prior art, in the process of preparing the bottom metal electrode 5, the third recessed portion 3a can also serve as a shaping structure, that is, the third recessed portion 3a can play a good shaping role on the raw materials used to form the bottom metal electrode 5. It can also be said that the size of the bottom metal electrode 5 that can be formed along the direction X can be limited by the third recessed portion 3a. The bottom metal electrode 5 is not easy to cover more doped medium layers 3 in the direction X. The area of ​​the doped medium layer 3 that can be illuminated by light is relatively large. More light enters the silicon substrate 1 through the doped medium layer 3, and the number of photogenerated electrons and photogenerated holes that can be generated by the silicon substrate 1 is relatively large.

[0080] Therefore, the photovoltaic cell prepared by the preparation method of the embodiment of the present application has a higher photoelectric conversion efficiency.

[0081] Furthermore, compared with the prior art, the preparation method of the embodiment of the present application makes the position accuracy of the formed bottom metal electrode 5 relatively high, that is, the probability that the formed bottom metal electrode 5 as a whole is within the predetermined range is high. In the subsequent process of forming a battery string, the contact area between the bottom metal electrode 5 and the welding strip (not shown in the figure) is relatively large, and the contact resistance between the bottom metal electrode 5 and the welding strip is relatively low, thereby making the output power of the finally formed photovoltaic module relatively high.

[0082] If the doped dielectric layer 3 is doped with an N-type element, the raw material used to form the bottom metal electrode 5 mainly includes silver, and a gap can be formed between the bottom metal electrode 5 and the doped dielectric layer 3. Figure 4 The crystallized portion 51 shown includes silver grains. The formation of the silver grains can provide a lower contact resistance between the bottom metal electrode 5 and the doped dielectric layer 3. Since the preparation method of the embodiment of the present application can make the area of ​​the contact surface extending along the direction Y between the bottom metal electrode 5 and the doped dielectric layer 3 relatively larger than that of the prior art, correspondingly, the number of silver grains between the bottom metal electrode 5 and the doped dielectric layer 3 is also greater than that of the prior art, so that the contact resistance between the bottom metal electrode 5 and the doped dielectric layer 3 is lower than that of the prior art.

[0083] If the doped dielectric layer 3 is doped with a P-type element, the raw materials used to form the bottom metal electrode 5 may include silver and aluminum. The effect of containing silver has been described above and will not be repeated here. Aluminum can recrystallize and precipitate with silicon in the doped dielectric layer 3 to form a heavily doped aluminum-containing region, and a high-low junction (P) can be formed between the heavily doped aluminum-containing region and the non-aluminum-containing region in the doped dielectric layer. + / P), the high-low junction helps to increase the diffusion length of photogenerated carriers (such as holes), reduce the recombination rate of photogenerated carriers, and thus improve the photoelectric conversion efficiency. Since the preparation method of the embodiment of the present application can make the area of ​​the contact surface extending along the direction Y between the bottom metal electrode 5 and the doped medium layer 3 relatively large compared with the prior art, accordingly, the area of ​​the high-low junction between the bottom metal electrode 5 and the doped medium layer 3 is relatively large, which helps to improve the photoelectric conversion efficiency.

[0084] In addition, the process of forming the bottom metal electrode 5 may include slurry printing and sintering. The slurry printing may be specifically screen printing or steel plate printing, both of which print the metal-containing slurry on the substrate (not finally forming the structural member of the photovoltaic cell), and make the slurry printed on the substrate in a line shape. After printing, the slurry is dried and then sintered to form the bottom metal electrode 5 in metallization contact with the doped medium layer 3.

[0085] In the prior art, it is necessary to use high temperature (greater than 300°C) to make the slurry burn through the doped medium layer without a recessed portion so that the slurry has a certain length dimension in the thickness direction of the photovoltaic cell, but the high temperature easily leads to a large thermal stress in the formed photovoltaic cell, which easily leads to the problem of rupture of the photovoltaic cell. In the preparation method of the embodiment of the present application, since the slurry has fluidity before being dried and sintered, the slurry can flow along the depth direction (direction Y) of the third recessed portion 3a to fill the third recessed portion 3a, so that the slurry has a corresponding length dimension in the depth direction (direction Y). Therefore, the slurry can be sintered at a low temperature (a temperature greater than 120°C but less than 300°C), and the low temperature is not easy to cause a large thermal stress in the formed photovoltaic cell, so that the photovoltaic cell is not prone to rupture.

[0086] In the preparation method of the embodiment of the present application, the third recessed portion 3a can limit the flow of the slurry relative to the substrate in the direction X, so that the slurry has a better shaping effect, thereby making the formed bottom metal electrode 5 have a higher dimensional accuracy in the direction X, and the bottom metal electrode 5 is not easy to cover too much of the doped medium layer 3, and the formed bottom metal electrode 5 has a higher position accuracy in the direction X, and the contact resistance between the bottom metal electrode 5 and the subsequent soldering strip to be soldered is lower.

[0087] In other embodiments, the process of forming the bottom metal electrode 5 may also include laser transfer, electroplating, inkjet or sputtering.

[0088] It should be noted that when forming the bottom metal electrode 5 , the opening of the third recessed portion 3 a needs to face upward, so that the material for forming the bottom metal electrode 5 falls into the third recessed portion 3 a .

[0089] Optionally, before providing the silicon substrate having the first recessed portion, the preparation method of the embodiment of the present application further comprises: removing the silicon substrate having the first recessed portion by laser. Figure 5 The local structure of the silicon substrate 1 is shown to form Figure 1 The first recessed portion 1a is shown.

[0090] In the formation of Figure 1 After the first recess 1a is formed, the surface of the first recess 1a can be polished using processes such as mechanical polishing, chemical mechanical polishing or plasma polishing to eliminate microscopic defects and impurities on the surface of the first recess 1a, which can reduce the number of recombination centers on the surface of the first recess 1a, thereby helping to improve the photoelectric conversion efficiency of the photovoltaic cell.

[0091] In other embodiments, alkaline solution can also be used to corrode the surface of the first recessed portion to form a velvet surface (having multiple micron-sized grooves) on the surface of the first recessed portion. The velvet surface is used to improve the efficiency of light entering the silicon substrate through the tunneling layer, thereby helping to improve the photoelectric conversion efficiency of the photovoltaic cell.

[0092] Optionally, before providing the silicon substrate having the first recessed portion, the preparation method of the embodiment of the present application further comprises: Figure 5 The silicon substrate 1 shown is formed as Figure 6 The patterned mask layer 9 shown in FIG. 1 is provided with a window 9a, and the patterned mask layer 9 is resistant to acid or alkali corrosion. The local structure of the part of the silicon substrate 1 exposed by the window 9a can be removed by acid or alkali to form a Figure 7 The first recessed portion 1a is shown.

[0093] The patterned mask layer 9 can be directly formed by screen printing. Alternatively, a photoresist (not shown in the figure) is applied to the silicon substrate 1 as shown in the figure, partial exposure is performed, and the exposed part or the unexposed part is cleaned to form the patterned mask layer 9. Alternatively, a mask layer (not shown in the figure) is formed on the silicon substrate 1 as shown in the figure by a printing or coating process, and a local structure of the mask layer is removed by laser to form the patterned mask layer 9.

[0094] After the first recessed portion 1 a is formed, the patterned mask layer 9 is removed by tearing off or washing with an organic solvent.

[0095] Optionally, the formed first recessed portion 1 a may be a hole structure or a groove structure.

[0096] Optionally, the method of removing a local structure of the silicon substrate 1 to form the first recessed portion 1a comprises: Figure 5 The silicon substrate 1 is removed to a depth D as shown. 1 The local structure is 1μm to 20μm to form Figure 1 Depth dimension D shown 1 The first recessed portion 1a is 1 μm to 20 μm. 1 The first recessed portion 1a is convenient for forming a tunneling layer 2 with a nanometer thickness naturally with a set depth dimension D when forming the tunneling layer 2 with a nanometer thickness. 2 The second recessed portion 2a is formed naturally with a set depth dimension D when the doped medium layer 3 with a nanometer thickness is formed later. 3 The third recessed portion 3a does not need to be formed by removing the third recessed portion 3a, that is, the depth dimension D is set without the need for additional removal. 2 The second recessed portion 2a and the belt setting depth dimension D 3Therefore, the preparation method of the embodiment of the present application has the advantage of high preparation efficiency.

[0097] Among them, the depth dimension D 1 Specifically, it can be 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm or 20μm.

[0098] Optionally, the method of removing a local structure of the silicon substrate 1 to form the first recessed portion 1a comprises: Figure 5 The silicon substrate 1 shown has a width dimension W removed. 1 The local structure is 10μm to 200μm to form Figure 1 Width dimension W shown 1 The first recessed portion 1a is 10 μm to 200 μm. 1 The first recessed portion 1a is convenient for forming a tunneling layer 2 with a nanometer thickness naturally with a set width W when forming the tunneling layer 2 with a nanometer thickness. 2 The second recessed portion 2a is formed naturally with a set width W when the doped medium layer 3 with a nanometer thickness is formed later. 3 The third recessed portion 3a does not need to be removed to form a set width dimension W. 2 The second recessed portion 2a and the set width dimension W 3 Therefore, the preparation method of the embodiment of the present application has the advantage of high preparation efficiency.

[0099] Among them, the width dimension W 1 Specifically, it can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm or 200μm.

[0100] Optionally, see Figure 3 As shown, the thickness H of the tunneling layer 2 is controlled 1 The thickness H of the doped dielectric layer 3 2 The sum is less than the depth dimension D of the first recessed portion 1a. 1 . Control the thickness H of the tunneling layer 2 1 The thickness H of the doped dielectric layer 3 2 The sum of the two is less than the width W of the first recessed portion 1a. 1Under this setting, in addition to not needing to form the second recessed portion 2a with a set size and the third recessed portion 3a with a set size by additional removal, that is, having the advantage of higher preparation efficiency, the third recessed portion 3a can also be recessed into the first recessed portion 1a, so that the bottom metal electrode 5 also extends into the first recessed portion 1a, so that the length dimension of the bottom metal electrode 5 in the direction Y is longer, so that the contact resistance between the bottom metal electrode 5 and the doped medium layer 3 is smaller, thereby making the prepared photovoltaic cell sheet have a higher photoelectric conversion efficiency.

[0101] The thickness of the tunneling layer 2 is H 1 The range is 0.5nm~5nm, and the thickness dimension H 1 Specifically, it can be 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm or 5 nm. It should be noted that if a portion of the tunneling layer 2 extends along the direction X, the thickness dimension H of the portion is 1 It can be the dimension along direction Y. If another part of the tunneling layer 2 extends along direction Y, the thickness dimension H of this part is 1 It can be the dimension along direction X.

[0102] In addition, the thickness dimension H of the doped dielectric layer 3 is 2 The range is between 50nm and 500nm, and the thickness dimension H 2 Specifically, it may be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm or 500 nm. It should be noted that if a portion of the doped dielectric layer 3 extends along the direction X, the thickness dimension H of the portion is 2 It can be the dimension along direction Y. If another part of the doped medium layer 3 extends along direction Y, the thickness dimension H of this part is 2 It can be the dimension along direction X.

[0103] In other embodiments (not shown in the figures), the size of the tunneling layer formed in the first recessed portion may not be controlled, that is, the tunneling layer may be formed entirely in the first recessed portion, and then a laser may be used to remove part of the tunneling layer to form the second recessed portion.

[0104] In other embodiments (not shown in the figure), the size of the doped dielectric layer formed in the second recessed portion may not be controlled, that is, the doped dielectric layer may be formed entirely in the second recessed portion, and then a laser may be used to remove part of the doped dielectric layer to form a third recessed portion.

[0105] In other embodiments (not shown in the figures), the second recessed portion may be recessed into the first recessed portion, and the third recessed portion may be recessed into the second recessed portion, but the third recessed portion may not be recessed into the first recessed portion, that is, the bottom metal electrode may not extend into the first recessed portion.

[0106] It should be noted that, the “into the recessed portion” described herein generally refers to “into the space enclosed by the recessed portion”.

[0107] Optionally, after forming the doped dielectric layer 3 and before forming the bottom metal electrode 5, the preparation method of the embodiment of the present application further includes forming at least one of the following indentations in the third recess 3a: Figure 8 The first passivation layer 4 containing hydrogen elements is shown, and the first passivation layer 4 is also formed with a fourth recessed portion 4a recessed into the third recessed portion 3a. After the first passivation layer 4 containing hydrogen elements is formed, annealing treatment is performed. During the annealing process, the hydrogen elements contained in the portion of the first passivation layer 4 located in the third recessed portion 3a can diffuse to the surface of the silicon substrate 1 used to enclose the first recessed portion 1a, that is, the dangling bonds of the surface of the silicon substrate 1 used to enclose the first recessed portion 1a can be combined with hydrogen elements to reduce the number of recombination centers of the surface of the silicon substrate 1 used to enclose the first recessed portion 1a, so that the rate of recombination of photogenerated electrons and photogenerated holes generated by the silicon substrate of the prepared photovoltaic cell is low near the surface of the silicon substrate 1 used to enclose the first recessed portion 1a, thereby making the photoelectric conversion efficiency of the prepared photovoltaic cell higher.

[0108] Compared with the prior art in which a metal electrode is formed in a passivation layer without a recess, the technical effect brought by the fourth recess 4a is the same as the technical effect brought by the third recess 3a described above, and will not be repeated here. Although the first passivation layer 4 is formed in the third recess 3a in this embodiment, the first passivation layer 4 is also formed with a fourth recess 4a that is recessed into the third recess 3a. In the process of forming the bottom metal electrode 5, the raw material used to form the bottom metal electrode 5 enters the fourth recess 4a, and the raw material used to form the bottom metal electrode 5 also enters the third recess 3a, and the raw material used to form the bottom metal electrode 5 will also pass through the first passivation layer 4 during the sintering process to be metallized with the doped medium layer 3, and at least part of the structure of the bottom metal electrode 5 finally formed is in the third recess 3a. Therefore, the preparation method of this embodiment still has the technical effect brought by the third recess 3a described in the above content.

[0109] In the process of forming the bottom metal electrode 5, the first passivation layer 4 can have a certain degree of mitigating effect on the raw materials used to form the bottom metal electrode 5, reducing the possibility of the raw materials used to form the bottom metal electrode 5 diffusing to the tunneling layer 2 and the silicon substrate 1, thereby reducing the number of recombination centers on the surface of the silicon substrate 1 used to enclose the first recessed portion 1a, so that the rate at which photogenerated electrons and photogenerated holes generated by the silicon substrate of the prepared photovoltaic cell piece recombine near the surface of the silicon substrate 1 used to enclose the first recessed portion 1a is low, thereby making the photoelectric conversion efficiency of the prepared photovoltaic cell piece higher.

[0110] Please refer to Figure 8 As shown, the fourth recessed portion 4a may have a set depth dimension D 4 , depth dimension D 4 Meet 1μm~20μm, depth dimension D 4 Specifically, the fourth recessed portion 4a may have a set width W. 4 , width dimension W 4 Meet 10μm~200μm. Width dimension W 4 Specifically, it can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm or 200μm.

[0111] In addition, the first passivation layer 4 may include silicon nitride (α-SiN x :H). The preparation process for forming the first passivation layer 4 may specifically include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atmospheric pressure chemical vapor deposition (APCVD).

[0112] Furthermore, after the annealing treatment, the crystallization rate in the doped dielectric layer 3 is improved, that is, the amount of polycrystalline silicon in the doped dielectric layer 3 is larger than the amount of amorphous silicon, and the conductivity of the doped dielectric layer 3 is better. The doped dielectric layer 3 can be regarded as a doped conductive layer. The doped conductive layer and the tunneling layer 2 are combined to form a tunneling passivation contact structure, so that the prepared photovoltaic cell is a tunneling passivation contact cell (TOPCon).

[0113] In other embodiments, after forming the doped dielectric layer and before forming the bottom metal electrode, a first passivation layer containing hydrogen elements and provided with a fourth recess may be formed at least in the third recess, but annealing is not performed, but annealing is performed after forming the bottom metal electrode.

[0114] In other embodiments, please refer to Fig. 9 As shown, the first passivation layer may not be formed in the third recessed portion 3a, but a patterned first passivation layer 4 may be formed at least in the bottom of the silicon substrate except the third recessed portion.

[0115] Optionally, in the preparation method of the embodiment of the present application, in addition to forming the tunneling layer 2, the doped medium layer 3 and the first passivation layer 4 layer by layer on the basis of the surface of the first recessed portion 1a, the tunneling layer 2, the doped medium layer 3 and the first passivation layer 4 can also be formed layer by layer on the basis of the bottom of the silicon substrate 1 except the first recessed portion 1a.

[0116] In other embodiments (not shown in the figure), tunneling layers and doped dielectric layers may be formed layer by layer only on the surface of the first recessed portion, and a patterned first passivation layer may be directly formed on the bottom of the silicon substrate except for the first recessed portion. The patterned first passivation layer may be formed before forming the first recessed portion, or after forming the third recessed portion.

[0117] Since there may be many situations for the structure on the top of the silicon substrate, in the preparation method of the embodiment of the present application, a diffusion layer can be prepared on the top of the silicon substrate (not shown in the figure) by using a diffusion process, and the type of elements doped in the diffusion layer is different from the type of elements doped in the silicon substrate. For example, if the silicon substrate is doped with N-type elements, the diffusion layer is doped with P-type elements, or if the silicon substrate is doped with P-type elements, the diffusion layer is doped with N-type elements, so that the diffusion layer and the silicon substrate form a PN junction, and the PN junction is used to make the photogenerated electrons and photogenerated holes that can be generated by the prepared photovoltaic cell piece gather in opposite directions, so that the prepared photovoltaic cell piece can output voltage and current to the external circuit.

[0118] In other embodiments, another tunneling passivation contact structure can also be prepared on top of the silicon substrate (not shown in the figure) by using a vapor deposition process. The type of elements doped in the polysilicon of the other tunneling passivation contact structure is different from the type of elements doped in the silicon substrate. The tunneling passivation contact structure and the silicon substrate can also form a PN junction. The PN junction is used to make the photogenerated electrons and photogenerated holes generated by the prepared photovoltaic cell gather in opposite directions, so that the prepared photovoltaic cell can output voltage and current to the external circuit.

[0119] The preparation method of the embodiment of the present application is not limited to the above-mentioned method for preparing other structures on top of the silicon substrate.

[0120] In a second aspect, an embodiment of the present application provides a photovoltaic cell, which is prepared by the method described above. The photovoltaic cell includes a silicon substrate, a tunneling layer, a doped conductive layer and a metal electrode. The silicon substrate is provided with a first recessed portion recessed toward the silicon substrate, at least part of the structure of the tunneling layer is located in the first recessed portion, the tunneling layer is provided with a second recessed portion recessed toward the first recessed portion, at least part of the structure of the doped conductive layer is at least located in the second recessed portion, and the doped conductive layer is provided with a third recessed portion recessed toward the second recessed portion and also recessed toward the first recessed portion. At least part of the structure of a portion of the metal electrodes is located in the third recessed portion, and the portion of the metal electrodes is in metallization contact with the doped conductive layer.

[0121] Please refer to Fig.10 As shown, the bottom of the silicon substrate 1 may be provided with a first recessed portion (not marked in the figure), the first recessed portion may be provided with a tunneling layer 2, the tunneling layer 2 may be provided with a second recessed portion (not marked in the figure), the second recessed portion may be recessed into the first recessed portion, the second recessed portion may be provided with a doped conductive layer 30, the doped conductive layer 30 may be provided with a third recessed portion (not marked in the figure), the third recessed portion may be recessed into the second recessed portion and the first recessed portion, at least part of the structure of the bottom metal electrode 5 may be located in the third recessed portion, and at least part of the structure of the bottom metal electrode 5 is also equivalent to being located in the second recessed portion and the first recessed portion. Under this setting, compared with the photovoltaic cell with a recessed portion in the prior art, the length dimension of the contact surface extending along the direction Y between the bottom metal electrode 5 and the doped conductive layer 30 in the embodiment of the present application is larger, so that the contact resistance between the bottom metal electrode 5 and the doped conductive layer 30 is smaller, so that the photovoltaic cell of the embodiment of the present application has a higher photoelectric conversion efficiency.

[0122] in, Fig.10 Please refer to the first concave part not marked in Figure 1 understand, Fig.10 Please refer to the unmarked second concave part Figure 2 understand, Fig.10Please refer to the third recessed part not marked in Figure 3 understand.

[0123] Optionally, see Figure 3 As shown, in the perspective without showing the bottom metal electrode, the third recessed portion 3a has a set depth dimension D 3 , depth dimension D 3 Meet 1μm~20μm, depth dimension D 3 Specifically, it can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, 16 μm, 17 μm, 18 μm, 19 μm or 20 μm. Under this setting, the contact resistance between the bottom metal electrode 5 and the doped conductive layer 30 is small, so that the photoelectric conversion efficiency of the photovoltaic cell is higher.

[0124] Optionally, see Figure 3 As shown, in the perspective without showing the bottom metal electrode, the third recessed portion 3a has a set width dimension W 3 , width dimension W 3 Meet 10μm~200μm. Width dimension W 3 Specifically, it can be 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm or 200 μm. Under this setting, the requirement of a relatively small shielding area of ​​the bottom metal electrode 5 in the direction X is met, so that the bottom of the silicon substrate 1 can receive more light, thereby making the photoelectric conversion efficiency of the photovoltaic cell higher.

[0125] Optionally, see Figure 2 As shown, in the perspective that the bottom metal electrode and the doped conductive layer are not shown, the second recessed portion 2a has a set depth dimension D 2 , depth dimension D 2 Meet 1μm~20μm, depth dimension D 2 Specifically, it can be 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm or 20μm.

[0126] Optionally, see Figure 2 As shown, in the perspective that the bottom metal electrode and the doped conductive layer are not shown, the second recessed portion 2a has a set width dimension W 2 , width dimension W2 Meet 10μm~200μm, width size W 2 Specifically, it can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm or 200μm.

[0127] Optionally, see Figure 1 As shown, in the perspective that the bottom metal electrode, the doped conductive layer and the tunneling layer are not shown, the first recessed portion 1a has a set depth dimension D 1 , depth dimension D 1 Meet 1μm~20μm, depth dimension D 1 Specifically, it can be 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm, 17μm, 18μm, 19μm or 20μm.

[0128] Optionally, see Figure 1 As shown, in the perspective that the bottom metal electrode, the doped conductive layer and the tunneling layer are not shown, the first recessed portion 1a has a set width dimension W 1 , width dimension W 1 Meet 10μm~200μm. Width dimension W 1 Specifically, it can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm, 180μm, 190μm or 200μm.

[0129] It should be noted that the width dimension W 1 Larger than width dimension W 2 , width dimension W 2 Larger than width dimension W 3 .

[0130] Optionally, see Fig.10 As shown, the bottom metal electrode 5 disposed in the third recessed portion (not marked in the figure) has a set height dimension D 5 , height dimension D 5 Meet 5μm~30μm. Height dimension D 5Specifically, it can be 5 μm, 10 μm, 15 μm, 20 μm, 25 μm or 30 μm. Under this setting, the area of ​​the contact surface between the bottom metal electrode 5 and the doped conductive layer 30 extending along the direction Y is large, and the contact resistance between the bottom metal electrode 5 and the doped conductive layer 30 is small, so that the photoelectric conversion efficiency of the photovoltaic cell is small.

[0131] Optionally, see Fig.10 As shown, the bottom metal electrode 5 disposed in the third recessed portion (not marked in the figure) has a set width dimension W 5 , width dimension W 5 Meet 10μm~50μm. Width dimension W 5 Specifically, it can be 10 μm, 20 μm, 30 μm, 40 μm or 50 μm. Under this setting, the shielding area of ​​the bottom metal electrode 5 in the direction X is relatively small, so that the bottom of the silicon substrate 1 can receive more light, thereby increasing the photoelectric conversion efficiency of the photovoltaic cell.

[0132] Optionally, see Fig.10 As shown, the portion other than the first recessed portion in the bottom of the silicon substrate 1 may also be provided with a stacked tunneling layer 2, a doped conductive layer 30 and a first passivation layer 4. The doped conductive layer 30 includes a first portion 301 and a second portion 302, wherein the first portion 301 is in the first recessed portion and the second recessed portion, and the first portion 301 is in metallization contact with the bottom metal electrode 5, and the second portion 302 is in the region other than the first recessed portion and the second recessed portion at the bottom of the silicon substrate 1 and is not in metallization contact with the bottom metal electrode 5, and the size of the first portion 301 in the direction Y is greater than the size of the second portion 302 in the direction Y. Under this setting, the contact resistance between the first portion 301 having a larger size in the direction Y and the bottom metal electrode 5 is smaller, and the second portion 302 having a smaller size in the direction Y absorbs less external light, so that more light can be incident into the silicon substrate 1 through the second portion 302, so that the silicon substrate 1 can generate more photogenerated electrons and photogenerated holes, and the above setting makes the photoelectric conversion efficiency of the photovoltaic cell sheet higher.

[0133] In other embodiments (not shown in the figures), the area in the bottom of the silicon substrate except the first recessed portion may not be provided with a stacked tunneling layer and a doped medium layer, but at least a first passivation layer is provided, so that the area in the bottom of the silicon substrate except the first recessed portion is passivated by the first passivation layer.

[0134] The materials of the silicon substrate 1, the tunneling layer 2, the doped conductive layer 30 and the first passivation layer 4 have been introduced above and will not be repeated here. It should be noted that after the doped dielectric layer 3 is annealed, the crystallization rate inside the doped dielectric layer 3 increases, that is, there is more polysilicon inside the doped dielectric layer 3, so the doped dielectric layer 3 becomes the doped conductive layer 30 after annealing.

[0135] Please refer to Fig.10 As shown, a stacked diffusion layer 6 and a second passivation layer 7 may be provided on the top of the silicon substrate 1. The diffusion layer 6 is between the silicon substrate 1 and the second passivation layer 7. The diffusion layer 6 forms a PN junction with the silicon substrate 1. The relevant functions have been described above and will not be repeated here. The second passivation layer 7 may include an aluminum oxide passivation layer 71 and a silicon nitride passivation layer 72. The aluminum oxide passivation layer 71 may play a field passivation role to improve the photoelectric conversion efficiency of the photovoltaic cell. The silicon nitride passivation layer 72 may play a role in reducing the reflected sunlight to improve the photoelectric conversion efficiency of the photovoltaic cell. The silicon nitride passivation layer 72 may include α-SiN x :H, the hydrogen element in the silicon nitride passivation layer 72 can perform chemical passivation to improve the photoelectric conversion efficiency of the photovoltaic cell.

[0136] Please refer to Fig.10 As shown, the top metal electrode 8 penetrates the second passivation layer 7, and the top metal electrode 8 is in metallization contact with the diffusion layer 6. The polarity of the top metal electrode 8 is opposite to that of the bottom metal electrode 5. If the silicon substrate 1 and the doped conductive layer 30 are both doped with N-type elements, and the diffusion layer 6 is doped with P-type elements, the bottom metal electrode 5 can be used as a negative electrode, and the top metal electrode 8 can be used as a positive electrode.

[0137] In other embodiments (not shown in the figures), another tunnel passivation contact structure and a corresponding top metal electrode may be provided on the top of the silicon substrate, that is, the photovoltaic cell is a dual TOPCon cell, which will not be described in detail here.

[0138] About Fig.10 The structure of the photovoltaic cell shown, and the related preparation method may include the following contents:

[0139] The top of the silicon substrate is etched by an alkaline solution to form a texture on the top of the silicon substrate.

[0140] A diffusion layer is formed on top of the silicon substrate using a diffusion process.

[0141] The bottom of the silicon substrate is etched to remove the surrounding plating layer.

[0142] A first recessed portion is formed at the bottom of the silicon substrate.

[0143] A tunneling layer and a doped dielectric layer are formed at the bottom of the silicon substrate.

[0144] The top of the silicon substrate is etched to remove the surrounding plating.

[0145] An aluminum oxide passivation layer is formed on the side of the diffusion layer facing away from the silicon substrate.

[0146] A silicon nitride passivation layer is formed on the side of the aluminum oxide passivation layer away from the diffusion layer, and a first passivation layer is formed on the side of the doped dielectric layer away from the tunneling layer.

[0147] Annealing treatment.

[0148] A bottom metal electrode and a top metal electrode are formed.

[0149] Then annealing treatment.

[0150] In a third aspect, an embodiment of the present application provides a photovoltaic module, which includes a laminate and a frame, and the frame is installed at the edge of the laminate. The laminate includes a stacked photovoltaic glass, a first encapsulation film, a battery string, a second encapsulation film and a backplane. Alternatively, the laminate includes a stacked first photovoltaic glass, a first encapsulation film, a battery string, a second encapsulation film and a second photovoltaic glass. Wherein, the battery string is formed by electrically connecting a plurality of photovoltaic cells described above.

[0151] The photovoltaic module of the embodiment of the present application also includes the technical effects of the photovoltaic cell in the above content, which will not be repeated here.

[0152] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a photovoltaic cell, characterized in that: The preparation method comprises: Providing a silicon substrate, wherein the silicon substrate is provided with a first recessed portion recessed into the silicon substrate; forming a tunneling layer at least in the first recessed portion, and forming a second recessed portion recessed into the first recessed portion in the tunneling layer; forming a doped medium layer at least in the second recessed portion, and forming a third recessed portion recessed into the second recessed portion in the doped medium layer; A metal electrode in metallization contact with the doped medium layer is formed in the third recess.

2. The method for preparing a photovoltaic cell according to claim 1, characterized in that: Before providing the silicon substrate having the first recessed portion, the preparation method further includes: Using laser to remove the local structure of the silicon substrate to form the first recessed portion; Alternatively, a patterned mask layer is formed on the silicon substrate, wherein the patterned mask layer is provided with a window, and an acid solution or an alkali solution is used to remove the local structure of the silicon substrate exposed by the window to form the first recessed portion.

3. The method for preparing a photovoltaic cell according to claim 2, characterized in that: The method of removing a local structure of the silicon substrate to form the first recessed portion comprises: Removing a local structure with a depth dimension D1 of 1 μm to 20 μm from the silicon substrate; And / or, a local structure with a width W1 of 10 μm to 200 μm is removed from the silicon substrate.

4. The method for preparing a photovoltaic cell according to claim 1, characterized in that: Controlling the sum of the thickness dimension H1 of the tunneling layer and the thickness dimension H2 of the doped medium layer to be smaller than the depth dimension D1 of the first recessed portion; The twice of the sum of the thickness dimension H1 of the tunneling layer and the thickness dimension H2 of the doped medium layer is controlled to be smaller than the width dimension W1 of the first recessed portion.

5. The method for preparing a photovoltaic cell according to claim 1, characterized in that: After forming the doped medium layer and before forming the metal electrode, the preparation method further includes: forming a first passivation layer containing hydrogen elements at least in the third recessed portion, and forming the first passivation layer with a fourth recessed portion recessed into the third recessed portion; annealing treatment.

6. A photovoltaic cell, characterized in that: The photovoltaic cell comprises: A silicon substrate is provided with a first recessed portion recessed toward the silicon substrate; a tunneling layer, wherein at least a portion of the structure of the tunneling layer is located in the first recessed portion, and the tunneling layer is provided with a second recessed portion recessed into the first recessed portion; a doped conductive layer, wherein at least a portion of the structure of the doped conductive layer is located at least in the second recessed portion, and the doped conductive layer is provided with a third recessed portion that is recessed into the second recessed portion and also recessed into the first recessed portion; A metal electrode, at least a portion of the structure of a portion of the metal electrodes is located in the third recessed portion, and the portion of the metal electrodes is in metallization contact with the doped conductive layer.

7. The photovoltaic cell according to claim 6, characterized in that: The first recessed portion has a set depth dimension D1, and the depth dimension D1 satisfies 1 μm to 20 μm; And / or, the first recessed portion has a set width dimension W1, and the width dimension W1 satisfies 10 μm to 200 μm.

8. The photovoltaic cell according to claim 6, characterized in that: The metal electrode disposed in the third recessed portion has a set height dimension D5, and the height dimension D5 satisfies 5 μm to 30 μm; And / or, the metal electrode provided in the third recessed portion has a set width dimension W5, and the width dimension W5 satisfies 10 μm to 50 μm.

9. The photovoltaic cell according to any one of claims 6 to 8, characterized in that: The doped conductive layer comprises a first portion and a second portion, the first portion is located in the second recessed portion, the first portion is in contact with the corresponding metal electrode metallization, and the second portion is located outside the second recessed portion, the second portion is not in contact with the metal electrode metallization; A size of the first portion in a thickness direction of the photovoltaic cell is greater than a size of the second portion in a thickness direction of the photovoltaic cell.

10. A photovoltaic module, characterized in that: The photovoltaic module comprises a plurality of photovoltaic cell strings formed by electrically connecting the photovoltaic cell sheets according to any one of claims 6 to 9.

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