Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a substrate, a plurality of data lines, a plurality of gate lines and a plurality of fan-out lines, wherein the fan-out lines are correspondingly connected with at least part of the data lines; in at least a part of the fan-out lines, the same fan-out line comprises a sub-connection section and a plurality of sub-extension sections, the adjacent sub-extension sections are connected through the sub-connection section, the plurality of sub-extension sections comprise a first sub-extension section and a second sub-extension section, and in the same refresh cycle, the first sub-extension section is connected with the second sub-extension section. At least one voltage jump moment of a pulse of a signal on at least one gate line adjacent to the first sub-extension section is different from a voltage jump moment of a pulse of a signal on a gate line adjacent to the second sub-extension section; the amplitude polarity of the pulse of the signal on at least one gate line adjacent to the first sub-extension segment is different from the amplitude polarity of the pulse of the signal on the gate line adjacent to the second sub-extension segment. Therefore, according to the display panel and the display device provided by the invention, the brightness uniformity of the display panel can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) display technology is regarded as the most promising new flat panel display technology of the next generation. Compared with liquid crystal display technology, OLED display technology has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed. However, the display panel formed by the above display technology has poor display brightness uniformity. Summary of the invention

[0003] Based on this, it is necessary to provide a display panel and a display device that can improve brightness uniformity.

[0004] In a first aspect, an embodiment of the present application provides a display panel, the display panel comprising:

[0005] substrate;

[0006] A plurality of data lines are disposed on the substrate;

[0007] A plurality of gate lines are disposed on the substrate;

[0008] A plurality of fan-out lines are disposed on the substrate, and the plurality of fan-out lines are electrically connected to at least a portion of the data lines;

[0009] Among them, in at least a part of the fan-out lines, in the same fan-out line, the fan-out line includes a sub-connecting segment and multiple sub-extension segments, two adjacent sub-extension segments are connected by the sub-connecting segment, the multiple sub-extension segments include a first sub-extension segment and a second sub-extension segment, and within the same refresh cycle, at least one voltage jump moment of a pulse of a signal on at least one gate line adjacent to the first sub-extension segment is different from the voltage jump moment of a pulse of a signal on a gate line adjacent to the second sub-extension segment, and / or, the amplitude polarity of a pulse of a signal on at least one gate line adjacent to the first sub-extension segment is different from the amplitude polarity of a pulse of a signal on a gate line adjacent to the second sub-extension segment.

[0010] In the display panel provided by the embodiment of the present application, in at least a part of the number of fan-out lines, in the same fan-out line, the at least one gate line adjacent to the first sub-extension segment can affect the signal voltage of the first sub-extension segment at the time of its voltage jump, but basically has no effect on the signal voltage of the second sub-extension segment, and the parasitic capacitance between the at least one gate line and the fan-out line is equal to the parasitic capacitance generated by the mutual coupling between the first sub-extension segment and the at least one gate line. The embodiment of the present application can shorten the coupling length between the at least one gate line and the fan-out line, thereby reducing the degree of coupling between the at least one gate line and the fan-out line, and reducing the parasitic capacitance between the at least one gate line and the fan-out line, or the signal of the gate line adjacent to the second sub-extension segment affects the signal voltage of the second sub-extension segment, which can partially or completely offset the effect of the at least one gate line adjacent to the first sub-extension segment on the signal voltage of the first sub-extension segment at the time of its voltage jump, thereby improving the uniformity of the display brightness of the display panel.

[0011] In one embodiment, the orthographic projection of the first sub-extension segment on the substrate is the first orthographic projection, the orthographic projection of the second sub-extension segment on the substrate is the second orthographic projection, and the orthographic projection of the gate line on the substrate is the third orthographic projection.

[0012] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, at least two third orthographic projections are arranged between the first orthographic projection and the second orthographic projection.

[0013] In one embodiment, the plurality of gate lines include at least one of a first gate line and a second gate line, at least one of a third gate line and a fourth gate line,

[0014] In the first sub-extension section and the second sub-extension section in the same fan-out line, the first sub-extension section is adjacent to the first gate line; the second sub-extension section is adjacent to the third gate line, and the signal of the first gate line adjacent to the first sub-extension section is different from the signal of the third gate line adjacent to the second sub-extension section;

[0015] Alternatively, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is adjacent to the first gate line and the second gate line respectively, and the first orthographic projection is located between the orthographic projection of the first gate line adjacent to the first sub-extension segment on the substrate and the orthographic projection of the second gate line adjacent to the first sub-extension segment on the substrate; the second sub-extension segment is adjacent to the third gate line and the fourth gate line respectively, and the second orthographic projection is located between the orthographic projection of the third gate line adjacent to the second sub-extension segment on the substrate and the orthographic projection of the fourth gate line adjacent to the second sub-extension segment on the substrate; the signal of the first gate line adjacent to the first sub-extension segment is different from the signals of the third gate line and the fourth gate line adjacent to the second sub-extension segment; the signal of the second gate line adjacent to the first sub-extension segment is different from the signals of the third gate line and the fourth gate line adjacent to the second sub-extension segment.

[0016] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, the gate lines extend along the row direction of the array, and the data lines extend along the column direction of the array;

[0017] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first orthographic projection is located between the orthographic projections of the first gate line and the second gate line adjacent to the corresponding pixel circuit in the same row on the substrate; the second orthographic projection is located between the orthographic projections of the third gate line and the fourth gate line adjacent to the corresponding pixel circuit in the same row on the substrate;

[0018] Preferably, the column direction is parallel to the first direction, and the row direction is parallel to the second direction.

[0019] In one embodiment, the orthographic projections of the first sub-extension segment and the second sub-extension segment in the same fan-out line on the substrate are located between the orthographic projections of the first gate line, the second gate line, the third gate line and the fourth gate line electrically connected to the corresponding pixel circuits in the same row on the substrate;

[0020] Alternatively, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first gate line and the second gate line adjacent to the first sub-extension segment, the third gate line and the fourth gate line adjacent to the second sub-extension segment are electrically connected to the corresponding pixel circuits in the same row.

[0021] In one of the embodiments, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first orthographic projection is located between the orthographic projections of the adjacent first gate line and the second gate line electrically connected to the corresponding row of pixel circuits on the substrate, and the second orthographic projection is located between the orthographic projections of the adjacent third gate line and the fourth gate line electrically connected to the corresponding another row of pixel circuits on the substrate.

[0022] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, the gate lines extend along the row direction of the array, and the data lines extend along the column direction of the array;

[0023] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first orthographic projection is located between the orthographic projections of the first gate line and the second gate line adjacent to the first sub-extension segment on the substrate; the second orthographic projection is located between the orthographic projections of the third gate line and the fourth gate line adjacent to the second sub-extension segment on the substrate; the orthographic projections of the second gate line adjacent to the first sub-extension segment and the third gate line adjacent to the second sub-extension segment on the substrate are located between the orthographic projections of the first gate line adjacent to the first sub-extension segment and the fourth gate line adjacent to the second sub-extension segment on the substrate; the second gate line adjacent to the first sub-extension segment and the third gate line adjacent to the second sub-extension segment are electrically connected to the same row of pixel circuits; the first gate line adjacent to the first sub-extension segment and the fourth gate line adjacent to the second sub-extension segment are electrically connected to different rows of pixel circuits;

[0024] Preferably, the column direction is parallel to the first direction, and the row direction is parallel to the second direction.

[0025] In one embodiment, the signals of any two of the first gate line, the second gate line, the third gate line and the fourth gate line are different;

[0026] and / or, the first gate line, the second gate line, the third gate line and the fourth gate line are used to transmit signals of different functions;

[0027] And / or, the display panel includes a plurality of pixel circuits arranged in an array, the pixel circuits include a plurality of transistors with different functions, the gate lines extend along the row direction of the array, and the data lines extend along the column direction of the array; the first gate line, the second gate line, the third gate line, and the fourth gate line are electrically connected to the transistors with different functions;

[0028] And / or, any two of the first gate line, the second gate line, the third gate line and the fourth gate line are alternately arranged along the first direction.

[0029] In one embodiment, the display panel includes one or more gate driving circuits, the gate driving circuits include cascaded multi-stage shift registers electrically connected to corresponding gate lines,

[0030] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first gate line and the second gate line adjacent to the first sub-extension segment are electrically connected to different shift registers; the third gate line and the fourth gate line adjacent to the second sub-extension segment are electrically connected to different shift registers; the shift register electrically connected to the first gate line and the second gate line adjacent to the first sub-extension segment is different from the shift register electrically connected to the third gate line and the fourth gate line adjacent to the second sub-extension segment.

[0031] In one embodiment, the plurality of gate lines comprises a plurality of gate line groups, each gate line group comprises a first gate line and a second gate line,

[0032] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is adjacent to the first gate line and the second gate line in a corresponding gate line group, and the first orthographic projection is located between the orthographic projection of the first gate line and the second gate line in the corresponding gate line group on the substrate; the second sub-extension segment is adjacent to the first gate line and the second gate line in another corresponding gate line group, and the second orthographic projection is located between the orthographic projection of the first gate line and the second gate line in another corresponding gate line group on the substrate.

[0033] In one embodiment, in a first sub-extension segment and a second sub-extension segment in the same fan-out line, a signal timing of a first gate line adjacent to the first sub-extension segment is different from a signal timing of a first gate line adjacent to the second sub-extension segment; a signal timing of a second gate line adjacent to the first sub-extension segment is different from a signal timing of a second gate line adjacent to the second sub-extension segment;

[0034] and / or, the first gate line and the second gate line are used to transmit signals of different functions;

[0035] And / or, the first gate lines and the second gate lines are alternately arranged along the first direction.

[0036] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, the gate lines extend along the row direction of the array, and the data lines extend along the column direction of the array;

[0037] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first gate line and the second gate line in a gate line group adjacent to the first sub-extension segment are electrically connected to pixel circuits in different rows; and / or, the first gate line and the second gate line in another gate line group adjacent to the second sub-extension segment are electrically connected to pixel circuits in different rows;

[0038] Preferably, the column direction is parallel to the first direction, and the row direction is parallel to the second direction.

[0039] In one embodiment, the display panel includes a first gate driving circuit, the first gate driving circuit includes a cascaded multi-stage first shift register, electrically connected to the corresponding first gate line,

[0040] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first gate line adjacent to the first sub-extension segment and the first gate line adjacent to the second sub-extension segment are electrically connected to different output ends of the first shift register;

[0041] The display panel includes a second gate driving circuit, the second gate driving circuit includes a cascaded multi-stage second shift register, and is electrically connected to the corresponding second gate line;

[0042] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the second gate line adjacent to the first sub-extension segment and the second gate line adjacent to the second sub-extension segment are electrically connected to different output ends of the second shift register.

[0043] In one embodiment, the output end of each stage of the first shift register is electrically connected to N first gate lines, where N is a positive integer;

[0044] The output end of each stage of the second shift register is electrically connected to M second gate lines correspondingly, where M is a positive integer;

[0045] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, at least K orthographic projections of the first gate line on the substrate are arranged between the first orthographic projection and the second orthographic projection, and / or at least K orthographic projections of the second gate line on the substrate are arranged between the first orthographic projection and the second orthographic projection, K=max(M,N);

[0046] Preferably, at least one of N and M is 1, and / or at least one of N and M is greater than or equal to 2.

[0047] In one embodiment, the output end of each stage of the first shift register is electrically connected to N first gate lines, where N is a positive integer;

[0048] The output end of each stage of the second shift register is electrically connected to M second gate lines correspondingly, where M is a positive integer;

[0049] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the length of the sub-connection segment connected between the first sub-extension segment and the second sub-extension segment along the first direction is greater than or equal to K times the first distance, and / or the distance between the first sub-extension segment and the second sub-extension segment along the first direction is greater than or equal to K times the first distance, K=max(M,N), and the first distance is the distance between two adjacent first gate lines along the first direction;

[0050] Preferably, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the length of the sub-connection segment connecting the first sub-extension segment and the second sub-extension segment along the first direction is an integer multiple of the first distance; and / or, the distance between the first sub-extension segment and the second sub-extension segment along the first direction is an integer multiple of the first distance; and / or,

[0051] In at least part of the adjacent fan-out lines, the distance between adjacent first sub-extension segments along the first direction is an integer multiple of the first distance; and / or, the distance between adjacent second sub-extension segments along the first direction is an integer multiple of the first distance; and / or, the distance between adjacent first sub-extension segments along the first direction is equal to the distance between adjacent second sub-extension segments along the first direction; and / or, the distance between adjacent first sub-extension segments along the first direction is less than or equal to the length of the sub-connection segment along the first direction; and / or, the distance between adjacent second sub-extension segments along the first direction is less than or equal to the length of the sub-connection segment along the first direction;

[0052] Preferably, at least one of N and M is 1, and / or at least one of N and M is greater than or equal to 2.

[0053] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, and the pixel circuits include a plurality of transistors with different functions.

[0054] The first gate lines in different gate line groups are electrically connected to transistors with the same function in pixel circuits of different rows; and / or, the second gate lines in different gate line groups are electrically connected to transistors with the same function in pixel circuits of different rows; and / or, the first gate line and the second gate line are electrically connected to transistors with different functions in the pixel circuit;

[0055] Preferably, the pixel circuit comprises: a driving transistor and a first initialization transistor, the first initialization transistor is connected between the first initialization signal line and the first electrode or the second electrode of the driving transistor, and the first gate line is electrically connected to the gate of the first initialization transistor;

[0056] And / or, the pixel circuit includes: a second initialization transistor, the second initialization transistor is connected between the second initialization signal line and the gate or the second electrode of the driving transistor, and the second gate line is electrically connected to the gate of the second initialization transistor;

[0057] And / or, the pixel circuit includes: a third initialization transistor, the third initialization transistor is connected between the third initialization signal line and the first electrode of the light emitting unit, and the first gate line is electrically connected to the gate of the third initialization transistor.

[0058] In one embodiment, the first gate lines in different gate line groups are used to transmit signals with the same function; the second gate lines in different gate line groups are used to transmit signals with the same function;

[0059] The output end of each stage of the first shift register is electrically connected to N first gate lines correspondingly, where N is a positive integer;

[0060] The output end of each stage of the second shift register is electrically connected to M second gate lines correspondingly, where M is a positive integer;

[0061] In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the length of the sub-connection segment connected between adjacent first sub-extension segments and second sub-extension segments along the first direction is greater than or equal to K times the first distance, K=max(M,N), and the first distance is the distance between two adjacent first gate lines along the first direction; the data line extends along the first direction;

[0062] At least one of N and M is greater than or equal to 2;

[0063] Preferably, the display panel includes a plurality of pixel circuits arranged in an array, the gate lines extend along the row direction of the array, and the data lines extend along the column direction of the array; the column direction is parallel to the first direction, and the row direction is parallel to the second direction;

[0064] The output end of each stage of the first shift register is electrically connected to N rows of pixel circuits via the first gate line;

[0065] The output end of each stage of the second shift register is electrically connected to M rows of pixel circuits via the second gate line.

[0066] In one embodiment, the plurality of fan-out lines include a plurality of first fan-out lines, and the plurality of sub-extension segments in the same first fan-out line include a first sub-extension segment and a second sub-extension segment;

[0067] The extension lengths of the second sub-extension segments in the plurality of first fan-out lines gradually decrease along the first direction; and / or, the extension lengths of the first sub-extension segments in the plurality of first fan-out lines are equal; and / or, the extension lengths of the sub-connection segments in the plurality of first fan-out lines are equal;

[0068] Preferably, the second sub-extension segments in a plurality of first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the first sub-extension segments in at least part of the adjacent first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the distance between the first sub-extension segments in two adjacent first fan-out lines is less than or equal to the distance between the first sub-extension segment and the second sub-extension segment in the same first fan-out line along the first direction; and / or, the distance between the first sub-extension segments in two adjacent first fan-out lines is less than or equal to the extension length of the sub-connection segment; and / or, the distance between the second sub-extension segments in two adjacent first fan-out lines is less than or equal to the distance between the first sub-extension segment and the second sub-extension segment in the same first fan-out line along the first direction; and / or, the distance between the second sub-extension segments in two adjacent first fan-out lines is less than or equal to the extension length of the sub-connection segment; and / or, the distance between the first sub-extension segments in two adjacent first fan-out lines is equal to the distance between the second sub-extension segments in two adjacent first fan-out lines;

[0069] Preferably, the extension length of the second sub-extension section with the largest extension length among the plurality of first fan-out lines is equal to the extension length of the first sub-extension section among the plurality of first fan-out lines;

[0070] Preferably, the first sub-extension sections in at least a portion of the adjacent first fan-out lines are partially opposite to each other and partially staggered along the first direction; and / or the sub-connection sections in at least a portion of the adjacent first fan-out lines are partially opposite to each other and partially staggered along the second direction;

[0071] Preferably, in the plurality of first fan-out lines, the offset distances of adjacent first sub-extension sections are equal; and / or, in the plurality of first fan-out lines, the offset distances of adjacent sub-connection sections are equal;

[0072] Preferably, in the same fan-out line, the second sub-extension section is connected between the first sub-extension section and the corresponding data line;

[0073] Preferably, the display panel comprises a display area and a first non-display area, the first non-display area is located on one side of the display area along a first direction, the data line, the gate line and the fan-out line are at least partially located in the display area; the data line extends along the first direction;

[0074] The extension length of the second sub-extension segment in the plurality of first fan-out lines gradually decreases along the direction from the display area to the first non-display area; and / or, the first fan-out line is connected to the corresponding data line via a first electrical connection node, and the extension lengths of the plurality of sub-extension segments in the first fan-out line corresponding to the first electrical connection node farthest from the first non-display area along the first direction are equal, and / or, the extension length of the second sub-extension segment is the largest;

[0075] Preferably, the first non-display area includes a binding area, and the binding pins of the binding area are electrically connected to the fan-out lines;

[0076] Preferably, the difference in extension lengths of the second sub-extension sections of two adjacent first fan-out lines is twice the second distance;

[0077] Preferably, the extension length of the second sub-extension section with the smallest extension length among the plurality of first fan-out lines is greater than or equal to twice the second distance;

[0078] Preferably, the distance between every two adjacent data lines is the same and is the second distance;

[0079] Alternatively, among the three adjacent data lines, the distance between the data line in the middle and the data line on one side is different from the distance between the data line in the middle and the data line on the other side; half of the distance between the data line on one side and the data line on the other side is the second distance;

[0080] Preferably, in the same first fan-out line, the distance between the second sub-extension segment and the first non-display area along the first direction is greater than the distance between the first sub-extension segment and the first non-display area along the first direction.

[0081] In one embodiment, the plurality of fan-out lines further include a plurality of second fan-out lines, the number of sub-extension segments in the same second fan-out line is greater than the number of sub-extension segments in the same first fan-out line; the plurality of sub-extension segments in the same second fan-out line include a first sub-extension segment, a second sub-extension segment and a third sub-extension segment, the third sub-extension segment being connected between the second sub-extension segment and the corresponding data line;

[0082] Preferably, in the same second fan-out line, a signal of at least one gate line adjacent to the third sub-extension segment is different from a signal of a gate line adjacent to the second sub-extension segment;

[0083] Preferably, the extension length of the third sub-extension segments in the plurality of second fan-out lines gradually decreases along the first direction; and / or, the extension lengths of the first sub-extension segments in the plurality of second fan-out lines are equal; and / or, the extension lengths of the second sub-extension segments in the plurality of second fan-out lines are equal; and / or, the extension lengths of the first sub-extension segment and the second sub-extension segment in the same second fan-out line are equal; and / or, the extension lengths of the first sub-extension segment in the second fan-out line and the first sub-extension segment in the first fan-out line are equal;

[0084] Preferably, the third sub-extension segments in the plurality of second fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the first sub-extension segments in at least part of the adjacent second fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the second sub-extension segments in at least part of the adjacent second fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the first sub-extension segments in at least part of the second fan-out lines and the first sub-extension segments in at least part of the first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the second sub-extension segments in at least part of the second fan-out lines and the first sub-extension segments in at least part of the first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; The sub-extension segments and at least part of the second sub-extension segments in the first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the extension length of the sub-connection segment in the second fan-out line is equal to the extension length of the sub-connection segment in the first fan-out line; and / or, the extension length of the third sub-extension segment with the largest extension length among the plurality of second fan-out lines is equal to the extension length of the first sub-extension segment in the first fan-out line; and / or, the extension length of the first sub-connection segment in the second fan-out line is equal to the extension length of the second sub-connection segment in the second fan-out line; the first sub-connection segment is connected between the first sub-extension segment and the second sub-extension segment, and the second sub-connection segment is connected between the second sub-extension segment and the third sub-extension segment,

[0085] Preferably, the extension length of the third sub-extension segments in the plurality of second fan-out lines gradually decreases along the direction from the display area to the first non-display area;

[0086] Preferably, the extension length of the second sub-extension section in the same second fan-out line is greater than or equal to the extension length of the third sub-extension section; and / or, in a portion of the second fan-out lines, the extension lengths of the second sub-extension section and the third sub-extension section in the same second fan-out line are equal; and / or, in a portion of the second fan-out lines, the extension length of the second sub-extension section in the same second fan-out line is greater than the extension length of the third sub-extension section;

[0087] Preferably, the difference between the extension lengths of the third sub-extension sections of two adjacent second fan-out lines is twice the second distance;

[0088] Preferably, the first sub-extension sections in at least a portion of the adjacent second fan-out lines are partially opposite to each other and partially staggered along the first direction; and / or, the second sub-extension sections in at least a portion of the adjacent second fan-out lines are partially opposite to each other and partially staggered along the first direction; the first sub-extension sections in at least a portion of the first fan-out lines are partially opposite to the first sub-extension sections in at least a portion of the second fan-out lines and partially staggered along the first direction; and / or, the second sub-extension sections in at least a portion of the first fan-out lines are partially opposite to the second sub-extension sections in at least a portion of the second fan-out lines and partially staggered along the first direction; and / or, in a plurality of second fan-out lines and / or a plurality of first fan-out lines, the staggered distances of adjacent first sub-extension sections are equal; and / or, in a plurality of second fan-out lines, the staggered distances of adjacent second sub-extension sections are equal to each other. The first sub-connection segments in at least a portion of the adjacent second fan-out lines are partially opposite to each other and partially offset along the second direction; and / or the second sub-connection segments in at least a portion of the adjacent second fan-out lines are partially opposite to each other and partially offset along the second direction; and / or, in a plurality of second fan-out lines and / or a plurality of first fan-out lines, the offset distances of adjacent first sub-connection segments are equal; and / or, in a plurality of second fan-out lines, the offset distances of adjacent second sub-connection segments are equal; and / or, in at least a portion of the first fan-out lines, the first sub-connection segments and in at least a portion of the second fan-out lines are partially opposite to each other and partially offset along the second direction; and / or, in a plurality of second fan-out lines, the offset distances of adjacent second sub-extension segments are equal to the offset distances of adjacent first sub-extension segments;

[0089] Preferably, the second fan-out line is connected to the corresponding data line via a second electrical connection node, the extension lengths of the plurality of sub-extension segments in the second fan-out line corresponding to the second electrical connection node farthest from the first non-display area along the first direction are equal, and / or the extension length of the third sub-extension segment is the largest;

[0090] Preferably, in the same second fan-out line, the distance between the third sub-extension segment and the first non-display area along the first direction is greater than the distance between the second sub-extension segment and the first non-display area along the first direction; the distance between the second sub-extension segment and the first non-display area along the first direction is greater than the distance between the first sub-extension segment and the first non-display area along the first direction;

[0091] Preferably, the first sub-extension section of the second fan-out line is located on a side of the first sub-extension section of the first fan-out line away from the first non-display area; the second sub-extension section of the second fan-out line is located on a side of the second sub-extension section of the first fan-out line away from the first non-display area;

[0092] Preferably, the data line electrically connected to the second fan-out line is located between the data line electrically connected to the first fan-out line and a frame of the display panel extending along the first direction.

[0093] In one embodiment, the display panel includes a first display area and a second display area, the second display area is located on two opposite sides of the first display area along a second direction, the plurality of data lines include a plurality of first data lines located in the second display area, and the plurality of first data lines are electrically connected to the plurality of first fan-out lines accordingly;

[0094] Preferably, the second display area includes a first sub-area and a second sub-area, the first sub-area is located on a side of the second sub-area away from the first display area, and the first data line is located in the first sub-area; the plurality of data lines further include a plurality of second data lines located in the second sub-area, the plurality of fan-out lines include a plurality of auxiliary fan-out lines, and the plurality of auxiliary fan-out lines are electrically connected to the plurality of second data lines accordingly;

[0095] Preferably, the same auxiliary fan-out line includes a first sub-extension segment, and the number of the sub-extension segments in the same auxiliary fan-out line is less than the number of the sub-extension segments in the same first fan-out line;

[0096] The first sub-extension segments in the plurality of auxiliary fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the first sub-extension segments in at least a portion of the first fan-out lines and the first sub-extension segments in at least a portion of the auxiliary fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction;

[0097] Preferably, the extension length of the first sub-extension segment with the largest extension length among the plurality of auxiliary fan-out lines is equal to the extension length of the first sub-extension segment in the first fan-out line; and / or, the distance between the first sub-extension segments in adjacent first fan-out lines along the first direction is equal to the distance between the first sub-extension segments in adjacent auxiliary fan-out lines along the first direction;

[0098] Preferably, the extension lengths of the first sub-extension sections of the plurality of auxiliary fan-out lines gradually decrease along the first direction;

[0099] Preferably, the extension lengths of the first sub-extension sections of the plurality of auxiliary fan-out lines gradually decrease along the direction from the display area to the first non-display area;

[0100] Preferably, the first sub-extension section of the first fan-out line is located on a side of the first sub-extension section of the auxiliary fan-out line away from the first non-display area;

[0101] Preferably, the difference between the extension lengths of the first sub-extension sections of two adjacent auxiliary fan-out lines is twice the second distance;

[0102] Preferably, the fan-out lines of two second display areas located on opposite sides of the first display area along the second direction are symmetrically arranged;

[0103] Preferably, the plurality of data lines further include a third data line located in the first display area, and the third data line is electrically connected to a binding pin in the binding area;

[0104] Preferably, in the same fan-out line, the fan-out line further comprises an auxiliary sub-connection segment electrically connected between the first sub-extension segment and the binding pin of the binding area of ​​the display panel;

[0105] Preferably, the plurality of auxiliary sub-connecting segments are arranged along the second direction and extend along the first direction;

[0106] Preferably, in at least a portion of the fan-out lines, the distance between two adjacent auxiliary sub-connection segments is an integer multiple of the second distance.

[0107] In one of the embodiments, the extension length of the first sub-extension segment in the same fan-out line is less than or greater than or equal to the extension length of the second sub-extension segment;

[0108] and / or, in a part of the number of fan-out lines, the extension lengths of the first sub-extension section and the second sub-extension section in the same fan-out line are equal;

[0109] and / or, in a portion of the number of fan-out lines, an extension length of a first sub-extension section in the same fan-out line is greater than an extension length of a second sub-extension section;

[0110] and / or, in at least some number of fan-out lines, the number of sub-extension segments in the same fan-out line is at least 3;

[0111] And / or, the plurality of data lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect;

[0112] And / or, a plurality of gate lines are arranged along the first direction and extend along the second direction;

[0113] and / or, in the same fan-out line, the extension directions of adjacent sub-connection segments and sub-extension segments intersect;

[0114] and / or, the sub-extension section extends along the second direction;

[0115] and / or, the sub-connecting segment extends along a first direction; and / or, an extending direction of the gate line intersects with an extending direction of the sub-connecting segment;

[0116] And / or, the display panel includes a display area and a first non-display area, the first non-display area is located on one side of the display area along the first direction, and the data line, the gate line and the fan-out line are at least partially located in the display area; the data line extends along the first direction; the first non-display area includes a binding area, and the binding pins in the binding area are electrically connected to the fan-out line; in at least a part of the number of fan-out lines, the farther the distance between the electrical connection node between the fan-out line and the corresponding data line and the first non-display area along the first direction, the more the number of sub-extension segments in the fan-out line is, the more the number of sub-connection segments in the fan-out line is, and the greater the sum of the extension lengths of the sub-extension segments in the fan-out line is;

[0117] And / or, the data lines and the sub-extension sections are arranged in different layers; adjacent data lines and sub-extension sections are connected through vias;

[0118] And / or, the conductive layer where the data line is located is located on a side of the conductive layer where the sub-extension section is located that is away from or close to the substrate; an insulating layer is provided between the conductive layer where the data line is located and the conductive layer where the sub-extension section is located;

[0119] And / or, the sub-connection segments and the sub-extension segments are arranged in different layers; adjacent sub-connection segments and sub-extension segments are connected through vias;

[0120] And / or, the conductive layer where the sub-connecting segment is located is located on a side of the conductive layer where the sub-extension segment is located that is away from or close to the substrate; an insulating layer is provided between the conductive layer where the sub-connecting segment is located and the conductive layer where the sub-extension segment is located;

[0121] and / or, the sub-connection segment and the data line are arranged at the same layer or at different layers;

[0122] and / or, in the same refresh cycle, the first voltage jump time of the pulse of the signal on at least one gate line adjacent to the first sub-extension segment is different from the voltage jump time of the pulse of the signal on the gate line adjacent to the second sub-extension segment;

[0123] and / or, in the same refresh cycle, in the same fan-out line, a pulse of a signal on at least one gate line adjacent to the first sub-extension segment does not overlap with a pulse of a signal on a gate line adjacent to the second sub-extension segment;

[0124] and / or, in the same refresh cycle, in the same fan-out line, a pulse of a signal on at least one gate line adjacent to the first sub-extension segment is not synchronized with a pulse of a signal on a gate line adjacent to the second sub-extension segment;

[0125] and / or, in the same refresh cycle, in the same fan-out line, the time when the pulse of the signal on at least one gate line adjacent to the first sub-extension segment jumps to its own effective level is different from the time when the pulse of the signal on the gate line adjacent to the second sub-extension segment jumps to its own effective level;

[0126] And / or, in the same refresh cycle, in the same fan-out line, the moment when the pulse of the signal on each gate line adjacent to the first sub-extension segment jumps to its own valid level is different from the moment when the pulse of the signal on the gate line adjacent to the second sub-extension segment jumps to its own valid level.

[0127] In one embodiment, the display panel includes a plurality of pixel circuits arranged in an array, and the pixel circuit includes a plurality of transistors with different functions;

[0128] Preferably, the plurality of gate lines include a first scan line, the plurality of transistors include a driving transistor and a first initialization transistor, the first initialization transistor is connected between the first initialization signal line and the first electrode or the second electrode of the driving transistor, and the first scan line is electrically connected to the gate of the first initialization transistor;

[0129] Preferably, the plurality of gate lines include a second scan line, the plurality of transistors include a second initialization transistor, the second initialization transistor is connected between the second initialization signal line and the gate or the second electrode of the driving transistor, and the second scan line is electrically connected to the gate of the second initialization transistor;

[0130] Preferably, the plurality of transistors include a third initialization transistor, the third initialization transistor is connected between a third initialization signal line and the first electrode of the light emitting unit, and the first scanning line is electrically connected to a gate of the third initialization transistor;

[0131] Preferably, the plurality of gate lines include a third scan line, the plurality of transistors include a write transistor, the write transistor is connected between the data line and the first electrode of the drive transistor; the third scan line is electrically connected to the gate of the write transistor;

[0132] Preferably, the plurality of gate lines include a fourth scan line, the plurality of transistors include a threshold compensation transistor, the threshold compensation transistor is connected between the gate and the second electrode of the driving transistor; the fourth scan line is electrically connected to the gate of the threshold compensation transistor;

[0133] Preferably, the plurality of gate lines include a light emitting control line, the plurality of transistors include a first light emitting control transistor and / or a second light emitting control transistor, the first light emitting control transistor is connected between the first power line and the first electrode of the driving transistor, the second light emitting control transistor is connected between the second electrode of the driving transistor and the first electrode of the light emitting unit, and the light emitting control line is electrically connected to the gate of the corresponding first light emitting control transistor and / or the gate of the second light emitting control transistor;

[0134] Preferably, the second scan line, the third scan line, the fourth scan line, the light emitting control line, and the first scan line electrically connected to the pixel circuits in the same row are arranged in sequence along the first direction;

[0135] Preferably, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is located between two adjacent ones of the second scan line, the third scan line, the fourth scan line, the light emitting control line, and the first scan line; and the second sub-extension segment is located between another two adjacent ones of the second scan line, the third scan line, the fourth scan line, the light emitting control line, and the first scan line;

[0136] Alternatively, the display panel includes one or more gate driving circuits, the gate driving circuit includes a cascaded multi-stage shift register, which is electrically connected to the corresponding gate line, and in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is located between two adjacent ones of the second scan line, the third scan line, the fourth scan line, the light emitting control line, and the first scan line; the gate lines adjacent to the first sub-extension segment and the second sub-extension segment have the same corresponding functions, different signal timings, and are electrically connected to different shift registers;

[0137] Preferably, the shift register electrically connected to the same first scan line is electrically connected to one or at least two first scan lines; the shift register electrically connected to the same second scan line is electrically connected to one or at least two second scan lines; the shift register electrically connected to the same third scan line is electrically connected to one or at least two third scan lines; the shift register electrically connected to the same fourth scan line is electrically connected to one or at least two fourth scan lines; and the shift register electrically connected to the same light-emitting control line is electrically connected to one or at least two light-emitting control lines.

[0138] In a second aspect, an embodiment of the present application provides a display panel, the display panel comprising:

[0139] substrate;

[0140] A plurality of data lines are disposed on the substrate;

[0141] A plurality of gate lines are disposed on the substrate;

[0142] A plurality of fan-out lines are disposed on the substrate, and the plurality of fan-out lines are electrically connected to at least a portion of the data lines;

[0143] One or more gate drive circuits, the gate drive circuits comprising cascaded multi-stage shift registers, the output ends of the shift registers being electrically connected to corresponding gate lines;

[0144] Among them, in at least a part of the fan-out lines, in the same fan-out line, the fan-out line includes a sub-connection segment and multiple sub-extension segments, two adjacent sub-extension segments are connected by the sub-connection segment, the multiple sub-extension segments include a first sub-extension segment and a second sub-extension segment, and at least one gate line adjacent to the first sub-extension segment and a gate line adjacent to the second sub-extension segment are electrically connected to the output ends of different shift registers.

[0145] In a third aspect, an embodiment of the present application provides a display panel, the display panel comprising:

[0146] substrate;

[0147] A plurality of data lines are disposed on the substrate;

[0148] A plurality of gate lines are disposed on the substrate;

[0149] A plurality of fan-out lines are disposed on the substrate, and the plurality of fan-out lines are electrically connected to at least a portion of the data lines;

[0150] A plurality of pixel circuits arranged in an array, electrically connected to corresponding gate lines and data lines, the pixel circuits comprising a plurality of transistors with different functions;

[0151] Among them, in at least a part of the fan-out lines, in the same fan-out line, the fan-out line includes a sub-connection segment and multiple sub-extension segments, two adjacent sub-extension segments are connected by the sub-connection segment, the multiple sub-extension segments include a first sub-extension segment and a second sub-extension segment, and the function of the transistor electrically connected to at least one gate line adjacent to the first sub-extension segment is different from that of the transistor electrically connected to the gate line adjacent to the second sub-extension segment.

[0152] In a fourth aspect, an embodiment of the present application provides a display device, comprising a driver chip and a display panel according to any one of the first to third aspects, wherein the driver chip is electrically connected to a fan-out line.

[0153] The display device provided by the embodiment of the present application includes a display panel, wherein the at least one gate line adjacent to the first sub-extension segment can affect the signal voltage of the first sub-extension segment at the time of its voltage jump, but basically has no effect on the signal voltage of the second sub-extension segment, and the parasitic capacitance between the at least one gate line and the fan-out line is equal to the parasitic capacitance generated by the mutual coupling of the first sub-extension segment and the at least one gate line, so that the coupling length between the at least one gate line and the fan-out line is shortened, thereby reducing the degree of coupling between the at least one gate line and the fan-out line, and reducing the parasitic capacitance between the at least one gate line and the fan-out line, or, the signal of the gate line adjacent to the second sub-extension segment affects the signal voltage of the second sub-extension segment, which can partially or completely offset the effect of the at least one gate line adjacent to the first sub-extension segment on the signal voltage of the first sub-extension segment at the time of its voltage jump, thereby improving the uniformity of display brightness of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0154] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0155] Figure 1 A top view of a display panel provided in an embodiment of the present application.

[0156] Figure 2 A top view of a data line, a first gate line, and a fan-out line provided in an embodiment of the present application.

[0157] Figure 3 Another top view of the data line, the first gate line and the fan-out line provided in the embodiment of the present application.

[0158] Figure 4 A top view of a gate line set and a pixel circuit provided in an embodiment of the present application.

[0159] Figure 5 A top view of a fan-out line and a gate line provided in an embodiment of the present application.

[0160] Figure 6a Another top view of a fan-out line and a gate line provided in an embodiment of the present application.

[0161] Figure 6b A top view of a fan-out line, a gate line, and a gate driving circuit provided in an embodiment of the present application.

[0162] Figure 6c Another top view of a fan-out line, a gate line, and a gate driving circuit provided in an embodiment of the present application.

[0163] Figure 7 A top view of a fan-out line, a gate line, and a row pixel circuit provided in an embodiment of the present application.

[0164] Figure 8a Another top view of a fan-out line, a gate line, and a pixel circuit provided in an embodiment of the present application.

[0165] Figure 8b Another top view of a fan-out line, a gate line, and a pixel circuit provided in an embodiment of the present application.

[0166] Figure 8c Another top view of a fan-out line, a gate line, and a pixel circuit provided in an embodiment of the present application.

[0167] Fig. 9 A top view of a fan-out line, a gate line, a pixel circuit, and a gate driving circuit provided in an embodiment of the present application.

[0168] Fig.10 Another top view of a fan-out line, a gate line, a pixel circuit and a gate driving circuit provided in an embodiment of the present application.

[0169] Fig.11a Another top view of a fan-out line, a gate line, a pixel circuit and a gate driving circuit provided in an embodiment of the present application.

[0170] Fig.11b Another top view of a fan-out line, a gate line, a pixel circuit and a gate driving circuit provided in an embodiment of the present application.

[0171] Fig.11cAnother top view of a fan-out line, a gate line, a pixel circuit and a gate driving circuit provided in an embodiment of the present application.

[0172] Fig.12 This is an equivalent circuit diagram of the pixel circuit, light-emitting unit and signal lines provided in an embodiment of the present application.

[0173] Fig.13 Another equivalent circuit diagram of the pixel circuit, the light-emitting unit and each signal line provided in an embodiment of the present application.

[0174] Fig.14a Another top view of a fan-out line, a gate line, and a pixel circuit provided in an embodiment of the present application.

[0175] Fig.14b Another top view of a fan-out line, a gate line, and a pixel circuit provided in an embodiment of the present application.

[0176] Fig.15 A top view of a data line group and a pixel circuit provided in an embodiment of the present application.

[0177] Fig.16 A timing diagram of a pixel circuit provided in an embodiment of the present application.

[0178] Fig.17 A timing diagram of a gate line adjacent to a first sub-extension segment and a gate line adjacent to a second sub-extension segment provided in an embodiment of the present application.

[0179] Fig.18 Another timing diagram of a gate line adjacent to a first sub-extension segment and a gate line adjacent to a second sub-extension segment provided in an embodiment of the present application.

[0180] Fig.19 Another timing diagram of a gate line adjacent to a first sub-extension segment and a gate line adjacent to a second sub-extension segment provided in an embodiment of the present application.

[0181] Fig. 20 Another timing diagram of a gate line adjacent to a first sub-extension segment and a gate line adjacent to a second sub-extension segment provided in an embodiment of the present application.

[0182] Description of reference numerals:

[0183] 100, display panel; 100a, display area; 101a, first display area; 102a, second display area; 102a1, first sub-area; 102a2, second sub-area; 100b, non-display area; 101b, first non-display area; 102b, second non-display area; 110, data line; 110a, data line group; 111, first data line; 112, second data line; 113, third data line; 120, gate line; 120a, gate line set; 120b, gate line group; Sa, first gate line; Sb, second gate line; Sc, third gate line; Sd, fourth gate line; Se, fifth gate line; 130, fan-out line; 131, first fan-out line; 132, The second fan-out line; 133, auxiliary fan-out line; 134, sub-connection segment; 1341, first sub-connection segment; 1342, second sub-connection segment; 135, sub-extension segment; 1351, first sub-extension segment; 1352, second sub-extension segment; 1353, third sub-extension segment; 136, electrical connection node; 1361, first electrical connection node; 1362, second electrical connection node; 137, auxiliary sub-connection segment; 140, gate drive circuit; 140a, shift register; 141, first gate drive circuit; 1411, first shift register; 142, second gate drive circuit; 1422, second shift register; 151, pixel circuit; 161, drive chip; 162, binding pin. DETAILED DESCRIPTION

[0184] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0185] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, they do not represent any order, quantity or importance, but are only used to distinguish different components. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0186] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0187] Organic Light Emitting Diode (OLED) display technology is regarded as the most promising new flat panel display technology of the next generation. Compared with liquid crystal display technology, OLED display technology has the advantages of low energy consumption, low cost, self-luminescence, wide viewing angle and fast response speed.

[0188] In the process of realizing the present application, the inventors found the following problems in the related art: the display panel includes a substrate, on which a plurality of gate lines, a plurality of data lines and a plurality of fan-out lines are arranged, the plurality of data lines extend in the column direction and are arranged at intervals in the row direction, and the plurality of gate lines extend in the row direction and are arranged at intervals in the column direction. Some or all of the data lines are connected to the fan-out lines correspondingly, and at least part of the fan-out lines is located in the display area. The fan-out lines include a first sub-fan-out line extending in the row direction and a second sub-fan-out line extending in the column direction, and the first sub-fan-out line is connected between the corresponding data line and the second sub-fan-out line. The first sub-fan-out line may be located in the display area, and at least part of the second sub-fan-out line is located in the display area.

[0189] However, there is a parasitic capacitance between the first sub-fan-out line and the adjacent gate line, and the extension length of the first sub-fan-out line along the row direction is relatively large, resulting in a large parasitic capacitance between the first sub-fan-out line and the adjacent gate line, so that when the gate line signal jumps, it will couple and pull the signal voltage of the adjacent fan-out line and the data line connected to the fan-out line, and ultimately cause the data signal voltage written by the pixel corresponding to the column data line at this moment to be inconsistent with that of other rows in the same column, and thus the brightness is different from that of other pixels, that is, among the multiple light-emitting units corresponding to the column data line, the brightness of the light-emitting unit corresponding to the gate line is different from that of other light-emitting units, resulting in poor display brightness uniformity of the display panel, and the display panel is prone to oblique uneven areas or dark spots.

[0190] In view of at least one of the above problems, embodiments of the present application provide a display panel and a display device, which can improve the brightness uniformity of the display panel and alleviate the occurrence of oblique line-shaped uneven areas or dark spots on the display panel.

[0191] The following will be combined Figure 1-Figure 20 The display panel and the display device provided in the embodiments of the present application are described.

[0192] The embodiment of the present application provides a display device, which may include a display panel 100. The display device may be an electronic paper, a mobile phone, a tablet computer, a television, a display, a laptop computer, a digital photo frame, a smart bracelet, a smart watch, a super personal computer, a navigator, a wireless device, a personal digital assistant (PDA), a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a camcorder, a game console, a clock, a calculator, a television monitor, a computer monitor, a car display (e.g., an odometer display, etc.), a cockpit controller and / or display, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), an electronic billboard or sign, a projector, or other mobile or fixed terminals.

[0193] Exemplarily, the display panel may be an organic light-emitting diode (OLED) display panel, a micro organic light-emitting diode (Micro OLED) display panel, a light emitting diode (LED) display panel, a quantum dot light emitting diode (QLED) display panel, a mini light emitting diode (Mini LED) display panel, a micro light emitting diode (Micro LED) display panel, or a liquid crystal (LCD) display panel. The embodiments of the present application are described by taking an OLED display panel as an example.

[0194] For example, see Figure 1, the display panel 100 may have a first direction A, a second direction B and a third direction, and the first direction A, the second direction B and the third direction are all different. The first direction A and the second direction B may be any two different directions parallel to the display panel 100, and the third direction may be any direction intersecting with a plane parallel to the display panel 100. For example, the first direction A, the second direction B and the third direction may be perpendicular to each other. Exemplarily, the first direction A may be the length direction of the display panel 100, the second direction B may be the width direction of the display panel 100, and the third direction may be the thickness direction of the display panel 100. The length, width and thickness in the embodiments of the present application are merely for the convenience of description and do not imply any limitation on the size. For example, the width may be greater than, equal to or less than the length. The direction of the display panel 100 may be consistent with the direction of the film layer such as the substrate.

[0195] The display panel 100 provided in the embodiment of the present application is described below.

[0196] In some embodiments, see Figure 1 The display panel 100 includes a display area 100a and a non-display area 100b. The non-display area 100b is disposed adjacent to the display area 100a. For example, the non-display area 100b may be disposed around the periphery of the display area 100a.

[0197] For example, see Figure 1 The non-display area 100b includes a first non-display area 101b, and the first non-display area 101b is located at one side of the display area 100a along the first direction A.

[0198] For example, see Figure 1 The non-display area 100b includes a second non-display area 102b, and the second non-display area 102b is located at both sides of the display area 100a along the second direction B.

[0199] For example, see Figure 1 The display area 100a includes a first display area 101a and a second display area 102a, and the second display area 102a is located on two opposite sides of the first display area 101a along the second direction B.

[0200] For example, see Figure 2 The second display area 102a includes a first sub-area 102a1 and a second sub-area 102a2. The first sub-area 102a1 is located on a side of the second sub-area 102a2 away from the first display area 101a.

[0201] In some embodiments, the display panel 100 may include a substrate, which may provide support for other film layers that are subsequently disposed.

[0202] In some embodiments, see Figure 2The display panel 100 may include a plurality of data lines 110 disposed on a substrate. For example, the plurality of data lines 110 extend along a first direction A, and the plurality of data lines 110 are arranged in a second direction B at intervals. Figure 2 The multiple data lines 110 in can be respectively D1, D2, D3, D4, D5...Dn.

[0203] See also Figure 2 The display panel 100 may include a plurality of gate lines 120, the plurality of gate lines 120 are disposed on a substrate, the plurality of gate lines 120 are arranged at intervals along a first direction A, and the plurality of gate lines 120 extend along a second direction B. Orthographic projections of the plurality of gate lines 120 on the substrate and orthographic projections of the plurality of data lines 110 on the substrate are interlaced with each other. Figure 2 The plurality of gate lines 120 shown in the figure are all first gate lines Sa, and the remaining gate lines 120 are not shown. The plurality of first gate lines Sa may be first gate lines Sa-1, Sa-2, Sa-3, Sa-4, Sa-5, Sa-6, ... Sa-n, respectively.

[0204] See also Figure 2 The display panel 100 may include a plurality of fan-out lines 130, the plurality of fan-out lines 130 are disposed on the substrate, and the plurality of fan-out lines 130 are electrically connected to at least a portion of the data lines 110. For example, the first non-display area 101b includes a binding area, in which a binding pin 162 ( Figure 1 ), one end of the fan-out line 130 is electrically connected to the corresponding data line, and the binding pin 162 is electrically connected to the other end of the fan-out line 130. Figure 2 The multiple fan-out lines 130 shown in FIG. 1 are F1, F2, F3, F4, F5, F6, F7, F8, and F9, respectively. Among them, F1, F2, F3, F4, and F5 are all first fan-out lines 131, and F6, F7, F8, and F9 are all auxiliary fan-out lines 133. At least part may include part or all.

[0205] Exemplarily, the data lines 110 , the gate lines 120 , and the fan-out lines 130 are at least partially located in the display area 100 a .

[0206] For example, see Figure 2 In at least some of the fan-out lines 130, in the same fan-out line 130, the fan-out line 130 includes a sub-connection segment 134 and a plurality of sub-extension segments 135, and two adjacent sub-extension segments 135 are connected by the sub-connection segment 134, for example, the extension direction of the adjacent sub-connection segments 134 intersects with the extension direction of the sub-extension segments 135. In at least some of the fan-out lines 130, in the same fan-out line 130, the number of the sub-extension segments 135 may be 2, 3, 4, or any number greater than 4.

[0207] For example, the sub-extension section 135 intersects with the extension direction of the data line 110. For example, see Figure 2 , the sub-extending segment 135 extends along the second direction B. For example, the sub-connecting segment 134 intersects with the extending direction of the gate line 120. For example, see Figure 2 , the sub-connecting section 134 extends along the first direction A.

[0208] For example, the extending direction of the gate line 120 intersects with the extending direction of the sub-connecting segment 134 .

[0209] Of course, the sub-extension section 135 and / or the sub-connection section 134 may also extend along other directions.

[0210] Exemplarily, among the at least some number of fan-out lines 130 , the numbers of sub-extension sections 135 in any two fan-out lines 130 may be the same or different.

[0211] For example, see Figure 1 and Figure 3 , among at least a part of the fan-out lines 130, the farther the distance between the electrical connection node 136 between the fan-out line 130 and the corresponding data line 110 and the first non-display area 101b along the first direction A, the greater the number of sub-extension segments 135 in the fan-out line 130, the greater the number of sub-connection segments 134 in the fan-out line 130, and the greater the sum of the extension lengths of the sub-extension segments 135 in the fan-out line 130. For example, the distance between the second electrical connection node 1362 of the second fan-out line 132 and the corresponding data line 110 and the first non-display area 101b along the first direction A is greater than the distance between the first electrical connection node 1361 of the first fan-out line 131 and the corresponding data line 110 and the first non-display area 101b along the first direction A, the number of sub-extension segments 135 in the second fan-out line 132 is greater than the number of sub-extension segments 135 in the first fan-out line 131, the number of sub-connection segments 134 in the second fan-out line 132 is greater than the number of sub-connection segments 134 in the first fan-out line 131, and the sum of the extension lengths of the multiple sub-extension segments 135 in the second fan-out line 132 is greater than the sum of the extension lengths of the multiple sub-extension segments 135 in the first fan-out line 131. Since the number of the sub-extension segments 135 in the second fan-out line 132 is greater than the number of the sub-extension segments 135 in the first fan-out line 131 , the effect of reducing the parasitic capacitance is better, which is more conducive to improving the pixel density of the display panel 100 .

[0212] See also Fig.17 and Fig.18 , the signal of at least one (e.g., multiple, part, or all) gate line 120 adjacent to the first sub-extension segment 1351 is different from the signal of the gate line 120 adjacent to the second sub-extension segment 1352. The difference in signal may include one or more of the pulse width, jump time, amplitude polarity, phase, frequency, function, etc. of the signal being different.

[0213] For example, within the same refresh cycle, at least one (for example, multiple times, part of the times, or all of the times) voltage jump moment of the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension segment 1351 is different from the voltage jump moment of the pulse of the signal on the gate line 120 adjacent to the second sub-extension segment 1352. For example, the amplitude polarity (for example, negative pulse or positive pulse) of the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension segment 1351 and the amplitude polarity of the pulse of the signal on the gate line 120 adjacent to the second sub-extension segment 1352 are the same or different. Among them, Sa-1 can be a gate line 120 adjacent to the first sub-extension segment 1351, Sa-2 can be a gate line 120 adjacent to the second sub-extension segment 1352, and Sa-1 and Sa-2 have the same function. Alternatively, Sa can be a gate line 120 adjacent to the first sub-extension segment 1351, Sc can be a gate line 120 adjacent to the second sub-extension segment 1352, and Sa and Sc have different functions. Taking Sa and Sc as an example, see Fig.17 , the pulses of the signals on Sa and Sc are negative pulses, and the pulses do not overlap and there is a delay. Fig.18 , the pulses of the signals on Sa and Sc are positive pulses, and the pulses partially overlap and there is a delay.

[0214] For example, see Fig.19 and Fig. 20 The amplitude polarity (e.g., negative pulse or positive pulse) of the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension segment 1351 is different from the amplitude polarity (e.g., positive pulse or negative pulse) of the pulse of the signal on the gate line 120 adjacent to the second sub-extension segment 1352. For example, the voltage jump moment of the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension segment 1351 and the voltage jump moment of the pulse of the signal on the gate line 120 adjacent to the second sub-extension segment 1352 are the same or different. Among them, Sa can be a gate line 120 adjacent to the first sub-extension segment 1351, and Sc can be a gate line 120 adjacent to the second sub-extension segment 1352, and Sa and Sc have different functions. The pulse of the signal on Sa is a negative pulse, and the pulse of the signal on Sc is a positive pulse. See. Fig.19 , the pulse amplitude polarity of Sa and Sc is different, and the voltage jump time is different. Fig. 20 , the pulse amplitude polarities of Sa and Sc are different, and the voltage jump time is the same.

[0215] Illustratively, in the same refresh cycle, the first voltage jump time of the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension segment 1351 is different from the voltage jump time of the pulse of the signal on the gate line 120 adjacent to the second sub-extension segment 1352 .

[0216] Exemplarily, in the same refresh cycle, in the same fan-out line 130 , the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension segment 1351 does not overlap with the pulse of the signal on the gate line adjacent to the second sub-extension segment 1352 .

[0217] Exemplarily, in the same refresh cycle, in the same fan-out line 130 , the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension segment 1351 is not synchronized with the pulse of the signal on the gate line 120 adjacent to the second sub-extension segment 1352 , for example, there is a delay.

[0218] Exemplarily, in the same refresh cycle, in the same fan-out line 130, the moment when the pulse of the signal on at least one gate line 120 adjacent to the first sub-extension segment 1351 jumps to its own effective level (which may be the level after the first voltage jump) is different from the moment when the pulse of the signal on the gate line 120 adjacent to the second sub-extension segment 1352 jumps to its own effective level. The effective level may be a high level or a low level. The effective level may be an on level or an off level.

[0219] Exemplarily, within the same refresh cycle, in the same fan-out line 130, the moment when the pulse of the signal on each gate line 120 adjacent to the first sub-extension segment 1351 jumps to its own valid level is different from the moment when the pulse of the signal on the gate line 120 adjacent to the second sub-extension segment 1352 jumps to its own valid level.

[0220] See also Figure 2In at least a portion of the fan-out lines 130, in the same fan-out line 130, the plurality of sub-extension segments 135 include a first sub-extension segment 1351 and a second sub-extension segment 1352, the signal voltage of the first sub-extension segment 1351 is mainly affected by the gate line 120 adjacent to the first sub-extension segment 1351, and the signal voltage of the second sub-extension segment 1352 is mainly affected by the gate line 120 adjacent to the second sub-extension segment 1352, wherein the signal of at least one gate line 120 adjacent to the first sub-extension segment 1351 is different from the signal of the gate line 120 adjacent to the second sub-extension segment 1352, so that at least one gate line 120 adjacent to the first sub-extension segment 1351 is not adjacent to the second sub-extension segment 1352, for example, separated by other gate lines, and the at least one gate line 120 adjacent to the first sub-extension segment 1351 can affect the signal voltage of the first sub-extension segment 1351 at the time of its signal jump, for example, a pull-up voltage or a pull-down voltage, but basically does not affect the signal voltage of the second sub-extension segment 1352 The voltage is affected. Since the signal of the gate line 120 adjacent to the second sub-extension segment 1352 is different from the signal of the at least one gate line 120, the signal of the gate line 120 adjacent to the second sub-extension segment 1352 will not jump at this moment, and the signal of the gate line 120 adjacent to the second sub-extension segment 1352 will not affect the signal voltage of the second sub-extension segment 1352. The parasitic capacitance between the at least one gate line 120 and the fan-out line 130 is equal to the parasitic capacitance generated by the mutual coupling of the first sub-extension segment 1351 and the at least one gate line 120, so that the coupling length between the at least one gate line 120 and the fan-out line 130 is shortened, thereby reducing the coupling degree between the at least one gate line 120 and the fan-out line 130, reducing the parasitic capacitance between the at least one gate line 120 and the fan-out line 130, and reducing the influence of the at least one gate line 120 on the signal voltage of the fan-out line 130 at the moment of its signal jumping, thereby improving the uniformity of the display brightness of the display panel 100. Since the signal of the gate line 120 adjacent to the second sub-extension segment 1352 is different from the signal of the at least one gate line 120, the signal of the gate line 120 adjacent to the second sub-extension segment 1352 jumps in the opposite direction at this moment, and the signal of the gate line 120 adjacent to the second sub-extension segment 1352 affects the signal voltage of the second sub-extension segment 1352, which can partially or completely offset the influence of the at least one gate line 120 adjacent to the first sub-extension segment 1351 on the signal voltage of the first sub-extension segment 1351 at the moment of its signal jump, thereby improving the uniformity of the display brightness of the display panel 100.

[0221] Therefore, in the embodiment of the present application, in the same fan-out line 130, by dividing the part of the fan-out line 130 extending along the second direction B into multiple sub-extension segments 135, the length of each sub-extension segment 135 is reduced, and the coupling length between the sub-extension segment 135 and the adjacent gate line 120 can be reduced, so as to reduce the parasitic capacitance between the sub-extension segment 135 and the adjacent gate line 120, thereby alleviating the oblique line-shaped uneven area or dark spot caused by the uneven display brightness, so that the design requirements of the parasitic capacitance in a single pixel are lower, which is conducive to improving the pixel density.

[0222] The difference in signals of the two gate lines 120 may mean that the two gate lines 120 are used to transmit signals of different functions, or the two gate lines 120 are used to transmit the same functional signal, but the timing of the two gate lines 120 is different, for example, there is a delay in the pulse signals on the two gate lines 120. The two gate lines 120 may be electrically connected to the output ends of different shift registers 140a, so that the signals of the two gate lines 120 are different. The two gate lines 120 may be electrically connected to transistors of different functions, in which case the two gate lines 120 are used to transmit signals of different functions.

[0223] Illustratively, in the same fan-out line 130 , the first sub-extension segment 1351 and the second sub-extension segment 1352 may be disposed adjacent to each other or may not be disposed adjacent to each other.

[0224] For example, see Figure 2 , the extension length of the first sub-extension segment 1351 in the same fan-out line 130 is less than or greater than or equal to the extension length of the second sub-extension segment 1352, so that the parasitic capacitance between the gate line 120 adjacent to the second sub-extension segment 1352 and the second sub-extension segment 1352 is small, which is beneficial to improving the uniformity of the display brightness of the display panel 100. For example, in a part of the number of fan-out lines 130, the extension length of the first sub-extension segment 1351 in the same fan-out line 130 is greater than the extension length of the second sub-extension segment 1352. The sub-extension segment 135 with the longest extension length in the same fan-out line 130 has the largest coupling capacitance with the adjacent gate line, so dividing the longest fan-out line into a plurality of sub-extension segments 135 with equal extension lengths is beneficial to reducing the maximum value of the coupling capacitance between the fan-out line 130 and the adjacent gate line.

[0225] In some other examples, the extension length of the first sub-extension segment 1351 in the same fan-out line 130 may be smaller than the extension length of the second sub-extension segment 1352 .

[0226] Illustratively, in a portion of the fan-out lines 130 , the extension lengths of the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130 are equal, thereby reducing the difficulty of setting the first sub-extension segment 1351 and the second sub-extension segment 1352 of the fan-out line 130 .

[0227] Exemplarily, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the number of gate lines 120 arranged adjacent to the first sub-extension segment 1351 may be one or more, and the number of gate lines 120 arranged adjacent to the second sub-extension segment 1352 may be one or more.

[0228] The sub-extension section 135 and the gate line 120 are arranged adjacent to each other, which may mean that: in an embodiment where the sub-extension section 135 and the adjacent gate line 120 do not overlap along the thickness direction of the substrate, there is no orthographic projection of other gate lines 120 on the substrate between the orthographic projection of the sub-extension section 135 on the substrate and the orthographic projection of the adjacent gate line 120 on the substrate. In an embodiment where the sub-extension section 135 and the adjacent gate line 120 at least partially overlap along the thickness direction of the substrate, no other gate line 120 is arranged between the sub-extension section 135 and the adjacent gate line 120 along the thickness direction of the substrate. No other gate lines, power lines, DC potential lines, shielding lines, etc. are arranged between the sub-extension section 135 and the gate line 120 adjacent to the sub-extension section 135.

[0229] In some embodiments, the orthographic projection of the first sub-extension segment 1351 on the substrate is the first orthographic projection, the orthographic projection of the second sub-extension segment 1352 on the substrate is the second orthographic projection, and the orthographic projection of the gate line 120 on the substrate is the third orthographic projection. In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, at least two third orthographic projections are arranged between the first orthographic projection and the second orthographic projection, so that at least two gate lines 120 are arranged between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A, so that the first sub-extension segment 1351 and the second sub-extension segment 1352 are not aligned with each other. The gate lines 120 are adjacent to the same gate line 120, so that only one gate line 120 is avoided between the first sub-extension segment 1351 and the second sub-extension segment 1352. The first sub-extension segment 1351 and the second sub-extension segment 1352 are adjacent to the same gate line 120, resulting in that the gate line 120 will affect the signal voltage of the first sub-extension segment 1351 and the second sub-extension segment 1352 at the signal jump moment. The parasitic capacitance between the gate line 120 and the fan-out line 130 is equal to the sum of the parasitic capacitances generated by the mutual coupling of the first sub-extension segment 1351 and the second sub-extension segment 1352 with the gate line 120, thereby causing poor display. Among the at least two gate lines 120, the gate line 120 corresponding to the third orthographic projection adjacent to the first orthographic projection is adjacent to the first sub-extension segment 1351, and the gate line 120 corresponding to the third orthographic projection adjacent to the second orthographic projection is adjacent to the second sub-extension segment 1352.

[0230] In some embodiments, see Figure 5 The plurality of gate lines 120 include at least one of a first gate line Sa and a second gate line Sb, and at least one of a third gate line Sc and a fourth gate line Sd. In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, at least one of the first gate line Sa and the second gate line Sb is disposed adjacent to the first sub-extension segment 1351, and at least one of the third gate line Sc and the fourth gate line Sd is disposed adjacent to the second sub-extension segment 1352.

[0231] For some examples, see Figure 5In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first sub-extension segment 1351 and the second sub-extension segment 1352 are both adjacent to a gate line 120. For example, the first sub-extension segment 1351 is adjacent to the first gate line Sa or the second gate line Sb (taking the first gate line Sa as an example), and the second sub-extension segment 1352 is adjacent to the third gate line Sc or the fourth gate line Sd (taking the third gate line Sc as an example). The signal of the first gate line Sa adjacent to the first sub-extension segment 1351 is different from the signal of the third gate line Sc adjacent to the second sub-extension segment 1352. In this way, the first sub-extension segment 1351 adjacent to the first gate line Sa or the second gate line Sb adjacent to the second gate line Sc The signal jump moment of the first gate line Sa is different from the signal jump moment of the third gate line Sc adjacent to the second sub-extension segment 1352. The influence of the signal jump of the first gate line Sa on the signal voltage of the fan-out line 130 is mainly related to the parasitic capacitance between the first gate line Sa and the first sub-extension segment 1351. The parasitic capacitance between the first gate line Sa and the fan-out line 130 is mainly formed by the coupling of the first sub-extension segment 1351 and the first gate line Sa, thereby reducing the coupling degree between the first gate line Sa and the fan-out line 130 and reducing the parasitic capacitance between the first gate line Sa and the fan-out line 130, thereby improving the uniformity of the display brightness of the display panel 100. The influence of the signal jump of the third gate line Sc on the signal voltage of the fan-out line 130 is mainly related to the parasitic capacitance between the third gate line Sc and the second sub-extension segment 1352. The parasitic capacitance between the third gate line Sc and the fan-out line 130 is mainly formed by the coupling between the second sub-extension segment 1352 and the third gate line Sc, so that the coupling degree between the third gate line Sc and the fan-out line 130 can be reduced, and the parasitic capacitance between the third gate line Sc and the fan-out line 130 can be reduced, so that the uniformity of the display brightness of the display panel 100 can be improved. In addition, in the embodiment where the first gate line Sa and the third gate line Sc are located between the first sub-extension segment 1351 and the second sub-extension segment 1352, the first gate line Sa and the third gate line Sc with different signals can isolate the first sub-extension segment 1351 and the second sub-extension segment 1352 from each other, so that the first sub-extension segment 1351 is only affected by the first gate line Sa, and the second sub-extension segment 1352 is only affected by the third gate line Sc.

[0232] For other examples, see Figure 6aIn the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, at least two gate lines 120 are adjacent to the first sub-extension segment 1351 and the second sub-extension segment 1352. For example, the first sub-extension segment 1351 is adjacent to the first gate line Sa and the second gate line Sb, respectively, and the first orthographic projection is located between the orthographic projection of the first gate line Sa adjacent to the first sub-extension segment 1351 on the substrate and the orthographic projection of the second gate line Sb adjacent to the first sub-extension segment 1351 on the substrate. The second sub-extension segment 1352 is adjacent to the third gate line Sc and the fourth gate line Sd, respectively, and the second orthographic projection is located between the orthographic projection of the third gate line Sc adjacent to the second sub-extension segment 1352 on the substrate and the orthographic projection of the fourth gate line Sd adjacent to the second sub-extension segment 1352 on the substrate. The signal of the first gate line Sa adjacent to the first sub-extension segment 1351 is different from the signals of the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352, and the signal of the second gate line Sb adjacent to the first sub-extension segment 1351 is different from the signals of the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352. For example, the signals of any two of the first gate line Sa and the second gate line Sb adjacent to the first sub-extension segment 1351, and the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352 are different, so that the parasitic capacitance between the first gate line Sa, the second gate line Sb, the third gate line Sc and the fourth gate line Sd and the fan-out line 130 can be reduced, so as to improve the uniformity of the display brightness of the display panel 100. The difference in the gate line signals can be, for example, the different jump moments of the pulses of the gate line signals, and / or the different amplitude polarities of the pulses of the signals.

[0233] In some embodiments, see Figure 4 The display panel 100 includes a plurality of pixel circuits 151 arranged in an array, the gate lines 120 extend along the row direction of the array (e.g., parallel to the second direction B), and the data lines 110 extend along the column direction of the array (e.g., parallel to the first direction A). The plurality of data lines 110 are electrically connected to the plurality of columns of pixel circuits 151. The embodiment of the present application is described by taking the corresponding arrangement of a column of pixel circuits 151 and a data line 110 as an example. The data line 110 is electrically connected to the corresponding column of pixel circuits 151.

[0234] In the embodiment of the present application, the corresponding arrangement of A and B may refer to: one A is correspondingly arranged with at least one B, or one B is correspondingly arranged with at least one A. The embodiment of the present application is described by taking the corresponding arrangement of one A and one B as an example.

[0235] Exemplarily, the pixel circuit 151 includes a plurality of transistors with different functions. In at least some of the fan-out lines 130, in the same fan-out line 130, the function of the transistor electrically connected to at least one (e.g., a plurality or a part or all) of the gate lines 120 adjacent to the first sub-extension segment 1351 is different from the function of the transistor electrically connected to the gate line 120 adjacent to the second sub-extension segment 1352.

[0236] For example, see Fig.12 and Fig.13 , the plurality of gate lines 120 include a first scan line S1, for example, the first scan line S1 can be used to transmit a scan signal for initializing the first electrode or the second electrode of the driving transistor T1. The plurality of transistors include a driving transistor T1 and a first initialization transistor T8, the first initialization transistor T8 is connected between the first initialization signal line Verf1 and the first electrode or the second electrode of the driving transistor T1, the first scan line S1 is electrically connected to the gate of the first initialization transistor T8, and the first scan line S1 is used to control the on and off of the first initialization transistor T8. When the first scan line S1 controls the conduction of the first initialization transistor T8, the first initialization transistor T8 can transmit the signal of the first initialization signal line Verf1 to the first electrode or the second electrode of the driving transistor T1. The first initialization transistor T8 may include an N-type transistor or a P-type transistor.

[0237] One of the first electrode and the second electrode of the transistor may be a source of the transistor, and the other of the first electrode and the second electrode of the transistor may be a drain of the transistor.

[0238] For example, see Fig.12 and Fig.13 , the plurality of gate lines 120 include a second scan line S2, for example, the second scan line S2 can be used to transmit a scan signal for initializing the gate or the second electrode of the driving transistor T1. The plurality of transistors include a second initialization transistor T4, the second initialization transistor T4 is connected between the second initialization signal line Verf2 and the gate or the second electrode of the driving transistor T1, the second scan line S2 is electrically connected to the gate of the second initialization transistor T4, and the second scan line S2 is used to control the on and off of the second initialization transistor T4. When the second scan line S2 controls the conduction of the second initialization transistor T4, the second initialization transistor T4 can transmit the signal of the second initialization signal line Verf2 to the gate or the second electrode of the driving transistor T1. The second initialization transistor T4 may include an N-type transistor or a P-type transistor.

[0239] For example, see Fig.12 and Fig.13, the plurality of transistors include a third initialization transistor T7, the third initialization transistor T7 is connected between the third initialization signal line Verf3 and the first electrode of the light-emitting unit OLED, the first scan line S1 is electrically connected to the gate of the third initialization transistor T7, and the first scan line S1 controls the on and off of the third initialization transistor T7. When the first scan line S1 controls the third initialization transistor T7 to be turned on, the third initialization transistor T7 can transmit the signal of the third initialization signal line Verf3 to the first electrode of the light-emitting unit OLED. For example, the first scan line S1 can be used to transmit a scan signal that controls the initialization of the first electrode of the light-emitting unit OLED. The third initialization transistor T7 may include an N-type transistor or a P-type transistor.

[0240] In some embodiments, the gate of the second initialization transistor T4 and the gate of the third initialization transistor T7 may be connected to the same scan line, such as the second scan line S2. In other embodiments, the gate of the second initialization transistor T4 and the gate of the third initialization transistor T7 may be connected to different scan lines.

[0241] For example, see Fig.12 and Fig.13 , the plurality of gate lines 120 include a third scan line S3, for example, the third scan line S3 can be used to transmit a scan signal for controlling data writing. The plurality of transistors include a write transistor T2, the write transistor T2 is connected between the data line 110 and the first electrode of the drive transistor T1, the third scan line S3 is electrically connected to the gate of the write transistor T2, and the third scan line S3 can control the on and off of the write transistor T2. When the third scan line S3 controls the write transistor T2 to be turned on, the write transistor T2 can transmit the data voltage of the data line 110 to the first electrode of the drive transistor T1. The write transistor T2 may include an N-type transistor or a P-type transistor. For example, see Fig.12 and Fig.13 , the plurality of gate lines 120 include a fourth scan line S4, for example, the fourth scan line S4 can be used to transmit a scan signal for controlling threshold compensation. The plurality of transistors include a threshold compensation transistor T3, the threshold compensation transistor T3 is connected between the gate and the second electrode of the driving transistor T1, the fourth scan line S4 is electrically connected to the gate of the threshold compensation transistor T3, and the fourth scan line S4 can control the on and off of the threshold compensation transistor T3. When the fourth scan line S4 controls the threshold compensation transistor T3 to be turned on, the threshold compensation transistor T3 can conduct between the gate and the second electrode of the driving transistor T1, and then the voltage value obtained by compensating the threshold voltage of the driving transistor T1 to the data voltage is transmitted to the gate of the driving transistor T1.

[0242] In some embodiments, the gate of the write transistor T2 and the gate of the threshold compensation transistor T3 may be connected to the same scan line, that is, the third scan line S3 is multiplexed as the fourth scan line S4. In other embodiments, the gate of the write transistor T2 and the gate of the threshold compensation transistor T3 may be connected to different scan lines, that is, the third scan line S3 and the fourth scan line S4 are different scan lines. The threshold compensation transistor T3 may include an N-type transistor or a P-type transistor.

[0243] For example, see Fig.12 and Fig.13 , the plurality of gate lines 120 include a light emitting control line EM, for example, the light emitting control line EM can be used to transmit a light emitting control signal. The plurality of transistors include a first light emitting control transistor T5 and / or a second light emitting control transistor T6, the first light emitting control transistor T5 is connected between the first power line ELVDD and the first electrode of the driving transistor T1, the second light emitting control transistor T6 is connected between the second electrode of the driving transistor T1 and the first electrode of the light emitting unit OLED, the light emitting control line EM is electrically connected to the gate of the corresponding first light emitting control transistor T5 and / or the gate of the second light emitting control transistor T6, and the light emitting control line EM can control the corresponding first light emitting control transistor T5 and / or the second light emitting control transistor T6 to be turned on and off. When the light emitting control line EM controls the corresponding first light emitting control transistor T5 and / or the second light emitting control transistor T6 to be turned on, the first light emitting control transistor T5 can transmit the signal of the first power line ELVDD to the first electrode of the driving transistor T1, the second light emitting control transistor T6 can conduct between the second electrode of the driving transistor T1 and the first electrode of the light emitting unit OLED, and the driving transistor T1 generates a driving current according to the voltage between its gate and the first electrode, and drives the light emitting unit OLED to emit light. The second electrode of the light emitting unit OLED may be electrically connected to the second power line ELVSS. One of the first electrode and the second electrode of the light emitting unit OLED may be an anode, and the other may be a cathode. For example, the first electrode of the light emitting unit OLED may be an anode. The second electrode of the light emitting unit OLED may be a cathode. The first light emitting control transistor T5 may include an N-type transistor or a P-type transistor. The second light emitting control transistor T6 may include an N-type transistor or a P-type transistor.

[0244] In some embodiments, the pixel circuit 151 may include a first initialization transistor T8. In other embodiments, the pixel circuit 151 may not include the first initialization transistor T8. The pixel circuit 151 may include some or all of the transistors T1 to T8.

[0245] In some embodiments, see Fig.13 and Fig.16In the first initialization stage (t1), the signal on the second scan line S2 controls the conduction of the second initialization transistor T4. In the data writing and threshold compensation stage (t2), the signal on the third scan line S3 controls the conduction of the write transistor T2, and the signal on the fourth scan line S4 controls the conduction of the threshold compensation transistor T3. In the second initialization stage (t3), the signal on the first scan line S1 controls the conduction of the third initialization transistor T7, and the signal on the first scan line S1 controls the conduction of the first initialization transistor T8. In the light-emitting stage (t4), the signal on the light-emitting control line EM controls the conduction of the corresponding first light-emitting control transistor T5 and / or the second light-emitting control transistor T6.

[0246] The gate line set 120a provided in the embodiment of the present application is described below.

[0247] In some embodiments, see Figure 4 The display panel 100 includes a plurality of gate line sets 120a, which are arranged along a first direction A. The plurality of gate line sets 120a are arranged correspondingly to a plurality of rows of pixel circuits 151. The embodiment of the present application is described by taking one gate line set 120a correspondingly to a row of pixel circuits 151 as an example. The gate line set 120a is electrically connected to the corresponding row of pixel circuits 151.

[0248] For example, see Figure 4 Each gate line set 120a includes a plurality of gate lines 120. The number of gate lines 120 in each gate line set 120a may be 2, 3, 4, 5 or more. The embodiment of the present application is described by taking the number of gate lines 120 in each gate line set 120a as 5 as an example.

[0249] Exemplarily, each gate line set 120a includes at least one of the first gate line Sa, the second gate line Sb, the third gate line Sc, the fourth gate line Sd, and the fifth gate line Se. The embodiment of the present application is described by taking each gate line set 120a including the first gate line Sa, the second gate line Sb, the third gate line Sc, the fourth gate line Sd, and the fifth gate line Se as an example. At least one may include one or more. At least one may include one or more.

[0250] Exemplarily, one of the first gate line Sa, the second gate line Sb, the third gate line Sc, the fourth gate line Sd, and the fifth gate line Se may be one of the first scan line S1, the second scan line S2, the third scan line S3, the fourth scan line S4, and the light emitting control line EM. The first scan line S1, the second scan line S2, the third scan line S3, the fourth scan line S4, and the light emitting control line EM classify the plurality of gate lines 120 according to their functions.

[0251] Exemplarily, the first gate line Sa may be the first scan line S1 , that is, the first gate line Sa is electrically connected to the gate of the first initialization transistor T8 , and the first gate line Sa is electrically connected to the gate of the third initialization transistor T7 .

[0252] Exemplarily, the second gate line Sb may be the second scan line S2 , that is, the second gate line Sb is electrically connected to the gate of the second initialization transistor T4 .

[0253] For example, the arrangement order of the gate lines 120 in any two gate line sets 120a may be the same or different. The embodiment of the present application is described by taking the case where the arrangement order of the gate lines 120 in any two gate line sets 120a is the same as an example.

[0254] Exemplarily, any two of the first gate line Sa, the second gate line Sb, the third gate line Sc and the fourth gate line Sd are alternately arranged along the first direction A, thereby reducing the difficulty of arranging the two. For example, the first gate line Sa and the second gate line Sb are alternately arranged along the first direction A.

[0255] For example, see Fig.14a and Fig.14b The second scan line S2, the third scan line S3, the fourth scan line S4, the light emitting control line EM, and the first scan line S1 electrically connected to the same row of pixel circuits 151 are arranged in sequence along the first direction A, which is equivalent to that in the same gate line set 120a, the second scan line S2, the third scan line S3, the fourth scan line S4, the light emitting control line EM, and the first scan line S1 are arranged in sequence along the first direction A.

[0256] Exemplarily, the signals of any two of the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd are different. For example, the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd can be used to transmit different functional signals so that the signals of any two of the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd are different. In an embodiment in which the pixel circuit 151 includes a plurality of transistors with different functions, the first gate line Sa, the second gate line Sb, the third gate line Sc, and the fourth gate line Sd are electrically connected to the transistors with different functions.

[0257] The first distance L1 and the second distance L2 provided in the embodiment of the present application are described below.

[0258] For example, the distance between the gate lines 120 with the same function in two adjacent gate line sets 120a along the first direction A may be a first distance L1 ( Figure 2). For example, taking the first gate line Sa as an example, the first distance L1 is the distance between two adjacent first gate lines Sa along the first direction A. The first distance L1 is the size of the pixel along the first direction A.

[0259] In some examples, a column of pixel circuits 151 is disposed corresponding to a data line 110, and the distance between every two adjacent data lines 110 is the same, and the distance between every two adjacent data lines 110 is a second distance L2 ( Figure 2 ). The second distance L2 may be a size of the pixel circuit 151 along the second direction B.

[0260] In some other examples, among the three adjacent data lines 110, the distance between the data line 110 in the middle and the data line 110 on one side is different from the distance between the data line 110 in the middle and the data line 110 on the other side, and half of the distance between the data line 110 on one side and the data line 110 on the other side is the second distance L2. Fig.15 , multiple pixel circuits 151 form multiple columns of pixel circuits 151 (taking 4 columns of pixel circuits 151 as an example), the multiple columns of pixel circuits 151 are arranged along the second direction B, multiple data lines 110 form multiple data line groups 110a, the multiple data line groups 110a are arranged along the second direction B, and each data line group 110a includes two data lines 110; one data line group 110a is connected to two columns of pixel circuits 151; in the corresponding two columns of pixel circuits 151 and data line groups 110a, the orthographic projections of the two data lines 110 on the substrate are at least partially located between the orthographic projections of the two columns of pixel circuits 151 on the substrate. Two adjacent data line groups 110a are defined as the first data line group and the second data line group, and half of the distance between a data line 110 in the first data line group close to the second data line group and a data line 110 in the second data line group far from the first data line group is the second distance L2.

[0261] The gate driving circuit 140 provided in the embodiment of the present application is described below.

[0262] In some embodiments, see Fig.11aThe display panel 100 includes at least one (for example, one or more) gate driving circuits 140, and one gate driving circuit 140 can be electrically connected to the gate lines 120 of the same function (i.e., transmitting the same functional signal) in each gate line set 120a. Alternatively, one gate driving circuit 140 can be electrically connected to the gate lines 120 of different functions (i.e., transmitting different functional signals) in each gate line set 120a, which is equivalent to at least two gate lines with different functions sharing a gate driving circuit. A gate driving circuit 140 includes a cascaded multi-stage shift register 140a, and the shift register 140a is electrically connected to the corresponding gate line 120. In the correspondingly arranged gate driving circuits 140 and gate lines 120, a first-stage shift register 140a can be corresponding to at least one gate line 120.

[0263] For example, the display panel 100 includes one or more gate driving circuits 140, the gate driving circuit 140 includes a cascaded multi-stage shift register 140a, and in at least a part of the fan-out lines 130, in the same fan-out line 130, at least one (for example, multiple or part or all) gate line 120 adjacent to the first sub-extension segment 1351 and the gate line 120 adjacent to the second sub-extension segment 1352 are electrically connected to the output ends of different shift registers 140a.

[0264] In an embodiment where each gate line set 120a includes five gate lines 120, there may be five gate drive circuits 140. The gate lines 120 corresponding to different gate drive circuits 140 are used to transmit signals with different functions, and in the same gate drive circuit 140, the output ends of the shift registers 140a at different levels are used to output signals with different timings. For example, in the same gate drive circuit 140, the shift registers 140a at different levels are used to transmit signals with the same function and different timings (for example, there is a delay in the pulse phase). The shift register 140a being electrically connected to the gate line 120 may refer to the output end of the shift register 140a being electrically connected to the gate line 120.

[0265] In some embodiments, gate lines transmitting signals of different functions may be connected to the same gate driving circuit, ie, a common gate driving circuit.

[0266] For example, see Fig.11aThe display panel 100 includes a first gate driving circuit 141, and the first gate driving circuit 141 includes a cascaded multi-stage first shift register 1411. The output end of the first shift register 1411 is electrically connected to the corresponding first gate line Sa. The output end of the first shift register 1411 of the first stage can be electrically connected to at least one or at least two first gate lines Sa, and is electrically connected to the pixel circuit 151 of the corresponding row through the first gate line Sa. The embodiment of the present application takes the output end of the first shift register 1411 of the first stage as an example of being electrically connected to two first gate lines Sa. At least one may include one or more or at least two, etc. The output end of the first shift register 1411 of the first stage can be electrically connected to at least one row or at least two rows of pixel circuits. One stage can be each stage or one of the stages.

[0267] For example, see Fig.11a The display panel 100 includes a second gate driving circuit 142, and the second gate driving circuit 142 includes a cascaded multi-stage second shift register 1422. The output end of the second shift register 1422 is electrically connected to the corresponding second gate line Sb. The output end of the first-stage second shift register 1422 can be electrically connected to at least one or at least two second gate lines Sb, and is electrically connected to the pixel circuit 151 of the corresponding row through the second gate line Sb. The embodiment of the present application takes the first-stage second shift register 1422 being electrically connected to one second gate line Sb as an example. The output end of the first-stage second shift register 1422 can be electrically connected to at least one row or at least two rows of pixel circuits.

[0268] Exemplarily, the display panel 100 includes a third gate driving circuit, which includes a cascaded multi-stage third shift register, the output end of the third shift register is electrically connected to the corresponding third gate line Sc, the output end of the first-stage third shift register can be electrically connected to at least one or at least two third gate lines Sc, and is electrically connected to the pixel circuit 151 of the corresponding row through the third gate line Sc. The output end of the first-stage third shift register can be electrically connected to at least one row or at least two rows of pixel circuits.

[0269] Exemplarily, the display panel 100 includes a fourth gate driving circuit, the fourth gate driving circuit includes a cascaded multi-stage fourth shift register, the output end of the fourth shift register is electrically connected to the corresponding fourth gate line Sd, the output end of the first-stage fourth shift register can be electrically connected to at least one or at least two fourth gate lines Sd, and is electrically connected to the pixel circuit 151 of the corresponding row through the fourth gate line Sd. The output end of the first-stage fourth shift register can be electrically connected to at least one row or at least two rows of pixel circuits.

[0270] Exemplarily, the display panel 100 includes a fifth gate driving circuit, the fifth gate driving circuit includes a cascaded multi-stage fifth shift register, the output end of the fifth shift register is electrically connected to the corresponding fifth gate line Se, the output end of the first stage fifth shift register can be electrically connected to at least one or at least two fifth gate lines Se, and is electrically connected to the pixel circuit 151 of the corresponding row through the fifth gate line Se. The output end of the first stage fifth shift register can be electrically connected to at least one row or at least two rows of pixel circuits.

[0271] In the same gate drive circuit, in two adjacent shift registers, the level transmission signal terminal of the previous shift register can be electrically connected to the input terminal of the next shift register. For example, the level transmission signal terminal and the output terminal of the same shift register can be the same signal terminal or different signal terminals. For example, in the same gate drive circuit, the pulse width of the signal output by the output terminal of two adjacent shift registers is the same, and there is a phase delay.

[0272] See also Figure 6a-Figure 8c In the following, in the same fan-out line 130, the first sub-extension segment 1351 is respectively adjacent to the first gate line Sa and the second gate line Sb, and the second sub-extension segment 1352 is respectively adjacent to the third gate line Sc and the fourth gate line Sd.

[0273] In some embodiments, see Figure 6a In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first orthographic projection is located between the orthographic projections of the adjacent first gate line Sa and the second gate line Sb electrically connected to the corresponding pixel circuit 151 in the same row on the substrate, and the second orthographic projection is located between the orthographic projections of the adjacent third gate line Sc and the fourth gate line Sd electrically connected to the corresponding pixel circuit 151 in the same row on the substrate.

[0274] For some examples, see Figure 7 In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension segment 1351, and the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352 are all electrically connected to the corresponding pixel circuit 151 in the same row. The orthographic projections of the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130 on the substrate are located between the orthographic projections of the first gate line Sa, the second gate line Sb, the third gate line Sc and the fourth gate line Sd electrically connected to the corresponding pixel circuit 151 in the same row on the substrate. In this way, the distance between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is relatively close, which is conducive to increasing the number of fan-out lines 130, improving the wiring density of the fan-out lines 130, and / or reducing the overall occupied space of the fan-out lines 130.

[0275] In an implementation manner in which the second scan line S2, the third scan line S3, the fourth scan line S4, the light-emitting control line EM, and the first scan line S1 of the same gate line set 120a are arranged in sequence along the first direction A, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first sub-extension segment 1351 is located between two adjacent ones of the second scan line S2, the third scan line S3, the fourth scan line S4, the light-emitting control line EM, and the first scan line S1, and the second sub-extension segment 1352 is located between another two adjacent ones of the second scan line S2, the third scan line S3, the fourth scan line S4, the light-emitting control line EM, and the first scan line S1.

[0276] For other examples, see Figure 8a In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension segment 1351 are electrically connected to a row of pixel circuits 151, and the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352 are electrically connected to another row of pixel circuits 151, and the first orthographic projection is located between the orthographic projections of the first gate line Sa and the second gate line Sb adjacent to the corresponding row of pixel circuits 151 on the substrate, and the second orthographic projection is located between the orthographic projections of the first gate line Sa and the second gate line Sb adjacent to the corresponding row of pixel circuits 151 on the substrate. 51 are between the positive projections of the adjacent third gate line Sc and the fourth gate line Sd electrically connected to each other on the substrate. Such an arrangement makes the distance between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A farther, which is beneficial to increase the number of gate lines 120 between the second gate line Sb adjacent to the first sub-extension segment 1351 and the third gate line Sc adjacent to the second sub-extension segment 1352, and better avoid the influence of the second gate line Sb on the second sub-extension segment 1352, and better avoid the influence of the third gate line Sc on the first sub-extension segment 1351.

[0277] For some other examples, see Figure 8b and Figure 8c In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the second gate line Sb adjacent to the first sub-extension segment 1351 and the third gate line Sc adjacent to the second sub-extension segment 1352 are electrically connected to the same row of pixel circuits 151, and the first gate line Sa adjacent to the first sub-extension segment 1351 and the fourth gate line Sd adjacent to the second sub-extension segment 1352 are electrically connected to different rows of pixel circuits 151. For example, see Figure 8bIn the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the second gate line Sb adjacent to the first sub-extension segment 1351, the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352 are all electrically connected to the same row of pixel circuits 151, and the first gate line Sa adjacent to the first sub-extension segment 1351 is electrically connected to another row of pixel circuits 151. Alternatively, see Figure 8c In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension segment 1351, and the third gate line Sc adjacent to the second sub-extension segment 1352 are all electrically connected to the same row of pixel circuits 151, and the fourth gate line Sd adjacent to the second sub-extension segment 1352 is electrically connected to another row of pixel circuits 151.

[0278] In some embodiments, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension segment 1351 are electrically connected to different shift registers 140a, for example, electrically connected to different gate driving circuits 140 (see Figure 6b ), or, electrically connected to the output end of a different shift register 140a of the same gate drive circuit 140 (see Figure 6b ), the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352 are electrically connected to different shift registers 140a, for example, electrically connected to different gate driving circuits 140 (see Figure 6b ), or, electrically connected to the output end of a different shift register 140a of the same gate drive circuit 140 (see Figure 6c ), the shift register 140a electrically connected to the first gate line Sa and the second gate line Sb adjacent to the first sub-extension segment 1351 is different from the shift register 140a electrically connected to the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352. For example, the first gate line Sa and the second gate line Sb adjacent to the first sub-extension segment 1351 and the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352 are electrically connected to different gate driving circuits, or are electrically connected to output ends of different shift registers of the same gate driving circuit. For example, any two of the first gate line Sa and the second gate line Sb adjacent to the first sub-extension segment 1351 and the third gate line Sc and the fourth gate line Sd adjacent to the second sub-extension segment 1352 are electrically connected to different shift registers 140a, so that the signals of any two are different.

[0279] See also Figure 9-10In the following, it is described that in the same fan-out line 130, the first sub-extension segment 1351 is respectively adjacent to the first gate line Sa and the second gate line Sb of one gate line group 120b, and the second sub-extension segment 1352 is respectively adjacent to the first gate line Sa and the second gate line Sb of another gate line group 120b.

[0280] In some embodiments, the plurality of gate lines 120 include a plurality of gate line groups 120b, each gate line group 120b including a first gate line Sa and a second gate line Sb. The first gate line Sa and the second gate line Sb in the same gate line group 120b may be located in the same gate line set 120a, in which case the first gate line Sa and the second gate line Sb in the same gate line group 120b may be electrically connected to the same row of pixel circuits 151, for example, the orthographic projections of the first gate line Sa and the second gate line Sb in the same gate line group 120b on the substrate overlap with the orthographic projections of the same row of pixel circuits 151 on the substrate. Alternatively, the first gate line Sa and the second gate line Sb in the same gate line group 120b may be respectively located in two different gate line sets 120a. In this case, the first gate line Sa and the second gate line Sb in the same gate line group 120b may be electrically connected to pixel circuits 151 in different rows. For example, the orthographic projections of the first gate line Sa and the second gate line Sb in the same gate line group 120b on the substrate overlap with the orthographic projections of pixel circuits 151 in different rows on the substrate.

[0281] In some embodiments, the first gate lines Sa in different gate line groups 120b are electrically connected to transistors with the same function in different rows of pixel circuits 151. And / or, the second gate lines Sa in different gate line groups 120b are electrically connected to transistors with the same function in different rows of pixel circuits 151. And / or, the first gate lines Sa and the second gate lines Sb are electrically connected to transistors with different functions in the pixel circuits 151. For example, the first gate lines Sa in different gate line groups are used to transmit signals with the same function; the second gate lines Sb in different gate line groups are used to transmit signals with the same function;

[0282] See also Fig. 9 and Fig.10In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first sub-extension segment 1351 is adjacent to the first gate line Sa and the second gate line Sb in the corresponding gate line group 120b, and the first orthographic projection is located between the orthographic projection of the first gate line Sa and the orthographic projection of the second gate line Sb in the corresponding gate line group 120b on the substrate. The second sub-extension segment 1352 is adjacent to the first gate line Sa and the second gate line Sb in the corresponding other gate line group 120b, and the second orthographic projection is located between the orthographic projection of the first gate line Sa and the orthographic projection of the second gate line Sb in the corresponding other gate line group 120b on the substrate. With such arrangement, the functions of two gate lines 120 adjacent to each other, the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, are the same, so that the arrangement of the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130 is relatively regular, which helps to reduce the difficulty of arranging the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, improve the uniformity of the off-screen display, and reduce the risk of uneven off-screen display (mura) due to the irregular arrangement of the first sub-extension segment 1351 and the second sub-extension segment 1352.

[0283] In some embodiments, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first gate line Sa adjacent to the first sub-extension segment 1351 and the first gate line Sa adjacent to the second sub-extension segment 1352 can be electrically connected to an output end of a gate driving circuit 140 or a shift register 140a (for example, a first shift register 1411) of different stages of the first gate driving circuit, so that the signal timing of the first gate line Sa adjacent to the first sub-extension segment 1351 is different from the signal timing of the first gate line Sa adjacent to the second sub-extension segment 1352, so that the signal timing of the first gate line Sa adjacent to the first sub-extension segment 1351 is different from the signal timing of the first gate line Sa adjacent to the second sub-extension segment 1352. 1352, in addition, the second gate line Sb adjacent to the first sub-extension segment 1351 and the second gate line Sb adjacent to the second sub-extension segment 1352 can be electrically connected to the output end of the shift register 140a (for example, the second shift register 1422) of different levels of another gate driving circuit 140 or the second gate driving circuit, so that the signal timing of the second gate line Sb adjacent to the first sub-extension segment 1351 is different from the signal timing of the second gate line Sb adjacent to the second sub-extension segment 1352, so that the signal of the second gate line Sb adjacent to the first sub-extension segment 1351 is different from the signal of the second gate line Sb adjacent to the second sub-extension segment 1352.

[0284] In an embodiment where the second scan line S2, the third scan line S3, the fourth scan line S4, the light emitting control line EM, and the first scan line S1 of the same gate line set 120a are arranged in sequence along the first direction A, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first sub-extension segment 1351 is located between two adjacent ones of the second scan line S2, the third scan line S3, the fourth scan line S4, the light emitting control line EM, and the first scan line S1, and the gate lines 120 adjacent to the first sub-extension segment 1351 and the second sub-extension segment 1352 have the same corresponding functions, different signal timings, and are electrically connected to different shift registers 140a. At this time, the first gate line Sa and the second gate line Sb in the same gate line group 120b can be two adjacent ones of the second scan line S2, the third scan line S3, the fourth scan line S4, the light emitting control line EM, and the first scan line S1. Taking the first gate line Sa and the second gate line Sb in the same gate line group 120b as an example, which are the second scan line S2 and the third scan line S3 respectively, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first sub-extension segment 1351 is arranged adjacent to the second scan line S2 and the third scan line S3 of one gate line set 120a, and the second sub-extension segment 1352 is arranged adjacent to the second scan line S2 and the third scan line S3 of another gate line set 120a, the second scan line S2 adjacent to the first sub-extension segment 1351 and the second scan line S2 adjacent to the second sub-extension segment 1352 are electrically connected to second shift registers 1422 of different levels, and the third scan line S3 adjacent to the first sub-extension segment 1351 and the third scan line S3 adjacent to the second sub-extension segment 1352 are electrically connected to third shift registers of different levels.

[0285] For example, see Fig.10In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the first gate line Sa and the second gate line Sb in a gate line group 120b adjacent to the first sub-extension segment 1351 are electrically connected to the pixel circuits 151 of different rows, the first gate line Sa and the second gate line Sb in a gate line group 120b adjacent to the first sub-extension segment 1351 are respectively located in different gate line sets 120a, and / or the first gate line Sa and the second gate line Sb in another gate line group 120b adjacent to the second sub-extension segment 1352 are electrically connected to the pixel circuits 151 of different rows. The element circuit 151 is equivalent to that two first gate lines Sa and second gate lines Sb adjacent to at least one of the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130 are respectively located in different gate line sets 120a, and the orthographic projection of the first sub-extension segment 1351 and / or the second sub-extension segment 1352 on the substrate can be located between the orthographic projections of two adjacent gate line sets 120a on the substrate, which is helpful to reduce the interference of the first sub-extension segment 1351 and / or the second sub-extension segment 1352 on the arrangement of multiple gate lines 120 in the gate line set 120a.

[0286] In some embodiments, see Figure 11a-Figure 11c , each level of the first shift register 1411 is electrically connected to N first gate lines Sa, where N is a positive integer. For example, N can be 1, 2, 3, or any number greater than 3. Each level of the second shift register 1422 is electrically connected to M second gate lines Sb, where M is a positive integer, and M can be 1, 2, 3, or any number greater than 3. The output end of each level of the first shift register 1411 is electrically connected to N rows of pixel circuits via the first gate lines Sa. The output end of each level of the second shift register 1422 is electrically connected to M rows of pixel circuits via the second gate lines Sb.

[0287] Exemplarily, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, at least K orthographic projections of the first gate lines Sa on the substrate are arranged between the first orthographic projection and the second orthographic projection, K=max(M,N), K is taken as the larger one of M and N, for example, when M=N, K=M=N, for example, when M is greater than N, K=M, for example, when M is less than N, K=N, so that at least K first gate lines Sa are arranged along the first direction A between the first sub-extension segment 1351 and the second sub-extension segment 1352, and it is easier to realize that the at least K first gate lines Sa are close to each other. One of the at least K first gate lines Sa close to the first sub-extension segment 1351 is connected to a first-level first shift register 1411, and one of the at least K first gate lines Sa close to the second sub-extension segment 1352 is connected to another first shift register 1411, so that the timing signals of the at least K first gate lines Sa close to the first sub-extension segment 1351 and the timing signals of the at least K first gate lines Sa close to the second sub-extension segment 1352 are different, which is beneficial to reducing the influence of the parasitic capacitance between the at least K first gate lines Sa and the fan-out line 130 on the signal voltage of the fan-out line, thereby improving the uniformity of the display brightness of the display panel 100. And / or, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, at least K orthographic projections of the second gate lines Sb on the substrate are arranged between the first orthographic projection and the second orthographic projection, K=max(M, N), which is beneficial to reduce the influence of the parasitic capacitance between the at least K second gate lines Sb and the fan-out line 130 on the signal voltage of the fan-out line, so as to improve the uniformity of the display brightness of the display panel 100. The principle has been explained and will not be repeated here.

[0288] Exemplarily, at least one of N and M is 1.

[0289] Exemplarily, at least one of N and M is greater than or equal to 2. Taking the example of a first shift register 1411 being electrically connected to two first gate lines Sa, the number of first shift registers 1411 can be reduced, which is beneficial to reducing the border width of the display panel 100 .

[0290] In some embodiments, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the length of the sub-connection segment 134 connecting the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is greater than or equal to K times the first distance L1 ( Figure 2), and / or, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the distance between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is greater than or equal to K times the first distance L1, K=max(M,N), for example, the distance between the adjacent first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is greater than or equal to K times the first distance L1, so as to facilitate the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the orthographic projections of at least K first gate lines Sa and at least K second gate lines Sb on the substrate are arranged between the first orthographic projection and the second orthographic projection.

[0291] For example, see Figure 2 In the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same fan-out line 130, the length of the sub-connection segment 134 connecting the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is an integer multiple of the first distance L1, and / or the distance between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A is an integer multiple of the first distance L1. This arrangement makes it easier to set the length of the sub-connection segment 134 along the first direction A, reduces the difficulty of setting the sub-connection segment 134, and makes the arrangement of the first sub-extension segment 1351 and the second sub-extension segment 1352 more regular.

[0292] For example, see Figure 2 Among at least a portion of the adjacent fan-out lines 130, the distance between adjacent first sub-extension segments 1351 along the first direction A is an integer multiple of the first distance L1, thereby making it easier to set the distance between the first sub-extension segments 1351 of the plurality of fan-out lines 130 along the first direction A, thereby reducing the difficulty of arranging the first sub-extension segments 1351 and making the arrangement of the first sub-extension segments 1351 along the first direction A more regular.

[0293] For example, see Figure 2 In at least a portion of the adjacent fan-out lines 130, the distance between adjacent second sub-extension segments 1352 along the first direction A is an integer multiple of the first distance L1, so that the distance setting of the second sub-extension segments 1352 of multiple fan-out lines 130 along the first direction A is relatively simple, which can reduce the difficulty of arranging the second sub-extension segments 1352 and make the arrangement of the second sub-extension segments 1352 along the first direction A more regular.

[0294] For example, see Figure 2In at least a portion of adjacent fan-out lines 130, the distance between adjacent first sub-extension segments 1351 along the first direction A is equal to the distance between adjacent second sub-extension segments 1352 along the first direction A, so that the first sub-extension segments 1351 and the second sub-extension segments 1352 of each fan-out line 130 are arranged more regularly, which helps to reduce the difficulty of arranging the first sub-extension segments 1351 and the second sub-extension segments 1352 of each fan-out line 130.

[0295] For example, see Figure 2 In at least a portion of the adjacent fan-out lines 130, the distance between adjacent first sub-extension segments 1351 along the first direction A is less than or equal to the length of the sub-connection segment 134 along the first direction A. The distance between adjacent first sub-extension segments 1351 along the first direction A can be set to be smaller so that more fan-out lines 130 can be set, and / or the space occupied by the fan-out lines can be reduced. In addition, the length of the sub-connection segment 134 along the first direction A can be set to be larger, which is conducive to setting more gate lines 120 with different signals between the first sub-extension segment 1351 and the second sub-extension segment 1352 along the first direction A, thereby better reducing the influence of the parasitic capacitance between the gate line 120 adjacent to the fan-out line 130 and the fan-out line 130 on the signal voltage of the fan-out line, so as to improve the uniformity of the display brightness of the display panel 100.

[0296] For example, see Figure 2 The distance between adjacent second sub-extension segments 1352 in at least a portion of adjacent fan-out lines 130 along the first direction A is less than or equal to the length of the sub-connection segment 134 along the first direction A. The distance between adjacent second sub-extension segments 1352 along the first direction A can be set to be smaller so that more fan-out lines 130 can be set, and / or the space occupied by the fan-out lines can be reduced.

[0297] The first fan-out line 131 provided in the embodiment of the present application is described below.

[0298] See also Figure 2 , the plurality of fan-out lines 130 include a plurality of first fan-out lines 131. The plurality of sub-extension segments 135 in the same first fan-out line 131 include a first sub-extension segment 1351 and a second sub-extension segment 1352. For example, the number of sub-extension segments 135 in the first fan-out line 131 can be any value of 2, 3, 4 or more. The embodiment of the present application is described by taking the number of sub-extension segments 135 in the first fan-out line 131 as two as an example. The first sub-extension segment 1351 and the corresponding data line 110 are connected through the second sub-extension segment 1352.

[0299] For example, see Figure 2, the extension length of the second sub-extension segments 1352 in the plurality of first fan-out lines 131 gradually decreases along the first direction A, so that the second sub-extension segments 1352 in the plurality of first fan-out lines 131 are arranged more regularly, which can reduce the difficulty of arranging the second sub-extension segments 1352 in the plurality of first fan-out lines 131, and can also facilitate the connection of the second sub-extension segments 1352 in the plurality of first fan-out lines 131 with the corresponding data lines 110. For example, the extension length of the second sub-extension segments 1352 in the plurality of first fan-out lines 131 along the display area 100a ( Figure 1 ) to the first non-display area 101b ( Figure 1 ) direction gradually decreases.

[0300] Exemplarily, the extension lengths of the first sub-extension segments 1351 in the plurality of first fan-out lines 131 are equal, so that the difficulty of setting the first sub-extension segments 1351 in the plurality of first fan-out lines 131 can be better reduced, and / or the extension lengths of the sub-extension segments with the largest extension lengths in the plurality of first fan-out lines 131 are equal, and the maximum parasitic capacitances between each first fan-out line and the adjacent gate line are equal or approximately equal, so as to improve the uniformity of the display brightness of the display panel 100. The first sub-extension segment 1351 can be the sub-extension segment with the largest extension in the first fan-out line 131.

[0301] Exemplarily, the extension lengths of the sub-connection segments 134 in the plurality of first fan-out lines 131 are equal, thereby better reducing the difficulty of disposing the sub-connection segments 134 in the plurality of first fan-out lines 131 .

[0302] Exemplarily, at least one of the first sub-extension segment 1351 and the second sub-extension segment 1352 may extend along the second direction B. Taking the second sub-extension segment 1352 as an example, the second sub-extension segment 1352 extends along the second direction B, and the extension direction of the second sub-extension segment 1352 may be the same as the extension direction of the gate line 120, which can avoid the second sub-extension segment 1352 and the adjacent gate line 120 being too close along the first direction A, which is conducive to reducing the parasitic capacitance between the second sub-extension segment 1352 and the adjacent gate line 120, and in addition, the difficulty of setting the second sub-extension segment 1352 can be reduced.

[0303] Exemplarily, the second sub-extension segments 1352 in the plurality of first fan-out lines 131 are arranged at equal intervals or unequal intervals along the first direction A, so that the second sub-extension segments 1352 in the plurality of first fan-out lines 131 can be arranged in a variety of ways and can be applied to more arrangement scenarios. For example, the second sub-extension segments 1352 in the plurality of first fan-out lines 131 are arranged at equal intervals along the first direction A, which is conducive to improving the display effect.

[0304] Exemplarily, the first sub-extension segments 1351 in at least a portion of the adjacent first fan-out lines 131 are arranged at equal intervals or unequal intervals along the first direction A, so that the first sub-extension segments 1351 in at least a portion of the adjacent first fan-out lines 131 are arranged in more ways and can be applied to more arrangement scenarios. For example, the first sub-extension segments 1351 in at least a portion of the adjacent first fan-out lines 131 are arranged at equal intervals along the first direction A, which is conducive to improving the display effect.

[0305] For example, see Figure 2 , the distance L3 between the first sub-extension segments 1351 in two adjacent first fan-out lines 131 is less than or equal to the distance L4 between the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same first fan-out line 131 along the first direction A, and / or, the distance between the first sub-extension segments 1351 in two adjacent first fan-out lines 131 is less than or equal to the extension length of the sub-connection segment 134, so that the distance between the first sub-extension segments 1351 in two adjacent first fan-out lines 131 can be closer, which is conducive to setting a larger number of first sub-extension segments 1351, so as to facilitate setting more fan-out lines 131. 0, and / or, reducing the space occupied by the fan-out line. In addition, the distance between the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same first fan-out line 131 along the first direction A is made larger, and / or, the extension length of the sub-connection segment 134 is set to be larger, which is conducive to setting more gate lines 120 with different signals along the first direction A between the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same first fan-out line 131, thereby better reducing the parasitic capacitance between the gate line 120 adjacent to the fan-out line 130 and the fan-out line 130, so as to improve the uniformity of the display brightness of the display panel 100.

[0306] For example, see Figure 2 , the distance L5 between the second sub-extension segments 1352 in two adjacent first fan-out lines 131 is less than or equal to the distance L4 between the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same first fan-out line 131 along the first direction A; and / or, the distance between the second sub-extension segments 1352 in two adjacent first fan-out lines 131 is less than or equal to the extension length of the sub-connection segment 134, so as to facilitate the arrangement of more fan-out lines 130, and / or, reduce the occupied space of the fan-out lines, and better reduce the parasitic capacitance between the gate line 120 adjacent to the fan-out line 130 and the fan-out line 130, so as to improve the uniformity of the display brightness of the display panel 100. The principle has been explained and will not be repeated.

[0307] For example, see Figure 2The distance between the first sub-extension segments 1351 in two adjacent first fan-out lines 131 is equal to the distance between the second sub-extension segments 1352 in two adjacent first fan-out lines 131, so that the first sub-extension segments 1351 and the second sub-extension segments 1352 in multiple first fan-out lines 131 are arranged more regularly, which helps to reduce the difficulty of setting.

[0308] For example, see Figure 2 The extension length of the second sub-extension segment 1352 with the largest extension length among the multiple first fan-out lines 131 is equal to the extension length of the first sub-extension segment 1351 among the multiple first fan-out lines 131, so that the extension lengths of the sub-extension segments 135 of all the first fan-out lines 131 can be set to be smaller, which is beneficial to reducing the parasitic capacitance between each sub-extension segment 135 and the adjacent gate line 120, thereby helping to improve the uniformity of the display brightness of the display panel 100.

[0309] For example, see Figure 2 The first fan-out line 131 is connected to the corresponding data line 110 through a first electrical connection node 1361 (where a via hole may be provided), and is connected to the first non-display area 101b ( Figure 2 ) along the first direction A and corresponding to the first electrical connection node 1361 which is the farthest ( Figure 2 The extension lengths of the multiple sub-extension segments 135 in F1) are equal, so that the extension lengths of the multiple sub-extension segments 135 in the first fan-out line 131 can be set shorter, so that the parasitic capacitances between the multiple sub-extension segments 135 in the first fan-out line 131 and the corresponding adjacent gate lines 120 are smaller, which is beneficial to improving the uniformity of the display brightness of the display panel 100. Among all the sub-extension segments 135 of the first fan-out line 131, the extension length of the second sub-extension segment 1352 in the first fan-out line 131 corresponding to the first electrical connection node 1361 farthest from the first non-display area 101b along the first direction A is the largest, so that the extension lengths of the sub-extension segments 135 in the first fan-out line 131 with the largest length are all set shorter, which is beneficial to improving the uniformity of the display brightness of the display panel 100.

[0310] For example, in the related art, in the same fan-out line, part of the fan-out line extending along the second direction B is not divided into a plurality of sub-extension segments, so that the parasitic capacitance between the part of the fan-out line extending along the second direction B and the adjacent gate line is relatively large. In the present application, in the first sub-extension segment 1351 and the second sub-extension segment 1352 in the first fan-out line 131 corresponding to the first electrical connection node 1361 farthest from the first non-display area 101b along the first direction A, the parasitic capacitance between the first sub-extension segment 1351 and the adjacent gate line 120, and the parasitic capacitance between the second sub-extension segment 1352 and the adjacent gate line 120 are both reduced by half. The second sub-extension segment 1352 in the first fan-out line 131 corresponding to the first electrical connection node 1361 which is farthest from the first non-display area 101b along the first direction A has the largest extension length. If the parasitic capacitance between the second sub-extension segment 1352 with the largest extension length and the adjacent gate line 120 is E, the parasitic capacitance between all other sub-extension segments 135 and the adjacent gate line 120 can be made less than or equal to E, thereby achieving the best effect of improving the parasitic capacitance and achieving the optimal design.

[0311] For example, see Figure 2 The first sub-extension segments 1351 in at least a portion of the adjacent first fan-out lines 131 are partially relative to each other along the first direction A and partially staggered. Thus, by the partially relative arrangement, the total extension length of the display panel 100 occupied by the first sub-extension segments 1351 in at least a portion of the first fan-out lines 131 along the second direction B can be reduced, which is conducive to setting a larger number of fan-out lines 130 and / or reducing the space occupied by the fan-out lines. In addition, by the partially staggered arrangement, mutual interference in the layout of the first sub-extension segments 1351 in at least a portion of the first fan-out lines 131 can be avoided.

[0312] For example, see Figure 2 In the plurality of first fan-out lines 131, the offset distances L6 of adjacent first sub-extension segments 1351 are equal, so that the arrangement of the first sub-extension segments 1351 in the plurality of first fan-out lines 131 can be more regular, which is conducive to reducing the difficulty of arranging the first sub-extension segments 1351 in the plurality of first fan-out lines 131.

[0313] For example, see Figure 2 The sub-connection segments 134 in at least a portion of the adjacent first fan-out lines 131 are partially relative to each other and partially staggered along the second direction B. Thus, by means of the partially relative arrangement, the total extension length of the display panel 100 occupied by the sub-connection segments 134 in at least a portion of the first fan-out lines 131 along the first direction A can be reduced, which is conducive to setting a larger number of fan-out lines 130 and / or reducing the space occupied by the fan-out lines. In addition, by means of the partially staggered arrangement, mutual interference in the layout between the sub-connection segments 134 in at least a portion of the first fan-out lines 131 can be avoided.

[0314] For example, see Figure 2 In the multiple first fan-out lines 131 , the offset distances L5 of adjacent sub-connection segments 134 are equal, so that the sub-connection segments 134 in the multiple first fan-out lines 131 can be arranged more regularly, which is conducive to reducing the difficulty of setting the sub-connection segments 134 in the multiple first fan-out lines 131 .

[0315] For example, see Figure 2 The difference in extension lengths of the second sub-extension segments 1352 of two adjacent first fan-out lines 131 is twice the second distance L2, thereby reducing the difficulty of setting the second sub-extension segments 1352 in each first fan-out line 131 and facilitating the connection of the second sub-extension segments 1352 of the first fan-out lines 131 with the corresponding data lines 110.

[0316] For example, see Figure 2 The extension length of the second sub-extension segment 1352 with the smallest extension length among the multiple first fan-out lines 131 is greater than or equal to twice the second distance L2, thereby avoiding the extension length of the second sub-extension segment 1352 being too short and reducing the difficulty of setting the second sub-extension segment 1352.

[0317] For example, see Figure 2 , in the same first fan-out line 131, the distance between the second sub-extension segment 1352 and the first non-display area 101b along the first direction A is greater than the distance between the first sub-extension segment 1351 and the first non-display area 101b ( Figure 1 ) along the first direction A, thereby making the distance between the first sub-extension segment 1351 and the first non-display area 101b along the first direction A closer, which is beneficial to shortening the extension length of the auxiliary sub-connection segment 137, thereby reducing the mutual interference between the auxiliary sub-connection segment 137 and other signal lines, and can also reduce the difficulty of setting the auxiliary sub-connection segment 137.

[0318] The second fan-out line 132 provided in the embodiment of the present application is described below.

[0319] In some embodiments, see Figure 3 , the plurality of fan-out lines 130 further include a plurality of second fan-out lines 132, and the number of sub-extension segments 135 in the same second fan-out line 132 is greater than the number of sub-extension segments 135 in the same first fan-out line 131. For example, the number of sub-extension segments 135 in the same second fan-out line 132 may be 3, 4, or any number greater than 4, and the embodiment of the present application is described with the number of sub-extension segments 135 in the same second fan-out line 132 being 3.

[0320] For example, see Figure 3, the plurality of sub-extension segments 135 in the same second fan-out line 132 include a first sub-extension segment 1351, a second sub-extension segment 1352 and a third sub-extension segment 1353, and the third sub-extension segment 1353 is connected between the second sub-extension segment 1352 and the corresponding data line 110. For example, in the same second fan-out line 132, the signal of at least one gate line 120 adjacent to the third sub-extension segment 1353 is different from the signal of the gate line 120 adjacent to the second sub-extension segment 1352, which can reduce the influence of the at least one gate line 120 on the signal voltage of the second fan-out line 132 at the time of its signal jump, thereby improving the uniformity of the display brightness of the display panel 100. Its principle is similar to that of the first sub-extension segment 1351 and the second sub-extension segment 1352, and will not be repeated.

[0321] For example, see Figure 3 , the extension length of the third sub-extension segments 1353 in the plurality of second fan-out lines 132 gradually decreases along the first direction A, so that the third sub-extension segments 1353 in the plurality of second fan-out lines 132 are arranged more regularly, which can reduce the difficulty of arranging the third sub-extension segments 1353 in the plurality of second fan-out lines 132, and can also facilitate the connection of the third sub-extension segments 1353 in the plurality of second fan-out lines 132 with the corresponding data. For example, the extension length of the third sub-extension segments 1353 in the plurality of second fan-out lines 132 is from the display area 100a to the first non-display area 101b ( Figure 1 ) direction gradually decreases.

[0322] For example, see Figure 3 , the extension lengths of the first sub-extension segments 1351 in the multiple second fan-out lines 132 are equal, and / or, the extension lengths of the second sub-extension segments 1352 in the multiple second fan-out lines 132 are equal, so as to better reduce the difficulty of setting the first sub-extension segments 1351 and / or the second sub-extension segments 1352 in the multiple second fan-out lines 132, and / or, make the parasitic capacitance between the first sub-extension segment of each second fan-out line and the adjacent gate line equal or approximately equal, and make the parasitic capacitance between the second sub-extension segment of each second fan-out line and the adjacent gate line equal or approximately equal, so as to improve the uniformity of the display brightness of the display panel 100.

[0323] For example, see Figure 3 The extension lengths of the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same second fan-out line 132 are equal, thereby reducing the difficulty of setting the first sub-extension segment 1351 and the second sub-extension segment 1352 in the same second fan-out line 132, and / or making the parasitic capacitance between the first sub-extension segment and the adjacent gate line and the parasitic capacitance between the second sub-extension segment and the adjacent gate line equal or approximately equal, so as to improve the uniformity of the display brightness of the display panel 100.

[0324] For example, see Figure 3 The extension lengths of the first sub-extension segment 1351 in the second fan-out line 132 and the first sub-extension segment 1351 in the first fan-out line 131 are equal, which is conducive to reducing the difficulty of setting the first sub-extension segment 1351 in the first fan-out line 131 and the second fan-out line 132, and / or, making the parasitic capacitance between the first sub-extension segment 1351 in the second fan-out line 132 and the adjacent gate line, and the parasitic capacitance between the first sub-extension segment 1351 in the first fan-out line 131 and the adjacent gate line equal or approximately equal, so as to improve the uniformity of the display brightness of the display panel 100.

[0325] For example, see Figure 3 The third sub-extension segment 1353 extends along the second direction B, which can avoid the third sub-extension segment 1353 and the adjacent gate line 120 being too close along the first direction A, which is beneficial to reducing the parasitic capacitance between the third sub-extension segment 1353 and the adjacent gate line 120. In addition, the difficulty of setting the third sub-extension segment 1353 can be reduced.

[0326] The first sub-extension section 1351 of the first fan-out line 131 and the second sub-extension section 1351 of the second fan-out line 132 may extend in the same or different directions. The second sub-extension section 1352 of the first fan-out line 131 and the second sub-extension section 1352 of the second fan-out line 132 may extend in the same or different directions.

[0327] Exemplarily, the third sub-extension segments 1353 in the plurality of second fan-out lines 132 are arranged at equal intervals or unequal intervals along the first direction A, and / or, the first sub-extension segments 1351 in at least a portion of the adjacent second fan-out lines 132 are arranged at equal intervals or unequal intervals along the first direction A, and / or, the second sub-extension segments 1352 in at least a portion of the adjacent second fan-out lines 132 are arranged at equal intervals or unequal intervals along the first direction A, so that the sub-extension segments 135 in the plurality of second fan-out lines 132 are arranged in more ways and can be applied to more arrangement scenarios, and the principle has been explained and will not be repeated. Equally spaced arrangement is conducive to improving display effects and / or reducing design difficulty.

[0328] Exemplarily, the first sub-extension segments 1351 in at least a portion of the second fan-out lines 132 and the first sub-extension segments 1351 in at least a portion of the first fan-out lines 131 are arranged at equal or unequal intervals along the first direction A; and / or, the second sub-extension segments 1352 in at least a portion of the second fan-out lines 132 and the second sub-extension segments 1352 in at least a portion of the first fan-out lines 131 are arranged at equal or unequal intervals along the first direction A, so that the sub-extension segments 135 in at least a portion of the first fan-out lines 131 and the second fan-out lines 132 can be arranged in more ways and can be applicable to more arrangement scenarios. The principle has been explained and will not be repeated here.

[0329] For example, see Figure 3 The extension length of the sub-connection segment 134 in the second fan-out line 132 is equal to the extension length of the sub-connection segment 134 in the first fan-out line 131, thereby reducing the difficulty of setting the sub-connection segment 134 of the first fan-out line 131 and the second fan-out line 132.

[0330] For example, see Figure 3 , the extension length of the third sub-extension segment 1353 with the largest extension length among the plurality of second fan-out lines 132 is equal to the extension length of the first sub-extension segment 1351 among the first fan-out lines 131. The extension length of the third sub-extension segment 1353 with the largest extension length among the plurality of second fan-out lines 132 is equal to the extension length of the second sub-extension segment 1352 with the largest extension length among the plurality of first fan-out lines 131.

[0331] For example, see Figure 3 , the extension length of the third sub-extension segment 1353 with the largest extension length among the plurality of second fan-out lines 132 is equal to the extension length of the first sub-extension segment 1351 among the second fan-out lines 132. The extension length of the third sub-extension segment 1353 with the largest extension length among the plurality of second fan-out lines 132 is equal to the extension length of the second sub-extension segment 1352 among the second fan-out lines 132.

[0332] For example, see Figure 3 In the same second fan-out line 132, the sub-connection segment 134 includes a first sub-connection segment 1341 and a second sub-connection segment 1342. The first sub-connection segment 1341 is connected between the first sub-extension segment 1351 and the second sub-extension segment 1352. The second sub-connection segment 1342 is connected between the second sub-extension segment 1352 and the third sub-extension segment 1353. The extension length of the first sub-connection segment 1341 in the second fan-out line 132 is equal to the extension length of the second sub-connection segment 1342 in the second fan-out line 132, which helps to reduce the difficulty of setting the first sub-connection segment 1341 and the second sub-connection segment 1342 in the second fan-out line 132.

[0333] For example, see Figure 3 , the extension length of the second sub-extension segment 1352 in the same second fan-out line 132 is greater than or equal to the extension length of the third sub-extension segment 1353 .

[0334] For example, see Figure 3 In a portion of the second fan-out lines 132 , the extension lengths of the second sub-extension section 1352 and the third sub-extension section 1353 in the same second fan-out line 132 are equal.

[0335] For example, see Figure 3 In a portion of the second fan-out lines 132 , the extension length of the second sub-extension section 1352 in the same second fan-out line 132 is greater than the extension length of the third sub-extension section 1353 .

[0336] For example, see Figure 3 The difference in extension lengths of the third sub-extension segments 1353 of two adjacent second fan-out lines 132 is twice the second distance L2, thereby reducing the difficulty of setting the third sub-extension segments 1353 in each second fan-out line 132, and is also beneficial for connecting the second fan-out line 132 with the corresponding data line 110. The principle has been explained and will not be repeated here.

[0337] Exemplarily, the first sub-extension segments 1351 in at least a portion of the adjacent second fan-out lines 132 are partially opposite to each other along the first direction A and are partially misaligned; and / or, the second sub-extension segments 1352 in at least a portion of the adjacent second fan-out lines 132 are partially opposite to each other along the first direction A and are partially misaligned; the first sub-extension segments 1351 in at least a portion of the first fan-out lines 131 and the first sub-extension segments 1351 in at least a portion of the second fan-out lines 132 are partially opposite to each other along the first direction A and are partially misaligned; and / or , the second sub-extension segments 1352 in at least a part of the first fan-out lines 131 and the second sub-extension segments 1352 in at least a part of the second fan-out lines 132 are partially opposite to each other along the first direction A and are partially misaligned. This is conducive to setting a larger number of fan-out lines 130 and / or reducing the space occupied by the fan-out lines. It can also avoid mutual interference in the layout between the first sub-extension segments 1351 of adjacent fan-out lines 130 and between the second sub-extension segments 1352 of adjacent fan-out lines 130. The principle has been explained and will not be repeated here.

[0338] For example, see Figure 3In the multiple second fan-out lines 132 and / or the multiple first fan-out lines 131, the offset distances of adjacent first sub-extension segments 1351 are equal, so that the arrangement of the first sub-extension segments 1351 in the multiple second fan-out lines 132 and / or the multiple first fan-out lines 131 can be more regular, which is conducive to reducing the difficulty of setting the first sub-extension segments 1351 in the multiple second fan-out lines 132 and / or the multiple first fan-out lines 131.

[0339] For example, see Figure 3 Among the multiple second fan-out lines 132, the offset distances of adjacent second sub-extension segments 1352 are equal, so that the second sub-extension segments 1352 of the multiple second fan-out lines 132 can be arranged more regularly, which is conducive to reducing the difficulty of setting the second sub-extension segments 1352 of the multiple second fan-out lines 132.

[0340] Exemplarily, the first sub-connection segments 1341 in at least a portion of the adjacent second fan-out lines 132 are partially relative and partially staggered along the second direction B. This is conducive to setting a larger number of second fan-out lines 132 and / or reducing the space occupied by the fan-out lines. It can also avoid mutual interference in the layout of the first sub-connection segments 1341 of adjacent second fan-out lines 132. The principle has been explained and will not be repeated here.

[0341] Exemplarily, the second sub-connection segments 1342 in at least a portion of the adjacent second fan-out lines 132 are partially relative to each other and partially staggered along the second direction B. This is conducive to setting a larger number of second fan-out lines 132 and / or reducing the space occupied by the fan-out lines. It can also avoid mutual interference in the layout of the second sub-connection segments 1342 of adjacent second fan-out lines 132. The principle has been explained and will not be repeated here.

[0342] Exemplarily, among multiple second fan-out lines 132 and / or multiple first fan-out lines 131, the staggered distances of adjacent first sub-connection segments 1341 are equal; and / or, among multiple second fan-out lines 132, the staggered distances of adjacent second sub-connection segments 1342 are equal, which helps to reduce the difficulty of setting up the second fan-out lines 132 and / or the first fan-out lines 131. The principle has been explained and will not be repeated here.

[0343] Illustratively, the first sub-connection segments 1341 in at least some of the first fan-out lines 131 and the second sub-connection segments 1342 in at least some of the second fan-out lines 132 are partially opposite and partially misaligned along the second direction B, and the principle has been explained and will not be repeated here.

[0344] Illustratively, among the plurality of second fan-out lines 132 , the offset distance between adjacent second sub-extension segments 1352 is equal to the offset distance between adjacent first sub-extension segments 1351 , thereby facilitating reducing the difficulty of setting up the second fan-out lines 132 , the principle of which has been explained and will not be repeated here.

[0345] For example, see Figure 3 The second fan-out line 132 is connected to the corresponding data line 110 via a second electrical connection node 1362 (where a via hole may be provided), and the second fan-out line 132 ( Figure 3 The extension lengths of the plurality of sub-extension segments 135 in F1) are equal, so that the extension lengths of the plurality of sub-extension segments 135 in the second fan-out line 132 can be set shorter, so that the parasitic capacitances between the plurality of sub-extension segments 135 in the second fan-out line 132 and the corresponding adjacent gate lines 120 are smaller, which is beneficial to improving the uniformity of the display brightness of the display panel 100. Among all the sub-extension segments 135 of the second fan-out line 132, the extension length of the third sub-extension segment 1353 in the second fan-out line 132 corresponding to the second electrical connection node 1362 farthest from the first non-display area 101b along the first direction A is the largest, so that the extension lengths of the sub-extension segments 135 in all the second fan-out lines 132 are set shorter, which is beneficial to improving the uniformity of the display brightness of the display panel 100.

[0346] For example, see Figure 3 In the same second fan-out line 132, the distance between the third sub-extension segment 1353 and the first non-display area 101b along the first direction A is greater than the distance between the second sub-extension segment 1352 and the first non-display area 101b along the first direction A, and the distance between the second sub-extension segment 1352 and the first non-display area 101b along the first direction A is greater than the distance between the first sub-extension segment 1351 and the first non-display area 101b along the first direction A, thereby making the distance between the first sub-extension segment 1351 and the first non-display area 101b along the first direction A closer, which is beneficial to shortening the extension length of the auxiliary sub-connection segment 137, thereby reducing the mutual interference between the auxiliary sub-connection segment 137 and other signal lines, and can also reduce the difficulty of setting the auxiliary sub-connection segment 137.

[0347] For example, see Figure 3The first sub-extension segment 1351 of the second fan-out line 132 is located on a side of the first sub-extension segment 1351 of the first fan-out line 131 away from the first non-display area 101b, and the second sub-extension segment 1352 of the second fan-out line 132 is located on a side of the second sub-extension segment 1352 of the first fan-out line 131 away from the first non-display area 101b, so that the second fan-out line 132 with a longer total extension length along the second direction B is arranged on a side of the first fan-out line 131 away from the first non-display area 101b, which is beneficial to avoid the second fan-out line 132 and the first fan-out line 131 from crossing each other and causing layout interference.

[0348] For example, see Figure 3 The data line 110 electrically connected to the second fan-out line 132 is located between the data line 110 electrically connected to the first fan-out line 131 and the frame of the display panel 100 extending along the first direction A, which is equivalent to the data line 110 electrically connected to the second fan-out line 132 being located between the data line 110 electrically connected to the first fan-out line 131 and the non-display area 102b ( Figure 2 )between.

[0349] The auxiliary fan-out line 133 provided in the embodiment of the present application is described below.

[0350] In some embodiments, see Figure 2 The plurality of data lines 110 include a plurality of first data lines 111 located in the second display area 102 a , and the plurality of first data lines 111 are electrically connected to the plurality of first fan-out lines 131 correspondingly.

[0351] For example, see Figure 2 The first data line 111 is located in the first sub-region 102a1, the multiple data lines 110 also include multiple second data lines 112 located in the second sub-region 102a2, the multiple fan-out lines 130 include multiple auxiliary fan-out lines 133, and the multiple auxiliary fan-out lines 133 are electrically connected to the multiple second data lines 112 respectively. The same auxiliary fan-out line 133 includes a first sub-extension segment 1351, and the number of sub-extension segments 135 in the same auxiliary fan-out line 133 is less than the number of sub-extension segments 135 in the same first fan-out line 131, so that the number of sub-extension segments 135 in the same auxiliary fan-out line 133 is small, which can simplify the structure of the auxiliary fan-out line 133 and reduce the difficulty of preparing the same auxiliary fan-out line 133.

[0352] For example, the same auxiliary fan-out line 133 may include one sub-extension segment 135 .

[0353] For example, see Figure 2The first sub-extension segment 1351 of the auxiliary fan-out line 133 can extend along the second direction B, which can avoid the first sub-extension segment 1351 and the adjacent gate line 120 being too close along the first direction A, which is beneficial to reducing the parasitic capacitance between the first sub-extension segment 1351 and the adjacent gate line 120. In addition, the difficulty of setting the first sub-extension segment 1351 can be reduced.

[0354] Exemplarily, the first sub-extension segments 1351 in multiple auxiliary fan-out lines 133 are arranged at equal or unequal intervals along the first direction A, and / or, the first sub-extension segments 1351 in at least a part of the first fan-out lines 131 and the first sub-extension segments 1351 in at least a part of the auxiliary fan-out lines 133 are arranged at equal or unequal intervals along the first direction A, so that the first sub-extension segments 1351 can be arranged in more ways and can be applicable to more arrangement scenarios. The principle has been explained and will not be repeated here.

[0355] For example, see Figure 2 The extension length of the first sub-extension segment 1351 with the largest extension length among the multiple auxiliary fan-out lines 133 is equal to the extension length of the first sub-extension segment 1351 in the first fan-out line 131, so that the first sub-extension segment 1351 of each auxiliary fan-out line 133 is smaller, which is beneficial to reducing the parasitic capacitance between the first sub-extension segment 1351 of each auxiliary fan-out line 133 and the corresponding adjacent gate line 120, and is beneficial to improving the uniformity of the display brightness of the display panel 100.

[0356] For example, see Figure 2 , the distance between the first sub-extension segments 1351 in adjacent first fan-out lines 131 along the first direction A is equal to the distance between the first sub-extension segments 1351 in adjacent auxiliary fan-out lines 133 along the first direction A, so that the first sub-extension segments 1351 in the first fan-out lines 131 and the auxiliary fan-out lines 133 are arranged more regularly, which is conducive to reducing the difficulty of setting the first sub-extension segments 1351 in the first fan-out lines 131 and the auxiliary fan-out lines 133.

[0357] For example, see Figure 2 , the extension lengths of the first sub-extension segments 1351 of the plurality of auxiliary fan-out lines 133 gradually decrease along the first direction A, so that the first sub-extension segments 1351 of the plurality of auxiliary fan-out lines 133 are arranged more regularly, which can reduce the difficulty of arranging the first sub-extension segments 1351 in the plurality of auxiliary fan-out lines 133, and can also facilitate the connection of the first sub-extension segments 1351 in the plurality of auxiliary fan-out lines 133 with the corresponding second data lines 112. For example, the extension lengths of the first sub-extension segments 1351 of the plurality of auxiliary fan-out lines 133 gradually decrease along the direction from the display area 100a to the first non-display area 101b.

[0358] For example, see Figure 2 The first sub-extension section 1351 of the first fan-out line 131 is located on a side of the first sub-extension section 1351 of the auxiliary fan-out line 133 away from the first non-display area 101b, which helps to avoid the first fan-out line 131 and the auxiliary fan-out line 133 crossing each other and causing layout interference.

[0359] For example, see Figure 2 The difference in extension lengths of the first sub-extension segments 1351 of two adjacent auxiliary fan-out lines 133 is twice the second distance L2, thereby reducing the difficulty of setting the first sub-extension segments 1351 in each auxiliary fan-out line 133 and facilitating the connection of the auxiliary fan-out line 133 with the corresponding second data line 112.

[0360] In some embodiments, the fan-out lines 130 of two second display areas 102 a located on opposite sides of the first display area 101 a along the second direction B are symmetrically arranged, thereby reducing the difficulty of arranging the fan-out lines 130 .

[0361] In some embodiments, the plurality of data lines 110 further include a third data line 113 located in the first display area 101a, and the third data line 113 is connected to a binding pin 162 ( Figure 1 ) electrical connection.

[0362] The auxiliary sub-connection segment 137 provided in the embodiment of the present application is described below.

[0363] See also Figure 2 In the same fan-out line 130, the fan-out line 130 further includes an auxiliary sub-connection segment 137, and the auxiliary sub-connection segment 137 is electrically connected to the first sub-extension segment 1351 and the binding pin 162 of the binding area ( Figure 1 ). Among them, the binding pin 162 ( Figure 1 ) can be used with the driver chip 161 ( Figure 1 ) electrical connection.

[0364] Exemplarily, the plurality of auxiliary sub-connecting segments 137 are arranged along the second direction B, and the plurality of auxiliary sub-connecting segments 137 extend along the first direction A.

[0365] Exemplarily, in at least a portion of the fan-out lines 130, the distance between two adjacent auxiliary sub-connection segments 137 is an integer multiple of the second distance L2, thereby making it simpler to set the distances of the multiple auxiliary sub-connection segments 137 along the second direction B, thereby reducing the difficulty of arranging the auxiliary sub-connection segments 137 and making the arrangement of the auxiliary sub-connection segments 137 along the second direction B more regular.

[0366] In some embodiments, the display panel 100 includes a plurality of conductive layers on a substrate, an insulating layer is disposed between two adjacent conductive layers, and at least one of the plurality of conductive layers may be a metal layer. Any one of the data line 110, the fan-out line 130, and the gate line 120 may be disposed on at least one of the plurality of conductive layers.

[0367] Exemplarily, the data line 110 and the sub-extension segment 135 are arranged in different layers, and adjacent data lines 110 and sub-extension segments 135 are connected through vias. The data line 110 and the sub-extension segment 135 are located in different conductive layers, thereby preventing the two from intersecting and short-circuiting.

[0368] Exemplarily, the conductive layer (eg, a metal layer or a light-transmitting conductive layer) where the data line 110 is located is located on a side of the conductive layer (eg, a metal layer or a light-transmitting conductive layer) where the sub-extension segment 135 is located that is away from or close to the substrate.

[0369] Exemplarily, the sub-connection segment 134 and the sub-extension segment 135 are arranged on different layers, and adjacent sub-connection segments 134 and sub-extension segments 135 are connected through vias, which is beneficial to improve the setting flexibility of the sub-connection segment 134 and the sub-extension segment 135 and avoid the fan-out line 130 intersecting with the adjacent signal line and short-circuiting.

[0370] Exemplarily, the conductive layer (eg, may include a metal layer or a light-transmitting conductive layer) where the sub-connecting segment 134 is located is located on a side of the conductive layer where the sub-extending segment 135 is located that is away from or close to the substrate.

[0371] Exemplarily, the sub-connection segment 134 and the data line 110 are arranged in the same layer or in different layers. There are many ways to arrange the sub-connection segment 134, and it can be applied in many scenarios.

[0372] Exemplarily, the sub-extension segment 135 and part or all of the gate lines 120 are arranged in different layers. Exemplarily, the sub-extension segment 135 and part or all of the gate lines 120 are arranged in the same layer. Exemplarily, the sub-connection segment 134 and the gate lines 120 are arranged in different layers. Exemplarily, the data lines 110 and the gate lines 120 are arranged in different layers. For example, the data lines 110 and the gate lines 120 are arranged in an insulated and cross-arranged manner.

[0373] Multiple structures arranged on the same layer can be obtained by patterning the same film layer to simplify the process.

[0374] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0375] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0376] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; A plurality of data lines are arranged on the substrate; A plurality of gate lines are disposed on the substrate; A plurality of fan-out lines are arranged on the substrate, and the plurality of fan-out lines are electrically connected to at least a portion of the data lines; Among them, in at least a part of the fan-out lines, in the same fan-out line, the fan-out line includes a sub-connection segment and a plurality of sub-extension segments, two adjacent sub-extension segments are connected by the sub-connection segment, and the plurality of sub-extension segments include a first sub-extension segment and a second sub-extension segment. In the same refresh cycle, at least one voltage jump moment of a pulse of a signal on at least one gate line adjacent to the first sub-extension segment is different from the voltage jump moment of a pulse of a signal on the gate line adjacent to the second sub-extension segment, and / or, the amplitude polarity of a pulse of a signal on at least one gate line adjacent to the first sub-extension segment is different from the amplitude polarity of a pulse of a signal on the gate line adjacent to the second sub-extension segment.

2. The display panel according to claim 1, characterized in that: The orthographic projection of the first sub-extension segment on the substrate is a first orthographic projection, the orthographic projection of the second sub-extension segment on the substrate is a second orthographic projection, and the orthographic projection of the gate line on the substrate is a third orthographic projection. In the first sub-extension segment and the second sub-extension segment in the same fan-out line, at least two third orthographic projections are arranged between the first orthographic projection and the second orthographic projection.

3. The display panel according to claim 2, characterized in that: The plurality of gate lines include at least one of a first gate line and a second gate line, and at least one of a third gate line and a fourth gate line. In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is adjacent to the first gate line; the second sub-extension segment is adjacent to the third gate line, and a signal of the first gate line adjacent to the first sub-extension segment is different from a signal of the third gate line adjacent to the second sub-extension segment; Alternatively, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is adjacent to the first gate line and the second gate line respectively, and the first orthographic projection is located between the orthographic projection of the first gate line adjacent to the first sub-extension segment on the substrate and the orthographic projection of the second gate line adjacent to the first sub-extension segment on the substrate; the second sub-extension segment is adjacent to the third gate line and the fourth gate line respectively, and the second orthographic projection is located between the orthographic projection of the third gate line adjacent to the second sub-extension segment on the substrate and the orthographic projection of the fourth gate line adjacent to the second sub-extension segment on the substrate; the signal of the first gate line adjacent to the first sub-extension segment is different from the signals of the third gate line and the fourth gate line adjacent to the second sub-extension segment; the signal of the second gate line adjacent to the first sub-extension segment is different from the signals of the third gate line and the fourth gate line adjacent to the second sub-extension segment.

4. The display panel according to claim 3, characterized in that: The display panel includes a plurality of pixel circuits arranged in an array, the gate lines extend along a row direction of the array, and the data lines extend along a column direction of the array; In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first orthographic projection is located between orthographic projections of the first gate line and the second gate line adjacent to the corresponding pixel circuit in the same row on the substrate; the second orthographic projection is located between orthographic projections of the third gate line and the fourth gate line adjacent to the corresponding pixel circuit in the same row on the substrate; Preferably, the column direction is parallel to the first direction, and the row direction is parallel to the second direction.

5. The display panel according to claim 4, characterized in that: The orthographic projections of the first sub-extension segment and the second sub-extension segment in the same fan-out line on the substrate are located between the orthographic projections of the first gate line, the second gate line, the third gate line and the fourth gate line electrically connected to the corresponding same row of pixel circuits on the substrate; Alternatively, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first gate line and the second gate line adjacent to the first sub-extension segment, and the third gate line and the fourth gate line adjacent to the second sub-extension segment are electrically connected to the corresponding pixel circuits in the same row.

6. The display panel according to claim 4, characterized in that: In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first orthographic projection is located between the orthographic projections of the first gate line and the second gate line adjacent to each other and electrically connected to a corresponding row of pixel circuits on the substrate, and the second orthographic projection is located between the orthographic projections of the third gate line and the fourth gate line adjacent to each other and electrically connected to a corresponding other row of pixel circuits on the substrate.

7. The display panel according to claim 3, characterized in that: The display panel includes a plurality of pixel circuits arranged in an array, the gate lines extend along a row direction of the array, and the data lines extend along a column direction of the array; In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first orthographic projection is located between the orthographic projections of the first gate line and the second gate line adjacent to the first sub-extension segment on the substrate; the second orthographic projection is located between the orthographic projections of the third gate line and the fourth gate line adjacent to the second sub-extension segment on the substrate; The orthographic projections of the second gate line adjacent to the first sub-extension segment and the third gate line adjacent to the second sub-extension segment on the substrate are located between the orthographic projections of the first gate line adjacent to the first sub-extension segment and the fourth gate line adjacent to the second sub-extension segment on the substrate; the second gate line adjacent to the first sub-extension segment and the third gate line adjacent to the second sub-extension segment are electrically connected to the same row of pixel circuits; the first gate line adjacent to the first sub-extension segment and the fourth gate line adjacent to the second sub-extension segment are electrically connected to different rows of pixel circuits; Preferably, the column direction is parallel to the first direction, and the row direction is parallel to the second direction.

8. The display panel according to claim 3, characterized in that: The signals of any two of the first gate line, the second gate line, the third gate line and the fourth gate line are different; And / or, the first gate line, the second gate line, the third gate line and the fourth gate line are used to transmit signals of different functions; And / or, the display panel includes a plurality of pixel circuits arranged in an array, the pixel circuits include a plurality of transistors with different functions, the gate lines extend along the row direction of the array, and the data lines extend along the column direction of the array; the first gate line, the second gate line, the third gate line and the fourth gate line are electrically connected to the transistors with different functions; And / or, any two of the first gate line, the second gate line, the third gate line and the fourth gate line are alternately arranged along the first direction.

9. The display panel according to claim 3, characterized in that: The display panel includes one or more gate driving circuits, wherein the gate driving circuit includes a cascaded multi-stage shift register electrically connected to the corresponding gate line. In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first gate line and the second gate line adjacent to the first sub-extension segment are electrically connected to different shift registers; the third gate line and the fourth gate line adjacent to the second sub-extension segment are electrically connected to different shift registers; the shift register electrically connected to the first gate line and the second gate line adjacent to the first sub-extension segment is different from the shift register electrically connected to the third gate line and the fourth gate line adjacent to the second sub-extension segment.

10. The display panel according to claim 2, characterized in that: The plurality of gate lines include a plurality of gate line groups, each of the gate line groups includes a first gate line and a second gate line, In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is adjacent to the first gate line and the second gate line in a corresponding gate line group, and the first orthographic projection is located between the orthographic projection of the first gate line and the orthographic projection of the second gate line in the corresponding gate line group on the substrate; the second sub-extension segment is adjacent to the first gate line and the second gate line in another corresponding gate line group, and the second orthographic projection is located between the orthographic projection of the first gate line and the orthographic projection of the second gate line in another corresponding gate line group on the substrate.

11. The display panel according to claim 10, characterized in that: In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the signal timing of the first gate line adjacent to the first sub-extension segment is different from the signal timing of the first gate line adjacent to the second sub-extension segment; the signal timing of the second gate line adjacent to the first sub-extension segment is different from the signal timing of the second gate line adjacent to the second sub-extension segment; And / or, the first gate line and the second gate line are used to transmit signals of different functions; And / or, the first gate lines and the second gate lines are alternately arranged along the first direction.

12. The display panel according to claim 10, characterized in that: The display panel includes a plurality of pixel circuits arranged in an array, the gate lines extend along a row direction of the array, and the data lines extend along a column direction of the array; In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first gate line and the second gate line in a gate line group adjacent to the first sub-extension segment are electrically connected to the pixel circuits of different rows; and / or, the first gate line and the second gate line in another gate line group adjacent to the second sub-extension segment are electrically connected to the pixel circuits of different rows; Preferably, the column direction is parallel to the first direction, and the row direction is parallel to the second direction.

13. The display panel according to claim 10, characterized in that: The display panel includes a first gate driving circuit, wherein the first gate driving circuit includes a cascaded multi-stage first shift register electrically connected to the corresponding first gate line. In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first gate line adjacent to the first sub-extension segment and the first gate line adjacent to the second sub-extension segment are electrically connected to different output ends of the first shift register; The display panel includes a second gate driving circuit, wherein the second gate driving circuit includes a cascaded multi-stage second shift register electrically connected to the corresponding second gate line; In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the second gate line adjacent to the first sub-extension segment and the second gate line adjacent to the second sub-extension segment are electrically connected to different output ends of the second shift register.

14. The display panel according to claim 13, characterized in that: The output end of each stage of the first shift register is electrically connected to N first gate lines correspondingly, where N is a positive integer; The output end of each stage of the second shift register is electrically connected to M second gate lines correspondingly, where M is a positive integer; In the first sub-extension segment and the second sub-extension segment in the same fan-out line, at least K orthographic projections of the first gate line on the substrate are arranged between the first orthographic projection and the second orthographic projection, and / or at least K orthographic projections of the second gate line on the substrate are arranged between the first orthographic projection and the second orthographic projection, K=max(M,N); Preferably, at least one of N and M is 1, and / or at least one of N and M is greater than or equal to 2.

15. The display panel according to claim 13, characterized in that: The output end of each stage of the first shift register is electrically connected to N first gate lines correspondingly, where N is a positive integer; The output end of each stage of the second shift register is electrically connected to M second gate lines correspondingly, where M is a positive integer; In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the length of the sub-connection segment connected between the first sub-extension segment and the second sub-extension segment along the first direction is greater than or equal to K times the first distance, and / or the distance between the first sub-extension segment and the second sub-extension segment along the first direction is greater than or equal to K times the first distance, K=max(M, N), and the first distance is the distance between two adjacent first gate lines along the first direction; Preferably, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the length of the sub-connection segment connecting the first sub-extension segment and the second sub-extension segment along the first direction is an integer multiple of the first distance; and / or, the distance between the first sub-extension segment and the second sub-extension segment along the first direction is an integer multiple of the first distance; and / or, Among at least a portion of the adjacent fan-out lines, the distance between adjacent first sub-extension segments along the first direction is an integer multiple of the first distance; and / or, the distance between adjacent second sub-extension segments along the first direction is an integer multiple of the first distance; and / or, the distance between adjacent first sub-extension segments along the first direction is equal to the distance between adjacent second sub-extension segments along the first direction; and / or, the distance between adjacent first sub-extension segments along the first direction is less than or equal to the length of the sub-connection segment along the first direction; and / or, the distance between adjacent second sub-extension segments along the first direction is less than or equal to the length of the sub-connection segment along the first direction; Preferably, at least one of N and M is 1, and / or at least one of N and M is greater than or equal to 2.

16. The display panel according to any one of claims 10 to 15, characterized in that: The display panel includes a plurality of pixel circuits arranged in an array, and the pixel circuits include a plurality of transistors with different functions. The first gate lines in different gate line groups are electrically connected to transistors with the same function in pixel circuits of different rows; and / or the second gate lines in different gate line groups are electrically connected to transistors with the same function in pixel circuits of different rows; And / or, the first gate line and the second gate line are electrically connected to transistors with different functions in the pixel circuit; Preferably, the pixel circuit comprises: a driving transistor and a first initialization transistor, the first initialization transistor is connected between a first initialization signal line and a first electrode or a second electrode of the driving transistor, and the first gate line is electrically connected to a gate of the first initialization transistor; And / or, the pixel circuit comprises: a second initialization transistor, the second initialization transistor is connected between a second initialization signal line and a gate or a second electrode of the driving transistor, and the second gate line is electrically connected to the gate of the second initialization transistor; And / or, the pixel circuit includes: a third initialization transistor, the third initialization transistor is connected between a third initialization signal line and a first electrode of the light emitting unit, and the first gate line is electrically connected to a gate of the third initialization transistor.

17. The display panel according to claim 13, characterized in that: The first gate lines in different gate line groups are used to transmit signals with the same function; the second gate lines in different gate line groups are used to transmit signals with the same function; The output end of each stage of the first shift register is electrically connected to N first gate lines correspondingly, where N is a positive integer; The output end of each stage of the second shift register is electrically connected to M second gate lines correspondingly, where M is a positive integer; In the first sub-extension segment and the second sub-extension segment in the same fan-out line, the length of the sub-connection segment connected between adjacent first sub-extension segments and second sub-extension segments along the first direction is greater than or equal to K times the first distance, K=max(M, N), and the first distance is the distance between two adjacent first gate lines along the first direction; the data line extends along the first direction; At least one of N and M is greater than or equal to 2; Preferably, the display panel comprises a plurality of pixel circuits arranged in an array, the gate lines extend along a row direction of the array, and the data lines extend along a column direction of the array; the column direction is parallel to the first direction, and the row direction is parallel to the second direction; The output end of each stage of the first shift register is electrically connected to the N rows of pixel circuits via the first gate line; The output end of each stage of the second shift register is electrically connected to the M rows of pixel circuits via the second gate line.

18. The display panel according to claim 1, characterized in that: The plurality of fan-out lines include a plurality of first fan-out lines, and the plurality of sub-extension segments in the same first fan-out line include the first sub-extension segment and the second sub-extension segment; The extension lengths of the second sub-extension segments in the plurality of first fan-out lines gradually decrease along the first direction; and / or, the extension lengths of the first sub-extension segments in the plurality of first fan-out lines are equal; and / or, the extension lengths of the sub-connection segments in the plurality of first fan-out lines are equal; Preferably, the second sub-extension segments in the plurality of first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the first sub-extension segments in at least part of the adjacent first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the distance between the first sub-extension segments in two adjacent first fan-out lines is less than or equal to the distance between the first sub-extension segment and the second sub-extension segment in the same first fan-out line along the first direction; and / or, the distance between the first sub-extension segments in two adjacent first fan-out lines is less than or equal to the extension length of the sub-connection segment; and / or, the distance between the second sub-extension segments in two adjacent first fan-out lines is less than or equal to the distance between the first sub-extension segment and the second sub-extension segment in the same first fan-out line along the first direction; and / or, the distance between the second sub-extension segments in two adjacent first fan-out lines is less than or equal to the extension length of the sub-connection segment; and / or, the distance between the first sub-extension segments in two adjacent first fan-out lines is equal to the distance between the second sub-extension segments in two adjacent first fan-out lines; Preferably, the extension length of the second sub-extension segment with the largest extension length among the plurality of first fan-out lines is equal to the extension length of the first sub-extension segment among the plurality of first fan-out lines; Preferably, the first sub-extension segments in at least a portion of adjacent first fan-out lines are partially opposite to each other and partially staggered along the first direction; and / or the sub-connection segments in at least a portion of adjacent first fan-out lines are partially opposite to each other and partially staggered along the second direction; Preferably, in the plurality of first fan-out lines, the offset distances of adjacent first sub-extension segments are equal; and / or, in the plurality of first fan-out lines, the offset distances of adjacent sub-connection segments are equal; Preferably, in the same fan-out line, the second sub-extension segment is connected between the first sub-extension segment and the corresponding data line; Preferably, the display panel comprises a display area and a first non-display area, the first non-display area is located on one side of the display area along a first direction, the data line, the gate line and the fan-out line are at least partially located in the display area; the data line extends along the first direction; The extension length of the second sub-extension segment in the plurality of first fan-out lines gradually decreases along the direction from the display area to the first non-display area; and / or, the first fan-out line is connected to the corresponding data line via a first electrical connection node, and the extension lengths of the plurality of sub-extension segments in the first fan-out line corresponding to the first electrical connection node farthest from the first non-display area along the first direction are equal, and / or, the extension length of the second sub-extension segment is the largest; Preferably, the first non-display area includes a binding area, and the binding pins of the binding area are electrically connected to the fan-out line; Preferably, the difference between the extension lengths of the second sub-extension sections of two adjacent first fan-out lines is twice the second distance; Preferably, the extension length of the second sub-extension segment with the smallest extension length among the plurality of first fan-out lines is greater than or equal to twice the second distance; Preferably, the distance between every two adjacent data lines is the same and is the second distance; Alternatively, among the three adjacent data lines, the distance between the data line located in the middle and the data line located on one side is different from the distance between the data line located in the middle and the data line located on the other side; half of the distance between the data line located on one side and the data line located on the other side is the second distance; Preferably, in the same first fan-out line, a distance between the second sub-extension segment and the first non-display area along the first direction is greater than a distance between the first sub-extension segment and the first non-display area along the first direction.

19. The display panel according to claim 18, characterized in that: The plurality of fan-out lines further include a plurality of second fan-out lines, the number of the sub-extension segments in the same second fan-out line is greater than the number of the sub-extension segments in the same first fan-out line; the plurality of sub-extension segments in the same second fan-out line include the first sub-extension segment, the second sub-extension segment and a third sub-extension segment, the third sub-extension segment being connected between the second sub-extension segment and the corresponding data line; Preferably, in the same second fan-out line, a signal of at least one of the gate lines adjacent to the third sub-extension segment is different from a signal of the gate line adjacent to the second sub-extension segment; Preferably, the extension length of the third sub-extension segment in the plurality of second fan-out lines gradually decreases along the first direction; and / or, the extension lengths of the first sub-extension segments in the plurality of second fan-out lines are equal; and / or, the extension lengths of the second sub-extension segments in the plurality of second fan-out lines are equal; and / or, the extension lengths of the first sub-extension segment and the second sub-extension segment in the same second fan-out line are equal; and / or, the extension lengths of the first sub-extension segment in the second fan-out line and the first sub-extension segment in the first fan-out line are equal; Preferably, the third sub-extension segments in the plurality of second fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the first sub-extension segments in at least a portion of the adjacent second fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the second sub-extension segments in at least a portion of the adjacent second fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the first sub-extension segments in at least a portion of the second fan-out lines and the first sub-extension segments in at least a portion of the first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the second sub-extension segments in at least a portion of the second fan-out lines and at least a portion of the first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction. The second sub-extension segments in the divided number of the first fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the extension length of the sub-connection segment in the second fan-out line is equal to the extension length of the sub-connection segment in the first fan-out line; and / or, the extension length of the third sub-extension segment with the largest extension length among the plurality of second fan-out lines is equal to the extension length of the first sub-extension segment in the first fan-out line; and / or, the extension length of the first sub-connection segment in the second fan-out line is equal to the extension length of the second sub-connection segment in the second fan-out line; the first sub-connection segment is connected between the first sub-extension segment and the second sub-extension segment, and the second sub-connection segment is connected between the second sub-extension segment and the third sub-extension segment, Preferably, the extension length of the third sub-extension segments in the plurality of second fan-out lines gradually decreases along the direction from the display area to the first non-display area; Preferably, the extension length of the second sub-extension segment in the same second fan-out line is greater than or equal to the extension length of the third sub-extension segment; and / or, in a part of the second fan-out lines, the extension lengths of the second sub-extension segment and the third sub-extension segment in the same second fan-out line are equal; and / or, in a part of the second fan-out lines, the extension length of the second sub-extension segment in the same second fan-out line is greater than the extension length of the third sub-extension segment; Preferably, the difference between the extension lengths of the third sub-extension sections of two adjacent second fan-out lines is twice the second distance; Preferably, the first sub-extension segments in at least a portion of adjacent second fan-out lines are partially opposite to each other and partially staggered along the first direction; and / or, the second sub-extension segments in at least a portion of adjacent second fan-out lines are partially opposite to each other and partially staggered along the first direction; the first sub-extension segments in at least a portion of the first fan-out lines are partially opposite to the first sub-extension segments in at least a portion of the second fan-out lines and partially staggered along the first direction; and / or, the second sub-extension segments in at least a portion of the first fan-out lines are partially opposite to the second sub-extension segments in at least a portion of the second fan-out lines and partially staggered along the first direction; and / or, among the multiple second fan-out lines and / or the multiple first fan-out lines, the staggered distances of adjacent first sub-extension segments are equal; and / or, among the multiple second fan-out lines, the adjacent second sub-extension segments The dislocation distances of the first sub-connection segments are equal; and / or, the first sub-connection segments in at least a portion of the adjacent second fan-out lines are partially opposite to each other along the second direction and are partially dislocated; and / or, the second sub-connection segments in at least a portion of the adjacent second fan-out lines are partially opposite to each other along the second direction and are partially dislocated; and / or, in the plurality of second fan-out lines and / or the plurality of first fan-out lines, the dislocation distances of the adjacent first sub-connection segments are equal; and / or, in the plurality of second fan-out lines, the dislocation distances of the adjacent second sub-connection segments are equal; and / or, in at least a portion of the first fan-out lines, the first sub-connection segments are partially opposite to each other and are partially dislocated with the second sub-connection segments in at least a portion of the second fan-out lines along the second direction; and / or, in the plurality of second fan-out lines, the dislocation distances of the adjacent second sub-extension segments are equal to the dislocation distances of the adjacent first sub-extension segments; Preferably, the second fan-out line is connected to the corresponding data line via a second electrical connection node, the extension lengths of a plurality of sub-extension segments in the second fan-out line corresponding to the second electrical connection node farthest from the first non-display area along the first direction are equal, and / or the extension length of the third sub-extension segment is the largest; Preferably, in the same second fan-out line, the distance between the third sub-extension segment and the first non-display area along the first direction is greater than the distance between the second sub-extension segment and the first non-display area along the first direction; the distance between the second sub-extension segment and the first non-display area along the first direction is greater than the distance between the first sub-extension segment and the first non-display area along the first direction; Preferably, the first sub-extension section of the second fan-out line is located at a side of the first sub-extension section of the first fan-out line away from the first non-display area; the second sub-extension section of the second fan-out line is located at a side of the second sub-extension section of the first fan-out line away from the first non-display area; Preferably, the data line electrically connected to the second fan-out line is located between the data line electrically connected to the first fan-out line and a frame of the display panel extending along the first direction.

20. The display panel according to claim 18, characterized in that: The display panel includes a first display area and a second display area, the second display area is located at two opposite sides of the first display area along a second direction, the plurality of data lines include a plurality of first data lines located in the second display area, and the plurality of first data lines are electrically connected to the plurality of first fan-out lines accordingly; Preferably, the second display area includes a first sub-area and a second sub-area, the first sub-area is located at a side of the second sub-area away from the first display area, and the first data line is located in the first sub-area; the plurality of data lines further include a plurality of second data lines located in the second sub-area, the plurality of fan-out lines include a plurality of auxiliary fan-out lines, and the plurality of auxiliary fan-out lines are electrically connected to the plurality of second data lines accordingly; Preferably, the same auxiliary fan-out line includes a first sub-extension segment, and the number of the sub-extension segments in the same auxiliary fan-out line is less than the number of the sub-extension segments in the same first fan-out line; The first sub-extension segments in the plurality of auxiliary fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; and / or, the first sub-extension segments in at least a portion of the first fan-out lines and the first sub-extension segments in at least a portion of the auxiliary fan-out lines are arranged at equal or unequal intervals along the first direction and extend along the second direction; Preferably, the extension length of the first sub-extension segment with the largest extension length among the multiple auxiliary fan-out lines is equal to the extension length of the first sub-extension segment in the first fan-out line; and / or, the distance between the first sub-extension segments in adjacent first fan-out lines along the first direction is equal to the distance between the first sub-extension segments in adjacent auxiliary fan-out lines along the first direction; Preferably, the extension length of the first sub-extension sections of the plurality of auxiliary fan-out lines gradually decreases along the first direction; Preferably, the extension length of the first sub-extension segments of the plurality of auxiliary fan-out lines gradually decreases along the direction from the display area to the first non-display area; Preferably, the first sub-extension section of the first fan-out line is located on a side of the first sub-extension section of the auxiliary fan-out line away from the first non-display area; Preferably, the difference between the extension lengths of the first sub-extension sections of two adjacent auxiliary fan-out lines is twice the second distance; Preferably, the fan-out lines of two second display areas located on opposite sides of the first display area along the second direction are symmetrically arranged; Preferably, the plurality of data lines further include a third data line located in the first display area, and the third data line is electrically connected to a binding pin of the binding area; Preferably, in the same fan-out line, the fan-out line further comprises an auxiliary sub-connection segment electrically connected between the first sub-extension segment and the binding pin of the binding area of ​​the display panel; Preferably, the plurality of auxiliary sub-connection segments are arranged along the second direction and extend along the first direction; Preferably, in at least a portion of the fan-out lines, the distance between two adjacent auxiliary sub-connection segments is an integer multiple of the second distance.

21. The display panel according to claim 1, characterized in that: The extension length of the first sub-extension section in the same fan-out line is less than, greater than, or equal to the extension length of the second sub-extension section; and / or, in a part of the fan-out lines, the extension lengths of the first sub-extension section and the second sub-extension section in the same fan-out line are equal; and / or, in a part of the fan-out lines, an extension length of the first sub-extension section in the same fan-out line is greater than an extension length of the second sub-extension section; and / or, in at least a part of the fan-out lines, the number of the sub-extension segments in the same fan-out line is at least 3; And / or, the plurality of data lines extend along a first direction and are arranged along a second direction, and the first direction and the second direction intersect; And / or, the plurality of gate lines are arranged along the first direction and extend along the second direction; and / or, in the same fan-out line, the extension directions of the adjacent sub-connection segments and the sub-extension segments intersect; and / or, the sub-extension section extends along the second direction; And / or, the sub-connection segment extends along the first direction; and / or, the extension direction of the gate line intersects with the extension direction of the sub-connection segment; And / or, the display panel comprises a display area and a first non-display area, the first non-display area is located on one side of the display area along a first direction, the data line, the gate line and the fan-out line are at least partially located in the display area; the data line extends along the first direction; the first non-display area comprises a binding area, and the binding pins of the binding area are electrically connected to the fan-out line; in at least a part of the fan-out lines, the farther the distance between the electrical connection node between the fan-out line and the corresponding data line and the first non-display area along the first direction, the more the number of sub-extension segments in the fan-out line is, the more the number of sub-connection segments in the fan-out line is, and the greater the sum of the extension lengths of the sub-extension segments in the fan-out line is; And / or, the data lines and the sub-extension sections are arranged in different layers; adjacent data lines and sub-extension sections are connected through vias; And / or, the conductive layer where the data line is located is located on a side of the conductive layer where the sub-extension segment is located that is away from or close to the substrate; an insulating layer is provided between the conductive layer where the data line is located and the conductive layer where the sub-extension segment is located; And / or, the sub-connection segments and the sub-extension segments are arranged in different layers; adjacent sub-connection segments and sub-extension segments are connected via vias; And / or, the conductive layer where the sub-connecting segment is located is located on a side of the conductive layer where the sub-extension segment is located that is away from or close to the substrate; an insulating layer is provided between the conductive layer where the sub-connecting segment is located and the conductive layer where the sub-extension segment is located; And / or, the sub-connection segment and the data line are arranged in the same layer or in different layers; and / or, in the same refresh cycle, the first voltage jump time of the pulse of the signal on at least one of the gate lines adjacent to the first sub-extension segment is different from the voltage jump time of the pulse of the signal on the gate line adjacent to the second sub-extension segment; and / or, in the same refresh cycle, in the same fan-out line, a pulse of a signal on at least one of the gate lines adjacent to the first sub-extension segment does not overlap with a pulse of a signal on the gate line adjacent to the second sub-extension segment; and / or, in the same refresh cycle, in the same fan-out line, a pulse of a signal on at least one of the gate lines adjacent to the first sub-extension segment is not synchronized with a pulse of a signal on the gate line adjacent to the second sub-extension segment; and / or, in the same refresh cycle, in the same fan-out line, the moment when the pulse of the signal on at least one of the gate lines adjacent to the first sub-extension segment jumps to its own valid level is different from the moment when the pulse of the signal on the gate line adjacent to the second sub-extension segment jumps to its own valid level; And / or, within the same refresh cycle, in the same fan-out line, the moment when the pulse of the signal on each gate line adjacent to the first sub-extension segment jumps to its own valid level is different from the moment when the pulse of the signal on the gate line adjacent to the second sub-extension segment jumps to its own valid level.

22. The display panel according to claim 1, characterized in that: The display panel includes a plurality of pixel circuits arranged in an array, and the pixel circuit includes a plurality of transistors with different functions; Preferably, the plurality of gate lines include a first scan line, the plurality of transistors include a driving transistor and a first initialization transistor, the first initialization transistor is connected between a first initialization signal line and a first electrode or a second electrode of the driving transistor, and the first scan line is electrically connected to a gate of the first initialization transistor; Preferably, the plurality of gate lines include a second scan line, the plurality of transistors include a second initialization transistor, the second initialization transistor is connected between the second initialization signal line and the gate or the second electrode of the driving transistor, and the second scan line is electrically connected to the gate of the second initialization transistor; Preferably, the plurality of transistors include a third initialization transistor, the third initialization transistor is connected between a third initialization signal line and a first electrode of the light emitting unit, and the first scan line is electrically connected to a gate of the third initialization transistor; Preferably, the plurality of gate lines include a third scan line, the plurality of transistors include a write transistor, the write transistor is connected between the data line and the first electrode of the drive transistor; the third scan line is electrically connected to the gate of the write transistor; Preferably, the plurality of gate lines include a fourth scan line, the plurality of transistors include a threshold compensation transistor, the threshold compensation transistor is connected between the gate and the second electrode of the driving transistor; the fourth scan line is electrically connected to the gate of the threshold compensation transistor; Preferably, the plurality of gate lines include a light emitting control line, the plurality of transistors include a first light emitting control transistor and / or a second light emitting control transistor, the first light emitting control transistor is connected between a first power line and a first electrode of the driving transistor, the second light emitting control transistor is connected between a second electrode of the driving transistor and a first electrode of the light emitting unit, and the light emitting control line is electrically connected to a gate of the corresponding first light emitting control transistor and / or a gate of the corresponding second light emitting control transistor; Preferably, the second scan line, the third scan line, the fourth scan line, the light emitting control line, and the first scan line electrically connected to the pixel circuits in the same row are arranged in sequence along the first direction; Preferably, in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is located between two adjacent ones of the second scan line, the third scan line, the fourth scan line, the light emitting control line, and the first scan line; and the second sub-extension segment is located between another two adjacent ones of the second scan line, the third scan line, the fourth scan line, the light emitting control line, and the first scan line; Alternatively, the display panel includes one or more gate driving circuits, the gate driving circuit includes a cascaded multi-stage shift register, which is electrically connected to the corresponding gate line; in the first sub-extension segment and the second sub-extension segment in the same fan-out line, the first sub-extension segment is located between two adjacent ones of the second scan line, the third scan line, the fourth scan line, the light emitting control line, and the first scan line; the gate lines adjacent to the first sub-extension segment and the second sub-extension segment have the same corresponding functions, different signal timings, and are electrically connected to different shift registers; Preferably, the shift register electrically connected to the same first scan line is electrically connected to one or at least two of the first scan lines; the shift register electrically connected to the same second scan line is electrically connected to one or at least two of the second scan lines; the shift register electrically connected to the same third scan line is electrically connected to one or at least two of the third scan lines; the shift register electrically connected to the same fourth scan line is electrically connected to one or at least two of the fourth scan lines; and the shift register electrically connected to the same light-emitting control line is electrically connected to one or at least two of the light-emitting control lines.

23. A display panel, characterized in that: The display panel comprises: substrate; A plurality of data lines are arranged on the substrate; A plurality of gate lines are disposed on the substrate; A plurality of fan-out lines are arranged on the substrate, and the plurality of fan-out lines are electrically connected to at least a portion of the data lines; One or more gate driving circuits, wherein the gate driving circuits include cascaded multi-stage shift registers, and output ends of the shift registers are electrically connected to the corresponding gate lines; Among them, in at least a part of the fan-out lines, in the same fan-out line, the fan-out line includes a sub-connection segment and a plurality of sub-extension segments, two adjacent sub-extension segments are connected by the sub-connection segment, the plurality of sub-extension segments include a first sub-extension segment and a second sub-extension segment, and at least one gate line adjacent to the first sub-extension segment and the gate line adjacent to the second sub-extension segment are electrically connected to different output ends of the shift register.

24. A display panel, characterized in that: The display panel comprises: substrate; A plurality of data lines are arranged on the substrate; A plurality of gate lines are disposed on the substrate; A plurality of fan-out lines are arranged on the substrate, and the plurality of fan-out lines are electrically connected to at least a portion of the data lines; A plurality of pixel circuits arranged in an array, electrically connected to the corresponding gate lines and the data lines, the pixel circuits comprising a plurality of transistors with different functions; Among them, in at least a part of the fan-out lines, in the same fan-out line, the fan-out line includes a sub-connection segment and a plurality of sub-extension segments, two adjacent sub-extension segments are connected by the sub-connection segment, the plurality of sub-extension segments include a first sub-extension segment and a second sub-extension segment, and the transistor electrically connected to at least one gate line adjacent to the first sub-extension segment and the transistor electrically connected to the gate line adjacent to the second sub-extension segment have different functions.

25. A display device, characterized in that: The invention comprises a driving chip and the display panel according to any one of claims 1 to 24, wherein the driving chip is electrically connected to the fan-out line.

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