Gating tube and manufacturing method thereof

Abstract

The present disclosure relates to a gate tube and a manufacturing method thereof, and relates to the field of integrated circuit technology. The gate tube includes a first electrode layer, a gate layer, a buffer layer, a barrier layer, and a second electrode layer. The gate layer, the buffer layer, and the barrier layer are stacked between the first electrode layer and the second electrode layer. The electron affinity of the barrier layer is less than that of the gate layer, and the electron affinity of the buffer layer is between the gate layer and the barrier layer. The barrier layer localizes electrons to prevent electrons from leaking outward, thereby reducing the leakage current of the gate tube, and a buffer layer is provided between the gate layer and the barrier layer. The buffer layer is used to buffer the difference in electron affinity between the gate layer and the barrier layer, thereby avoiding fluctuations in the performance of the gate tube caused by excessive difference in electron affinity between the gate layer and the barrier layer. The buffer layer can also reduce the barrier layer voltage drop to prevent the barrier layer from being broken down by the high voltage drop.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a gate transistor and a manufacturing method thereof. Background Art

[0002] With the continuous development of fields such as artificial intelligence and autonomous driving, higher requirements are being placed on memories, such as higher integration density and better reliability. A selector is a two-terminal nonlinear or threshold transition device used to select and control the on and off of a memory cell. The selector can be combined with a memory to form a 1S1R memory cell, such as resistive random access memory (RRAM), phase change random access memory (PCRAM), magnetoresistive random access memory (MRAM), or ferroelectric random access memory (FeRAM). Introducing a two-terminal selector into a memory cell can suppress leakage current in a crossbar memory array. Compared to a three-terminal transistor (feature size 6F2), the selector has a simpler structure (feature size 4 / N F2, where N is the number of stacked layers), which facilitates the three-dimensional integration of memory cells.

[0003] However, the limited leakage current suppression capability of the gate transistor is difficult to solve, and this leakage current hinders the practical application of the 1S1R structure memory cell. Therefore, improving the leakage current suppression capability and reliability of the gate transistor is crucial to increasing the integration density of the memory cell. Summary of the Invention

[0004] Based on this, it is necessary to provide a gate transistor and a manufacturing method thereof to address the leakage current and reliability issues of the gate transistor in the prior art.

[0005] In a first aspect, the present disclosure provides a gate transistor, the gate transistor comprising a first electrode layer, a gate layer, a buffer layer, a barrier layer, and a second electrode layer, wherein the gate layer, the buffer layer, and the barrier layer are stacked between the first electrode layer and the second electrode layer;

[0006] The electron affinity of the barrier layer is smaller than that of the gate layer, and the electron affinity of the buffer layer is between that of the gate layer and the barrier layer.

[0007] Optionally, one side surface of the gating layer contacts the first electrode layer, and a potential barrier is formed between the gating layer and the first electrode layer;

[0008] A potential barrier is formed between a surface of the barrier layer on a side away from the buffer layer and the second electrode layer.

[0009] Optionally, a difference between the work function of the first electrode layer and the electron affinity of the gating layer is greater than 2 eV;

[0010] The difference between the work function of the second electrode layer and the electron affinity of the barrier layer is greater than 2 eV.

[0011] Optionally, the electron affinity of the gating layer is 2 eV to 4.5 eV; and the electron affinity of the barrier layer is 1 eV to 2 eV.

[0012] Optionally, a content of oxygen in a side of the buffer layer close to the barrier layer is greater than a content of oxygen in a side of the buffer layer close to the gate layer.

[0013] Optionally, the oxygen content of the buffer layer gradually increases from the gate layer toward the barrier layer.

[0014] Optionally, the gate layer includes multiple gate material layers, and the oxygen content of the gate material layer on the side away from the first electrode layer is greater than the oxygen content of the gate material layer on the side close to the first electrode layer.

[0015] Optionally, the oxygen content of the multiple gate material layers gradually increases from the gate layer toward the barrier layer.

[0016] Optionally, the material of the barrier layer includes at least one of neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide;

[0017] The material of the buffer layer includes at least one of titanium oxide, nickel oxide, zinc oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, indium oxide, vanadium oxide, niobium oxide, manganese oxide, neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide;

[0018] The material of the gate layer includes at least one of niobium oxide, vanadium oxide, germanium telluride, germanium telluride, germanium selenide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, and gadolinium cobalt oxide.

[0019] In a second aspect, the present disclosure provides a method for manufacturing a gate tube, comprising the following steps:

[0020] providing a substrate, and forming a first electrode layer on the substrate;

[0021] forming a gating layer on the first electrode layer;

[0022] forming a buffer layer on a side of the gating layer away from the first electrode layer;

[0023] forming a barrier layer on a side of the buffer layer away from the gate layer, wherein the electron affinity of the barrier layer is lower than the electron affinity of the gate layer, and the electron affinity of the buffer layer is between the gate layer and the barrier layer;

[0024] A second electrode layer is formed on a side of the barrier layer away from the buffer layer.

[0025] Optionally, forming a buffer layer on a side of the gating layer away from the first electrode layer includes:

[0026] A first conductive layer is deposited on a side of the gating layer away from the first electrode layer to form the barrier layer, and then the gating layer, the first conductive layer and the barrier layer are annealed so that the oxygen elements in the gating layer and the barrier layer oxidize the first conductive layer to form the buffer layer.

[0027] Optionally, a content of oxygen in a side of the buffer layer close to the barrier layer is greater than a content of oxygen in a side of the buffer layer close to the gate layer.

[0028] Optionally, forming a gating layer on the first electrode layer includes:

[0029] Multiple gate material layers are sequentially deposited on the first electrode layer, wherein the oxygen content of the gate material layer on the side away from the first electrode layer is greater than the oxygen content of the gate material layer on the side close to the first electrode layer.

[0030] The present invention discloses a gate tube and a manufacturing method thereof. Electrons are localized in a barrier layer to prevent outward leakage of electrons, thereby reducing leakage current of the gate tube. A buffer layer is provided between the gate layer and the barrier layer. The buffer layer is used to buffer the difference in electron affinity between the gate layer and the barrier layer, thereby preventing performance fluctuations of the gate tube caused by a large difference in electron affinity between the gate layer and the barrier layer, thereby improving the performance stability of the gate tube. At the same time, when the gate tube is turned on, the gate layer changes from a high-resistance state to a low-resistance state, and the potential voltage drop of the barrier layer increases. The buffer layer can reduce the potential voltage drop of the barrier layer, thereby preventing the barrier layer from being broken down by the high potential drop, further reducing the leakage risk of the gate tube, improving the performance stability and reliability of the gate tube, and helping to optimize the performance of the device and extend its service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A schematic structural diagram of a gating tube is provided in one embodiment;

[0033] Figure 2 A schematic structural diagram of a gating tube is provided in another embodiment;

[0034] Figure 3 A flow chart of a method for manufacturing a gate tube is provided in one embodiment.

[0035] Description of reference numerals:

[0036] 11. First electrode layer; 12. Gating layer; 121. First gating material layer; 122. Second gating material layer; 123. Third gating material layer; 124. Fourth gating material layer; 13. Buffer layer; 14. Barrier layer; 15. Second electrode layer. DETAILED DESCRIPTION

[0037] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0039] According to an exemplary embodiment, the present disclosure provides a gate tube, such as Figure 1 or Figure 2 As shown, the gate tube includes a first electrode layer 11, a gate layer 12, a buffer layer 13, a barrier layer 14 and a second electrode layer 15. The gate layer 12, the buffer layer 13 and the barrier layer 14 are stacked between the first electrode layer 11 and the second electrode layer 15; the electron affinity of the barrier layer 14 is smaller than the electron affinity of the gate layer 12, and the electron affinity of the buffer layer 13 is between the gate layer 12 and the barrier layer 14.

[0040] A buffer layer 13 and a barrier layer 14 are sequentially stacked between the gating layer 12 and the first electrode layer 11, and / or between the gating layer 12 and the second electrode layer 15. In one example, a buffer layer 13 and a barrier layer 14 are sequentially stacked between the gating layer 12 and the first electrode layer 11; in another example, a buffer layer 13 and a barrier layer 14 are sequentially stacked between the gating layer 12 and the second electrode layer 15; in yet another example, a buffer layer 13 and a barrier layer 14 are sequentially stacked between the gating layer 12 and the first electrode layer 11, and a buffer layer 13 and a barrier layer 14 are also sequentially stacked between the gating layer 12 and the second electrode layer 15.

[0041] The electron affinity of the barrier layer 14 is smaller than that of the gate layer 12. The barrier layer 14 is arranged between the gate layer 12 and the first electrode layer 11 or between the gate layer 12 and the second electrode layer 15. The barrier layer 14 is used to localize electrons and prevent electrons from leaking outward, thereby reducing the leakage current of the gate tube.

[0042] A buffer layer 13 is provided between the gate layer 12 and the barrier layer 14. The electron affinity of the buffer layer 13 is between that of the gate layer 12 and the barrier layer 14. The buffer layer 13 is used to buffer the difference in electron affinity between the gate layer 12 and the barrier layer 14, thereby avoiding fluctuations in the performance of the gate tube caused by a large difference in the electron affinity between the gate layer 12 and the barrier layer 14, and thus improving the performance stability of the gate tube. At the same time, when the gate tube is turned on, the gate layer 12 changes from a high-resistance state to a low-resistance state, and the voltage drop of the barrier layer 14 increases. The present application provides a buffer layer 13 between the gate layer 12 and the barrier layer 14. The buffer layer 13 can reduce the voltage drop of the barrier layer 14, thereby preventing the barrier layer 14 from being broken down by the high voltage drop, further reducing the risk of leakage of the gate tube, improving the performance stability and reliability of the gate tube, and helping to optimize the performance of the device and extend its service life.

[0043] In some embodiments, reference Figure 1 or Figure 2 The breakdown voltage of the buffer layer 13 is greater than the breakdown voltage of the barrier layer 14. This can further prevent the barrier layer 14 from being broken down by the high voltage when the gate transistor is turned on, further reducing the leakage risk of the gate transistor, improving the performance stability and reliability of the gate transistor, and helping to optimize the performance of the device and extend its service life.

[0044] In some embodiments, reference Figure 1 or Figure 2 The buffer layer 13 has better lattice matching with the gate layer 12, which can avoid the adverse effects caused by the mismatch of the direct contact interface between the gate layer 12 and the barrier layer 14. In addition, the buffer layer 13 has better adhesion with the gate layer 12, which can avoid the problems of delamination and falling off of the layers of the gate tube, which is beneficial to improving the structural stability of the gate tube.

[0045] In some embodiments, reference Figure 1 or Figure 2 One side surface of the gate layer 12 contacts the first electrode layer 11 , forming a potential barrier between the gate layer 12 and the first electrode layer 11 ; and a side surface of the barrier layer 14 away from the buffer layer 13 forms a potential barrier with the second electrode layer 15 .

[0046] In this embodiment, a buffer layer 13 and a barrier layer 14 are stacked in sequence between the gating layer 12 and the second electrode layer 15, which can localize electrons at the barrier between the gating layer 12 and the first electrode layer 11, and localize electrons at the barrier between the barrier layer 14 and the second electrode layer 15, thereby avoiding electron leakage and reducing the leakage current of the gating tube.

[0047] In some embodiments, the difference between the work function of the first electrode layer 11 and the electron affinity of the gate layer 12 is greater than 2 eV; the difference between the work function of the second electrode layer 15 and the electron affinity of the barrier layer 14 is greater than 2 eV.

[0048] In some embodiments, the electron affinity of the gate layer 12 is 2 eV to 4.5 eV, the electron affinity of the barrier layer 14 is 1 eV to 2 eV, and the electron affinity of the buffer layer 13 is 1 eV to 4.5 eV.

[0049] In some embodiments, reference Figure 1 or Figure 2 The oxygen content of the buffer layer 13 on the side close to the barrier layer 14 is greater than the oxygen content of the buffer layer 13 on the side close to the gate layer 12. In this embodiment, the electron affinity of the buffer layer 13 is adjusted by adjusting the oxygen content of the buffer layer 13. The electron affinity of the buffer layer 13 on the side close to the barrier layer 14 is closer to that of the barrier layer 14, and the electron affinity of the buffer layer 13 on the side close to the gate layer 12 is closer to that of the gate layer 12. This further avoids performance fluctuations of the gate tube caused by a large difference in electron affinity between the gate layer 12 and the barrier layer 14, and further improves the performance stability of the gate tube.

[0050] In some embodiments, reference Figure 1 or Figure 2 The oxygen content of the buffer layer 13 gradually increases from the gate layer 12 toward the barrier layer 14. In this embodiment, the electron affinity of the buffer layer 13 gradually changes from the gate layer 12 toward the barrier layer 14, and the electron affinities of the gate layer 12, the buffer layer 13, and the barrier layer 14 transition smoothly. This avoids fluctuations in gate transistor performance caused by an excessively large difference in electron affinity between the gate layer 12 and the barrier layer 14, thereby improving the stability and performance of the gate transistor.

[0051] In some embodiments, reference Figure 1 or Figure 2The gate layer 12 includes multiple gate material layers, and the oxygen content of the gate material layer farther from the first electrode layer 11 is greater than the oxygen content of the gate material layer closer to the first electrode layer 11. This allows the electron affinity at the interface between the gate layer 12 and the buffer layer 13 to change more smoothly, further improving the stability and performance of the gate transistor.

[0052] In one example, referring to Figure 2 The gate layer 12 includes a first gate material layer 121, a second gate material layer 122, a third gate material layer 123, and a fourth gate material layer 124 stacked in sequence. The first gate material layer 121 includes niobium monoxide, the second gate material layer 122 includes niobium dioxide, the third gate material layer 123 includes niobium trioxide, and the fourth gate material layer 124 includes niobium pentoxide.

[0053] In some embodiments, reference Figure 1 or Figure 2 The oxygen content of the multiple gate material layers gradually increases from the gate layer 12 toward the barrier layer 14. This allows the electron affinity of the gate layer 12 to change smoothly from the gate layer 12 toward the barrier layer 14, further reducing the difference in electron affinity between the gate layer 12 and the barrier layer 14 and improving the stability and performance of the gate transistor.

[0054] In some embodiments, reference Figure 1 or Figure 2 The barrier layer 14 includes multiple barrier material layers, and the oxygen content of the barrier material layer on the side away from the buffer layer 13 is greater than the oxygen content of the barrier material layer on the side close to the buffer layer 13. This further weakens the difference in electron affinity between the gate layer 12 and the barrier layer 14.

[0055] From the gate layer 12 toward the barrier layer 14 , the oxygen content of the multi-layer barrier material layer gradually increases, further weakening the difference in electron affinity between the gate layer 12 and the barrier layer 14 .

[0056] In some embodiments, the material of the gate layer 12 includes metal oxide; the oxygen affinity of the buffer layer 13 is less than the oxygen affinity of the barrier layer 14. In this way, the buffer layer 13 is arranged between the gate layer 12 and the barrier layer 14, which can also reduce the oxygen loss of the gate tube, help improve the stability of the working performance of the gate tube and extend its service life.

[0057] In some embodiments, the material of the barrier layer 14 includes neodymium oxide (NdO x ), strontium oxide (SrO x ), Germanium oxide (GeO x ), lanthanum oxide (LaO x ), hafnium oxide (HfOx ), gallium oxide (GaO x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), silicon oxide (SiO x ), Ytterbium oxide (YbO x ) or magnesium oxide (MgO x ) at least one of;

[0058] The material of the buffer layer 13 includes titanium oxide (TiO x ), nickel oxide (NiO x ), zinc oxide (ZnO x ), chromium oxide (CrO x ), molybdenum oxide (MoO x ), tungsten oxide (WO x ), bismuth oxide (BiO x ), antimony oxide (SbO x ), indium oxide (InO x ), vanadium oxide (VO x ), niobium oxide (NbO x ), manganese oxide (MnO x ), neodymium oxide (NdO x ), strontium oxide (SrO x ), Germanium oxide (GeO x ), lanthanum oxide (LaO x ), hafnium oxide (HfO x ), gallium oxide (GaO x ), aluminum oxide (AlO x ), zirconium oxide (ZrO x ), silicon oxide (SiO x ), Ytterbium oxide (YbO x ) or magnesium oxide (MgO x ) at least one of;

[0059] The material of the gate layer 12 includes niobium oxide (NbO x ), vanadium oxide (VO x ), Germanium Telluride (GeTe x ), Germanium Telluride (GeTe x ), Germanium selenide (GeSe x ), iron oxide (FeO x ), neodymium nickel oxide (NdNiO x ), samarium nickel oxide (SmNiO x ), lanthanum cobalt oxide (LaCoO x ), gadolinium cobalt oxide (GdCoO x ) at least one.

[0060] In some embodiments, reference Figure 1 or Figure 2 The gate layer 12 is made of a metal oxide; the buffer layer 13 is made of a metal oxide or a non-metal oxide; and the barrier layer 14 is made of a metal oxide or a non-metal oxide. The buffer layer 13 is in contact with the gate layer 12. During operation of the gate transistor, oxygen in the gate layer 12 may be captured by the first electrode layer 11. The buffer layer 13 supplies oxygen to the gate layer 12, maintaining a balanced oxygen content in the gate layer 12 and improving the performance stability of the gate transistor.

[0061] In one example, the gate tube includes a first electrode layer 11, a gate layer 12, a buffer layer 13, a barrier layer 14 and a second electrode layer 15 stacked in sequence, the material of the gate layer 12 includes niobium oxide, the material of the buffer layer 13 includes titanium nitride, and the material of the barrier layer 14 includes aluminum oxide.

[0062] According to an exemplary embodiment, Figure 3 As shown, refer to Figure 1 、 Figure 2 The present disclosure provides a method for manufacturing a gate tube, comprising the following steps:

[0063] Step S101: providing a substrate, and forming a first electrode layer 11 on the substrate;

[0064] Step S102: forming a gate layer 12 on the first electrode layer 11;

[0065] Step S103: forming a buffer layer 13 on a side of the gate layer 12 away from the first electrode layer 11;

[0066] Step S104: forming a barrier layer 14 on a side of the buffer layer 13 away from the gate layer 12, wherein the electron affinity of the barrier layer 14 is lower than that of the gate layer 12, and the electron affinity of the buffer layer 13 is between that of the gate layer 12 and the barrier layer 14;

[0067] Step S105 : forming a second electrode layer 15 on a side of the barrier layer 14 away from the buffer layer 13 .

[0068] In the manufacturing method of the gating layer 12 of this embodiment, a buffer layer 13 and a barrier layer 14 are sequentially formed between the gating layer 12 and the second electrode layer 15. The barrier layer 14 is used to localize electrons to prevent electrons from leaking outward, thereby reducing the leakage current of the gating tube. The buffer layer 13 is used to buffer the difference in electron affinity between the gating layer 12 and the barrier layer 14, thereby avoiding fluctuations in the performance of the gating tube caused by a large difference in the electron affinity between the gating layer 12 and the barrier layer 14, which is beneficial to improving the performance stability of the gating tube. At the same time, when the gating tube is turned on, the gating layer 12 changes from a high-resistance state to a low-resistance state, and the voltage drop of the barrier layer 14 increases. The buffer layer 13 can reduce the voltage drop of the barrier layer 14, thereby preventing the barrier layer 14 from being broken down by the high voltage drop, further reducing the leakage risk of the gating tube, improving the performance stability and reliability of the gating tube, and helping to optimize the performance of the device and extend its service life.

[0069] In step S101, the substrate (not shown) may be a semiconductor substrate. Semiconductor substrate materials include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. Alternatively, in some cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP).

[0070] The first electrode layer 11 may be formed by deposition on the substrate by physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

[0071] Reference Figure 1 、 Figure 2 The material of the first electrode layer 11 may include one or more of vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, aluminum nitride, aluminum titanium nitride, hafnium, iridium, manganese, zinc, platinum, palladium, copper, or alloys thereof. The first electrode layer 11 may have a single-layer structure or a multi-layer structure.

[0072] For example, the thickness of the first electrode layer 11 may be 10 nm-2500 nm.

[0073] In step S102, refer to Figure 1 、 Figure 2 The gate layer 12 can be formed on the first electrode layer 11 by using PVD, PECVD, ALD, ion beam sputtering, electron beam evaporation or thermal evaporation.

[0074] Illustratively, the material of the gate layer 12 includes at least one of niobium oxide, vanadium oxide, germanium telluride, germanium telluride, germanium selenide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, and gadolinium cobalt oxide.

[0075] For example, the gate layer 12 may include a single gate material layer or multiple gate material layers stacked in sequence.

[0076] In some embodiments, during the process of depositing the gate layer 12 , a conductive material is doped into the gate layer 12 to improve the conductivity of the gate layer 12 .

[0077] For example, ion implantation (IMP) and / or co-sputtering (Co-Sputter) may be used to dope the gate layer 12 with a conductive material.

[0078] For example, the conductive material doped into the gate layer 12 may include one or more of Al, Cu, Au, Ti, etc.

[0079] In step S103, refer to Figure 1 、 Figure 2 The buffer layer 13 may be formed by PVD, CVD or ALD deposition. The electron affinity of the buffer layer 13 is lower than that of the gate layer 12.

[0080] For example, the material of the buffer layer 13 may include at least one of titanium oxide, nickel oxide, zinc oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, indium oxide, vanadium oxide, niobium oxide, manganese oxide, neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide.

[0081] For example, the buffer layer 13 may include a single buffer dielectric layer or multiple buffer dielectric layers stacked in sequence.

[0082] For example, the buffer layer 13 may be 1 nm to 5 nm. For example, the buffer layer 13 may be 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 4 nm, 4.5 nm, or 5 nm.

[0083] In step S104, refer to Figure 1 、 Figure 2 The barrier layer 14 may be formed by PVD, CVD or ALD deposition, and the electron affinity of the barrier layer 14 is smaller than the electron affinity of the buffer layer 13 .

[0084] For example, the material of the barrier layer 14 may include at least one of neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide, or magnesium oxide.

[0085] For example, the barrier layer 14 may include a single barrier material layer or multiple barrier material layers stacked in sequence.

[0086] For example, the barrier layer 14 may be 1 nm to 5 nm. For example, the barrier layer 14 may be 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 4 nm, 4.5 nm, or 5 nm.

[0087] In step S105, refer to Figure 1 、 Figure 2 The second electrode layer 15 can be deposited on the barrier layer 14 by PVD, CVD, PECVD, or ALD. The material of the second electrode layer 15 can include one or more of vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, aluminum aluminum titanium nitride, aluminum nitride, aluminum titanium nitride, hafnium, iridium, manganese, zinc, platinum, palladium, copper, or alloys of the above materials. The second electrode layer 15 can have a single-layer structure or a multi-layer structure.

[0088] For example, the thickness of the second electrode layer 15 may be 10 nm-2500 nm.

[0089] The manufacturing method of the gate tube of this embodiment forms a buffer layer 13 and a barrier layer 14 stacked in sequence between the gate layer 12 and the second electrode layer 15. The leakage current of the gate tube is reduced by localized electrons in the barrier layer 14. At the same time, the electron affinities of the gate layer 12, the buffer layer 13, and the barrier layer 14 are reduced in sequence. The buffer layer 13 reduces the performance fluctuation of the gate tube caused by an excessively large difference in the electron affinity between the gate layer 12 and the barrier layer 14, which is beneficial to improving the performance stability of the gate tube.

[0090] In some embodiments, reference Figure 1 、 Figure 2 The breakdown voltage of the buffer layer 13 is greater than the breakdown voltage of the barrier layer 14. This can further prevent the barrier layer 14 from being broken down by the high voltage when the gate transistor is turned on, further reducing the leakage risk of the gate transistor, improving the performance stability and reliability of the gate transistor, and helping to optimize the performance of the device and extend its service life.

[0091] In some embodiments, reference Figure 1 、 Figure 2 One side surface of the gate layer 12 contacts the first electrode layer 11 , forming a potential barrier between the gate layer 12 and the first electrode layer 11 ; and a side surface of the barrier layer 14 away from the buffer layer 13 forms a potential barrier with the second electrode layer 15 .

[0092] In this embodiment, a buffer layer 13 and a barrier layer 14 are stacked in sequence between the gating layer 12 and the second electrode layer 15, which can localize electrons at the barrier between the gating layer 12 and the first electrode layer 11, and localize electrons at the barrier between the barrier layer 14 and the second electrode layer 15, thereby avoiding electron leakage and reducing the leakage current of the gating tube.

[0093] In some embodiments, reference Figure 1 、 Figure 2 , a difference between the work function of the first electrode layer 11 and the electron affinity of the gate layer 12 is greater than 2 eV; a difference between the work function of the second electrode layer 15 and the electron affinity of the barrier layer 14 is greater than 2 eV.

[0094] In some embodiments, the electron affinity of the gate layer 12 is 2 eV to 4.5 eV, the electron affinity of the barrier layer 14 is 1 eV to 2 eV, and the electron affinity of the buffer layer 13 is 1 eV to 4.5 eV.

[0095] In some embodiments, a buffer layer 13 is formed on a side of the gating layer 12 away from the first electrode layer 11, including: depositing a first conductive layer on a side of the gating layer 12 away from the first electrode layer 11 to form a barrier layer 14, and then annealing the gating layer 12, the first conductive layer and the barrier layer 14, so that the oxygen elements in the gating layer 12 and the barrier layer 14 oxidize the first conductive layer to form a buffer layer 13.

[0096] In this embodiment, after the gating layer 12 is formed, a first conductive layer is formed on the gating layer 12, and then the steps of forming the barrier layer 14 and the second electrode layer 15 are performed, and then the structure is subjected to thermal annealing treatment so that the oxygen elements in the gating layer 12 and the barrier layer 14 oxidize the first conductive layer, and the material of the first conductive layer is oxidized to form a buffer layer 13.

[0097] For example, the material of the first conductive layer may include at least one of titanium, nickel, zinc, chromium, molybdenum, tungsten, bismuth, antimony, indium, vanadium, niobium, manganese, neodymium, strontium, germanium, lanthanum, hafnium, gallium, aluminum, zirconium, silicon, ytterbium, or magnesium. The material of the buffer layer 13 may include a metal oxide or a non-metal oxide.

[0098] In some embodiments, the content of oxygen in the buffer layer 13 on a side close to the barrier layer 14 is greater than the content of oxygen in the buffer layer 13 on a side close to the gate layer 12 .

[0099] In this embodiment, the buffer layer 13 is formed by oxidizing the first conductive layer through the oxygen elements in the gate layer 12 and the barrier layer 14, so that the content of oxygen elements on the side of the buffer layer 13 close to the barrier layer 14 is greater than the content of oxygen elements on the side of the buffer layer 13 close to the gate layer 12. The electron affinity of the side of the buffer layer 13 close to the barrier layer 14 is closer to the electron affinity of the barrier layer 14, and the electron affinity of the side of the buffer layer 13 close to the gate layer 12 is closer to the electron affinity of the gate layer 12. This further avoids the performance fluctuation of the gate tube caused by the excessive difference in electron affinity between the gate layer 12 and the barrier layer 14, and further improves the performance stability of the gate tube.

[0100] In this embodiment, the material of the first conductive layer and the thermal annealing parameters may be adjusted so that the oxygen content of the buffer layer 13 gradually increases from the gate layer 12 toward the barrier layer 14 .

[0101] In other embodiments, multiple buffer dielectric layers may be deposited when depositing the buffer layer 13 so that the oxygen content of the buffer dielectric layer near the barrier layer 14 is greater than that of the buffer dielectric layer near the gate layer 12 .

[0102] In some embodiments, forming the gate layer 12 on the first electrode layer 11 includes: sequentially depositing multiple gate material layers on the first electrode layer 11, wherein the oxygen content of the gate material layer on the side away from the first electrode layer 11 is greater than the oxygen content of the gate material layer on the side close to the first electrode layer 11. This allows the electron affinity at the contact interface between the gate layer 12 and the buffer layer 13 to change more smoothly, further improving the stability and performance of the gate transistor.

[0103] In some embodiments, the oxygen content of the multiple gate material layers gradually increases from the gate layer 12 to the barrier layer 14, which can further weaken the difference in electron affinity between the gate layer 12 and the barrier layer 14, thereby improving the stability and performance of the gate transistor.

[0104] In one example, referring to Figure 2 , forming a gate layer 12 on the first electrode layer 11, including: depositing a first gate material layer 121, a second gate material layer 122, a third gate material layer 123, and a fourth gate material layer 124 in sequence on the first electrode layer 11. The first gate material layer 121 includes niobium monoxide, the second gate material layer 122 includes niobium dioxide, the third gate material layer 123 includes niobium trioxide, and the fourth gate material layer 124 includes niobium trioxide.

[0105] In some embodiments, forming the barrier layer 14 on the side of the buffer layer 13 away from the gate layer 12 includes sequentially depositing multiple barrier material layers on the buffer layer 13, wherein the oxygen content of the barrier material layers on the side away from the buffer layer is greater than the oxygen content of the barrier material layers on the side close to the buffer layer 13. This further reduces the difference in electron affinity between the gate layer 12 and the barrier layer 14.

[0106] In some embodiments, reference Figure 1 、 Figure 2 From the gate layer 12 to the barrier layer 14 , the oxygen content of the multi-layer barrier material layer gradually increases, further weakening the difference in electron affinity between the gate layer 12 and the barrier layer 14 .

[0107] In some embodiments, the material of the gate layer 12 includes a metal oxide; the material of the buffer layer 13 includes a metal oxide or a non-metal oxide; and the material of the barrier layer 14 includes a metal oxide or a non-metal oxide. The buffer layer 13 is in contact with the gate layer 12. During operation of the gate transistor, oxygen in the gate layer 12 may be captured by the first electrode layer 11. The buffer layer 13 can supply oxygen to the gate layer 12, maintaining a balanced oxygen content in the gate layer 12 and improving the performance stability of the gate transistor.

[0108] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A gate tube, characterized in that: The gate tube includes a first electrode layer, a gate layer, a buffer layer, a barrier layer and a second electrode layer, wherein the gate layer, the buffer layer and the barrier layer are stacked between the first electrode layer and the second electrode layer; The electron affinity of the barrier layer is smaller than that of the gate layer, and the electron affinity of the buffer layer is between that of the gate layer and the barrier layer; The oxygen content of the buffer layer on a side close to the barrier layer is greater than the oxygen content of the buffer layer on a side close to the gate layer, and the oxygen content of the buffer layer gradually increases from the gate layer toward the barrier layer; the breakdown voltage of the buffer layer is greater than the breakdown voltage of the barrier layer; The gate layer includes multiple gate material layers. The oxygen content of the multiple gate material layers gradually increases from the gate layer to the barrier layer, and the electron affinity of the gate layer changes smoothly and gradually.

2. The gating tube according to claim 1, characterized in that One side surface of the gating layer is in contact with the first electrode layer, and a potential barrier is formed between the gating layer and the first electrode layer; A potential barrier is formed between a surface of the barrier layer on a side away from the buffer layer and the second electrode layer.

3. The gate tube according to claim 2, characterized in that The difference between the work function of the first electrode layer and the electron affinity of the gating layer is greater than 2 eV; The difference between the work function of the second electrode layer and the electron affinity of the barrier layer is greater than 2 eV.

4. The gating tube according to claim 1, characterized in that The electron affinity of the gating layer is 2eV to 4.5eV; the electron affinity of the barrier layer is 1eV to 2eV.

5. The gate tube according to claim 1, characterized in that The material of the barrier layer includes at least one of neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide; The material of the buffer layer includes at least one of titanium oxide, nickel oxide, zinc oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, indium oxide, vanadium oxide, niobium oxide, manganese oxide, neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide; The material of the gate layer includes at least one of niobium oxide, vanadium oxide, germanium telluride, germanium telluride, germanium selenide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, and gadolinium cobalt oxide.

6. A method for manufacturing a gate tube, characterized in that: The following steps are involved: providing a substrate, and forming a first electrode layer on the substrate; forming a gating layer on the first electrode layer; Depositing a first conductive layer on a side of the gating layer away from the first electrode layer; forming a barrier layer on a side of the first conductive layer away from the gating layer; Annealing the gate layer, the first conductive layer, and the barrier layer, so that oxygen in the gate layer and the barrier layer oxidizes the first conductive layer to form a buffer layer; the electron affinity of the barrier layer is lower than that of the gate layer, and the electron affinity of the buffer layer is between that of the gate layer and the barrier layer; forming a second electrode layer on a side of the barrier layer away from the buffer layer; The oxygen content of the buffer layer on a side close to the barrier layer is greater than the oxygen content of the buffer layer on a side close to the gate layer, and the oxygen content of the buffer layer gradually increases from the gate layer toward the barrier layer; the breakdown voltage of the buffer layer is greater than the breakdown voltage of the barrier layer; The gate layer includes multiple gate material layers. The oxygen content of the multiple gate material layers gradually increases from the gate layer to the barrier layer, and the electron affinity of the gate layer changes smoothly and gradually.

7. The method for manufacturing a gate tube according to claim 6, wherein: The content of oxygen in the buffer layer on a side close to the barrier layer is greater than the content of oxygen in the buffer layer on a side close to the gate layer.

8. The method for manufacturing a gate tube according to claim 7, characterized in that: forming a gating layer on the first electrode layer, comprising: Multiple gate material layers are sequentially deposited on the first electrode layer, wherein the oxygen content of the gate material layer on the side away from the first electrode layer is greater than the oxygen content of the gate material layer on the side close to the first electrode layer.

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