Side wall memristor, memory and side wall memristor preparation method
By designing a protruding structure on the memory resistor electrode, the side wall memory resistor can achieve the same electric field strength and physical and chemical process at a lower operating voltage, solving the voltage and energy consumption in the low power consumption in low power consumption applications in low power consumption applications. The problem realizes higher energy efficiency and better CMOS integration.
Patent Information
- Application Number
- CN202411344475.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-25
- Publication Date
- 2025-01-24
AI Technical Summary
Traditional memristors require large write voltage and energy consumption, which limit their advantages in low-power applications, especially in advanced CMOS process nodes.
Design a side wall memory resistor. The edge of the lower electrode, blocking layer and upper electrode has at least one protrusion, and the layer direction is parallel to the circuit negatives. The protruding structure is formed through the photoresistic process to reduce the operating voltage requirements.
By generating high -density and other potential lines such as high -density and significant reinforced electric field strength at the electrode protrusion, the side wall memory resistor can achieve the same physical and chemical processes with less than half of the operation voltage, reducing the operating voltage and energy consumption, so that the energy consumption is reduced, so that the energy consumption and energy consumption can be reduced, so that the operating voltage and energy consumption can be reduced. It is more suitable for integration with low -voltage CMOS process.
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Figure CN119365064A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of semiconductors and electronic devices, and in particular to a sidewall memristor, a memory, and a method for preparing the sidewall memristor. Background Art
[0002] Memristors are considered to be a new type of semiconductor memory with great application potential due to their advantages such as high speed, low power consumption, simple process and back-end integration. Memristors store information by converting the conductivity state (or resistance state). By applying voltage between the upper and lower electrodes of the memristor, an electric field can be formed inside the resistive layer. This electric field drives the physical and chemical processes in the resistive layer, thereby changing the resistance value of the memristor and writing data. After the data is written, the memristor will maintain the written resistance value, realizing non-volatile storage.
[0003] Traditional memristors usually adopt a structure with parallel upper and lower electrodes. When voltage is applied, a uniform electric field distribution is generated inside the resistive layer. This structure requires a large voltage to be applied across the memristor to form a large enough electric field inside the resistive layer to trigger the physical and chemical process of resistive switching. However, this feature brings about higher write voltage and energy consumption, limiting its advantages in low-power applications. Summary of the invention
[0004] Based on this, it is necessary to provide a sidewall memristor, a memory and a method for preparing a sidewall memristor that can reduce power consumption in response to the above technical problems.
[0005] In a first aspect, the present application provides a sidewall memristor, which includes a lower electrode, a resistive switching layer, and an upper electrode stacked in layers; wherein the stacking direction is parallel to the circuit substrate;
[0006] At least one protrusion is correspondingly arranged on the edges of the lower electrode, the resistive switching layer and the upper electrode.
[0007] In one of the embodiments, a first functional layer is disposed between the lower electrode and the resistive layer; and at least one protrusion is disposed correspondingly to the edges of the lower electrode, the first functional layer, the resistive layer and the upper electrode.
[0008] In one embodiment, a second functional layer is disposed between the upper electrode and the resistive layer; and at least one protrusion is disposed correspondingly to the edges of the lower electrode, the first functional layer, the resistive layer, the second functional layer and the upper electrode.
[0009] In a second aspect, the present application further provides a memory, which is applied to the sidewall memristor of any embodiment in the first aspect above.
[0010] In a third aspect, the present application further provides a method for preparing a sidewall memristor, which is applied to the sidewall memristor of any embodiment of the first aspect, and the method comprises:
[0011] Provide circuit film;
[0012] Forming a first lower electrode layer and a first insulating layer in sequence on the circuit substrate;
[0013] The first lower electrode layer and the first insulating layer are patterned to obtain a second lower electrode layer and a second insulating layer; at least one protrusion is provided corresponding to the edge lines of the second lower electrode layer and the second insulating layer;
[0014] Sequentially forming a resistive film layer and an upper electrode film layer on the circuit substrate and the second lower electrode layer;
[0015] The upper electrode film layer, the resistive film layer, the second insulating layer and the second lower electrode layer are patterned to form a sidewall memristor; the sidewall memristor includes a stacked lower electrode, a resistive layer and an upper electrode; wherein the stacking direction is parallel to the circuit substrate; and at least one protrusion is correspondingly arranged at the edge lines of the lower electrode, the resistive layer and the upper electrode.
[0016] In one embodiment, the first lower electrode layer and the first insulating layer are patterned to obtain the second lower electrode layer and the second insulating layer, including:
[0017] Using a photolithography process to form a first photoresist pattern corresponding to the shape of the second lower electrode layer on the first insulating layer;
[0018] Etching the first lower electrode layer and the first insulating layer based on the first photoresist pattern to form a second lower electrode layer and a second insulating layer;
[0019] The first photoresist pattern is removed.
[0020] In one embodiment, the upper electrode film layer, the resistive film layer, the second insulating layer, and the second lower electrode layer are patterned to form a sidewall memristor, including:
[0021] Using a photolithography process to form a second photoresist pattern corresponding to the shape of the sidewall memristor on the upper electrode film layer;
[0022] Based on the second photoresist pattern, an upper electrode film layer, a resistive film layer and a second lower electrode layer are etched to form a sidewall memristor;
[0023] The second photoresist pattern is removed.
[0024] In one embodiment, the resistive film layer and the upper electrode film layer are sequentially formed on the circuit substrate and the second lower electrode layer, including:
[0025] Sequentially forming a first functional layer, a resistive film layer and an upper electrode film layer on the circuit substrate and the second lower electrode layer;
[0026] Correspondingly, the upper electrode film layer, the resistive film layer, the second insulating layer and the second lower electrode layer are patterned to form a sidewall memristor, including:
[0027] The upper electrode material film layer, the resistive film layer, the first functional layer and the second lower electrode layer are patterned to form a sidewall memristor.
[0028] In one embodiment, the resistive film layer and the upper electrode film layer are sequentially formed on the circuit substrate and the second lower electrode layer, including:
[0029] Sequentially forming a first functional layer, a resistive film layer, a second functional layer and an upper electrode film layer on the circuit substrate and the second lower electrode layer;
[0030] Correspondingly, the upper electrode film layer, the resistive film layer, the second insulating layer and the second lower electrode layer are patterned to form a sidewall memristor, including:
[0031] The upper electrode material film layer, the second functional layer, the resistive film layer, the first functional layer and the second lower electrode layer are patterned to form a sidewall memristor.
[0032] In one embodiment, the circuit substrate provided above includes:
[0033] Provide complementary metal oxide semiconductor (CMOS) wafers;
[0034] forming a third insulating layer on the CMOS substrate;
[0035] A connection hole is formed in the third insulating layer; the connection hole corresponds to the position of the lower electrode of the sidewall memristor;
[0036] A wiring metal is arranged in the wiring hole to obtain a circuit bottom sheet.
[0037] In one embodiment, the material of the resistive film layer is any one of metal oxide, non-metal oxide, multi-metal oxide, metal-non-metal mixed oxide and perovskite oxide.
[0038] In one embodiment, the material of the upper electrode film layer and the first lower electrode layer is any one of an inert metal material, a metal material and a metallic compound material.
[0039] In one embodiment, the material of the first functional layer and the second functional layer is any one of a metal material, a binary transition metal oxide, a metal oxide, a non-metal oxide, a multi-component oxygen-phobic metal oxide and a metal-non-metal mixed oxide.
[0040] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0042] FIG1 is a schematic diagram of the structure of a sidewall memristor in one embodiment;
[0043] FIG2 is a diagram showing the normalized potential equipotential line distribution of the sidewall memristor at the electrode protrusion after the operating voltage is applied in one embodiment;
[0044] FIG3 is a diagram showing the distribution of normalized electric field and other electric field lines at the electrode protrusion of the sidewall memristor after the operating voltage is applied in one embodiment;
[0045] FIG4 a is a schematic structural diagram of a sidewall memristor in another embodiment;
[0046] FIG4 b is a schematic structural diagram of a sidewall memristor in another embodiment;
[0047] FIG4c is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0048] FIG4 d is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0049] FIG5 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0050] FIG6 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0051] FIG7 is a schematic flow chart of a method for preparing a sidewall memristor in one embodiment;
[0052] FIG8 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0053] FIG9 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0054] FIG10 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0055] FIG11 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0056] FIG12 is a schematic flow chart of a method for preparing a sidewall memristor in another embodiment;
[0057] FIG13 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0058] FIG14 is a schematic flow chart of a method for preparing a sidewall memristor in another embodiment;
[0059] FIG15 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0060] FIG16 is a schematic flow chart of a method for preparing a sidewall memristor in another embodiment;
[0061] FIG17 is a schematic diagram of the structure of a sidewall memristor in another embodiment;
[0062] Lower electrode 101; first lower electrode layer 1011; second lower electrode layer 1012;
[0063] Resistive layer 102; Resistive film layer 1021; Upper electrode 103;
[0064] Upper electrode film layer 1031; protrusion 104; first functional layer 105;
[0065] Second functional layer 106; circuit substrate 107; CMOS substrate 1071;
[0066] A third insulating layer 1072; a wiring hole 1073; and a wiring metal 1074;
[0067] A first insulating layer 108 ; a second insulating layer 109 . DETAILED DESCRIPTION
[0068] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the above-mentioned figure descriptions and any variations thereof are intended to cover non-exclusive inclusions.
[0070] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.
[0071] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.
[0072] As a new type of non-volatile memory, memristor usually consists of three parts: lower electrode, resistive material layer and upper electrode. Compared with traditional memory, memristor has significant advantages such as high speed, low power consumption, simple process and back-end integration, making it an important development direction of future semiconductor storage technology.
[0073] The working principle of memristor is based on the controllable conversion of conductivity state. By applying voltage between the upper and lower electrodes, an electric field can be established inside the resistive material layer. This electric field drives the physical and chemical processes inside the resistive material layer, thereby changing the resistance value of the memristor and realizing the writing of data. The written data will still be retained after the memristor is powered off, reflecting the characteristics of non-volatile storage.
[0074] If the voltage amplitude applied to the memristor electrode is not enough to form a strong enough electric field inside the resistive material layer, the physical and chemical process cannot be driven and the resistance value of the memristor will remain unchanged. By using this characteristic, the data reading function can be realized by applying a small voltage to measure the on-current of the memristor without changing its stored resistance value.
[0075] Existing memristors use a structure with parallel upper and lower electrodes, including an upper electrode, a resistive switching layer, and a lower electrode arranged in sequence from top to bottom. When voltage is applied, a uniform electric field distribution is generated inside the resistive switching layer. A large voltage needs to be applied to both ends of the memristor to form a sufficiently large electric field inside the resistive switching layer to trigger the physical and chemical process of resistive switching. In addition, as the silicon-based complementary metal oxide semiconductor (CMOS) process continues to shrink, the operating voltage of CMOS circuits continues to decline. At advanced CMOS process nodes (e.g. <14nm), the voltage that CMOS circuits can provide is no longer sufficient to establish a sufficiently strong electric field inside the resistive switching material layer of the memristor, making it impossible to realize the resistive switching function of the memristor. This problem hinders the integration of memristors with advanced CMOS process circuits.
[0076] Based on this, the present application provides a sidewall memristor, a memory and a method for preparing a sidewall memristor, aiming to solve the above technical problems. The following embodiments will specifically illustrate the sidewall memristor, the memory and the method for preparing a sidewall memristor of the present application.
[0077] In one embodiment, as shown in FIG. 1 , a sidewall memristor is provided, which includes a lower electrode 101, a resistive layer 102, and an upper electrode 103 which are stacked; wherein the stacking direction is parallel to the circuit substrate 107; and at least one protrusion 104 is correspondingly arranged at the edges of the lower electrode 101, the resistive layer 102, and the upper electrode 103.
[0078] As shown in FIG. 2 , FIG. 2 is a normalized potential equipotential line distribution diagram of the electrode protrusion of the sidewall memristor after the operating voltage is applied. When the voltage is applied between the electrodes of the sidewall memristor, the equipotential lines are dense at the protrusion 104 of the lower electrode 101 .
[0079] As shown in FIG. 3 , FIG. 3 is a distribution diagram of normalized electric field equifield lines at the electrode protrusion of the sidewall memristor after the operating voltage is applied. When a voltage is applied between the electrodes of the sidewall memristor, the electric field strength is greater than twice that of the parallel region of the electrodes.
[0080] It can be seen from Figures 2 and 3 that, compared with the memristor with parallel electrodes in traditional technology, the sidewall memristor in the embodiment of the present application only needs to apply less than 1 / 2 of the operating voltage to generate an electric field of the same intensity at the protrusion 104 of the electrode to drive the physical and chemical process of resistive change.
[0081] Among them, the examples shown in Figures 1 to 3 are for a case where there is one protrusion 104, and the embodiment of the present application does not limit the number of protrusions 104.
[0082] In some embodiments, the protrusion 104 includes but is not limited to: as shown in FIG4a, the lower electrode 101 has one protrusion 104; as shown in FIG4b, the upper electrode 103 has one protrusion 104; as shown in FIG4c, the upper electrode 103 and the lower electrode 101 each have one protrusion 104. As shown in FIG4d, the lower electrode 101 and the upper electrode 103 have multiple protrusions 104.
[0083] In the sidewall memristor provided by this embodiment, when a voltage is applied between the electrodes, the density of equipotential lines at the protruding portion of the lower electrode is significantly higher than that in the parallel region of the electrodes. This significantly enhances the electric field strength at the protruding portion, which can be more than twice the electric field strength in the parallel region of the electrodes. Therefore, compared with the memristor of the traditional planar structure, the sidewall memristor only needs to apply less than half of the operating voltage to generate an electric field of the same intensity at the protruding portion, thereby driving the physical and chemical processes of the resistive material layer and realizing the writing and reading of data. This design advantage effectively reduces the operating voltage of the sidewall memristor, making it easier to integrate with advanced low-voltage CMOS processes and have higher energy efficiency.
[0084] In one embodiment, as shown in FIG. 5 , a first functional layer 105 is disposed between the lower electrode 101 and the resistive layer 102 ; at least one protrusion 104 is disposed corresponding to the edges of the lower electrode 101 , the first functional layer 105 , the resistive layer 102 and the upper electrode 103 .
[0085] In the sidewall memristor provided in this embodiment, the first functional layer can adjust the electric field distribution inside the resistive layer and optimize the electric field strength, thereby improving the accuracy and reliability of data writing and reading. In addition, the first functional layer can form a special interface structure with the resistive layer to enhance the resistive properties of the resistive material and improve the performance and stability of the memristor. Finally, the first functional layer can serve as a protective layer to prevent the resistive layer from being affected by the external environment and extend the service life of the memristor.
[0086] In one embodiment, as shown in FIG. 6 , a second functional layer 106 is disposed between the upper electrode 103 and the resistive layer 102 ; at least one protrusion 104 is disposed corresponding to the edges of the lower electrode 101 , the first functional layer 105 , the resistive layer 102 , the second functional layer 106 and the upper electrode 103 .
[0087] In the sidewall memristor provided in this embodiment, the second functional layer can adjust the electric field distribution inside the resistive layer and optimize the electric field strength, thereby improving the accuracy and reliability of data writing and reading. In addition, the second functional layer can form a special interface structure with the resistive layer to enhance the resistive properties of the resistive material and improve the performance and stability of the memristor. Finally, the second functional layer can serve as a protective layer to prevent the resistive layer from being affected by the external environment and extend the service life of the memristor.
[0088] Based on any sidewall memristor provided in the above embodiments, the present application also provides a memory, which includes a sidewall memristor, and the sidewall memristor includes a lower electrode 101, a resistive layer 102 and an upper electrode 103 arranged in a stacked manner; wherein the stacking direction is parallel to the circuit substrate 107; and at least one protrusion 104 is correspondingly arranged at the edge lines of the lower electrode 101, the resistive layer 102 and the upper electrode 103.
[0089] In the sidewall memristor provided by this embodiment, when a voltage is applied between the electrodes, the density of equipotential lines at the protruding portion of the lower electrode is significantly higher than that in the parallel region of the electrode, which significantly enhances the electric field strength at the protruding portion, which can reach more than twice the electric field strength in the parallel region of the electrode. Therefore, compared with the memristor with a traditional planar structure, the sidewall memristor only needs to apply less than half of the operating voltage to generate an electric field of the same intensity at the protruding portion, thereby driving the physical and chemical processes of the resistive material layer and realizing the writing and reading of data. This design advantage effectively reduces the operating voltage of the sidewall memristor, making it easier to integrate with advanced low-voltage CMOS processes and have higher energy efficiency.
[0090] In one embodiment, the present application further provides a memory, wherein a first functional layer 105 is disposed between the lower electrode 101 and the resistive layer 102 ; at least one protrusion 104 is disposed corresponding to the edges of the lower electrode 101 , the first functional layer 105 , the resistive layer 102 and the upper electrode 103 .
[0091] In the sidewall memristor provided in this embodiment, the first functional layer can adjust the electric field distribution inside the resistive layer and optimize the electric field strength, thereby improving the accuracy and reliability of data writing and reading. In addition, the first functional layer can form a special interface structure with the resistive layer to enhance the resistive properties of the resistive material and improve the performance and stability of the memristor. Finally, the first functional layer can serve as a protective layer to prevent the resistive layer from being affected by the external environment and extend the service life of the memristor.
[0092] In one embodiment, the present application also provides a memory, wherein a second functional layer 106 is arranged between the upper electrode 103 and the resistive layer 102; at least one protrusion 104 is arranged corresponding to the edges of the lower electrode 101, the first functional layer 105, the resistive layer 102, the second functional layer 106 and the upper electrode 103.
[0093] In the sidewall memristor provided in this embodiment, the second functional layer can adjust the electric field distribution inside the resistive layer and optimize the electric field strength, thereby improving the accuracy and reliability of data writing and reading. In addition, the second functional layer can form a special interface structure with the resistive layer to enhance the resistive properties of the resistive material and improve the performance and stability of the memristor. Finally, the second functional layer can serve as a protective layer to prevent the resistive layer from being affected by the external environment and extend the service life of the memristor.
[0094] Based on any sidewall memristor provided in the above embodiments, the present application further provides a method for preparing a sidewall memristor, as shown in FIG7 . The method for preparing a sidewall memristor can be applied to a sidewall memristor device as an example for illustration. The method includes:
[0095] Step 701, providing a circuit substrate 107.
[0096] In the embodiment of the present application, a circuit substrate 107 connected to the CMOS circuit is provided as a basic platform for the entire processing process.
[0097] Step 702 , forming a first lower electrode layer 1011 and a first insulating layer 108 in sequence on the circuit substrate 107 .
[0098] In the embodiment of the present application, as shown in FIG8 , a first lower electrode layer 1011 and a first insulating layer 108 are sequentially deposited on the circuit substrate 107. The first lower electrode layer 1011 is composed of a conductive material and is usually deposited by a physical vapor deposition method or a chemical vapor deposition method. Next, a layer of insulating material is deposited on the first lower electrode layer 1011 by also using a physical vapor deposition method or a chemical vapor deposition method to form the first insulating layer 108.
[0099] Step 703 , patterning the first lower electrode layer 1011 and the first insulating layer 108 to obtain a second lower electrode layer 1012 and a second insulating layer 109 ; at least one protrusion 104 is provided corresponding to the edge lines of the second lower electrode layer 1012 and the second insulating layer 109 .
[0100] In the embodiment of the present application, as shown in FIG8 and FIG9, a dry etching technique, such as deep reactive ion etching, is used to etch a pattern having a protrusion 104 shape on the first lower electrode layer 1011 and the first insulating layer 108. Among them, at least one protrusion 104 is correspondingly provided at the edge of the second lower electrode layer 1012 and the second insulating layer 109.
[0101] Step 704 , forming a resistive film layer 1021 and an upper electrode film layer 1031 on the circuit substrate 107 and the second lower electrode layer 1012 in sequence.
[0102] In the embodiment of the present application, as shown in FIG10 , a resistive film layer 1021 and an upper electrode film layer 1031 are sequentially deposited on the circuit substrate 107 and the second lower electrode layer 1012. The resistive film layer 1021 is composed of materials such as titanium oxide or zirconium oxide, and is deposited by physical vapor deposition or chemical vapor deposition. A layer of conductive material is deposited on the resistive film layer 1021 to form an upper electrode film layer 1031 as a top electrode.
[0103] Step 705 , patterning the upper electrode film layer 1031 , the resistive film layer 1021 , the second insulating layer 109 and the second lower electrode layer 1012 to form a sidewall memristor.
[0104] The sidewall memristor comprises a stacked lower electrode 101, a resistive layer 102 and an upper electrode 103, wherein the stacking direction is parallel to the circuit substrate 107, and at least one protrusion 104 is correspondingly arranged at the edges of the lower electrode 101, the resistive layer 102 and the upper electrode 103.
[0105] In an embodiment of the present application, as shown in FIG. 11 , a dry etching technique, such as deep reactive ion etching, is used to etch a pattern having a protrusion 104 shape on the upper electrode film layer 1031 , the resistive film layer 1021 , the second insulating layer 109 , and the second lower electrode layer 1012 to form a sidewall memristor.
[0106] In the above-mentioned sidewall memristor preparation method, when a voltage is applied between the electrodes, the density of equipotential lines at the protruding portion of the lower electrode is significantly higher than that in the parallel region of the electrode. This significantly enhances the electric field strength at the protruding portion, which can be more than twice the electric field strength in the parallel region of the electrode. Therefore, compared with the traditional planar structure memristor, the sidewall memristor only needs to apply less than half of the operating voltage to generate an electric field of the same intensity at the protruding portion, thereby driving the physical and chemical processes of the resistive material layer and realizing the writing and reading of data. This design advantage effectively reduces the operating voltage of the sidewall memristor, making it easier to integrate with advanced low-voltage CMOS processes and have higher energy efficiency.
[0107] In an exemplary embodiment, as shown in FIG. 12 , in step 703, “patterning the first lower electrode layer 1011 and the first insulating layer 108 to obtain the second lower electrode layer 1012 and the second insulating layer 109 ” includes:
[0108] Step 1201 , forming a first photoresist pattern corresponding to the shape of the second lower electrode layer 1012 on the first insulating layer 108 by using a photolithography process.
[0109] In the embodiment of the present application, as shown in FIG13 , a layer of photoresist is firstly uniformly coated on the surface of the first insulating layer 108, and then pre-baked to remove the solvent in the photoresist and improve the adhesion of the photoresist. Then, a photolithography mask and an ultraviolet light source are used to project the pattern on the photolithography mask onto the photoresist layer. Depending on the type of photoresist (positive photoresist or negative photoresist), the exposed area will produce different reactions: the positive photoresist becomes soluble after exposure, and the negative photoresist becomes insoluble after exposure. It is then immersed in a developer to remove the photoresist that becomes soluble after exposure, and a first photoresist pattern corresponding to the shape of the second lower electrode layer 1012 is formed. Finally, the developed photoresist pattern is post-baked to enhance the stability and etching resistance of the photoresist.
[0110] Step 1202 , etching the first lower electrode layer 1011 and the first insulating layer 108 based on the first photoresist pattern to form a second lower electrode layer 1012 and a second insulating layer 109 .
[0111] In the embodiment of the present application, in step 1202, the first insulating layer 108 and the first lower electrode layer 1011 of the exposed area are etched according to the first photoresist pattern. Etching can be performed by dry etching or wet etching. Dry etching uses plasma to anisotropically etch the material under a low pressure environment, while wet etching immerses it in an etching solution to remove the material through a chemical reaction. After etching is completed, as shown in FIG9, the structure of the second lower electrode layer 1012 and the second insulating layer 109 is formed.
[0112] Step 1203, removing the first photoresist pattern.
[0113] In the embodiment of the present application, a stripper or a plasma ashing process is used to remove the remaining first photoresist pattern.
[0114] In the above embodiment, photolithography is performed on the first insulating layer through a photolithography process to form a first photoresist pattern corresponding to the shape of the second lower electrode layer, which improves the accuracy of the subsequent etching process.
[0115] In an exemplary embodiment, as shown in FIG. 14 , in step 705 , “patterning the upper electrode film layer 1031 , the resistive film layer 1021 , the second insulating layer 109 , and the second lower electrode layer 1012 to form a sidewall memristor” includes:
[0116] Step 1401 , forming a second photoresist pattern corresponding to the shape of the sidewall memristor on the upper electrode film layer 1031 by using a photolithography process.
[0117] In the embodiment of the present application, as shown in FIG15 , a layer of photoresist is uniformly coated on the surface of the upper electrode film layer 1031, and then pre-baked to remove the solvent in the photoresist and improve its adhesion. Next, by using a photolithography mask and an ultraviolet light source, the pattern on the mask is accurately projected onto the photoresist layer, and the exposed photoresist undergoes different dissolution reactions during the development process according to its type (positive photoresist or negative photoresist), forming the desired second photoresist pattern.
[0118] Step 1402 , etching the upper electrode film layer 1031 , the resistive film layer 1021 , and the second lower electrode layer 1012 based on the second photoresist pattern to form a sidewall memristor.
[0119] In the embodiment of the present application, after the photolithography process is completed, the upper electrode film layer 1031, the resistive film layer 1021, and the second lower electrode layer 1012 are etched based on the second photoresist pattern. The etching process can be completed by dry etching (such as reactive ion etching) or wet etching, and the upper electrode film layer 1031, the resistive film layer 1021, and the second lower electrode layer 1012 in the exposed area are selectively removed according to the photoresist pattern, thereby forming a sidewall memristor.
[0120] Step 1403, removing the second photoresist pattern.
[0121] In the embodiment of the present application, after etching is completed, a stripper or plasma ashing technology is used to remove the second photoresist pattern.
[0122] In the above embodiment, by using a photolithography process to form a second photoresist pattern corresponding to the shape of the sidewall memristor on the upper electrode film layer, the accuracy of the size and shape of the sidewall memristor finally formed can be improved.
[0123] In an exemplary embodiment, in step 704, “forming a resistive film layer 1021 and an upper electrode film layer 1031 on the circuit substrate 107 and the second lower electrode layer 1012 in sequence” includes:
[0124] A first functional layer 105 , a resistive film layer 1021 and an upper electrode film layer 1031 are sequentially formed on the circuit substrate 107 and the second lower electrode layer 1012 .
[0125] Correspondingly, the upper electrode film layer 1031, the resistive film layer 1021, the second insulating layer 109 and the second lower electrode layer 1012 are patterned to form a sidewall memristor, including:
[0126] The upper electrode 103 material film layer, the resistive film layer 1021 , the first functional layer 105 and the second lower electrode layer 1012 are patterned to form a sidewall memristor.
[0127] In the embodiment of the present application, the second lower electrode layer 1012 is first deposited on the circuit substrate 107, and then the first functional layer 105, the resistive film layer 1021 and the upper electrode film layer 1031 are sequentially deposited thereon. Next, a photolithography process is used to perform photolithography on the upper electrode film layer 1031. First, a photoresist is coated on the surface of the upper electrode film layer 1031 and pre-baked. The photoresist is exposed through a photolithography mask and an ultraviolet light source to form a pattern corresponding to the shape of the sidewall memristor. After development treatment, the desired photoresist pattern is obtained. Based on the photoresist pattern, an etching process is used to selectively remove the upper electrode film layer 1031, the resistive film layer 1021, the first functional layer 105 and the second lower electrode layer 1012. After etching is completed, the residual photoresist pattern is removed, and then a comprehensive cleaning is performed to remove any residues and etching byproducts.
[0128] In the above embodiment, the first functional layer can adjust the electric field distribution inside the resistive layer and optimize the electric field strength, thereby improving the accuracy and reliability of data writing and reading. In addition, the first functional layer can form a special interface structure with the resistive layer to enhance the resistive properties of the resistive material and improve the performance and stability of the memristor. Finally, the first functional layer can serve as a protective layer to prevent the resistive layer from being affected by the external environment and extend the service life of the memristor.
[0129] In an exemplary embodiment, in step 704, “forming a resistive film layer 1021 and an upper electrode film layer 1031 on the circuit substrate 107 and the second lower electrode layer 1012 in sequence” includes:
[0130] A first functional layer 105, a resistive film layer 1021, a second functional layer 106 and an upper electrode film layer 1031 are sequentially formed on the circuit substrate 107 and the second lower electrode layer 1012;
[0131] Correspondingly, the upper electrode film layer 1031, the resistive film layer 1021, the second insulating layer 109 and the second lower electrode layer 1012 are patterned to form a sidewall memristor, including:
[0132] The upper electrode 103 material film layer, the second functional layer 106 , the resistive film layer 1021 , the first functional layer 105 and the second lower electrode layer 1012 are patterned to form a sidewall memristor.
[0133] In the embodiment of the present application, first, the second lower electrode layer 1012 is deposited on the circuit substrate 107 to ensure that its thickness and uniformity meet the design requirements. Subsequently, the first functional layer 105, the resistive film layer 1021, the second functional layer 106 and the upper electrode film layer 1031 are sequentially deposited on the second lower electrode layer 1012, and each step requires precise control of the deposition of materials to ensure the thickness and uniformity of each layer.
[0134] Next, a photolithography process is used to perform photolithography on the upper electrode film layer 1031. First, a layer of photoresist is evenly coated on the surface of the upper electrode film layer 1031, and then pre-baked to remove the solvent in the photoresist and improve its adhesion. Next, by using a photolithography mask and an ultraviolet light source, the pattern on the mask is accurately projected onto the photoresist layer. The exposed photoresist, depending on its type (positive photoresist or negative photoresist), undergoes different dissolution reactions during the development process, thereby forming the desired photoresist pattern.
[0135] Based on the formed photoresist pattern, an etching process is used to selectively remove the upper electrode film layer 1031, the second functional layer 106, the resistive film layer 1021, the first functional layer 105 and the second lower electrode layer 1012. The etching process can be dry etching or wet etching. Dry etching uses plasma to anisotropically etch materials under low pressure, while wet etching selectively removes materials through chemical reactions. During the etching process, the etching rate and selectivity need to be precisely controlled to ensure the accurate removal of each layer of material, thereby forming the expected sidewall memristor structure.
[0136] After etching is complete, the remaining photoresist pattern is removed, usually by using a stripper or plasma ashing technology. After stripping, a comprehensive cleaning is performed.
[0137] In the above embodiment, the second functional layer can adjust the electric field distribution inside the resistive layer and optimize the electric field strength, thereby improving the accuracy and reliability of data writing and reading. In addition, the second functional layer can form a special interface structure with the resistive layer, enhance the resistive properties of the resistive material, and improve the performance and stability of the memristor. Finally, the second functional layer can serve as a protective layer to prevent the resistive layer from being affected by the external environment and extend the service life of the memristor.
[0138] In an exemplary embodiment, as shown in FIG. 16 , the step 801 of “providing a circuit substrate 107 ” includes:
[0139] Step 1601 , providing a complementary metal oxide semiconductor (CMOS) substrate 1071 .
[0140] Step 1602 , forming a third insulating layer 1072 on the CMOS substrate 1071 .
[0141] In the embodiment of the present application, as shown in FIG. 17 , after providing a CMOS film 1071 , a third insulating layer 1072 is first formed on the surface thereof by chemical vapor deposition or physical vapor deposition technology.
[0142] Step 1603 , forming a connection hole 1073 in the third insulating layer 1072 ; the connection hole 1073 corresponds to the position of the lower electrode 101 of the sidewall memristor.
[0143] In the embodiment of the present application, a photoresist is coated on the third insulating layer 1072, and then a photoresist pattern of the connection hole 1073 is formed through an exposure and development process. Then, the third insulating layer 1072 is selectively removed through dry etching or wet etching technology to form the connection hole 1073.
[0144] Step 1604 , disposing a connection metal 1074 in the connection hole 1073 to obtain the circuit substrate 107 .
[0145] In the embodiment of the present application, after etching is completed, the photoresist residue is removed and cleaning is performed to ensure that the inner surface of the hole is clean. Next, a wiring metal 1074 is set in the wiring hole 1073, and the metal filling is usually performed by sputtering, evaporation or electroplating technology. Commonly used materials for the wiring metal 1074 include aluminum, copper or tungsten. During the metal filling process, it is necessary to ensure that the metal completely fills the wiring hole 1073 and the surface is flat.
[0146] After the metal filling is completed, chemical mechanical polishing is performed to remove the excess metal and ensure surface flatness. Finally, the circuit substrate 107 is cleaned and dried to ensure that there are no residual pollutants and moisture on its surface.
[0147] In the above embodiment, by forming a third insulating layer on the CMOS substrate and forming a connection hole corresponding to the lower electrode of the sidewall memristor therein, the memristor can be seamlessly integrated with the CMOS circuit. This integration helps to realize storage and logic operation functions on the same chip at the same time, and promotes the development of high-density, high-performance integrated circuits.
[0148] In an exemplary embodiment, the material of the resistive film layer 1021 is any one of metal oxide, non-metal oxide, multi-metal oxide, metal-non-metal mixed oxide and perovskite oxide.
[0149] In the embodiment of the present application, the material of the resistive film layer 1021 includes but is not limited to binary transition metal oxides such as HfOx, TaOx, TiOx, ZrOx, metal oxides such as AlOx, non-metal oxides such as SiOx, and multi-metal oxides, metal-non-metal mixed oxides, perovskite oxides, etc. composed thereof.
[0150] The above embodiments provide a variety of resistive switching film layer material options, which can achieve different resistive switching mechanisms and performances to meet different application requirements.
[0151] In an exemplary embodiment, the material of the upper electrode film layer 1031 and the first lower electrode layer 1011 is any one of an inert metal material, a metal material and a metallic compound material.
[0152] In the embodiment of the present application, the materials of the upper electrode film layer 1031 and the first lower electrode layer 1011 include but are not limited to combinations of inert metal materials such as Pt, Pd, Ir and their alloys, metal materials such as Ta, Hf, Ti, Zr, W, Ru, Al and their alloys, and metallic compound materials such as TiN, TaN, and Poly-Si.
[0153] The above embodiments provide a variety of material options, including inert metals, transition metals, metal alloys, and metallic compounds, etc. Different materials can be selected according to different application requirements to meet different performance requirements.
[0154] In an exemplary embodiment, the material of the first functional layer 105 and the second functional layer 106 is any one of a metal material, a binary transition metal oxide, a metal oxide, a non-metal oxide, a multi-element oxygen-phobic metal oxide, and a metal-non-metal mixed oxide.
[0155] In the embodiment of the present application, the materials of the first functional layer 105 and the second functional layer 106 include but are not limited to metals such as Hf, Ta, Ti, Al, binary transition metal oxides such as oxophobic HfOx, TaOx, TiOx, metal oxides such as oxophobic AlOx, non-metal oxides such as oxophobic SiOx, and multi-component oxophobic metal oxides and metal-non-metal mixed oxides composed thereof.
[0156] In the above embodiments, the diverse material selection provides more flexibility for the design of the memristor, and a suitable material combination can be selected according to different application requirements and performance indicators.
[0157] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0158] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0159] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.
Claims
1. A sidewall memristor, characterized in that: The sidewall memristor comprises a lower electrode, a resistive switching layer and an upper electrode which are stacked; wherein the stacking direction is parallel to the circuit substrate; At least one protrusion is correspondingly arranged on the edges of the lower electrode, the resistive switching layer and the upper electrode.
2. The sidewall memristor according to claim 1, characterized in that: A first functional layer is arranged between the lower electrode and the resistive layer; and at least one protrusion is arranged correspondingly on the edges of the lower electrode, the first functional layer, the resistive layer and the upper electrode.
3. The sidewall memristor according to claim 2, characterized in that: A second functional layer is arranged between the upper electrode and the resistive layer; and at least one protrusion is arranged correspondingly on the edges of the lower electrode, the first functional layer, the resistive layer, the second functional layer and the upper electrode.
4. A memory, characterized in that: Comprising the sidewall memristor as described in any one of claims 1-3.
5. A method for preparing a sidewall memristor, characterized in that: The method comprises: Provide circuit film; Sequentially forming a first lower electrode layer and a first insulating layer on the circuit substrate; The first lower electrode layer and the first insulating layer are patterned to obtain a second lower electrode layer and a second insulating layer; at least one protrusion is provided corresponding to the edge lines of the second lower electrode layer and the second insulating layer; Sequentially forming a resistive film layer and an upper electrode film layer on the circuit substrate and the second lower electrode layer; The upper electrode film layer, the resistive film layer, the second insulating layer and the second lower electrode layer are patterned to form a sidewall memristor; the sidewall memristor includes a stacked lower electrode, a resistive layer and an upper electrode; wherein the stacking direction is parallel to the circuit substrate; and at least one protrusion is correspondingly arranged at the edges of the lower electrode, the resistive layer and the upper electrode.
6. The method according to claim 5, characterized in that The step of patterning the first lower electrode layer and the first insulating layer to obtain a second lower electrode layer and a second insulating layer comprises: forming a first photoresist pattern corresponding to the shape of the second lower electrode layer on the first insulating layer by using a photolithography process; Etching the first lower electrode layer and the first insulating layer based on the first photoresist pattern to form the second lower electrode layer and the second insulating layer; The first photoresist pattern is removed.
7. The method according to claim 5, characterized in that The patterning of the upper electrode film layer, the resistive film layer, the second insulating layer and the second lower electrode layer to form a sidewall memristor includes: Forming a second photoresist pattern corresponding to the shape of the sidewall memristor on the upper electrode film layer by using a photolithography process; Based on the second photoresist pattern, the upper electrode film layer, the resistive film layer and the second lower electrode layer are etched to form the sidewall memristor; The second photoresist pattern is removed.
8. The method according to claim 5, characterized in that The step of sequentially forming a resistive film layer and an upper electrode film layer on the circuit substrate and the second lower electrode layer comprises: Sequentially forming a first functional layer, the resistive film layer and the upper electrode film layer on the circuit substrate and the second lower electrode layer; Correspondingly, the upper electrode film layer, the resistive film layer, the second insulating layer and the second lower electrode layer are patterned to form a sidewall memristor, including: The upper electrode material film layer, the resistive film layer, the first functional layer and the second lower electrode layer are patterned to form the sidewall memristor.
9. The method according to claim 8, characterized in that The step of sequentially forming a resistive film layer and an upper electrode film layer on the circuit substrate and the second lower electrode layer comprises: Sequentially forming the first functional layer, the resistive film layer, the second functional layer and the upper electrode film layer on the circuit substrate and the second lower electrode layer; Correspondingly, the upper electrode film layer, the resistive film layer, the second insulating layer and the second lower electrode layer are patterned to form a sidewall memristor, including: The upper electrode material film layer, the second functional layer, the resistive film layer, the first functional layer and the second lower electrode layer are patterned to form the sidewall memristor.
10. The method according to claim 5, characterized in that The circuit substrate is provided, comprising: Provide complementary metal oxide semiconductor (CMOS) wafers; forming a third insulating layer on the CMOS substrate; A connection hole is formed in the third insulating layer; the connection hole corresponds to the position of the lower electrode of the sidewall memristor; A connection metal is arranged in the connection hole to obtain the circuit bottom sheet.
11. The method according to claim 5, characterized in that The material of the resistive film layer is any one of metal oxide, non-metal oxide, multi-metal oxide, metal-non-metal mixed oxide and perovskite oxide.
12. The method according to claim 5, characterized in that The material of the upper electrode film layer and the first lower electrode layer is any one of an inert metal material, a metal material and a metallic compound material.
13. The method according to claim 5, characterized in that The material of the first functional layer and the second functional layer is any one of a metal material, a binary transition metal oxide, a metal oxide, a non-metal oxide, a multi-component oxygen-phobic metal oxide and a metal-non-metal mixed oxide.